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authorAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:27:03 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:27:03 -0400
commit806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch)
treebf8944a02c194cb657534276190f2a17859b3675 /tests/quick/se/40.m5threads-test-atomic
parenta9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff)
downloadgem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt3984
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt58
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt1984
3 files changed, 3022 insertions, 3004 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index b23c645a0..053bb8ee0 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,64 +1,64 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000107 # Number of seconds simulated
-sim_ticks 107049000 # Number of ticks simulated
-final_tick 107049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000108 # Number of seconds simulated
+sim_ticks 107711000 # Number of ticks simulated
+final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93620 # Simulator instruction rate (inst/s)
-host_op_rate 93620 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 10161795 # Simulator tick rate (ticks/s)
-host_mem_usage 304708 # Number of bytes of host memory used
-host_seconds 10.53 # Real time elapsed on the host
-sim_insts 986230 # Number of instructions simulated
-sim_ops 986230 # Number of ops (including micro ops) simulated
+host_inst_rate 152784 # Simulator instruction rate (inst/s)
+host_op_rate 152784 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 16568657 # Simulator tick rate (ticks/s)
+host_mem_usage 311444 # Number of bytes of host memory used
+host_seconds 6.50 # Real time elapsed on the host
+sim_insts 993230 # Number of instructions simulated
+sim_ops 993230 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 5248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
system.physmem.bytes_read::total 42560 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 5248 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 82 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
system.physmem.num_reads::total 665 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 215228540 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 101037842 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 49024279 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 11957141 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 1793571 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7772142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 2989285 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7772142 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 397574942 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 215228540 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 49024279 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 1793571 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 2989285 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 269035675 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 215228540 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 101037842 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 49024279 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11957141 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 1793571 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7772142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 2989285 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7772142 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 397574942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 666 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue
@@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 114 # Per bank write bursts
system.physmem.perBankRdBursts::1 42 # Per bank write bursts
system.physmem.perBankRdBursts::2 30 # Per bank write bursts
@@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 107021000 # Total gap between requests
+system.physmem.totGap 107683000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
@@ -120,9 +120,9 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 399 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 198 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 396 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 199 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
@@ -216,446 +216,446 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 144 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 276.444444 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 188.969078 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 251.786617 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 43 29.86% 29.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 36 25.00% 54.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 28 19.44% 74.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 12 8.33% 82.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 7 4.86% 87.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8 5.56% 93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 2 1.39% 94.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 2.08% 96.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 5 3.47% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 144 # Bytes accessed per row activation
-system.physmem.totQLat 6009250 # Total ticks spent queuing
-system.physmem.totMemAccLat 18496750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.bytesPerActivate::samples 145 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 274.537931 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 187.244268 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 251.506931 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 44 30.34% 30.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 37 25.52% 55.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 28 19.31% 75.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 11 7.59% 82.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 7 4.83% 87.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8 5.52% 93.10% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation
+system.physmem.totQLat 6590000 # Total ticks spent queuing
+system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9022.90 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27772.90 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 398.17 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 398.17 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 3.11 # Data bus utilization in percentage
-system.physmem.busUtilRead 3.11 # Data bus utilization in percentage for reads
+system.physmem.busUtil 3.09 # Data bus utilization in percentage
+system.physmem.busUtilRead 3.09 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
+system.physmem.avgRdQLen 1.29 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 511 # Number of row buffer hits during reads
+system.physmem.readRowHits 510 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.73 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 160692.19 # Average gap between requests
-system.physmem.pageHitRate 76.73 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 703080 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 383625 # Energy for precharge commands per rank (pJ)
+system.physmem.avgGap 161686.19 # Average gap between requests
+system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 37638810 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27872250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 75978045 # Total energy per rank (pJ)
-system.physmem_0.averagePower 748.690472 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 47858250 # Time in different power states
+system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ)
+system.physmem_0.averagePower 749.440907 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states
system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 51979250 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 32994450 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 31946250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 74129175 # Total energy per rank (pJ)
-system.physmem_1.averagePower 730.471639 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 55670750 # Time in different power states
+system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ)
+system.physmem_1.averagePower 729.430757 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states
system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 45162250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu0.branchPred.lookups 81022 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 78376 # Number of conditional branches predicted
+system.cpu0.branchPred.lookups 81565 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 78355 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 75640 # Number of BTB hits
+system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 96.535001 # BTB Hit Percentage
+system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage
system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 214099 # number of cpu cycles simulated
+system.cpu0.numCycles 215423 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 19687 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 478911 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 81022 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 76285 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 164512 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 1992 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps
system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 617 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 187540 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.553647 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.214546 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 30407 16.21% 16.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 77695 41.43% 57.64% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 798 0.43% 58.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1205 0.64% 58.71% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 612 0.33% 59.04% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 73095 38.98% 98.01% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 670 0.36% 98.37% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 402 0.21% 98.58% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 2656 1.42% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 187540 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.378432 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.236867 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 15435 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 18383 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 151822 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 650 # Number of cycles decode is unblocking
+system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 468409 # Number of instructions handled by decode
+system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode
system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 16041 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2079 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 14982 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 151818 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1370 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 465227 # Number of instructions processed by rename
-system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 867 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 318145 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 927822 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 700792 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 305063 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13082 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 821 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 831 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 4377 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 148776 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 75241 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 72733 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 72329 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 389183 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename
+system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups
+system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 385745 # Number of instructions issued
+system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 12312 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 11729 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 187540 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu0.iq.issued_per_cycle::2 73531 39.21% 59.32% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 73185 39.02% 98.34% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1601 0.85% 99.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 889 0.47% 99.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 403 0.21% 99.88% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 187540 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 61 21.11% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.11% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 125 43.25% 64.36% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.45% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.45% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.45% # attempts to use FU when none available
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+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.45% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 124 42.91% 64.36% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 163127 42.29% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.29% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 148129 38.40% 80.69% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 74489 19.31% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 385745 # Type of FU issued
-system.cpu0.iq.rate 1.801713 # Inst issue rate
+system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued
+system.cpu0.iq.rate 1.803452 # Inst issue rate
system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000749 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 959350 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 402446 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 383893 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 386034 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 71845 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2655 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1674 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 2043 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 463105 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 148776 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 75241 # Number of dispatched store instructions
+system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 990 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1308 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 384734 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 147791 # Number of load instructions executed
+system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 73033 # number of nop insts executed
-system.cpu0.iew.exec_refs 222131 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 76355 # Number of branches executed
-system.cpu0.iew.exec_stores 74340 # Number of stores executed
-system.cpu0.iew.exec_rate 1.796991 # Inst execution rate
-system.cpu0.iew.wb_sent 384301 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 383893 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 227714 # num instructions producing a value
-system.cpu0.iew.wb_consumers 230757 # num instructions consuming a value
+system.cpu0.iew.exec_nop 73578 # number of nop insts executed
+system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 76909 # Number of branches executed
+system.cpu0.iew.exec_stores 74891 # Number of stores executed
+system.cpu0.iew.exec_rate 1.798759 # Inst execution rate
+system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 229361 # num instructions producing a value
+system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 1.793063 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.986813 # average fanout of values written-back
+system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 13101 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 185078 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.431116 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.149204 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 33718 18.22% 18.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 75423 40.75% 58.97% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 1935 1.05% 60.02% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 662 0.36% 60.37% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 535 0.29% 60.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 71534 38.65% 99.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 523 0.28% 99.60% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 185078 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 449946 # Number of instructions committed
-system.cpu0.commit.committedOps 449946 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 453252 # Number of instructions committed
+system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 219688 # Number of memory references committed
-system.cpu0.commit.loads 146121 # Number of loads committed
+system.cpu0.commit.refs 221341 # Number of memory references committed
+system.cpu0.commit.loads 147223 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 75454 # Number of branches committed
+system.cpu0.commit.branches 76005 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 303394 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 305598 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 72186 16.04% 16.04% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 157988 35.11% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.16% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 146205 32.49% 83.65% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 73567 16.35% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMult 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShift 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 449946 # Class of committed instruction
+system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction
system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 646481 # The number of ROB reads
-system.cpu0.rob.rob_writes 928572 # The number of ROB writes
+system.cpu0.rob.rob_reads 651013 # The number of ROB reads
+system.cpu0.rob.rob_writes 935136 # The number of ROB writes
system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26559 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 377676 # Number of Instructions Simulated
-system.cpu0.committedOps 377676 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 0.566885 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.566885 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.764025 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.764025 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 688304 # number of integer regfile reads
-system.cpu0.int_regfile_writes 310378 # number of integer regfile writes
+system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 380431 # Number of Instructions Simulated
+system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 693268 # number of integer regfile reads
+system.cpu0.int_regfile_writes 312587 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 223999 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 141.054653 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 148243 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 866.918129 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.054653 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275497 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.275497 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 82 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 598124 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 598124 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 75326 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 75326 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 72968 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 72968 # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 148294 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 148294 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 148294 # number of overall hits
-system.cpu0.dcache.overall_hits::total 148294 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 561 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 561 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses
+system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits
+system.cpu0.dcache.overall_hits::total 149410 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses
system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses
system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1118 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1118 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1118 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1118 # number of overall misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 17156000 # number of ReadReq miss cycles
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system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 50913980 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 50913980 # number of overall miss cycles
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system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 30581.105169 # average ReadReq miss latency
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 60606.786355 # average WriteReq miss latency
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 45540.232558 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45540.232558 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 45540.232558 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked
@@ -666,68 +666,68 @@ system.cpu0.dcache.fast_writes 0 # nu
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
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system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses
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system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
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system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles
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system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 315 # number of replacements
-system.cpu0.icache.tags.tagsinuse 241.042514 # Cycle average of tags in use
+system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.042514 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.470786 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.470786 # Average percentage of cache occupancy
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system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 182 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 51 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses
@@ -743,12 +743,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 784 #
system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses
system.cpu0.icache.overall_misses::total 784 # number of overall misses
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses
@@ -761,12 +761,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441
system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses
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system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
@@ -787,399 +787,399 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 608
system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses
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+system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51277.960526 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51277.960526 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 51277.960526 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 50039 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 46665 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 42823 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 41749 # Number of BTB hits
+system.cpu1.branchPred.lookups 53924 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 97.492002 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 914 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu1.numCycles 161348 # number of cpu cycles simulated
+system.cpu1.numCycles 162664 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 31303 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 275372 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 50039 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 42663 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 121719 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 2699 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 21928 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 442 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 155480 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.771109 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.178899 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 58088 37.36% 37.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 49421 31.79% 69.15% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 6835 4.40% 73.54% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3518 2.26% 75.81% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 944 0.61% 76.41% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 30727 19.76% 96.18% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1228 0.79% 96.96% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 804 0.52% 97.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 3915 2.52% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 155480 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.310131 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.706696 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 17833 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 58352 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 74506 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3430 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1349 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 260078 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 1349 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 18539 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 27109 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 13862 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 76429 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 18182 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 256857 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 16651 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 180872 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 489824 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 382391 # Number of integer rename lookups
-system.cpu1.rename.CommittedMaps 167019 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13853 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1180 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1251 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 22657 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 71171 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 33454 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 33920 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 28372 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 213121 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 6586 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 214969 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 13076 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 10906 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 730 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 155480 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.382615 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.383057 # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups
+system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 61906 39.82% 39.82% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 21977 14.13% 53.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 32894 21.16% 75.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 32429 20.86% 95.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3365 2.16% 98.13% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1605 1.03% 99.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 896 0.58% 99.74% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 208 0.13% 99.87% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 155480 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 79 23.72% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.72% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 45 13.51% 37.24% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 106597 49.59% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.59% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 75532 35.14% 84.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 32840 15.28% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 214969 # Type of FU issued
-system.cpu1.iq.rate 1.332331 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 333 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001549 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 585768 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 232822 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 213429 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued
+system.cpu1.iq.rate 1.453419 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 215302 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 28182 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2653 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1503 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1349 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 7989 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 73 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 254448 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 142 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 71171 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 33454 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 42 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 1051 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 213962 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 70077 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 1007 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 34741 # number of nop insts executed
-system.cpu1.iew.exec_refs 102825 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 44094 # Number of branches executed
-system.cpu1.iew.exec_stores 32748 # Number of stores executed
-system.cpu1.iew.exec_rate 1.326090 # Inst execution rate
-system.cpu1.iew.wb_sent 213711 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 213429 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 120431 # num instructions producing a value
-system.cpu1.iew.wb_consumers 127039 # num instructions consuming a value
+system.cpu1.iew.exec_nop 38619 # number of nop insts executed
+system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 48027 # Number of branches executed
+system.cpu1.iew.exec_stores 37584 # Number of stores executed
+system.cpu1.iew.exec_rate 1.447253 # Inst execution rate
+system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 134020 # num instructions producing a value
+system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 1.322787 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.947984 # average fanout of values written-back
+system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 13922 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 5856 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 152910 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.572631 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.035068 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 67472 44.13% 44.13% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 40678 26.60% 70.73% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 5251 3.43% 74.16% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 6680 4.37% 78.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1520 0.99% 79.52% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 28236 18.47% 97.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 823 0.54% 98.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 947 0.62% 99.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1303 0.85% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 152910 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 240471 # Number of instructions committed
-system.cpu1.commit.committedOps 240471 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 265858 # Number of instructions committed
+system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 100469 # Number of memory references committed
-system.cpu1.commit.loads 68518 # Number of loads committed
-system.cpu1.commit.membars 5139 # Number of memory barriers committed
-system.cpu1.commit.branches 43053 # Number of branches committed
+system.cpu1.commit.refs 114070 # Number of memory references committed
+system.cpu1.commit.loads 77284 # Number of loads committed
+system.cpu1.commit.membars 4232 # Number of memory barriers committed
+system.cpu1.commit.branches 46981 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 165641 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 183171 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 33840 14.07% 14.07% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 101023 42.01% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.08% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 73657 30.63% 86.71% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 31951 13.29% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction
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system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
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system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
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-system.cpu1.committedOps 201492 # Number of Ops (including micro ops) Simulated
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-system.cpu1.cpi_total 0.800766 # CPI: Total CPI of All Threads
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system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
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system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
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system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1188,106 +1188,106 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 383 # number of replacements
-system.cpu1.icache.tags.tagsinuse 84.275379 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 21349 # Total number of references to valid blocks.
+system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 43.042339 # Average number of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.275379 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164600 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.164600 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 22424 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 22424 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 21349 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 21349 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 21349 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 21349 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 21349 # number of overall hits
-system.cpu1.icache.overall_hits::total 21349 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 579 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 579 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 579 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 579 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 579 # number of overall misses
-system.cpu1.icache.overall_misses::total 579 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 13955500 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 13955500 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 13955500 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 13955500 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 13955500 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 13955500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 21928 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 21928 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 21928 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 21928 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 21928 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 21928 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.026405 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.026405 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.026405 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.026405 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.026405 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.026405 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24102.763385 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 24102.763385 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 24102.763385 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24102.763385 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 24102.763385 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses
+system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits
+system.cpu1.icache.overall_hits::total 19439 # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses
+system.cpu1.icache.overall_misses::total 581 # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked
@@ -1296,409 +1296,409 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 83 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 83 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 83 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 83 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 83 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 83 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11502500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 11502500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11502500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 11502500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11502500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 11502500 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022619 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.022619 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022619 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.022619 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23190.524194 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23190.524194 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 23190.524194 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.branchPred.lookups 42880 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 39445 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1259 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 35521 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 34492 # Number of BTB hits
+system.cpu2.branchPred.lookups 55489 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 97.103122 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 904 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu2.numCycles 160976 # number of cpu cycles simulated
+system.cpu2.numCycles 162291 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 36449 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 226588 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 42880 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 35396 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 120624 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 2677 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1157 # Number of stall cycles due to pending traps
-system.cpu2.fetch.CacheLines 27680 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 159581 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.419893 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.036694 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps
+system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 73772 46.23% 46.23% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 45044 28.23% 74.45% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 9695 6.08% 80.53% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3476 2.18% 82.71% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 968 0.61% 83.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 20661 12.95% 96.26% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 1186 0.74% 97.01% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 799 0.50% 97.51% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3980 2.49% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 159581 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.266375 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.407589 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 17760 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 80804 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 54882 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 4787 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 1338 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 211151 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 1338 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 18439 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 40468 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 13548 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 56825 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 28953 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 208031 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 26065 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 143630 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 381000 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 300757 # Number of integer rename lookups
-system.cpu2.rename.CommittedMaps 129882 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 13748 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1262 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 33404 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 53977 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 23458 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 26723 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 18373 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 168634 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 9408 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 173236 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 15 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 12983 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 10808 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 781 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 159581 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.085568 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.335871 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers
+system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups
+system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 77748 48.72% 48.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 30232 18.94% 67.66% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 22868 14.33% 81.99% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 22470 14.08% 96.08% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3364 2.11% 98.18% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1606 1.01% 99.19% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 879 0.55% 99.74% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 214 0.13% 99.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 200 0.13% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 159581 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 79 23.94% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.94% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 42 12.73% 36.67% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 209 63.33% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 89318 51.56% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.56% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 61054 35.24% 86.80% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 22864 13.20% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 173236 # Type of FU issued
-system.cpu2.iq.rate 1.076160 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 330 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.001905 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 506398 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 191064 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 171727 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued
+system.cpu2.iq.rate 1.508309 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 173566 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 18193 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 2642 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 1338 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 10563 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 81 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 205567 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 184 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 53977 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 23458 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1137 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
+system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 1053 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 1483 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 172231 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 52840 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 1005 # Number of squashed instructions skipped in execute
+system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 27525 # number of nop insts executed
-system.cpu2.iew.exec_refs 75615 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 36863 # Number of branches executed
-system.cpu2.iew.exec_stores 22775 # Number of stores executed
-system.cpu2.iew.exec_rate 1.069917 # Inst execution rate
-system.cpu2.iew.wb_sent 171997 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 171727 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 93200 # num instructions producing a value
-system.cpu2.iew.wb_consumers 99800 # num instructions consuming a value
+system.cpu2.iew.exec_nop 40321 # number of nop insts executed
+system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 49723 # Number of branches executed
+system.cpu2.iew.exec_stores 39200 # Number of stores executed
+system.cpu2.iew.exec_rate 1.501993 # Inst execution rate
+system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 138958 # num instructions producing a value
+system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 1.066786 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.933868 # average fanout of values written-back
+system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 13823 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 8627 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 1259 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 157016 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.220837 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.865055 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 86039 54.80% 54.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 33434 21.29% 76.09% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 5238 3.34% 79.43% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 9429 6.01% 85.43% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1533 0.98% 86.41% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 18255 11.63% 98.03% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 831 0.53% 98.56% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1302 0.83% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 157016 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 191691 # Number of instructions committed
-system.cpu2.commit.committedOps 191691 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 275802 # Number of instructions committed
+system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 73311 # Number of memory references committed
-system.cpu2.commit.loads 51335 # Number of loads committed
-system.cpu2.commit.membars 7910 # Number of memory barriers committed
-system.cpu2.commit.branches 35845 # Number of branches committed
+system.cpu2.commit.refs 118948 # Number of memory references committed
+system.cpu2.commit.loads 80570 # Number of loads committed
+system.cpu2.commit.membars 4324 # Number of memory barriers committed
+system.cpu2.commit.branches 48669 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 131277 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 189737 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 26632 13.89% 13.89% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 83838 43.74% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 59245 30.91% 88.54% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 21976 11.46% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 191691 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1302 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 360642 # The number of ROB reads
-system.cpu2.rob.rob_writes 413593 # The number of ROB writes
-system.cpu2.timesIdled 204 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1395 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 445356 # The number of ROB reads
+system.cpu2.rob.rob_writes 582010 # The number of ROB writes
+system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 157149 # Number of Instructions Simulated
-system.cpu2.committedOps 157149 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.024353 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.024353 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.976226 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.976226 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 286558 # number of integer regfile reads
-system.cpu2.int_regfile_writes 135654 # number of integer regfile writes
+system.cpu2.committedInsts 232019 # Number of Instructions Simulated
+system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 423842 # number of integer regfile reads
+system.cpu2.int_regfile_writes 197927 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 77226 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 23.071332 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 27978 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 999.214286 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.071332 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045061 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.045061 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 226658 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 226658 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 34141 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 34141 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 21749 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 21749 # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits
-system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 55890 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 55890 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 55890 # number of overall hits
-system.cpu2.dcache.overall_hits::total 55890 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 483 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 483 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 156 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 156 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 52 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 52 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 639 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 639 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 639 # number of overall misses
-system.cpu2.dcache.overall_misses::total 639 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7783500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 7783500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3187000 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 3187000 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 671500 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total 671500 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 10970500 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 10970500 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency::cpu2.data 10970500 # number of overall miss cycles
-system.cpu2.dcache.overall_miss_latency::total 10970500 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 34624 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 34624 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 21905 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 21905 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 56529 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 56529 # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses::cpu2.data 56529 # number of overall (read+write) accesses
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-system.cpu2.dcache.overall_avg_miss_latency::total 17168.231612 # average overall miss latency
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system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1707,517 +1707,517 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
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system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.icache.tags.replacements 386 # number of replacements
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-system.cpu2.icache.tags.total_refs 27109 # Total number of references to valid blocks.
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system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks.
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system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id
system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
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-system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13207.530648 # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency::total 13207.530648 # average overall miss latency
-system.cpu2.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked
+system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses
+system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses
+system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits
+system.cpu2.icache.overall_hits::total 19454 # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses
+system.cpu2.icache.overall_misses::total 573 # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses
+system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses
+system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency
+system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
+system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency
+system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.icache.avg_blocked_cycles::no_mshrs 4 # average number of cycles each access was blocked
+system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 71 # number of ReadReq MSHR hits
-system.cpu2.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits::cpu2.inst 71 # number of demand (read+write) MSHR hits
-system.cpu2.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits::cpu2.inst 71 # number of overall MSHR hits
-system.cpu2.icache.overall_mshr_hits::total 71 # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst 73 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total 73 # number of overall MSHR hits
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 500 # number of ReadReq MSHR misses
system.cpu2.icache.ReadReq_mshr_misses::total 500 # number of ReadReq MSHR misses
system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 # number of demand (read+write) MSHR misses
system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses
-system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6543500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_latency::total 6543500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6543500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency::total 6543500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6543500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency::total 6543500 # number of overall MSHR miss cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.018064 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for demand accesses
-system.cpu2.icache.demand_mshr_miss_rate::total 0.018064 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.018064 # mshr miss rate for overall accesses
-system.cpu2.icache.overall_mshr_miss_rate::total 0.018064 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13087 # average ReadReq mshr miss latency
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13087 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13087 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 13087 # average overall mshr miss latency
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.branchPred.lookups 58611 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 55067 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 1279 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 51125 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 50131 # Number of BTB hits
+system.cpu3.branchPred.lookups 42820 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 98.055746 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu3.numCycles 160611 # number of cpu cycles simulated
+system.cpu3.numCycles 161928 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 27021 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 330369 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 58611 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 51037 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 129883 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 2715 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 1165 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 18269 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 450 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 159439 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 2.072071 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.246890 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 47077 29.53% 29.53% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 55913 35.07% 64.60% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 4932 3.09% 67.69% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3522 2.21% 69.90% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 934 0.59% 70.48% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 40952 25.69% 96.17% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1272 0.80% 96.97% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 798 0.50% 97.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 4039 2.53% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 159439 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.364925 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 2.056951 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 16993 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 43740 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 94729 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 2610 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 1357 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 315004 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 1357 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 17735 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 17944 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 14128 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 95562 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 12703 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 311495 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 10931 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 220426 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 606441 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 469854 # Number of integer rename lookups
-system.cpu3.rename.CommittedMaps 206787 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 13639 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1207 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1278 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 17457 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 89942 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 43802 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 42282 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 38692 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 261084 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 4750 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 261694 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 12498 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 9712 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 614 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 159439 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.641342 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.359128 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups
+system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 50249 31.52% 31.52% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 16842 10.56% 42.08% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 43259 27.13% 69.21% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 42799 26.84% 96.05% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3393 2.13% 98.18% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1616 1.01% 99.20% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 876 0.55% 99.75% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 194 0.12% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 159439 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 81 26.21% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.21% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 19 6.15% 32.36% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 209 67.64% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 125700 48.03% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 92778 35.45% 83.49% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 43216 16.51% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued
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+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 261694 # Type of FU issued
-system.cpu3.iq.rate 1.629365 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001181 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 683137 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 278366 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 260191 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued
+system.cpu3.iq.rate 1.068166 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 262003 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 38539 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 2394 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 1484 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 1357 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 5389 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 51 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 309030 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 159 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 89942 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 43802 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 441 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1075 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 1516 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 260676 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 89042 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 1018 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 43196 # number of nop insts executed
-system.cpu3.iew.exec_refs 132177 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 52784 # Number of branches executed
-system.cpu3.iew.exec_stores 43135 # Number of stores executed
-system.cpu3.iew.exec_rate 1.623027 # Inst execution rate
-system.cpu3.iew.wb_sent 260451 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 260191 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 149829 # num instructions producing a value
-system.cpu3.iew.wb_consumers 156442 # num instructions consuming a value
+system.cpu3.iew.exec_nop 27464 # number of nop insts executed
+system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 36861 # Number of branches executed
+system.cpu3.iew.exec_stores 22696 # Number of stores executed
+system.cpu3.iew.exec_rate 1.062126 # Inst execution rate
+system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 92998 # num instructions producing a value
+system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 1.620007 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.957729 # average fanout of values written-back
+system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 13144 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 4136 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 1279 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 156952 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.884863 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 2.121598 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 54210 34.54% 34.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 49323 31.43% 65.96% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 5280 3.36% 69.33% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 4930 3.14% 72.47% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1531 0.98% 73.45% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 38585 24.58% 98.03% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 839 0.53% 98.56% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 955 0.61% 99.17% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 1299 0.83% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 156952 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 295833 # Number of instructions committed
-system.cpu3.commit.committedOps 295833 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 191557 # Number of instructions committed
+system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 129866 # Number of memory references committed
-system.cpu3.commit.loads 87548 # Number of loads committed
-system.cpu3.commit.membars 3423 # Number of memory barriers committed
-system.cpu3.commit.branches 51706 # Number of branches committed
+system.cpu3.commit.refs 73159 # Number of memory references committed
+system.cpu3.commit.loads 51261 # Number of loads committed
+system.cpu3.commit.membars 7996 # Number of memory barriers committed
+system.cpu3.commit.branches 35851 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 203693 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 131131 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass 42497 14.37% 14.37% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 120047 40.58% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.94% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 90971 30.75% 85.70% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 42318 14.30% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction
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+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction
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system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 295833 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 1299 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 464044 # The number of ROB reads
-system.cpu3.rob.rob_writes 620441 # The number of ROB writes
-system.cpu3.timesIdled 203 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1172 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 361140 # The number of ROB reads
+system.cpu3.rob.rob_writes 412450 # The number of ROB writes
+system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 249913 # Number of Instructions Simulated
-system.cpu3.committedOps 249913 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 0.642668 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.642668 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.556014 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.556014 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 456401 # number of integer regfile reads
-system.cpu3.int_regfile_writes 212686 # number of integer regfile writes
+system.cpu3.committedInsts 156923 # Number of Instructions Simulated
+system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 285937 # number of integer regfile reads
+system.cpu3.int_regfile_writes 135307 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 133817 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 24.217896 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 48316 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 1725.571429 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.217896 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047301 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.047301 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor
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+system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy
system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 371433 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 371433 # Number of data accesses
-system.cpu3.dcache.ReadReq_hits::cpu3.data 49959 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 49959 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 42098 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 42098 # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data 13 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total 13 # number of SwapReq hits
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-system.cpu3.dcache.demand_hits::total 92057 # number of demand (read+write) hits
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-system.cpu3.dcache.overall_hits::total 92057 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 521 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 521 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 153 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 153 # number of WriteReq misses
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-system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses
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-system.cpu3.dcache.demand_misses::total 674 # number of demand (read+write) misses
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-system.cpu3.dcache.overall_misses::total 674 # number of overall misses
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-system.cpu3.dcache.ReadReq_miss_latency::total 8076500 # number of ReadReq miss cycles
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-system.cpu3.dcache.WriteReq_miss_latency::total 3408500 # number of WriteReq miss cycles
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-system.cpu3.dcache.SwapReq_miss_latency::total 574500 # number of SwapReq miss cycles
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-system.cpu3.dcache.demand_miss_latency::total 11485000 # number of demand (read+write) miss cycles
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-system.cpu3.dcache.overall_miss_latency::total 11485000 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 50480 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 50480 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 42251 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 42251 # number of WriteReq accesses(hits+misses)
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-system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
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-system.cpu3.dcache.demand_accesses::total 92731 # number of demand (read+write) accesses
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-system.cpu3.dcache.WriteReq_miss_rate::total 0.003621 # miss rate for WriteReq accesses
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-system.cpu3.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses
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-system.cpu3.dcache.demand_miss_rate::total 0.007268 # miss rate for demand accesses
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-system.cpu3.dcache.overall_miss_rate::total 0.007268 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15501.919386 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 15501.919386 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 22277.777778 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 22277.777778 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10638.888889 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 10638.888889 # average SwapReq miss latency
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-system.cpu3.dcache.demand_avg_miss_latency::total 17040.059347 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17040.059347 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 17040.059347 # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses
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+system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits
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+system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses
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+system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses
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+system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses
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+system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses
+system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
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+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency
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@@ -2226,106 +2226,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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@@ -2334,77 +2334,77 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses
@@ -2732,104 +2732,110 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333
system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.165323 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010040 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20759.259259 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20842.105263 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20880.761905 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20886.318182 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20837.022472 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 68617.021277 # average ReadExReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 69708.333333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 99041.666667 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 71786.259542 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72800 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66273.835920 # average ReadCleanReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66145.429363 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 69115.384615 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66219.512195 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72333.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69923.076923 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72800 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 98076.923077 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 67798.048048 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 534 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 292 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 89 # Transaction distribution
-system.membus.trans_dist::ReadExReq 161 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 287 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 87 # Transaction distribution
+system.membus.trans_dist::ReadExReq 162 # Transaction distribution
system.membus.trans_dist::ReadExResp 131 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1742 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1742 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 233 # Total snoops (count)
-system.membus.snoop_fanout::samples 988 # Request fanout histogram
+system.membus.snoops 231 # Total snoops (count)
+system.membus.snoop_fanout::samples 984 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 988 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 988 # Request fanout histogram
-system.membus.reqLayer0.occupancy 929005 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 984 # Request fanout histogram
+system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.9 # Layer utilization (%)
-system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadResp 2782 # Transaction distribution
+system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 3.4 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 677 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 295 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 295 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 389 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 389 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 681 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 595 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 380 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 357 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 6585 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes)
@@ -2839,41 +2845,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1026 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4937 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoops 1019 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 4937 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4937 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2487961 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 509492 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 443468 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 752993 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 440464 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 407479 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 6ed919c46..9e7ba2833 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,10 +4,10 @@ sim_seconds 0.000088 # Nu
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1750110 # Simulator instruction rate (inst/s)
-host_op_rate 1750047 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 226603798 # Simulator tick rate (ticks/s)
-host_mem_usage 303668 # Number of bytes of host memory used
+host_inst_rate 1726221 # Simulator instruction rate (inst/s)
+host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 223510854 # Simulator tick rate (ticks/s)
+host_mem_usage 306324 # Number of bytes of host memory used
host_seconds 0.39 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
@@ -743,9 +743,9 @@ system.cpu3.icache.cache_copies 0 # nu
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.l2c.tags.replacements 0 # number of replacements
system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use
-system.l2c.tags.total_refs 2271 # Total number of references to valid blocks.
+system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 421 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 5.394299 # Average number of references to valid blocks.
+system.l2c.tags.avg_refs 4.076010 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
@@ -770,8 +770,8 @@ system.l2c.tags.occ_task_id_blocks::1024 421 # Oc
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 373 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 23864 # Number of tag accesses
-system.l2c.tags.data_accesses 23864 # Number of data accesses
+system.l2c.tags.tag_accesses 19424 # Number of tag accesses
+system.l2c.tags.data_accesses 19424 # Number of data accesses
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
system.l2c.Writeback_hits::total 1 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
@@ -950,24 +950,30 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
system.membus.snoop_fanout::total 1108 # Request fanout histogram
+system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 1051 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 412 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1542 # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq 637 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 712 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 838 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 696 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 994 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 830 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 618 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 997 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 6784 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes)
@@ -979,21 +985,21 @@ system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side
system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 0 # Total snoops (count)
system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.199505 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3918 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 1485 37.90% 37.90% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 951 24.27% 62.17% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 513 13.09% 75.27% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 969 24.73% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 3918 # Request fanout histogram
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 89934d478..f34aec4c9 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,16 +1,16 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000260 # Number of seconds simulated
-sim_ticks 260073500 # Number of ticks simulated
-final_tick 260073500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000261 # Number of seconds simulated
+sim_ticks 260712500 # Number of ticks simulated
+final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1077387 # Simulator instruction rate (inst/s)
-host_op_rate 1077364 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 425087977 # Simulator tick rate (ticks/s)
-host_mem_usage 303432 # Number of bytes of host memory used
-host_seconds 0.61 # Real time elapsed on the host
-sim_insts 659129 # Number of instructions simulated
-sim_ops 659129 # Number of ops (including micro ops) simulated
+host_inst_rate 1018019 # Simulator instruction rate (inst/s)
+host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 401917302 # Simulator tick rate (ticks/s)
+host_mem_usage 306320 # Number of bytes of host memory used
+host_seconds 0.65 # Real time elapsed on the host
+sim_insts 660333 # Number of instructions simulated
+sim_ops 660333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
@@ -36,164 +36,164 @@ system.physmem.num_reads::cpu2.data 22 # Nu
system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 70134020 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 40603906 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 3445180 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3937348 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 13288551 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 5413854 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 246084 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3691264 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 140760208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 70134020 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 3445180 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 13288551 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 246084 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 87113835 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 70134020 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 40603906 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 3445180 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3937348 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 13288551 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 5413854 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 246084 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3691264 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 140760208 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.numCycles 520147 # number of cpu cycles simulated
+system.cpu0.numCycles 521425 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 157434 # Number of instructions committed
-system.cpu0.committedOps 157434 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 108448 # Number of integer alu accesses
+system.cpu0.committedInsts 157788 # Number of instructions committed
+system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 25842 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 108448 # number of integer instructions
+system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 108684 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 313502 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110054 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 73451 # number of memory refs
-system.cpu0.num_load_insts 48627 # Number of load instructions
-system.cpu0.num_store_insts 24824 # Number of store instructions
+system.cpu0.num_mem_refs 73628 # number of memory refs
+system.cpu0.num_load_insts 48745 # Number of load instructions
+system.cpu0.num_store_insts 24883 # Number of store instructions
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu0.num_busy_cycles 520146.998000 # Number of busy cycles
+system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu0.Branches 26707 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 23434 14.88% 14.88% # Class of executed instruction
-system.cpu0.op_class::IntAlu 60527 38.43% 53.31% # Class of executed instruction
-system.cpu0.op_class::IntMult 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.31% # Class of executed instruction
-system.cpu0.op_class::MemRead 48711 30.93% 84.24% # Class of executed instruction
-system.cpu0.op_class::MemWrite 24824 15.76% 100.00% # Class of executed instruction
+system.cpu0.Branches 26766 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction
+system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction
+system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction
+system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction
+system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 157496 # Class of executed instruction
+system.cpu0.op_class::total 157850 # Class of executed instruction
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system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
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system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
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system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -204,98 +204,98 @@ system.cpu0.dcache.fast_writes 0 # nu
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
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-system.cpu0.icache.overall_miss_latency::total 18042500 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 157497 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 157497 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 157497 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 157497 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 157497 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 157497 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002965 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.002965 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002965 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.002965 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002965 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.002965 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38634.903640 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 38634.903640 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 38634.903640 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38634.903640 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 38634.903640 # average overall miss latency
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -310,158 +310,158 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17575500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 17575500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17575500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 17575500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17575500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 17575500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002965 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.002965 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002965 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.002965 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37634.903640 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37634.903640 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 37634.903640 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.numCycles 520147 # number of cpu cycles simulated
+system.cpu1.numCycles 521425 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 165571 # Number of instructions committed
-system.cpu1.committedOps 165571 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 111555 # Number of integer alu accesses
+system.cpu1.committedInsts 168182 # Number of instructions committed
+system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 31016 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 111555 # number of integer instructions
+system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 110851 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 284333 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 108565 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 56707 # number of memory refs
-system.cpu1.num_load_insts 41448 # Number of load instructions
-system.cpu1.num_store_insts 15259 # Number of store instructions
-system.cpu1.num_idle_cycles 67727.001740 # Number of idle cycles
-system.cpu1.num_busy_cycles 452419.998260 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.869793 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.130207 # Percentage of idle cycles
-system.cpu1.Branches 32668 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 23452 14.16% 14.16% # Class of executed instruction
-system.cpu1.op_class::IntAlu 74986 45.28% 59.44% # Class of executed instruction
-system.cpu1.op_class::IntMult 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.44% # Class of executed instruction
-system.cpu1.op_class::MemRead 51906 31.34% 90.79% # Class of executed instruction
-system.cpu1.op_class::MemWrite 15259 9.21% 100.00% # Class of executed instruction
+system.cpu1.num_mem_refs 54346 # number of memory refs
+system.cpu1.num_load_insts 41092 # Number of load instructions
+system.cpu1.num_store_insts 13254 # Number of store instructions
+system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles
+system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles
+system.cpu1.Branches 34327 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction
+system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction
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+system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction
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+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction
+system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction
+system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 165603 # Class of executed instruction
+system.cpu1.op_class::total 168214 # Class of executed instruction
system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 26.035238 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 32753 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1129.413793 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.035238 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050850 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.050850 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 227042 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 227042 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 41284 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 41284 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 15082 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 15082 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 56366 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 56366 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 56366 # number of overall hits
-system.cpu1.dcache.overall_hits::total 56366 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 156 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 156 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 109 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 109 # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses
-system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 265 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 265 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 265 # number of overall misses
-system.cpu1.dcache.overall_misses::total 265 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2383000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2383000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2068000 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2068000 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 251500 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 251500 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 4451000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 4451000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 4451000 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 4451000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 41440 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 41440 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 15191 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 15191 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 56631 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 56631 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 56631 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 56631 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003764 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007175 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.007175 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.833333 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004679 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.004679 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004679 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.004679 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15275.641026 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15275.641026 # average ReadReq miss latency
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-system.cpu1.dcache.SwapReq_avg_miss_latency::total 4572.727273 # average SwapReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 16796.226415 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16796.226415 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16796.226415 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -470,99 +470,99 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency
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+system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -577,158 +577,158 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4985500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 4985500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4985500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 4985500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4985500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 4985500 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002210 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13621.584699 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13621.584699 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 13621.584699 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.numCycles 520146 # number of cpu cycles simulated
+system.cpu2.numCycles 521424 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 160598 # Number of instructions committed
-system.cpu2.committedOps 160598 # Number of ops (including micro ops) committed
-system.cpu2.num_int_alu_accesses 111601 # Number of integer alu accesses
+system.cpu2.committedInsts 165155 # Number of instructions committed
+system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed
+system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses
system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu2.num_func_calls 637 # number of times a function call or return occured
-system.cpu2.num_conditional_control_insts 28506 # number of instructions that are conditional controls
-system.cpu2.num_int_insts 111601 # number of integer instructions
+system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls
+system.cpu2.num_int_insts 110249 # number of integer instructions
system.cpu2.num_fp_insts 0 # number of float instructions
-system.cpu2.num_int_register_reads 294560 # number of times the integer registers were read
-system.cpu2.num_int_register_writes 113655 # number of times the integer registers were written
+system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read
+system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written
system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu2.num_mem_refs 59264 # number of memory refs
-system.cpu2.num_load_insts 41473 # Number of load instructions
-system.cpu2.num_store_insts 17791 # Number of store instructions
-system.cpu2.num_idle_cycles 67981.871041 # Number of idle cycles
-system.cpu2.num_busy_cycles 452164.128959 # Number of busy cycles
-system.cpu2.not_idle_fraction 0.869302 # Percentage of non-idle cycles
-system.cpu2.idle_fraction 0.130698 # Percentage of idle cycles
-system.cpu2.Branches 30158 # Number of branches fetched
-system.cpu2.op_class::No_OpClass 20943 13.04% 13.04% # Class of executed instruction
-system.cpu2.op_class::IntAlu 75009 46.70% 59.73% # Class of executed instruction
-system.cpu2.op_class::IntMult 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::IntDiv 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatAdd 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatCmp 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatCvt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatMult 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatDiv 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::FloatSqrt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdAdd 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdAddAcc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdAlu 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdCmp 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdCvt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdMisc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdMult 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdMultAcc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdShift 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdSqrt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMult 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.73% # Class of executed instruction
-system.cpu2.op_class::MemRead 46887 29.19% 88.92% # Class of executed instruction
-system.cpu2.op_class::MemWrite 17791 11.08% 100.00% # Class of executed instruction
+system.cpu2.num_mem_refs 54956 # number of memory refs
+system.cpu2.num_load_insts 40791 # Number of load instructions
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+system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles
+system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles
+system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles
+system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles
+system.cpu2.Branches 33115 # Number of branches fetched
+system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction
+system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction
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+system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction
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+system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction
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+system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction
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+system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction
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+system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction
+system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction
+system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 160630 # Class of executed instruction
+system.cpu2.op_class::total 165187 # Class of executed instruction
system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 27.808310 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 37821 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 1304.172414 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.808310 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054313 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.054313 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 237265 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 237265 # Number of data accesses
-system.cpu2.dcache.ReadReq_hits::cpu2.data 41314 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 41314 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 17614 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 17614 # number of WriteReq hits
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-system.cpu2.dcache.SwapReq_hits::total 10 # number of SwapReq hits
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-system.cpu2.dcache.demand_hits::total 58928 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 58928 # number of overall hits
-system.cpu2.dcache.overall_hits::total 58928 # number of overall hits
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-system.cpu2.dcache.ReadReq_misses::total 151 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses::cpu2.data 110 # number of WriteReq misses
-system.cpu2.dcache.WriteReq_misses::total 110 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses
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-system.cpu2.dcache.demand_misses::total 261 # number of demand (read+write) misses
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-system.cpu2.dcache.overall_misses::total 261 # number of overall misses
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-system.cpu2.dcache.ReadReq_miss_latency::total 2416500 # number of ReadReq miss cycles
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-system.cpu2.dcache.SwapReq_miss_latency::total 248000 # number of SwapReq miss cycles
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-system.cpu2.dcache.demand_miss_latency::total 4652000 # number of demand (read+write) miss cycles
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-system.cpu2.dcache.overall_miss_latency::total 4652000 # number of overall miss cycles
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-system.cpu2.dcache.ReadReq_accesses::total 41465 # number of ReadReq accesses(hits+misses)
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-system.cpu2.dcache.WriteReq_accesses::total 17724 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 65 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses)
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-system.cpu2.dcache.demand_accesses::total 59189 # number of demand (read+write) accesses
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-system.cpu2.dcache.overall_accesses::total 59189 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003642 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.003642 # miss rate for ReadReq accesses
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-system.cpu2.dcache.SwapReq_miss_rate::total 0.846154 # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004410 # miss rate for demand accesses
-system.cpu2.dcache.demand_miss_rate::total 0.004410 # miss rate for demand accesses
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-system.cpu2.dcache.overall_miss_rate::total 0.004410 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16003.311258 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16003.311258 # average ReadReq miss latency
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-system.cpu2.dcache.WriteReq_avg_miss_latency::total 20322.727273 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4509.090909 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 4509.090909 # average SwapReq miss latency
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-system.cpu2.dcache.demand_avg_miss_latency::total 17823.754789 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17823.754789 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17823.754789 # average overall miss latency
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+system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits
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+system.cpu2.dcache.overall_hits::total 54608 # number of overall hits
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+system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles
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+system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles
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@@ -737,99 +737,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.numCycles 520146 # number of cpu cycles simulated
+system.cpu3.numCycles 521424 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.committedInsts 175526 # Number of instructions committed
-system.cpu3.committedOps 175526 # Number of ops (including micro ops) committed
-system.cpu3.num_int_alu_accesses 107877 # Number of integer alu accesses
+system.cpu3.committedInsts 169208 # Number of instructions committed
+system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed
+system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses
system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
-system.cpu3.num_conditional_control_insts 37833 # number of instructions that are conditional controls
-system.cpu3.num_int_insts 107877 # number of integer instructions
+system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls
+system.cpu3.num_int_insts 110441 # number of integer instructions
system.cpu3.num_fp_insts 0 # number of float instructions
-system.cpu3.num_int_register_reads 242346 # number of times the integer registers were read
-system.cpu3.num_int_register_writes 89400 # number of times the integer registers were written
+system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read
+system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written
system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu3.num_mem_refs 46213 # number of memory refs
-system.cpu3.num_load_insts 39592 # Number of load instructions
-system.cpu3.num_store_insts 6621 # Number of store instructions
-system.cpu3.num_idle_cycles 68237.870548 # Number of idle cycles
-system.cpu3.num_busy_cycles 451908.129452 # Number of busy cycles
-system.cpu3.not_idle_fraction 0.868810 # Percentage of non-idle cycles
-system.cpu3.idle_fraction 0.131190 # Percentage of idle cycles
-system.cpu3.Branches 39491 # Number of branches fetched
-system.cpu3.op_class::No_OpClass 30262 17.24% 17.24% # Class of executed instruction
-system.cpu3.op_class::IntAlu 73148 41.67% 58.90% # Class of executed instruction
-system.cpu3.op_class::IntMult 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::IntDiv 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatAdd 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatCmp 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatCvt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatMult 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatDiv 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::FloatSqrt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdAdd 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdAddAcc 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdAlu 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdCmp 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdCvt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdMisc 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdMult 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdMultAcc 0 0.00% 58.90% # Class of executed instruction
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-system.cpu3.op_class::SimdShiftAcc 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdSqrt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAdd 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatAlu 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCmp 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatCvt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatDiv 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMisc 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMult 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::SimdFloatSqrt 0 0.00% 58.90% # Class of executed instruction
-system.cpu3.op_class::MemRead 65527 37.32% 96.23% # Class of executed instruction
-system.cpu3.op_class::MemWrite 6621 3.77% 100.00% # Class of executed instruction
+system.cpu3.num_mem_refs 53219 # number of memory refs
+system.cpu3.num_load_insts 40883 # Number of load instructions
+system.cpu3.num_store_insts 12336 # Number of store instructions
+system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles
+system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles
+system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles
+system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles
+system.cpu3.Branches 35047 # Number of branches fetched
+system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction
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+system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction
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+system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction
+system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction
system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu3.op_class::total 175558 # Class of executed instruction
+system.cpu3.op_class::total 169240 # Class of executed instruction
system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 26.732151 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 15554 # Total number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks.
system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 518.466667 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.732151 # Average occupied blocks per requestor
-system.cpu3.dcache.tags.occ_percent::cpu3.data 0.052211 # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total 0.052211 # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor
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system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id
system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 185088 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 185088 # Number of data accesses
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-system.cpu3.dcache.ReadReq_hits::total 39402 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 6435 # number of WriteReq hits
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-system.cpu3.dcache.demand_hits::total 45837 # number of demand (read+write) hits
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-system.cpu3.dcache.overall_hits::total 45837 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 182 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 182 # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
-system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
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-system.cpu3.dcache.demand_misses::total 287 # number of demand (read+write) misses
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-system.cpu3.dcache.overall_misses::total 287 # number of overall misses
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-system.cpu3.dcache.demand_miss_latency::total 4951500 # number of demand (read+write) miss cycles
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-system.cpu3.dcache.overall_miss_latency::total 4951500 # number of overall miss cycles
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-system.cpu3.dcache.ReadReq_accesses::total 39584 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::cpu3.data 6540 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses::total 6540 # number of WriteReq accesses(hits+misses)
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-system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses)
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-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004598 # miss rate for ReadReq accesses
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-system.cpu3.dcache.WriteReq_miss_rate::total 0.016055 # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.759494 # miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_miss_rate::total 0.759494 # miss rate for SwapReq accesses
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-system.cpu3.dcache.demand_miss_rate::total 0.006222 # miss rate for demand accesses
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-system.cpu3.dcache.overall_miss_rate::total 0.006222 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17708.791209 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 17708.791209 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16461.904762 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 16461.904762 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4608.333333 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 4608.333333 # average SwapReq miss latency
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-system.cpu3.dcache.demand_avg_miss_latency::total 17252.613240 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17252.613240 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 17252.613240 # average overall miss latency
+system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses
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+system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits
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+system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits
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+system.cpu3.dcache.overall_hits::total 52867 # number of overall hits
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+system.cpu3.dcache.overall_misses::total 270 # number of overall misses
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+system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles
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+system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
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+system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses
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+system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses
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+system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
+system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -1004,99 +1004,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 182 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42707.688312 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 43642.857143 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 43781.062500 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 43781.062500 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 43687.375000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 43710.421053 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43133.333333 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 43033.333333 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 43142.857143 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 42630.281690 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average ReadCleanReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42619.718310 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 42500 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42519.774011 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 42518.361582 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 42500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 42500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 42500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 42500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42505.263158 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42503.508772 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 42500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 42857.142857 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 42509.259259 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42931.818182 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 42863.636364 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 42500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43100 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 42544.580420 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadResp 430 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 77 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 271 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 76 # Transaction distribution
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1559 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1559 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1557 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1557 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 261 # Total snoops (count)
-system.membus.snoop_fanout::samples 914 # Request fanout histogram
+system.membus.snoop_fanout::samples 913 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 914 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 914 # Request fanout histogram
-system.membus.reqLayer0.occupancy 665648 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 913 # Request fanout histogram
+system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2948008 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
+system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 274 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 274 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution
system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 659 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 363 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 846 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 856 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 383 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5316 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes)
@@ -1604,41 +1610,41 @@ system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side
system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1037 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3986 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
+system.toL2Bus.snoops 1034 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 3986 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3986 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1998491 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 503490 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 419983 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 412483 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 467954 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------