diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-11-06 03:26:50 -0500 |
| commit | 324bc9771d1f3129aee87ccb73bcf23ea4c3b60e (patch) | |
| tree | e5ca02cc181b18d2806e30b99da07d6072724988 /tests/quick/se/40.m5threads-test-atomic | |
| parent | 337774e192cb9268244d05e828b395060ba1cefb (diff) | |
| download | gem5-324bc9771d1f3129aee87ccb73bcf23ea4c3b60e.tar.xz | |
stats: Update stats to match cache changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
3 files changed, 3134 insertions, 3092 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 053bb8ee0..beaa1a0e8 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,64 +1,64 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000108 # Number of seconds simulated -sim_ticks 107711000 # Number of ticks simulated -final_tick 107711000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 107836000 # Number of ticks simulated +final_tick 107836000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 152784 # Simulator instruction rate (inst/s) -host_op_rate 152784 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 16568657 # Simulator tick rate (ticks/s) -host_mem_usage 311444 # Number of bytes of host memory used -host_seconds 6.50 # Real time elapsed on the host -sim_insts 993230 # Number of instructions simulated -sim_ops 993230 # Number of ops (including micro ops) simulated +host_inst_rate 166566 # Simulator instruction rate (inst/s) +host_op_rate 166565 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 18067031 # Simulator tick rate (ticks/s) +host_mem_usage 311540 # Number of bytes of host memory used +host_seconds 5.97 # Real time elapsed on the host +sim_insts 994171 # Number of instructions simulated +sim_ops 994171 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 23040 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5312 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42560 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 23040 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 320 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 192 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 448 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28800 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 360 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 83 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 665 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 213905729 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 100416856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49317154 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 11883652 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2970913 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7724374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1188365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7724374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 395131416 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213905729 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49317154 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2970913 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1188365 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 267382162 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213905729 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 100416856 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49317154 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 11883652 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2970913 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7724374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1188365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7724374 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 395131416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213657777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 100300456 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47479506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11869876 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1780481 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7715420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 4154457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7715420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 394673393 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213657777 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47479506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1780481 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 4154457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 267072221 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213657777 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 100300456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47479506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11869876 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1780481 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7715420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 4154457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7715420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 394673393 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 666 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 666 # Number of DRAM read bursts, including those serviced by the write queue @@ -70,7 +70,7 @@ system.physmem.bytesReadSys 42624 # To system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 87 # Number of requests that are neither read nor write +system.physmem.neitherReadNorWriteReqs 89 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 114 # Per bank write bursts system.physmem.perBankRdBursts::1 42 # Per bank write bursts system.physmem.perBankRdBursts::2 30 # Per bank write bursts @@ -105,7 +105,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 107683000 # Total gap between requests +system.physmem.totGap 107808000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -230,15 +230,15 @@ system.physmem.bytesPerActivate::768-895 2 1.38% 94.48% # By system.physmem.bytesPerActivate::896-1023 3 2.07% 96.55% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 5 3.45% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 145 # Bytes accessed per row activation -system.physmem.totQLat 6590000 # Total ticks spent queuing -system.physmem.totMemAccLat 19077500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 6565250 # Total ticks spent queuing +system.physmem.totMemAccLat 19052750 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 3330000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9894.89 # Average queueing delay per DRAM burst +system.physmem.avgQLat 9857.73 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28644.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 395.73 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28607.73 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 395.27 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 395.73 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 395.27 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 3.09 # Data bus utilization in percentage @@ -250,133 +250,133 @@ system.physmem.readRowHits 510 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.58 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 161686.19 # Average gap between requests +system.physmem.avgGap 161873.87 # Average gap between requests system.physmem.pageHitRate 76.58 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 710640 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 387750 # Energy for precharge commands per rank (pJ) system.physmem_0.readEnergy 2769000 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 38163780 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 27411750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 76054200 # Total energy per rank (pJ) -system.physmem_0.averagePower 749.440907 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 47737250 # Time in different power states +system.physmem_0.actBackEnergy 38088540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 27477750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 76044960 # Total energy per rank (pJ) +system.physmem_0.averagePower 749.349855 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 47969250 # Time in different power states system.physmem_0.memoryStateTime::REF 3380000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 52758750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 52649750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 355320 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 193875 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 2028000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 6611280 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 32134320 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 32700750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 74023545 # Total energy per rank (pJ) -system.physmem_1.averagePower 729.430757 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 57587750 # Time in different power states +system.physmem_1.actBackEnergy 32065065 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 32761500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 74015040 # Total energy per rank (pJ) +system.physmem_1.averagePower 729.346948 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 57811250 # Time in different power states system.physmem_1.memoryStateTime::REF 3380000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 43903750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 43803750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu0.branchPred.lookups 81565 # Number of BP lookups -system.cpu0.branchPred.condPredicted 78921 # Number of conditional branches predicted +system.cpu0.branchPred.lookups 81652 # Number of BP lookups +system.cpu0.branchPred.condPredicted 79008 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1100 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 78897 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 76181 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 78985 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 76270 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 96.557537 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 96.562638 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 645 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 215423 # number of cpu cycles simulated +system.cpu0.numCycles 215673 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 19725 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 482162 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 81565 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 76826 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 165719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.icacheStallCycles 19729 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 482689 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 81652 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 76915 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 165939 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 2501 # Number of cycles fetch has spent squashing system.cpu0.fetch.TlbCycles 96 # Number of cycles fetch has spent waiting for tlb system.cpu0.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1994 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6733 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 620 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.CacheLines 6734 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 621 # Number of outstanding Icache misses that were squashed system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 188787 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.554000 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.213947 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::samples 189011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.553761 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.213837 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 30573 16.19% 16.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 78235 41.44% 57.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 796 0.42% 58.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1203 0.64% 58.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 613 0.32% 59.02% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 73639 39.01% 98.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 671 0.36% 98.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 403 0.21% 98.59% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2654 1.41% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 30617 16.20% 16.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 78326 41.44% 57.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 798 0.42% 58.06% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1203 0.64% 58.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 614 0.32% 59.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 73725 39.01% 98.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 672 0.36% 98.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 403 0.21% 98.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2653 1.40% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 188787 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.378627 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.238210 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 15472 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 18515 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 152899 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 651 # Number of cycles decode is unblocking +system.cpu0.fetch.rateDist::total 189011 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.378592 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.238059 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 15475 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 18570 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 153063 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 653 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 1250 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 471677 # Number of instructions handled by decode +system.cpu0.decode.DecodedInsts 472193 # Number of instructions handled by decode system.cpu0.rename.SquashCycles 1250 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 16075 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 2062 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 15118 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 152899 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 1383 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 468509 # Number of instructions processed by rename -system.cpu0.rename.IQFullEvents 10 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full +system.cpu0.rename.IdleCycles 16079 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2117 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 15116 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 153063 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1386 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 469016 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full system.cpu0.rename.SQFullEvents 883 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 320339 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 934389 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 705719 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 307267 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13072 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RenamedOperands 320676 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 935403 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 706479 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 307583 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13093 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 822 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 832 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4372 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 149868 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 75788 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 73280 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 72874 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 391921 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.rename.skidInsts 4383 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 150037 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 75873 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 73364 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 72959 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 392343 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 889 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 388505 # Number of instructions issued +system.cpu0.iq.iqInstsIssued 388906 # Number of instructions issued system.cpu0.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 12295 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 11684 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedInstsExamined 12322 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 11733 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 330 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 188787 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.057901 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.125475 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 189011 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.057584 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.125737 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33627 17.81% 17.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4227 2.24% 20.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 74093 39.25% 59.30% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 73707 39.04% 98.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1618 0.86% 99.20% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33687 17.82% 17.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4243 2.24% 20.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 74165 39.24% 59.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 73776 39.03% 98.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1622 0.86% 99.20% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 890 0.47% 99.67% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 402 0.21% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 405 0.21% 99.88% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 147 0.08% 99.96% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 76 0.04% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 188787 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189011 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 62 21.45% 21.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 21.45% # attempts to use FU when none available @@ -412,7 +412,7 @@ system.cpu0.iq.fu_full::MemWrite 103 35.64% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 164238 42.27% 42.27% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 164396 42.27% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.27% # Type of FU issued @@ -441,96 +441,96 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.27% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.27% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 149226 38.41% 80.68% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 75041 19.32% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 149390 38.41% 80.68% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 75120 19.32% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 388505 # Type of FU issued -system.cpu0.iq.rate 1.803452 # Inst issue rate +system.cpu0.iq.FU_type_0::total 388906 # Type of FU issued +system.cpu0.iq.rate 1.803221 # Inst issue rate system.cpu0.iq.fu_busy_cnt 289 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000744 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 966117 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 405167 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 386653 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000743 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 967143 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 405616 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 387054 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 388794 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 389195 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 72393 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 72474 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 63 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1670 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1676 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu0.iew.iewSquashCycles 1250 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 2029 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 36 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 466388 # Number of instructions dispatched to IQ +system.cpu0.iew.iewBlockCycles 2081 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 38 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 466895 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 243 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 149868 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 75788 # Number of dispatched store instructions +system.cpu0.iew.iewDispLoadInsts 150037 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 75873 # Number of dispatched store instructions system.cpu0.iew.iewDispNonSpecInsts 770 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 63 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 318 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 991 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1309 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 387494 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 148888 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1011 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 387894 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 149051 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 73578 # number of nop insts executed -system.cpu0.iew.exec_refs 223779 # number of memory reference insts executed -system.cpu0.iew.exec_branches 76909 # Number of branches executed -system.cpu0.iew.exec_stores 74891 # Number of stores executed -system.cpu0.iew.exec_rate 1.798759 # Inst execution rate -system.cpu0.iew.wb_sent 387061 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 386653 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 229361 # num instructions producing a value -system.cpu0.iew.wb_consumers 232407 # num instructions consuming a value +system.cpu0.iew.exec_nop 73663 # number of nop insts executed +system.cpu0.iew.exec_refs 224021 # number of memory reference insts executed +system.cpu0.iew.exec_branches 76988 # Number of branches executed +system.cpu0.iew.exec_stores 74970 # Number of stores executed +system.cpu0.iew.exec_rate 1.798528 # Inst execution rate +system.cpu0.iew.wb_sent 387462 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 387054 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 229603 # num instructions producing a value +system.cpu0.iew.wb_consumers 232649 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.794855 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.986894 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.794634 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.986907 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 13078 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 13111 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1100 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 186327 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.432562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.148979 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 186547 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.432234 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.149146 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33862 18.17% 18.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 75972 40.77% 58.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1939 1.04% 59.99% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 672 0.36% 60.35% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 526 0.28% 60.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 72083 38.69% 99.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 527 0.28% 99.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 263 0.14% 99.74% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33930 18.19% 18.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 76047 40.77% 58.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1940 1.04% 59.99% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 670 0.36% 60.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 524 0.28% 60.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 72154 38.68% 99.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 534 0.29% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 265 0.14% 99.74% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 483 0.26% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 186327 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 453252 # Number of instructions committed -system.cpu0.commit.committedOps 453252 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186547 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 453726 # Number of instructions committed +system.cpu0.commit.committedOps 453726 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 221341 # Number of memory references committed -system.cpu0.commit.loads 147223 # Number of loads committed +system.cpu0.commit.refs 221578 # Number of memory references committed +system.cpu0.commit.loads 147381 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 76005 # Number of branches committed +system.cpu0.commit.branches 76084 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 305598 # Number of committed integer instructions. +system.cpu0.commit.int_insts 305914 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.op_class_0::No_OpClass 72737 16.05% 16.05% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 159090 35.10% 51.15% # Class of committed instruction +system.cpu0.commit.op_class_0::No_OpClass 72816 16.05% 16.05% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 159248 35.10% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 51.15% # Class of committed instruction @@ -559,103 +559,103 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 51.15% system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 51.15% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 51.15% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 147307 32.50% 83.65% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 74118 16.35% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 147465 32.50% 83.65% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 74197 16.35% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 453252 # Class of committed instruction +system.cpu0.commit.op_class_0::total 453726 # Class of committed instruction system.cpu0.commit.bw_lim_events 483 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 651013 # The number of ROB reads -system.cpu0.rob.rob_writes 935136 # The number of ROB writes +system.cpu0.rob.rob_reads 651740 # The number of ROB reads +system.cpu0.rob.rob_writes 936154 # The number of ROB writes system.cpu0.timesIdled 313 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26636 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 380431 # Number of Instructions Simulated -system.cpu0.committedOps 380431 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 0.566260 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.566260 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.765972 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.765972 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 693268 # number of integer regfile reads -system.cpu0.int_regfile_writes 312587 # number of integer regfile writes +system.cpu0.idleCycles 26662 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 380826 # Number of Instructions Simulated +system.cpu0.committedOps 380826 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 0.566330 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.566330 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.765756 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.765756 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 693989 # number of integer regfile reads +system.cpu0.int_regfile_writes 312909 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 225648 # number of misc regfile reads +system.cpu0.misc_regfile_reads 225890 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 141.123038 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 149358 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 141.137199 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 149509 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 171 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 873.438596 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 874.321637 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.123038 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275631 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.275631 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 141.137199 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.275659 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.275659 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::1 67 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 602523 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 602523 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 75889 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 75889 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 73521 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 73521 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 603167 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 603167 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 75961 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 75961 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 73598 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 73598 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 149410 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 149410 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 149410 # number of overall hits -system.cpu0.dcache.overall_hits::total 149410 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 547 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 547 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 149559 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 149559 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 149559 # number of overall hits +system.cpu0.dcache.overall_hits::total 149559 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 557 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 557 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 557 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 557 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1102 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1102 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1102 # number of overall misses -system.cpu0.dcache.overall_misses::total 1102 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 16913500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 16913500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34798980 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 34798980 # number of WriteReq miss cycles +system.cpu0.dcache.demand_misses::cpu0.data 1114 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1114 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1114 # number of overall misses +system.cpu0.dcache.overall_misses::total 1114 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 17293500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 17293500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 34774980 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 34774980 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 472500 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 472500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 51712480 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 51712480 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 51712480 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 51712480 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 76436 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 76436 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 74076 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 74076 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 52068480 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 52068480 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 52068480 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 52068480 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 76518 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 76518 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 74155 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 74155 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 150512 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 150512 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 150512 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 150512 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007156 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.007156 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007492 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007492 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 150673 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 150673 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 150673 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 150673 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.007279 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.007279 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007511 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007511 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007322 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.007322 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007322 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.007322 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30920.475320 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 30920.475320 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62700.864865 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 62700.864865 # average WriteReq miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.007393 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.007393 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.007393 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.007393 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 31047.576302 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 31047.576302 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 62432.639138 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 62432.639138 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18173.076923 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 18173.076923 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 46926.025408 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46926.025408 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 46926.025408 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 46740.107720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 46740.107720 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 46740.107720 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 891 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 27 # number of cycles access was blocked @@ -666,14 +666,14 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 365 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 365 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 377 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 377 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 742 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 742 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 742 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 742 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 375 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 375 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 379 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 379 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 754 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 754 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 754 # number of overall MSHR hits system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 178 # number of WriteReq MSHR misses @@ -684,89 +684,89 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6860000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6860000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8493000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8493000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 6892000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6892000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8487000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8487000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 446500 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 446500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15353000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 15353000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15353000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 15353000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002381 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002381 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002403 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002403 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15379000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 15379000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15379000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 15379000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002379 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002379 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002400 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002400 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002392 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002392 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37692.307692 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37692.307692 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47713.483146 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47713.483146 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002389 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002389 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002389 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 37868.131868 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 37868.131868 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 47679.775281 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 47679.775281 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17173.076923 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17173.076923 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42647.222222 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42647.222222 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42719.444444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42719.444444 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 315 # number of replacements -system.cpu0.icache.tags.tagsinuse 241.163907 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 5949 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 241.200073 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 5951 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 607 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.800659 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.803954 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.163907 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471023 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.471023 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 241.200073 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.471094 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.471094 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 176 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.570312 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 7340 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 7340 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 5949 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5949 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5949 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5949 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5949 # number of overall hits -system.cpu0.icache.overall_hits::total 5949 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 784 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 784 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 784 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 784 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 784 # number of overall misses -system.cpu0.icache.overall_misses::total 784 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40406000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 40406000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 40406000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 40406000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 40406000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 40406000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6733 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6733 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6733 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6733 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6733 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116441 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.116441 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116441 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.116441 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116441 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.116441 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51538.265306 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 51538.265306 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 51538.265306 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51538.265306 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 51538.265306 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 7341 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 7341 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 5951 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5951 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5951 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5951 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5951 # number of overall hits +system.cpu0.icache.overall_hits::total 5951 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 783 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 783 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 783 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 783 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 783 # number of overall misses +system.cpu0.icache.overall_misses::total 783 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 40367500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 40367500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 40367500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 40367500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 40367500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 40367500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6734 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6734 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6734 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6734 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6734 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6734 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116276 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.116276 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116276 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.116276 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116276 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.116276 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51554.916986 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 51554.916986 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 51554.916986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51554.916986 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 51554.916986 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 4 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -775,411 +775,412 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 4 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 176 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 176 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 176 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 176 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 176 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 176 # number of overall MSHR hits +system.cpu0.icache.writebacks::writebacks 315 # number of writebacks +system.cpu0.icache.writebacks::total 315 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 175 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 175 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 175 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 175 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 175 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 175 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 608 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 608 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 608 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 608 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 608 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 608 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31294000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 31294000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31294000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 31294000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31294000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 31294000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090302 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.090302 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.090302 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51470.394737 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51470.394737 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 51470.394737 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 31309500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 31309500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 31309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 31309500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 31309500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 31309500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.090288 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.090288 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.090288 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.090288 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51495.888158 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51495.888158 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 51495.888158 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 53924 # Number of BP lookups -system.cpu1.branchPred.condPredicted 50532 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1274 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 46687 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 45618 # Number of BTB hits +system.cpu1.branchPred.lookups 53782 # Number of BP lookups +system.cpu1.branchPred.condPredicted 50347 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1277 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 46315 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 45397 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 97.710283 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 909 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.017921 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 899 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu1.numCycles 162664 # number of cpu cycles simulated +system.cpu1.numCycles 162898 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 29507 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 300555 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 53924 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46527 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 124688 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2705 # Number of cycles fetch has spent squashing +system.cpu1.fetch.icacheStallCycles 29679 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 299544 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 53782 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46296 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 124703 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2711 # Number of cycles fetch has spent squashing system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 1084 # Number of stall cycles due to pending traps system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 20020 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 156656 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.918567 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.216659 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 20165 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 457 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 156846 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.909797 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.217375 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 52489 33.51% 33.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52328 33.40% 66.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 5864 3.74% 70.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3542 2.26% 72.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 937 0.60% 73.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 35524 22.68% 96.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1237 0.79% 96.98% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 797 0.51% 97.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3938 2.51% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 53057 33.83% 33.83% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52143 33.24% 67.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 5878 3.75% 70.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3526 2.25% 73.07% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 939 0.60% 73.67% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 35272 22.49% 96.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1247 0.80% 96.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 803 0.51% 97.46% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3981 2.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 156656 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.331505 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.847704 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 17844 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 50371 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 84089 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 2990 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1352 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 285365 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 1352 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18555 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 22336 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13775 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 85993 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 14635 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 282118 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 13530 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15 # Number of times rename has blocked due to LQ full +system.cpu1.fetch.rateDist::total 156846 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.330158 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.838844 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 17882 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 51023 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 83554 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3022 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1355 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 284108 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 1355 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 18601 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 22664 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 13899 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 84840 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 15477 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 280728 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 13732 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu1.rename.FullRegisterEvents 6 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 199297 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 544091 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 423098 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 185456 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 13841 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1187 # count of serializing insts renamed +system.cpu1.rename.RenamedOperands 198394 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 541219 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 420944 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 184552 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13842 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1192 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1257 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 19159 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 79883 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 38287 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 37783 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 33197 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 235383 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 5651 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 236419 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 14 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12945 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10680 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 703 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 156656 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.509160 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.379040 # Number of insts issued each cycle +system.cpu1.rename.skidInsts 20109 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 79403 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 38032 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 37516 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 32939 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 234221 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 5649 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 235400 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12841 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 661 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 156846 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.500835 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.378978 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 56139 35.84% 35.84% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 19247 12.29% 48.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 37725 24.08% 72.20% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 37266 23.79% 95.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3381 2.16% 98.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1595 1.02% 99.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 897 0.57% 99.74% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 205 0.13% 99.87% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 201 0.13% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 56627 36.10% 36.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 19405 12.37% 48.48% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 37510 23.92% 72.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 37026 23.61% 96.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3380 2.15% 98.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1607 1.02% 99.18% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 891 0.57% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 204 0.13% 99.88% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 156656 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 156846 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 79 23.65% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 23.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 46 13.77% 37.43% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 79 24.38% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 24.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 36 11.11% 35.49% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 209 64.51% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 115374 48.80% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.80% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 83373 35.26% 84.07% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 37672 15.93% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 114995 48.85% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.85% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 82971 35.25% 84.10% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 37434 15.90% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 236419 # Type of FU issued -system.cpu1.iq.rate 1.453419 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 334 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001413 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 629842 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 254017 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 234890 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 235400 # Type of FU issued +system.cpu1.iq.rate 1.445076 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 324 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001376 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 627977 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 252747 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 233879 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 236753 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 235724 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 33006 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 32768 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2599 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2551 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 38 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1483 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1352 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 6792 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 279653 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 149 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 79883 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 38287 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1135 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 39 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 1355 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 6889 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 278263 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 133 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 79403 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 38032 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1130 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 38 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 444 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1061 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1505 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 235416 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 78826 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1003 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 36 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 442 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1069 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1511 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 234388 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 78381 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1012 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 38619 # number of nop insts executed -system.cpu1.iew.exec_refs 116410 # number of memory reference insts executed -system.cpu1.iew.exec_branches 48027 # Number of branches executed -system.cpu1.iew.exec_stores 37584 # Number of stores executed -system.cpu1.iew.exec_rate 1.447253 # Inst execution rate -system.cpu1.iew.wb_sent 235168 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 234890 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 134020 # num instructions producing a value -system.cpu1.iew.wb_consumers 140635 # num instructions consuming a value +system.cpu1.iew.exec_nop 38393 # number of nop insts executed +system.cpu1.iew.exec_refs 115730 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47858 # Number of branches executed +system.cpu1.iew.exec_stores 37349 # Number of stores executed +system.cpu1.iew.exec_rate 1.438864 # Inst execution rate +system.cpu1.iew.wb_sent 234148 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 233879 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 133368 # num instructions producing a value +system.cpu1.iew.wb_consumers 139978 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.444020 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.952963 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.435739 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.952778 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13740 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 4948 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 154106 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.725163 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.084593 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13605 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4988 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1277 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 154309 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.714761 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.081585 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 60830 39.47% 39.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 44602 28.94% 68.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 5225 3.39% 71.81% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 5769 3.74% 75.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1531 0.99% 76.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 33080 21.47% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 818 0.53% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 941 0.61% 99.15% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1310 0.85% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 61394 39.79% 39.79% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 44430 28.79% 68.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 5247 3.40% 71.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5803 3.76% 75.74% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1533 0.99% 76.73% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 32828 21.27% 98.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 824 0.53% 98.54% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 946 0.61% 99.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1304 0.85% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 154106 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 265858 # Number of instructions committed -system.cpu1.commit.committedOps 265858 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 154309 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 264603 # Number of instructions committed +system.cpu1.commit.committedOps 264603 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 114070 # Number of memory references committed -system.cpu1.commit.loads 77284 # Number of loads committed -system.cpu1.commit.membars 4232 # Number of memory barriers committed -system.cpu1.commit.branches 46981 # Number of branches committed +system.cpu1.commit.refs 113401 # Number of memory references committed +system.cpu1.commit.loads 76852 # Number of loads committed +system.cpu1.commit.membars 4272 # Number of memory barriers committed +system.cpu1.commit.branches 46786 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 183171 # Number of committed integer instructions. +system.cpu1.commit.int_insts 182306 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.op_class_0::No_OpClass 37769 14.21% 14.21% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 109787 41.30% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.50% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 81516 30.66% 86.16% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 36786 13.84% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::No_OpClass 37574 14.20% 14.20% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 109356 41.33% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.53% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 81124 30.66% 86.19% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 36549 13.81% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 265858 # Class of committed instruction -system.cpu1.commit.bw_lim_events 1310 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 431808 # The number of ROB reads -system.cpu1.rob.rob_writes 561746 # The number of ROB writes -system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 6008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 45259 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 223857 # Number of Instructions Simulated -system.cpu1.committedOps 223857 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 0.726642 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.726642 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.376193 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.376193 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 409049 # number of integer regfile reads -system.cpu1.int_regfile_writes 191377 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 264603 # Class of committed instruction +system.cpu1.commit.bw_lim_events 1304 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 430627 # The number of ROB reads +system.cpu1.rob.rob_writes 558953 # The number of ROB writes +system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 6052 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 45271 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 222757 # Number of Instructions Simulated +system.cpu1.committedOps 222757 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 0.731281 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.731281 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.367463 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.367463 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 407061 # number of integer regfile reads +system.cpu1.int_regfile_writes 190501 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 118040 # number of misc regfile reads +system.cpu1.misc_regfile_reads 117378 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 25.752806 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 42910 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 1479.655172 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 25.769381 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 42560 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 1520 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.752806 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050298 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.050298 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 25.769381 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.050331 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.050331 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 330593 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 330593 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 45309 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 45309 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 36557 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 36557 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 15 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 81866 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 81866 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 81866 # number of overall hits -system.cpu1.dcache.overall_hits::total 81866 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 489 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 489 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 159 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 648 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 648 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 648 # number of overall misses -system.cpu1.dcache.overall_misses::total 648 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9556000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9556000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3376000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3376000 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 667000 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 667000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12932000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12932000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12932000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12932000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 45798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 45798 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 36716 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 36716 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 328816 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 328816 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 45076 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 45076 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 36319 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 36319 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 81395 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 81395 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 81395 # number of overall hits +system.cpu1.dcache.overall_hits::total 81395 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 515 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 515 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 160 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 160 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 675 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 675 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 675 # number of overall misses +system.cpu1.dcache.overall_misses::total 675 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 10357000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 10357000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3384000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3384000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 705000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 705000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13741000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13741000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13741000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45591 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45591 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 36479 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 36479 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 82514 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 82514 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 82514 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 82514 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.010677 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.010677 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004331 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.004331 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.785714 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007853 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.007853 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007853 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.007853 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19541.922290 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19541.922290 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21232.704403 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21232.704403 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12127.272727 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 12127.272727 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19956.790123 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19956.790123 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 19956.790123 # average overall miss latency +system.cpu1.dcache.demand_accesses::cpu1.data 82070 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 82070 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 82070 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 82070 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011296 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.011296 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004386 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004386 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.800000 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.008225 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.008225 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.008225 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.008225 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20110.679612 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20110.679612 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21150 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21150 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 12589.285714 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 12589.285714 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20357.037037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20357.037037 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20357.037037 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1188,517 +1189,520 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 325 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 325 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 349 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 349 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 53 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 378 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 378 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 164 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2051500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2051500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1754500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1754500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 612000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 612000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3806000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3806000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3806000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3806000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003581 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002887 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002887 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.785714 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.003272 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003272 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.003272 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12509.146341 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12509.146341 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16551.886792 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16551.886792 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11127.272727 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11127.272727 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14096.296296 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14096.296296 # average overall mshr miss latency +system.cpu1.dcache.demand_mshr_hits::cpu1.data 402 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 402 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 402 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 402 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 273 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 273 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2153500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2153500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1760500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 649000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 649000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3914000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3914000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3914000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3914000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003641 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003641 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002933 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002933 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.800000 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003326 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003326 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003326 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12972.891566 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12972.891566 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16453.271028 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16453.271028 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 11589.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 11589.285714 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14336.996337 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14336.996337 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 383 # number of replacements -system.cpu1.icache.tags.tagsinuse 84.461587 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 19439 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 84.449474 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 19585 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 496 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 39.191532 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.485887 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.461587 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164964 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.164964 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 84.449474 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.164940 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.164940 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 113 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.220703 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 20516 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 20516 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 19439 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19439 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19439 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19439 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19439 # number of overall hits -system.cpu1.icache.overall_hits::total 19439 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 581 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 581 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 581 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 581 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 581 # number of overall misses -system.cpu1.icache.overall_misses::total 581 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14331000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 14331000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 14331000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 14331000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 14331000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 14331000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 20020 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 20020 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 20020 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 20020 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 20020 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 20020 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029021 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.029021 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029021 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.029021 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029021 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.029021 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24666.092943 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 24666.092943 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 24666.092943 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24666.092943 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 24666.092943 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 20661 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 20661 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 19585 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 19585 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 19585 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 19585 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 19585 # number of overall hits +system.cpu1.icache.overall_hits::total 19585 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 580 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 580 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 580 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 580 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 580 # number of overall misses +system.cpu1.icache.overall_misses::total 580 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 14033000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 14033000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 14033000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 14033000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 14033000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 14033000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 20165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 20165 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 20165 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 20165 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 20165 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 20165 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.028763 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.028763 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.028763 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.028763 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.028763 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.028763 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24194.827586 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 24194.827586 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24194.827586 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 24194.827586 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 128 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 64 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 85 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 85 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 85 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu1.icache.writebacks::writebacks 383 # number of writebacks +system.cpu1.icache.writebacks::total 383 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 84 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 84 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 84 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 84 # number of overall MSHR hits system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 496 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 496 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 496 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 496 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 496 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 496 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11831000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 11831000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11831000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 11831000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11831000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 11831000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024775 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.024775 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024775 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.024775 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23852.822581 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23852.822581 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 23852.822581 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 11668000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 11668000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 11668000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 11668000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 11668000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 11668000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024597 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024597 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024597 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024597 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 23524.193548 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 23524.193548 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 23524.193548 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 55489 # Number of BP lookups -system.cpu2.branchPred.condPredicted 52130 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1272 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 48168 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 47221 # Number of BTB hits +system.cpu2.branchPred.lookups 46151 # Number of BP lookups +system.cpu2.branchPred.condPredicted 42669 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1261 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 38744 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 37721 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.033964 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 905 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 97.359591 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 903 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu2.numCycles 162291 # number of cpu cycles simulated +system.cpu2.numCycles 162526 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 28975 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 310103 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 55489 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 48126 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 128617 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 2701 # Number of cycles fetch has spent squashing +system.cpu2.fetch.icacheStallCycles 35053 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 247865 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 46151 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 38624 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 123337 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 2679 # Number of cycles fetch has spent squashing system.cpu2.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 20027 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 452 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 160121 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.936679 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.215928 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 26088 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 160896 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.540529 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.092892 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 52703 32.91% 32.91% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 53972 33.71% 66.62% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 5883 3.67% 70.30% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3530 2.20% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 955 0.60% 73.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 37143 23.20% 96.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1222 0.76% 97.06% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 796 0.50% 97.55% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3917 2.45% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 69454 43.17% 43.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 47444 29.49% 72.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8853 5.50% 78.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3439 2.14% 80.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 969 0.60% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 24720 15.36% 96.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1203 0.75% 97.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 808 0.50% 97.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 4006 2.49% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 160121 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.341911 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.910784 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 17197 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 51483 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 87022 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 3059 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1350 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 295507 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 1350 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 17911 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 22825 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13935 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 88104 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 15986 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 292291 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 14001 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full +system.cpu2.fetch.rateDist::total 160896 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.283961 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.525079 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 17877 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 74268 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 63015 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 4387 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1339 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 232406 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 1339 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 18566 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 36272 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13923 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 64728 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 26058 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 229231 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 23352 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full system.cpu2.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 205997 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 564188 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 438175 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 191932 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 14065 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1173 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1240 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 20395 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 83226 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 39943 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 39492 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 34851 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 243755 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 5682 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 244785 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13094 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10962 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 644 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 160121 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.528750 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.374157 # Number of insts issued each cycle +system.cpu2.rename.RenamedOperands 159189 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 426806 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 335096 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 145681 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 13508 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1198 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1266 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 30557 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 61312 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 27565 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 29913 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 22477 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 187400 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8554 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 191519 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 12551 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10065 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 731 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 160896 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.190328 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.355636 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 56124 35.05% 35.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 19550 12.21% 47.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 39272 24.53% 71.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 38854 24.27% 96.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3402 2.12% 98.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1615 1.01% 99.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 887 0.55% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 212 0.13% 99.87% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 205 0.13% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 73129 45.45% 45.45% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 27885 17.33% 62.78% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 27023 16.80% 79.58% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 26608 16.54% 96.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3367 2.09% 98.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1611 1.00% 99.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 866 0.54% 99.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 196 0.12% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 160121 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 160896 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 80 23.32% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 23.32% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 54 15.74% 39.07% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 209 60.93% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 80 24.02% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 24.02% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 44 13.21% 37.24% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 209 62.76% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 118682 48.48% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.48% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 86809 35.46% 83.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 39294 16.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 96792 50.54% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.54% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 67722 35.36% 85.90% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 27005 14.10% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 244785 # Type of FU issued -system.cpu2.iq.rate 1.508309 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 343 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001401 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 650053 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 262570 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 243225 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 191519 # Type of FU issued +system.cpu2.iq.rate 1.178390 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 333 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001739 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 544280 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 208542 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 190032 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 245128 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 191852 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 34614 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 22329 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2656 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2475 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1565 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1441 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1350 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 6752 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 63 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 289758 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 176 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 83226 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 39943 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1125 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 1339 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 9482 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 226726 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 191 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 61312 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 27565 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1142 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 39 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1057 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1503 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 243760 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 82166 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1025 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 430 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1052 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1482 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 190532 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 60316 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 987 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 40321 # number of nop insts executed -system.cpu2.iew.exec_refs 121366 # number of memory reference insts executed -system.cpu2.iew.exec_branches 49723 # Number of branches executed -system.cpu2.iew.exec_stores 39200 # Number of stores executed -system.cpu2.iew.exec_rate 1.501993 # Inst execution rate -system.cpu2.iew.wb_sent 243514 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 243225 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 138958 # num instructions producing a value -system.cpu2.iew.wb_consumers 145563 # num instructions consuming a value +system.cpu2.iew.exec_nop 30772 # number of nop insts executed +system.cpu2.iew.exec_refs 87235 # number of memory reference insts executed +system.cpu2.iew.exec_branches 40210 # Number of branches executed +system.cpu2.iew.exec_stores 26919 # Number of stores executed +system.cpu2.iew.exec_rate 1.172317 # Inst execution rate +system.cpu2.iew.wb_sent 190296 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 190032 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 104798 # num instructions producing a value +system.cpu2.iew.wb_consumers 111375 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.498697 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.954624 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.169241 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.940947 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 13911 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 5038 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1272 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 157537 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.750713 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 2.089801 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 13298 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7823 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1261 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 158397 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.347140 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.933730 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 60893 38.65% 38.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46269 29.37% 68.02% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 5250 3.33% 71.36% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 5861 3.72% 75.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1535 0.97% 76.05% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 34623 21.98% 98.03% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 855 0.54% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 943 0.60% 99.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1308 0.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 80708 50.95% 50.95% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 36780 23.22% 74.17% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 5258 3.32% 77.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8633 5.45% 82.94% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1531 0.97% 83.91% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 22393 14.14% 98.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 849 0.54% 98.58% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 955 0.60% 99.19% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1290 0.81% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 157537 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 275802 # Number of instructions committed -system.cpu2.commit.committedOps 275802 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 158397 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 213383 # Number of instructions committed +system.cpu2.commit.committedOps 213383 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 118948 # Number of memory references committed -system.cpu2.commit.loads 80570 # Number of loads committed -system.cpu2.commit.membars 4324 # Number of memory barriers committed -system.cpu2.commit.branches 48669 # Number of branches committed +system.cpu2.commit.refs 84961 # Number of memory references committed +system.cpu2.commit.loads 58837 # Number of loads committed +system.cpu2.commit.membars 7109 # Number of memory barriers committed +system.cpu2.commit.branches 39190 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 189737 # Number of committed integer instructions. +system.cpu2.commit.int_insts 146276 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.op_class_0::No_OpClass 39459 14.31% 14.31% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 113071 41.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.30% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 84894 30.78% 86.08% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 38378 13.92% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::No_OpClass 29980 14.05% 14.05% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 91333 42.80% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 56.85% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 65946 30.90% 87.76% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 26124 12.24% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 275802 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1308 # number cycles where commit BW limit reached -system.cpu2.rob.rob_reads 445356 # The number of ROB reads -system.cpu2.rob.rob_writes 582010 # The number of ROB writes -system.cpu2.timesIdled 208 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 2170 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 45631 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 232019 # Number of Instructions Simulated -system.cpu2.committedOps 232019 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 0.699473 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.699473 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.429648 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.429648 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 423842 # number of integer regfile reads -system.cpu2.int_regfile_writes 197927 # number of integer regfile writes +system.cpu2.commit.op_class_0::total 213383 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1290 # number cycles where commit BW limit reached +system.cpu2.rob.rob_reads 383202 # The number of ROB reads +system.cpu2.rob.rob_writes 455861 # The number of ROB writes +system.cpu2.timesIdled 213 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1630 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 45643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 176294 # Number of Instructions Simulated +system.cpu2.committedOps 176294 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 0.921903 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.921903 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.084713 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.084713 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 321409 # number of integer regfile reads +system.cpu2.int_regfile_writes 151400 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 122993 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88848 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 24.276146 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 44407 # Total number of references to valid blocks. -system.cpu2.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1585.964286 # Average number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 23.120660 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 32242 # Total number of references to valid blocks. +system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1111.793103 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.276146 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047414 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.047414 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id +system.cpu2.dcache.tags.occ_blocks::cpu2.data 23.120660 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.045158 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.045158 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu2.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 343879 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 343879 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 47002 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 47002 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 38151 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 38151 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 12 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 85153 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 85153 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 85153 # number of overall hits -system.cpu2.dcache.overall_hits::total 85153 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 527 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 527 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 159 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 159 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 686 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 686 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 686 # number of overall misses -system.cpu2.dcache.overall_misses::total 686 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9963000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 9963000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 4178000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 4178000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 670500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 670500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 14141000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 14141000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 14141000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 14141000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 47529 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 47529 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 38310 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 38310 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu2.dcache.tags.tag_accesses 256599 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 256599 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 37491 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 37491 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 25903 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 25903 # number of WriteReq hits +system.cpu2.dcache.SwapReq_hits::cpu2.data 19 # number of SwapReq hits +system.cpu2.dcache.SwapReq_hits::total 19 # number of SwapReq hits +system.cpu2.dcache.demand_hits::cpu2.data 63394 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 63394 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 63394 # number of overall hits +system.cpu2.dcache.overall_hits::total 63394 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 473 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 473 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 153 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 153 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 49 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 49 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 626 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 626 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 626 # number of overall misses +system.cpu2.dcache.overall_misses::total 626 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 7957500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 7957500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3701500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 3701500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 605000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 605000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 11659000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 11659000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 11659000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 11659000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 37964 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 37964 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 26056 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 26056 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 85839 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 85839 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 85839 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 85839 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.011088 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.011088 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004150 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004150 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.823529 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.823529 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007992 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007992 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007992 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007992 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18905.123340 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 18905.123340 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 26276.729560 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 26276.729560 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 11973.214286 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 11973.214286 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 20613.702624 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20613.702624 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 20613.702624 # average overall miss latency +system.cpu2.dcache.demand_accesses::cpu2.data 64020 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 64020 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 64020 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 64020 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.012459 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.012459 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.005872 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.005872 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.720588 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.720588 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.009778 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.009778 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.009778 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.009778 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16823.467230 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16823.467230 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24192.810458 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 24192.810458 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 12346.938776 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 12346.938776 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 18624.600639 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18624.600639 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 18624.600639 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1707,106 +1711,106 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 367 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 367 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 51 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 51 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 418 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 418 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 418 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 418 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 160 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1620500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1620500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2159500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2159500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 614500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 614500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3780000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3780000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3780000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3780000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003366 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003366 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002819 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002819 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.823529 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.823529 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003122 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003122 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003122 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10128.125000 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10128.125000 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19995.370370 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19995.370370 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 10973.214286 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 10973.214286 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14104.477612 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14104.477612 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 311 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 311 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 50 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 50 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 361 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 361 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 162 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 103 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 103 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 49 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 49 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1647500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1647500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1967500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1967500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 556000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 556000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3615000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3615000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3615000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3615000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004267 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004267 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003953 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003953 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.720588 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.720588 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004139 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004139 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004139 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 10169.753086 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 10169.753086 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 19101.941748 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 19101.941748 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 11346.938776 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 11346.938776 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13641.509434 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13641.509434 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 386 # number of replacements -system.cpu2.icache.tags.tagsinuse 80.953803 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 19454 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 77.580266 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 25515 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 500 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 38.908000 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 51.030000 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 80.953803 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.158113 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.158113 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 77.580266 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.151524 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.151524 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 20527 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 20527 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 19454 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 19454 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 19454 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 19454 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 19454 # number of overall hits -system.cpu2.icache.overall_hits::total 19454 # number of overall hits +system.cpu2.icache.tags.tag_accesses 26588 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 26588 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 25515 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 25515 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 25515 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 25515 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 25515 # number of overall hits +system.cpu2.icache.overall_hits::total 25515 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 573 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 573 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 573 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 573 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 573 # number of overall misses system.cpu2.icache.overall_misses::total 573 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8014500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 8014500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 8014500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 8014500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 8014500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 8014500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 20027 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 20027 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 20027 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 20027 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 20027 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 20027 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.028611 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.028611 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.028611 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.028611 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.028611 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.028611 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13986.910995 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13986.910995 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13986.910995 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13986.910995 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13986.910995 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7955500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7955500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7955500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7955500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7955500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7955500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 26088 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 26088 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 26088 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 26088 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 26088 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 26088 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021964 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.021964 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021964 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.021964 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021964 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.021964 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13883.944154 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13883.944154 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13883.944154 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13883.944154 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13883.944154 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1815,6 +1819,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs 5 system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 386 # number of writebacks +system.cpu2.icache.writebacks::total 386 # number of writebacks system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 73 # number of ReadReq MSHR hits system.cpu2.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits system.cpu2.icache.demand_mshr_hits::cpu2.inst 73 # number of demand (read+write) MSHR hits @@ -1827,397 +1833,397 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 500 system.cpu2.icache.demand_mshr_misses::total 500 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 500 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 500 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6952000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 6952000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6952000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 6952000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6952000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 6952000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024966 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.024966 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024966 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.024966 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13904 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13904 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13904 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 13904 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 6895000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 6895000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 6895000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 6895000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 6895000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 6895000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019166 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.019166 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019166 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.019166 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 13790 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 13790 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 13790 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 13790 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 42820 # Number of BP lookups -system.cpu3.branchPred.condPredicted 39316 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1255 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 35479 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 34386 # Number of BTB hits +system.cpu3.branchPred.lookups 52678 # Number of BP lookups +system.cpu3.branchPred.condPredicted 49211 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1284 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 45275 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 44303 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 96.919304 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 900 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.853120 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 906 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions. -system.cpu3.numCycles 161928 # number of cpu cycles simulated +system.cpu3.numCycles 162161 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 36909 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 226016 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 42820 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 35286 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 121156 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 2665 # Number of cycles fetch has spent squashing +system.cpu3.fetch.icacheStallCycles 30846 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 291154 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 52678 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 45209 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 126827 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2723 # Number of cycles fetch has spent squashing system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1154 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 27941 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 455 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 160564 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.407638 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.031731 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.PendingTrapStallCycles 1166 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 21882 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 451 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 160213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.817293 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.188011 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 74840 46.61% 46.61% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 45030 28.04% 74.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 9823 6.12% 80.77% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3413 2.13% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 964 0.60% 83.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 20524 12.78% 96.28% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1162 0.72% 97.01% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 811 0.51% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3997 2.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 57700 36.01% 36.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 51927 32.41% 68.43% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 6814 4.25% 72.68% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3535 2.21% 74.89% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 932 0.58% 75.47% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 33301 20.79% 96.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1242 0.78% 97.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 787 0.49% 97.52% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3975 2.48% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 160564 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.264439 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.395781 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 17966 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 81801 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 54656 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 4799 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 1332 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 210555 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 1332 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 18639 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 40771 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13962 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 56374 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 29476 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 207391 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 26344 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full +system.cpu3.fetch.rateDist::total 160213 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.324850 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.795463 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 17433 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 58368 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 79576 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 3465 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1361 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 275763 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1361 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 18155 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 26788 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 14101 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 81078 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 18720 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 272367 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 16743 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full system.cpu3.rename.FullRegisterEvents 3 # Number of times there has been no free registers -system.cpu3.rename.RenamedOperands 143048 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 379530 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 299622 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 129648 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 13400 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1181 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1248 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 33973 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 53782 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 23352 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 26620 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 18276 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 168080 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 9470 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 172966 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 9 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12631 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10295 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 757 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 160564 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.077240 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.332251 # Number of insts issued each cycle +system.cpu3.rename.RenamedOperands 191251 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 520897 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 405695 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 177247 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 14004 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1196 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1267 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 23402 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 76309 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 36069 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 36463 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 30962 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 226032 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6585 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 227862 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 13 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13164 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10986 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 709 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 160213 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.422244 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.377526 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 78662 48.99% 48.99% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 30467 18.97% 67.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 22821 14.21% 82.18% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 22372 13.93% 96.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3353 2.09% 98.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1614 1.01% 99.21% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 863 0.54% 99.74% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 215 0.13% 99.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 197 0.12% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 61467 38.37% 38.37% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 22016 13.74% 52.11% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 35438 22.12% 74.23% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 35000 21.85% 96.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3395 2.12% 98.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1603 1.00% 99.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 883 0.55% 99.74% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 211 0.13% 99.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 200 0.12% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 160564 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 160213 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 82 24.55% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.55% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 43 12.87% 37.43% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 209 62.57% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 82 24.12% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 24.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 49 14.41% 38.53% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 209 61.47% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 89169 51.55% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 51.55% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 61014 35.28% 86.83% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 22783 13.17% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 111773 49.05% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.05% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 80677 35.41% 84.46% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 35412 15.54% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 172966 # Type of FU issued -system.cpu3.iq.rate 1.068166 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 334 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001931 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 506839 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 190218 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 171502 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 227862 # Type of FU issued +system.cpu3.iq.rate 1.405159 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 340 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001492 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 616290 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 245818 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 226322 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 173300 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 228202 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 18096 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 30727 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2521 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2667 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu3.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1454 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 1332 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 10558 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 75 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 205014 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 53782 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 23352 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 1361 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 7576 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 269910 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 166 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 76309 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 36069 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1148 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 41 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu3.iew.memOrderViolationEvents 37 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 429 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1047 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1476 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 171988 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 52726 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 978 # Number of squashed instructions skipped in execute +system.cpu3.iew.predictedTakenIncorrect 452 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1067 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1519 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 226838 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 75201 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1024 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 27464 # number of nop insts executed -system.cpu3.iew.exec_refs 75422 # number of memory reference insts executed -system.cpu3.iew.exec_branches 36861 # Number of branches executed -system.cpu3.iew.exec_stores 22696 # Number of stores executed -system.cpu3.iew.exec_rate 1.062126 # Inst execution rate -system.cpu3.iew.wb_sent 171762 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 171502 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 92998 # num instructions producing a value -system.cpu3.iew.wb_consumers 99577 # num instructions consuming a value +system.cpu3.iew.exec_nop 37293 # number of nop insts executed +system.cpu3.iew.exec_refs 110524 # number of memory reference insts executed +system.cpu3.iew.exec_branches 46686 # Number of branches executed +system.cpu3.iew.exec_stores 35323 # Number of stores executed +system.cpu3.iew.exec_rate 1.398844 # Inst execution rate +system.cpu3.iew.wb_sent 226605 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 226322 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 128132 # num instructions producing a value +system.cpu3.iew.wb_consumers 134738 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.059125 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.933931 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.395662 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.950972 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 13412 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 8713 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1255 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 158053 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.211980 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.860135 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 13998 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5876 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1284 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 157615 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.623367 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.050526 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 87086 55.10% 55.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 33413 21.14% 76.24% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 5238 3.31% 79.55% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 9506 6.01% 85.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1538 0.97% 86.54% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 18185 11.51% 98.05% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 832 0.53% 98.57% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 959 0.61% 99.18% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 1296 0.82% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 67043 42.54% 42.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 43238 27.43% 69.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 5262 3.34% 73.31% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6673 4.23% 77.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1534 0.97% 78.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 30788 19.53% 98.05% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 827 0.52% 98.57% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 952 0.60% 99.18% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 1298 0.82% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 158053 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 191557 # Number of instructions committed -system.cpu3.commit.committedOps 191557 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 157615 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 255867 # Number of instructions committed +system.cpu3.commit.committedOps 255867 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 73159 # Number of memory references committed -system.cpu3.commit.loads 51261 # Number of loads committed -system.cpu3.commit.membars 7996 # Number of memory barriers committed -system.cpu3.commit.branches 35851 # Number of branches committed +system.cpu3.commit.refs 108145 # Number of memory references committed +system.cpu3.commit.loads 73642 # Number of loads committed +system.cpu3.commit.membars 5159 # Number of memory barriers committed +system.cpu3.commit.branches 45627 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 131131 # Number of committed integer instructions. +system.cpu3.commit.int_insts 175889 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.op_class_0::No_OpClass 26638 13.91% 13.91% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 83764 43.73% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 57.63% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 59257 30.93% 88.57% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 21898 11.43% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::No_OpClass 36414 14.23% 14.23% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 106149 41.49% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.72% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 78801 30.80% 86.52% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 34503 13.48% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 191557 # Class of committed instruction -system.cpu3.commit.bw_lim_events 1296 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 361140 # The number of ROB reads -system.cpu3.rob.rob_writes 412450 # The number of ROB writes -system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1364 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 45995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 156923 # Number of Instructions Simulated -system.cpu3.committedOps 156923 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.031895 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.031895 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.969091 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.969091 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 285937 # number of integer regfile reads -system.cpu3.int_regfile_writes 135307 # number of integer regfile writes +system.cpu3.commit.op_class_0::total 255867 # Class of committed instruction +system.cpu3.commit.bw_lim_events 1298 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 425596 # The number of ROB reads +system.cpu3.rob.rob_writes 542328 # The number of ROB writes +system.cpu3.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1948 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 46007 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 214294 # Number of Instructions Simulated +system.cpu3.committedOps 214294 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 0.756722 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.756722 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.321489 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.321489 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 391365 # number of integer regfile reads +system.cpu3.int_regfile_writes 183208 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 77019 # number of misc regfile reads +system.cpu3.misc_regfile_reads 112150 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 23.138417 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27896 # Total number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 24.277315 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 40522 # Total number of references to valid blocks. system.cpu3.dcache.tags.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 996.285714 # Average number of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 1447.214286 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 23.138417 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.045192 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.045192 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.277315 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.047417 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.047417 # Average percentage of cache occupancy system.cpu3.dcache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id system.cpu3.dcache.tags.occ_task_id_percent::1024 0.054688 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 226271 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 226271 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 34144 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 34144 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 21673 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 21673 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 19 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 19 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55817 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55817 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55817 # number of overall hits -system.cpu3.dcache.overall_hits::total 55817 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 463 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 463 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 154 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 154 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 617 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 617 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 617 # number of overall misses -system.cpu3.dcache.overall_misses::total 617 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 7346500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 7346500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3280500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3280500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 658000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 658000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 10627000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 10627000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 10627000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 10627000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 34607 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 34607 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 21827 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 21827 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.tags.tag_accesses 316074 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 316074 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 43937 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 43937 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 34273 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 34273 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 78210 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 78210 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 78210 # number of overall hits +system.cpu3.dcache.overall_hits::total 78210 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 514 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 514 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 159 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 159 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 673 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 673 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 673 # number of overall misses +system.cpu3.dcache.overall_misses::total 673 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 9349000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 9349000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3790500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 3790500 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 680500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 680500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 13139500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 13139500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 13139500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 13139500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 44451 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 44451 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 34432 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 34432 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 56434 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 56434 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 56434 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 56434 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.013379 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.013379 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007055 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007055 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.732394 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.732394 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.010933 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.010933 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.010933 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.010933 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15867.170626 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 15867.170626 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21301.948052 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 21301.948052 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 12653.846154 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 12653.846154 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17223.662885 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17223.662885 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17223.662885 # average overall miss latency +system.cpu3.dcache.demand_accesses::cpu3.data 78883 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 78883 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 78883 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 78883 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.011563 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.011563 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004618 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.004618 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008532 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.008532 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008532 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.008532 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 18188.715953 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 18188.715953 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 23839.622642 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 23839.622642 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 11938.596491 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 11938.596491 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19523.774146 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19523.774146 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19523.774146 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2226,106 +2232,106 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 299 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 299 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 347 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 347 # number of ReadReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 52 # number of WriteReq MSHR hits system.cpu3.dcache.WriteReq_mshr_hits::total 52 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 351 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 351 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 351 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 164 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 102 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 102 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 266 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 266 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1762500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1762500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1886000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1886000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 606000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 606000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3648500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3648500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3648500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3648500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004739 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004739 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.004673 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.004673 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.732394 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.732394 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004713 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004713 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004713 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10746.951220 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10746.951220 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 18490.196078 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 18490.196078 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 11653.846154 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 11653.846154 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13716.165414 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 13716.165414 # average overall mshr miss latency +system.cpu3.dcache.demand_mshr_hits::cpu3.data 399 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 399 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 399 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 399 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 167 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 167 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 274 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 274 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 274 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1719000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1719000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2129500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2129500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 623500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 623500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3848500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3848500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3848500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3848500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003757 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003757 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003108 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003108 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.003473 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003473 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.003473 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10293.413174 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10293.413174 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19901.869159 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19901.869159 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 10938.596491 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 10938.596491 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14045.620438 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14045.620438 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 384 # number of replacements -system.cpu3.icache.tags.tagsinuse 77.554391 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 27370 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 81.046367 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 21310 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 498 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 54.959839 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 42.791165 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 77.554391 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.151473 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.151473 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 81.046367 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.158294 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.158294 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 114 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.222656 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 28439 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 28439 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 27370 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 27370 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 27370 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 27370 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 27370 # number of overall hits -system.cpu3.icache.overall_hits::total 27370 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 571 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 571 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 571 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 571 # number of overall misses -system.cpu3.icache.overall_misses::total 571 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7675000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7675000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7675000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7675000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7675000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7675000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 27941 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 27941 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 27941 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 27941 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 27941 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 27941 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020436 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020436 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020436 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020436 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020436 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020436 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13441.330998 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13441.330998 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13441.330998 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13441.330998 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13441.330998 # average overall miss latency +system.cpu3.icache.tags.tag_accesses 22380 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 22380 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 21310 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 21310 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 21310 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 21310 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 21310 # number of overall hits +system.cpu3.icache.overall_hits::total 21310 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 572 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 572 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 572 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 572 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 572 # number of overall misses +system.cpu3.icache.overall_misses::total 572 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 8104500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 8104500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 8104500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 8104500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 8104500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 8104500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 21882 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 21882 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 21882 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 21882 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 21882 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 21882 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026140 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026140 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026140 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026140 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026140 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026140 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14168.706294 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14168.706294 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14168.706294 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14168.706294 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14168.706294 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2334,77 +2340,81 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 73 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 73 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 73 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 73 # number of overall MSHR hits +system.cpu3.icache.writebacks::writebacks 384 # number of writebacks +system.cpu3.icache.writebacks::total 384 # number of writebacks +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 74 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 74 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 74 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 74 # number of overall MSHR hits system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 498 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 498 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 498 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 498 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 498 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 498 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6616000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6616000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6616000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6616000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6616000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6616000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017823 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017823 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017823 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017823 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13285.140562 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13285.140562 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13285.140562 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 6912000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 6912000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6912000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 6912000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022758 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.022758 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022758 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.022758 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13879.518072 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13879.518072 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13879.518072 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 419.148333 # Cycle average of tags in use -system.l2c.tags.total_refs 2348 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 419.218954 # Cycle average of tags in use +system.l2c.tags.total_refs 2347 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 532 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4.413534 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 4.411654 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.788271 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 288.012358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 58.076849 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 62.302913 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 5.322223 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 3.076380 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 0.717940 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.174188 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.677210 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::writebacks 0.788461 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 288.048945 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 58.083381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 60.484959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 5.324168 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2.350458 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 0.677584 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2.742702 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.718294 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.000012 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.inst 0.004395 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.data 0.000886 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000951 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000923 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000081 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000047 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.000003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.000010 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.006396 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000036 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.000042 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.006397 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 532 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.008118 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 25610 # Number of tag accesses -system.l2c.tags.data_accesses 25610 # Number of data accesses -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.tags.tag_accesses 25618 # Number of tag accesses +system.l2c.tags.data_accesses 25618 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 676 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 676 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 246 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu1.inst 409 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 490 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 493 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu1.inst 412 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 491 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 489 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::total 1638 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 5 # number of ReadSharedReq hits @@ -2413,36 +2423,36 @@ system.l2c.ReadSharedReq_hits::cpu3.data 11 # nu system.l2c.ReadSharedReq_hits::total 32 # number of ReadSharedReq hits system.l2c.demand_hits::cpu0.inst 246 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 409 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 412 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 490 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 491 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 493 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 489 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits system.l2c.demand_hits::total 1670 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 246 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 409 # number of overall hits +system.l2c.overall_hits::cpu1.inst 412 # number of overall hits system.l2c.overall_hits::cpu1.data 5 # number of overall hits -system.l2c.overall_hits::cpu2.inst 490 # number of overall hits +system.l2c.overall_hits::cpu2.inst 491 # number of overall hits system.l2c.overall_hits::cpu2.data 11 # number of overall hits -system.l2c.overall_hits::cpu3.inst 493 # number of overall hits +system.l2c.overall_hits::cpu3.inst 489 # number of overall hits system.l2c.overall_hits::cpu3.data 11 # number of overall hits system.l2c.overall_hits::total 1670 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 27 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 21 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 89 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 362 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu1.inst 87 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 10 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 5 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu1.inst 84 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 9 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::total 464 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 75 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 7 # number of ReadSharedReq misses @@ -2451,62 +2461,64 @@ system.l2c.ReadSharedReq_misses::cpu3.data 1 # system.l2c.ReadSharedReq_misses::total 84 # number of ReadSharedReq misses system.l2c.demand_misses::cpu0.inst 362 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 87 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 84 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses system.l2c.demand_misses::total 679 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.inst 362 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses -system.l2c.overall_misses::cpu1.inst 87 # number of overall misses +system.l2c.overall_misses::cpu1.inst 84 # number of overall misses system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 10 # number of overall misses +system.l2c.overall_misses::cpu2.inst 9 # number of overall misses system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 5 # number of overall misses +system.l2c.overall_misses::cpu3.inst 9 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 679 # number of overall misses -system.l2c.ReadExReq_miss_latency::cpu0.data 7619000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 7611000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu1.data 1059000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 1485500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 1133500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 11297000 # number of ReadExReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu0.inst 27679000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu1.inst 6525500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu2.inst 707500 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::cpu3.inst 342000 # number of ReadCleanReq miss cycles -system.l2c.ReadCleanReq_miss_latency::total 35254000 # number of ReadCleanReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0.data 5980500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1.data 540500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2.data 96500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3.data 82500 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 6700000 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 27679000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 13599500 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 660000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 1495500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 53223500 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 676 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 676 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 21 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 90 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 92 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2544,16 +2556,16 @@ system.l2c.UpgradeReq_miss_rate::cpu0.data 0.900000 # system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.966667 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.967391 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.595395 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.175403 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.020000 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010040 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.169355 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.018000 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.018072 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::total 0.220742 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadSharedReq accesses @@ -2562,55 +2574,55 @@ system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_miss_rate::total 0.724138 # miss rate for ReadSharedReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.595395 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.175403 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.169355 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.020000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.018000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.010040 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.018072 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.289059 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.595395 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.175403 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.169355 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.020000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.018000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # 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number of overall MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.900000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.966667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.967391 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_mshr_miss_rate::total 0.214558 # mshr miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadSharedReq accesses @@ -2732,128 +2744,129 @@ system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.083333 system.l2c.ReadSharedReq_mshr_miss_rate::total 0.724138 # mshr miss rate for ReadSharedReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.283525 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.593750 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.167339 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161290 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.004016 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.014056 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.283525 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21722.222222 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21763.157895 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21800 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21809.380952 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21770.080460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 71053.191489 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 21740.740741 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21850 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 21904.571429 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 21785.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 21814.561798 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 70968.085106 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 71461.538462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 113791.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 84458.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 76236.641221 # average ReadExReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 72700 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 73000 # average ReadCleanReq mshr miss latency -system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66278.270510 # average ReadCleanReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69740 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67214.285714 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 86500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 72500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69761.904762 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66164.819945 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70470.414201 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66222.891566 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69975 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 72700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 111692.307692 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 73000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 83538.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 68676.426426 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 90875 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 106583.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 76103.053435 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73000 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 66272.727273 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 69753.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 67142.857143 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 86500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 69767.857143 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 66174.515235 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 70428.994083 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 66068.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69950 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89461.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 70785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 105038.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 68647.147147 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 534 # Transaction distribution -system.membus.trans_dist::UpgradeReq 287 # Transaction distribution -system.membus.trans_dist::UpgradeResp 87 # Transaction distribution +system.membus.trans_dist::UpgradeReq 290 # Transaction distribution +system.membus.trans_dist::UpgradeResp 89 # Transaction distribution system.membus.trans_dist::ReadExReq 162 # Transaction distribution system.membus.trans_dist::ReadExResp 131 # Transaction distribution system.membus.trans_dist::ReadSharedReq 535 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 1736 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1741 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 1741 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 42560 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 42560 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 231 # Total snoops (count) -system.membus.snoop_fanout::samples 984 # Request fanout histogram +system.membus.snoops 232 # Total snoops (count) +system.membus.snoop_fanout::samples 987 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 984 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 987 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 984 # Request fanout histogram -system.membus.reqLayer0.occupancy 923503 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 987 # Request fanout histogram +system.membus.reqLayer0.occupancy 936504 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 3708663 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 3712661 # Layer occupancy (ticks) system.membus.respLayer1.utilization 3.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 4928 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.tot_requests 4933 # Total number of requests made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_requests 1339 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 2358 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 2364 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2773 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 678 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 290 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 290 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 394 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 394 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2778 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 676 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 293 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 293 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 391 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 391 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 2102 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 672 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 677 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1448 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 592 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1141 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 370 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1145 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1146 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 6575 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 38848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 374 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1151 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 360 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1140 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 376 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 6581 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 53760 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 31744 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 41216 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 32000 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 41664 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31872 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 41088 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1536 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 150336 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1019 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 4928 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.293425 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.231126 # Request fanout histogram +system.toL2Bus.pkt_size::total 193600 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1022 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 3463 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.289633 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.182691 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1910 38.76% 38.76% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 975 19.78% 58.54% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 730 14.81% 73.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1313 26.64% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1230 35.52% 35.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 835 24.11% 59.63% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 563 16.26% 75.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 835 24.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -2862,24 +2875,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 4928 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2484958 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 910999 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 3463 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3953462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 3.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 911498 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 505496 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 505495 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 745995 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 746495 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 435966 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 439455 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 752494 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 752991 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 426475 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 419474 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 748497 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 747998 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 424472 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 434475 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index 9e7ba2833..374f2beb4 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87707000 # Number of ticks simulated final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1726221 # Simulator instruction rate (inst/s) -host_op_rate 1726160 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 223510854 # Simulator tick rate (ticks/s) -host_mem_usage 306324 # Number of bytes of host memory used -host_seconds 0.39 # Real time elapsed on the host +host_inst_rate 1763094 # Simulator instruction rate (inst/s) +host_op_rate 1763034 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 228285342 # Simulator tick rate (ticks/s) +host_mem_usage 306164 # Number of bytes of host memory used +host_seconds 0.38 # Real time elapsed on the host sim_insts 677333 # Number of instructions simulated sim_ops 677333 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -232,6 +232,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173297 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -401,6 +403,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 278 # number of writebacks +system.cpu1.icache.writebacks::total 278 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173296 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -571,6 +575,8 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 278 # number of writebacks +system.cpu2.icache.writebacks::total 278 # number of writebacks system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173297 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -740,6 +746,8 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.writebacks::writebacks 279 # number of writebacks +system.cpu3.icache.writebacks::total 279 # number of writebacks system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements system.l2c.tags.tagsinuse 366.582953 # Cycle average of tags in use @@ -772,8 +780,10 @@ system.l2c.tags.age_task_id_blocks_1024::1 373 # system.l2c.tags.occ_task_id_percent::1024 0.006424 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19424 # Number of tag accesses system.l2c.tags.data_accesses 19424 # Number of data accesses -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits @@ -842,8 +852,10 @@ system.l2c.overall_misses::cpu2.data 13 # nu system.l2c.overall_misses::cpu3.inst 1 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.WritebackDirty_accesses::writebacks 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 1 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) @@ -957,8 +969,9 @@ system.toL2Bus.snoop_filter.tot_snoops 0 # To system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.trans_dist::ReadResp 2179 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 275 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 275 # Transaction distribution system.toL2Bus.trans_dist::ReadExReq 412 # Transaction distribution @@ -974,15 +987,15 @@ system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 834 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 624 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count::total 6229 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30720 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 22912 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30208 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 22976 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 30400 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 165888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 197568 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.snoops 0 # Total snoops (count) system.toL2Bus.snoop_fanout::samples 3918 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1.246554 # Request fanout histogram diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index f34aec4c9..73bc4c073 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,199 +1,199 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000261 # Number of seconds simulated -sim_ticks 260712500 # Number of ticks simulated -final_tick 260712500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000265 # Number of seconds simulated +sim_ticks 264840500 # Number of ticks simulated +final_tick 264840500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1018019 # Simulator instruction rate (inst/s) -host_op_rate 1017997 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 401917302 # Simulator tick rate (ticks/s) -host_mem_usage 306320 # Number of bytes of host memory used +host_inst_rate 1022675 # Simulator instruction rate (inst/s) +host_op_rate 1022653 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 408888728 # Simulator tick rate (ticks/s) +host_mem_usage 306160 # Number of bytes of host memory used host_seconds 0.65 # Real time elapsed on the host -sim_insts 660333 # Number of instructions simulated -sim_ops 660333 # Number of ops (including micro ops) simulated +sim_insts 662366 # Number of instructions simulated +sim_ops 662366 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 3456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 3456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 54 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 22 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69962123 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40504387 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 3436736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3927698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 13255981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 5400585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 245481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3682217 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 140415208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69962123 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 3436736 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 13255981 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 245481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86900321 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69962123 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40504387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 3436736 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3927698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 13255981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 5400585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 245481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3682217 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 140415208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 68871642 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 39873056 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 1691584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 3624823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 14015983 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 5558062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 966620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3624823 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 138226593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 68871642 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 1691584 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 14015983 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 966620 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 85545829 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 68871642 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 39873056 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1691584 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3624823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 14015983 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 5558062 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 966620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3624823 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 138226593 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 521425 # number of cpu cycles simulated +system.cpu0.numCycles 529681 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 157788 # Number of instructions committed -system.cpu0.committedOps 157788 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108684 # Number of integer alu accesses +system.cpu0.committedInsts 158238 # Number of instructions committed +system.cpu0.committedOps 158238 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 108984 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25901 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108684 # number of integer instructions +system.cpu0.num_conditional_control_insts 25976 # number of instructions that are conditional controls +system.cpu0.num_int_insts 108984 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 314210 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110290 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315110 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110590 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73628 # number of memory refs -system.cpu0.num_load_insts 48745 # Number of load instructions -system.cpu0.num_store_insts 24883 # Number of store instructions +system.cpu0.num_mem_refs 73853 # number of memory refs +system.cpu0.num_load_insts 48895 # Number of load instructions +system.cpu0.num_store_insts 24958 # Number of store instructions system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu0.num_busy_cycles 521424.998000 # Number of busy cycles +system.cpu0.num_busy_cycles 529680.998000 # Number of busy cycles system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu0.Branches 26766 # Number of branches fetched -system.cpu0.op_class::No_OpClass 23493 14.88% 14.88% # Class of executed instruction -system.cpu0.op_class::IntAlu 60645 38.42% 53.30% # Class of executed instruction -system.cpu0.op_class::IntMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.30% # Class of executed instruction -system.cpu0.op_class::MemRead 48829 30.93% 84.24% # Class of executed instruction -system.cpu0.op_class::MemWrite 24883 15.76% 100.00% # Class of executed instruction +system.cpu0.Branches 26841 # Number of branches fetched +system.cpu0.op_class::No_OpClass 23568 14.89% 14.89% # Class of executed instruction +system.cpu0.op_class::IntAlu 60795 38.40% 53.29% # Class of executed instruction +system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction +system.cpu0.op_class::MemRead 48979 30.94% 84.23% # Class of executed instruction +system.cpu0.op_class::MemWrite 24958 15.77% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 157850 # Class of executed instruction +system.cpu0.op_class::total 158300 # Class of executed instruction system.cpu0.dcache.tags.replacements 2 # number of replacements -system.cpu0.dcache.tags.tagsinuse 145.664312 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 73097 # Total number of references to valid blocks. +system.cpu0.dcache.tags.tagsinuse 145.090849 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 73323 # Total number of references to valid blocks. system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 437.706587 # Average number of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 439.059880 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.664312 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.284501 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.284501 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 145.090849 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283381 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.283381 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 294744 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 294744 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 48566 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48566 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24649 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24649 # number of WriteReq hits +system.cpu0.dcache.tags.tag_accesses 295643 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 295643 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24724 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24724 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73215 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73215 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73215 # number of overall hits -system.cpu0.dcache.overall_hits::total 73215 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 169 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 169 # number of ReadReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73441 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73441 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73441 # number of overall hits +system.cpu0.dcache.overall_hits::total 73441 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 168 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 168 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 352 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 352 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 352 # number of overall misses -system.cpu0.dcache.overall_misses::total 352 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4596500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4596500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7006000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7006000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 359000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 359000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11602500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11602500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11602500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11602500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48735 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48735 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24832 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24832 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 351 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 351 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 351 # number of overall misses +system.cpu0.dcache.overall_misses::total 351 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5149000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5149000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7867000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 395000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 395000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 13016000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 13016000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 13016000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 13016000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48885 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48885 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24907 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24907 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73567 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73567 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73567 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73567 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003468 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003468 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007370 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007370 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73792 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73792 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73792 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73792 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003437 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003437 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004785 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004785 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004785 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004785 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27198.224852 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 27198.224852 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38284.153005 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38284.153005 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13807.692308 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 32961.647727 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 32961.647727 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 32961.647727 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004757 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004757 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004757 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004757 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 30648.809524 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 30648.809524 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 42989.071038 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15192.307692 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 15192.307692 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 37082.621083 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37082.621083 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 37082.621083 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -204,98 +204,98 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 169 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 168 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 168 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 352 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 352 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 352 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4427500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6823000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6823000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 333000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11250500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11250500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11250500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11250500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003468 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003468 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007370 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007370 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 351 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4981000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4981000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 369000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 369000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12665000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12665000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12665000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003437 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003437 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007347 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007347 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004785 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004785 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004785 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26198.224852 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26198.224852 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37284.153005 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37284.153005 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12807.692308 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31961.647727 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31961.647727 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004757 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004757 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004757 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29648.809524 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29648.809524 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 41989.071038 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14192.307692 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14192.307692 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 36082.621083 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 36082.621083 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 215 # number of replacements -system.cpu0.icache.tags.tagsinuse 212.605336 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 157384 # Total number of references to valid blocks. +system.cpu0.icache.tags.tagsinuse 211.456411 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 157834 # Total number of references to valid blocks. system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 337.010707 # Average number of references to valid blocks. +system.cpu0.icache.tags.avg_refs 337.974304 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 212.605336 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.415245 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.415245 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 211.456411 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.413001 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.413001 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 252 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 158318 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 158318 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 157384 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157384 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157384 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157384 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157384 # number of overall hits -system.cpu0.icache.overall_hits::total 157384 # number of overall hits +system.cpu0.icache.tags.tag_accesses 158768 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 158768 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 157834 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 157834 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 157834 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 157834 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 157834 # number of overall hits +system.cpu0.icache.overall_hits::total 157834 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18137000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18137000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18137000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18137000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18137000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18137000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 157851 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 157851 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 157851 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 157851 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 157851 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 157851 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002958 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002958 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002958 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002958 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002958 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002958 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38837.259101 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38837.259101 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38837.259101 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38837.259101 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38837.259101 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20139500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20139500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20139500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20139500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20139500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20139500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158301 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158301 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158301 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158301 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158301 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43125.267666 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 43125.267666 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 43125.267666 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43125.267666 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 43125.267666 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -304,164 +304,166 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.writebacks::writebacks 215 # number of writebacks +system.cpu0.icache.writebacks::total 215 # number of writebacks system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17670000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17670000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17670000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17670000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17670000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17670000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002958 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002958 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002958 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002958 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 37837.259101 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 37837.259101 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 37837.259101 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19672500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19672500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19672500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19672500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19672500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19672500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 42125.267666 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42125.267666 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 42125.267666 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 521425 # number of cpu cycles simulated +system.cpu1.numCycles 529680 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 168182 # Number of instructions committed -system.cpu1.committedOps 168182 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 110851 # Number of integer alu accesses +system.cpu1.committedInsts 168829 # Number of instructions committed +system.cpu1.committedOps 168829 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 111193 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32674 # number of instructions that are conditional controls -system.cpu1.num_int_insts 110851 # number of integer instructions +system.cpu1.num_conditional_control_insts 32827 # number of instructions that are conditional controls +system.cpu1.num_int_insts 111193 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 274889 # number of times the integer registers were read -system.cpu1.num_int_register_writes 104194 # number of times the integer registers were written +system.cpu1.num_int_register_reads 275699 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104505 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 54346 # number of memory refs -system.cpu1.num_load_insts 41092 # Number of load instructions -system.cpu1.num_store_insts 13254 # Number of store instructions -system.cpu1.num_idle_cycles 67743.001740 # Number of idle cycles -system.cpu1.num_busy_cycles 453681.998260 # Number of busy cycles -system.cpu1.not_idle_fraction 0.870081 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.129919 # Percentage of idle cycles -system.cpu1.Branches 34327 # Number of branches fetched -system.cpu1.op_class::No_OpClass 25108 14.93% 14.93% # Class of executed instruction -system.cpu1.op_class::IntAlu 74636 44.37% 59.30% # Class of executed instruction -system.cpu1.op_class::IntMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.30% # Class of executed instruction -system.cpu1.op_class::MemRead 55216 32.82% 92.12% # Class of executed instruction -system.cpu1.op_class::MemWrite 13254 7.88% 100.00% # Class of executed instruction +system.cpu1.num_mem_refs 54535 # number of memory refs +system.cpu1.num_load_insts 41264 # Number of load instructions +system.cpu1.num_store_insts 13271 # Number of store instructions +system.cpu1.num_idle_cycles 73879.862241 # Number of idle cycles +system.cpu1.num_busy_cycles 455800.137759 # Number of busy cycles +system.cpu1.not_idle_fraction 0.860520 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.139480 # Percentage of idle cycles +system.cpu1.Branches 34479 # Number of branches fetched +system.cpu1.op_class::No_OpClass 25261 14.96% 14.96% # Class of executed instruction +system.cpu1.op_class::IntAlu 74858 44.33% 59.29% # Class of executed instruction +system.cpu1.op_class::IntMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.29% # Class of executed instruction +system.cpu1.op_class::MemRead 55471 32.85% 92.14% # Class of executed instruction +system.cpu1.op_class::MemWrite 13271 7.86% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 168214 # Class of executed instruction +system.cpu1.op_class::total 168861 # Class of executed instruction system.cpu1.dcache.tags.replacements 0 # number of replacements -system.cpu1.dcache.tags.tagsinuse 26.819046 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 28734 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 990.827586 # Average number of references to valid blocks. +system.cpu1.dcache.tags.tagsinuse 26.495164 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 28944 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 964.800000 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.819046 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052381 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.052381 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.495164 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051748 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.051748 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 217604 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 217604 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 40921 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40921 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 13075 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 13075 # number of WriteReq hits +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 218364 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 218364 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 41094 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 41094 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 13094 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 13094 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53996 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53996 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53996 # number of overall hits -system.cpu1.dcache.overall_hits::total 53996 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 54188 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 54188 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 54188 # number of overall hits +system.cpu1.dcache.overall_hits::total 54188 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 163 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 163 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 56 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 271 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 271 # number of overall misses -system.cpu1.dcache.overall_misses::total 271 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2627500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2627500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1987500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1987500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 248500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 248500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 4615000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 4615000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 4615000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 4615000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 41084 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 41084 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 13183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 13183 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 54267 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 54267 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 54267 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 54267 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003967 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.003967 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008192 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008192 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004994 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.004994 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004994 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.004994 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16119.631902 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16119.631902 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18402.777778 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 18402.777778 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4437.500000 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 4437.500000 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 17029.520295 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17029.520295 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17029.520295 # average overall miss latency +system.cpu1.dcache.WriteReq_misses::cpu1.data 107 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 107 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 270 # 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number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003951 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003951 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008105 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.008105 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.808824 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.808824 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004958 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004958 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004958 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004958 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17914.110429 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17914.110429 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20088.785047 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20088.785047 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 4463.636364 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 4463.636364 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18775.925926 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18775.925926 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18775.925926 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -472,97 +474,97 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 56 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 271 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 271 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2464500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2464500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1879500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1879500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 192500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 192500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4344000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4344000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344000 # 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average overall mshr miss latency +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 270 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2757000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2757000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2042500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2042500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 190500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 190500 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4799500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4799500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4799500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4799500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003951 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.008105 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.008105 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.808824 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.808824 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004958 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004958 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004958 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16914.110429 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16914.110429 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19088.785047 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19088.785047 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3463.636364 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3463.636364 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17775.925926 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17775.925926 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 280 # number of replacements -system.cpu1.icache.tags.tagsinuse 67.790334 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 167849 # Total number of references to valid blocks. +system.cpu1.icache.tags.tagsinuse 67.000483 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 168496 # Total number of references to valid blocks. system.cpu1.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 458.603825 # Average number of references to valid blocks. +system.cpu1.icache.tags.avg_refs 460.371585 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.790334 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.132403 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.132403 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_blocks::cpu1.inst 67.000483 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.130860 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.130860 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 168581 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 168581 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 167849 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167849 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167849 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167849 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167849 # number of overall hits -system.cpu1.icache.overall_hits::total 167849 # number of overall hits +system.cpu1.icache.tags.tag_accesses 169228 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 169228 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 168496 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 168496 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 168496 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 168496 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 168496 # number of overall hits +system.cpu1.icache.overall_hits::total 168496 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5586500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5586500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5586500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5586500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5586500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5586500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 168215 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 168215 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 168215 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 168215 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 168215 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 168215 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002176 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002176 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002176 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002176 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002176 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002176 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15263.661202 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15263.661202 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15263.661202 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15263.661202 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15263.661202 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5681500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5681500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5681500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5681500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5681500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5681500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 168862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 168862 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 168862 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 168862 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 168862 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 168862 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002167 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002167 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002167 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002167 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002167 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002167 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15523.224044 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 15523.224044 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 15523.224044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15523.224044 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 15523.224044 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -571,164 +573,166 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.writebacks::writebacks 280 # number of writebacks +system.cpu1.icache.writebacks::total 280 # number of writebacks system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 366 # number of ReadReq MSHR misses system.cpu1.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 # number of demand (read+write) MSHR misses system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5220500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5220500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5220500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5220500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5220500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5220500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002176 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002176 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002176 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002176 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14263.661202 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14263.661202 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 14263.661202 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5315500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5315500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5315500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5315500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002167 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002167 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002167 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002167 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 14523.224044 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14523.224044 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 14523.224044 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 521424 # number of cpu cycles simulated +system.cpu2.numCycles 529681 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165155 # Number of instructions committed -system.cpu2.committedOps 165155 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 110249 # Number of integer alu accesses +system.cpu2.committedInsts 165415 # Number of instructions committed +system.cpu2.committedOps 165415 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110386 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31462 # number of instructions that are conditional controls -system.cpu2.num_int_insts 110249 # number of integer instructions +system.cpu2.num_conditional_control_insts 31522 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110386 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 277329 # number of times the integer registers were read -system.cpu2.num_int_register_writes 105715 # number of times the integer registers were written +system.cpu2.num_int_register_reads 277687 # number of times the integer registers were read +system.cpu2.num_int_register_writes 105904 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 54956 # number of memory refs -system.cpu2.num_load_insts 40791 # Number of load instructions -system.cpu2.num_store_insts 14165 # Number of store instructions -system.cpu2.num_idle_cycles 67997.871331 # Number of idle cycles -system.cpu2.num_busy_cycles 453426.128669 # Number of busy cycles -system.cpu2.not_idle_fraction 0.869592 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.130408 # Percentage of idle cycles -system.cpu2.Branches 33115 # Number of branches fetched -system.cpu2.op_class::No_OpClass 23895 14.47% 14.47% # Class of executed instruction -system.cpu2.op_class::IntAlu 74335 45.00% 59.47% # Class of executed instruction -system.cpu2.op_class::IntMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::IntDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::FloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAddAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShift 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMult 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.47% # Class of executed instruction -system.cpu2.op_class::MemRead 52792 31.96% 91.42% # Class of executed instruction -system.cpu2.op_class::MemWrite 14165 8.58% 100.00% # Class of executed instruction +system.cpu2.num_mem_refs 55033 # number of memory refs +system.cpu2.num_load_insts 40858 # Number of load instructions +system.cpu2.num_store_insts 14175 # Number of store instructions +system.cpu2.num_idle_cycles 74150.001720 # Number of idle cycles +system.cpu2.num_busy_cycles 455530.998280 # Number of busy cycles +system.cpu2.not_idle_fraction 0.860010 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.139990 # Percentage of idle cycles +system.cpu2.Branches 33177 # Number of branches fetched +system.cpu2.op_class::No_OpClass 23956 14.48% 14.48% # Class of executed instruction +system.cpu2.op_class::IntAlu 74457 45.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::IntDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::FloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAddAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShift 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdShiftAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAdd 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatAlu 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCmp 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatCvt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatDiv 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMisc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMult 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.48% # Class of executed instruction +system.cpu2.op_class::MemRead 52859 31.95% 91.43% # Class of executed instruction +system.cpu2.op_class::MemWrite 14175 8.57% 100.00% # Class of executed instruction system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu2.op_class::total 165187 # Class of executed instruction +system.cpu2.op_class::total 165447 # Class of executed instruction system.cpu2.dcache.tags.replacements 0 # number of replacements -system.cpu2.dcache.tags.tagsinuse 27.775093 # Cycle average of tags in use -system.cpu2.dcache.tags.total_refs 30556 # Total number of references to valid blocks. +system.cpu2.dcache.tags.tagsinuse 27.486829 # Cycle average of tags in use +system.cpu2.dcache.tags.total_refs 30625 # Total number of references to valid blocks. system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.tags.avg_refs 1053.655172 # Average number of references to valid blocks. +system.cpu2.dcache.tags.avg_refs 1056.034483 # Average number of references to valid blocks. system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.775093 # Average occupied blocks per requestor -system.cpu2.dcache.tags.occ_percent::cpu2.data 0.054248 # Average percentage of cache occupancy -system.cpu2.dcache.tags.occ_percent::total 0.054248 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.486829 # Average occupied blocks per requestor +system.cpu2.dcache.tags.occ_percent::cpu2.data 0.053685 # Average percentage of cache occupancy +system.cpu2.dcache.tags.occ_percent::total 0.053685 # Average percentage of cache occupancy system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id -system.cpu2.dcache.tags.tag_accesses 220041 # Number of tag accesses -system.cpu2.dcache.tags.data_accesses 220041 # Number of data accesses -system.cpu2.dcache.ReadReq_hits::cpu2.data 40622 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 40622 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 13986 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 13986 # number of WriteReq hits +system.cpu2.dcache.tags.tag_accesses 220352 # Number of tag accesses +system.cpu2.dcache.tags.data_accesses 220352 # Number of data accesses +system.cpu2.dcache.ReadReq_hits::cpu2.data 40687 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 40687 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 13994 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 13994 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 54608 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 54608 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 54608 # number of overall hits -system.cpu2.dcache.overall_hits::total 54608 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 161 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 161 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 54681 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 54681 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 54681 # number of overall hits +system.cpu2.dcache.overall_hits::total 54681 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 163 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 163 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 108 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 108 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 56 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 56 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses -system.cpu2.dcache.overall_misses::total 269 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2814500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2814500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2046000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2046000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 249500 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 249500 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4860500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4860500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4860500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4860500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 40783 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 40783 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 14094 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 14094 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 69 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 54877 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 54877 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 54877 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 54877 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003948 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003948 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007663 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.007663 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.811594 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004902 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004902 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004902 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004902 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 17481.366460 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 17481.366460 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18944.444444 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 18944.444444 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4455.357143 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 4455.357143 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 18068.773234 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 18068.773234 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 18068.773234 # average overall miss latency +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses +system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3093500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 3093500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2328000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2328000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 260500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 260500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 5421500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 5421500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 5421500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 5421500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 40850 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 40850 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 14102 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 14102 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 54952 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 54952 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 54952 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 54952 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003990 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003990 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.007658 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.007658 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004932 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004932 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004932 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004932 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 18978.527607 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 18978.527607 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21555.555556 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 21555.555556 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 4491.379310 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 4491.379310 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 20005.535055 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 20005.535055 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 20005.535055 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -737,99 +741,99 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 163 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 108 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 56 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 56 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 269 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 269 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2653500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2653500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1938000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1938000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 193500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 193500 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 4591500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 4591500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 4591500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 4591500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003948 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003948 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007663 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007663 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.811594 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004902 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004902 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004902 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 16481.366460 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 16481.366460 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 17944.444444 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 17944.444444 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3455.357143 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3455.357143 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 17068.773234 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 17068.773234 # average overall mshr miss latency +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2930500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2930500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 2220000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 2220000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 202500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 202500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 5150500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 5150500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 5150500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 5150500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003990 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003990 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.007658 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.007658 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.816901 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004932 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004932 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004932 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 17978.527607 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 17978.527607 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20555.555556 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 20555.555556 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3491.379310 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19005.535055 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 19005.535055 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.icache.tags.replacements 280 # number of replacements -system.cpu2.icache.tags.tagsinuse 70.166597 # Cycle average of tags in use -system.cpu2.icache.tags.total_refs 164822 # Total number of references to valid blocks. +system.cpu2.icache.tags.tagsinuse 69.407713 # Cycle average of tags in use +system.cpu2.icache.tags.total_refs 165082 # Total number of references to valid blocks. system.cpu2.icache.tags.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.tags.avg_refs 450.333333 # Average number of references to valid blocks. +system.cpu2.icache.tags.avg_refs 451.043716 # Average number of references to valid blocks. system.cpu2.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.tags.occ_blocks::cpu2.inst 70.166597 # Average occupied blocks per requestor -system.cpu2.icache.tags.occ_percent::cpu2.inst 0.137044 # Average percentage of cache occupancy -system.cpu2.icache.tags.occ_percent::total 0.137044 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_blocks::cpu2.inst 69.407713 # Average occupied blocks per requestor +system.cpu2.icache.tags.occ_percent::cpu2.inst 0.135562 # Average percentage of cache occupancy +system.cpu2.icache.tags.occ_percent::total 0.135562 # Average percentage of cache occupancy system.cpu2.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu2.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu2.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu2.icache.tags.tag_accesses 165554 # Number of tag accesses -system.cpu2.icache.tags.data_accesses 165554 # Number of data accesses -system.cpu2.icache.ReadReq_hits::cpu2.inst 164822 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 164822 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 164822 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 164822 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 164822 # number of overall hits -system.cpu2.icache.overall_hits::total 164822 # number of overall hits +system.cpu2.icache.tags.tag_accesses 165814 # Number of tag accesses +system.cpu2.icache.tags.data_accesses 165814 # Number of data accesses +system.cpu2.icache.ReadReq_hits::cpu2.inst 165082 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165082 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165082 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165082 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165082 # number of overall hits +system.cpu2.icache.overall_hits::total 165082 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses system.cpu2.icache.overall_misses::total 366 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7626500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 7626500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 7626500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 7626500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 7626500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 7626500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165188 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165188 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165188 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165188 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165188 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165188 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002216 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002216 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002216 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002216 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002216 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002216 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 20837.431694 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 20837.431694 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 20837.431694 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 20837.431694 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 20837.431694 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 8101000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 8101000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 8101000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 8101000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 8101000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 8101000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165448 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165448 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165448 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165448 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165448 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165448 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002212 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002212 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002212 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002212 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002212 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002212 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 22133.879781 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 22133.879781 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 22133.879781 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 22133.879781 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 22133.879781 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -838,164 +842,166 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs nan system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.writebacks::writebacks 280 # number of writebacks +system.cpu2.icache.writebacks::total 280 # number of writebacks system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 366 # number of ReadReq MSHR misses system.cpu2.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses system.cpu2.icache.demand_mshr_misses::cpu2.inst 366 # number of demand (read+write) MSHR misses system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7260500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 7260500 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7260500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 7260500 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7260500 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 7260500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002216 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002216 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002216 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002216 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19837.431694 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19837.431694 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19837.431694 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 7735000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 7735000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 7735000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 7735000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 7735000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 7735000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002212 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002212 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002212 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002212 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 21133.879781 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21133.879781 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 21133.879781 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 521424 # number of cpu cycles simulated +system.cpu3.numCycles 529680 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 169208 # Number of instructions committed -system.cpu3.committedOps 169208 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 110441 # Number of integer alu accesses +system.cpu3.committedInsts 169884 # Number of instructions committed +system.cpu3.committedOps 169884 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 110793 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33391 # number of instructions that are conditional controls -system.cpu3.num_int_insts 110441 # number of integer instructions +system.cpu3.num_conditional_control_insts 33553 # number of instructions that are conditional controls +system.cpu3.num_int_insts 110793 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 270379 # number of times the integer registers were read -system.cpu3.num_int_register_writes 102142 # number of times the integer registers were written +system.cpu3.num_int_register_reads 271193 # number of times the integer registers were read +system.cpu3.num_int_register_writes 102450 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 53219 # number of memory refs -system.cpu3.num_load_insts 40883 # Number of load instructions -system.cpu3.num_store_insts 12336 # Number of store instructions -system.cpu3.num_idle_cycles 68253.870839 # Number of idle cycles -system.cpu3.num_busy_cycles 453170.129161 # Number of busy cycles -system.cpu3.not_idle_fraction 0.869101 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.130899 # Percentage of idle cycles -system.cpu3.Branches 35047 # Number of branches fetched -system.cpu3.op_class::No_OpClass 25824 15.26% 15.26% # Class of executed instruction -system.cpu3.op_class::IntAlu 74433 43.98% 59.24% # Class of executed instruction -system.cpu3.op_class::IntMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::IntDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::FloatSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAddAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdAlu 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMisc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdMultAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdShift 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMult 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.24% # Class of executed instruction -system.cpu3.op_class::MemRead 56647 33.47% 92.71% # Class of executed instruction -system.cpu3.op_class::MemWrite 12336 7.29% 100.00% # Class of executed instruction +system.cpu3.num_mem_refs 53409 # number of memory refs +system.cpu3.num_load_insts 41060 # Number of load instructions +system.cpu3.num_store_insts 12349 # Number of store instructions +system.cpu3.num_idle_cycles 74420.861217 # Number of idle cycles +system.cpu3.num_busy_cycles 455259.138783 # Number of busy cycles +system.cpu3.not_idle_fraction 0.859498 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.140502 # Percentage of idle cycles +system.cpu3.Branches 35208 # Number of branches fetched +system.cpu3.op_class::No_OpClass 25987 15.29% 15.29% # Class of executed instruction +system.cpu3.op_class::IntAlu 74660 43.94% 59.23% # Class of executed instruction +system.cpu3.op_class::IntMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::IntDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdShift 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatMultAcc 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction +system.cpu3.op_class::MemRead 56920 33.50% 92.73% # Class of executed instruction +system.cpu3.op_class::MemWrite 12349 7.27% 100.00% # Class of executed instruction system.cpu3.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu3.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu3.op_class::total 169240 # Class of executed instruction +system.cpu3.op_class::total 169916 # Class of executed instruction system.cpu3.dcache.tags.replacements 0 # number of replacements -system.cpu3.dcache.tags.tagsinuse 25.991280 # Cycle average of tags in use -system.cpu3.dcache.tags.total_refs 27009 # Total number of references to valid blocks. -system.cpu3.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.tags.avg_refs 900.300000 # Average number of references to valid blocks. +system.cpu3.dcache.tags.tagsinuse 25.679518 # Cycle average of tags in use +system.cpu3.dcache.tags.total_refs 26969 # Total number of references to valid blocks. +system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu3.dcache.tags.avg_refs 929.965517 # Average number of references to valid blocks. system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.991280 # Average occupied blocks per requestor -system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050764 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_percent::total 0.050764 # Average percentage of cache occupancy -system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id -system.cpu3.dcache.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id +system.cpu3.dcache.tags.occ_blocks::cpu3.data 25.679518 # Average occupied blocks per requestor +system.cpu3.dcache.tags.occ_percent::cpu3.data 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_percent::total 0.050155 # Average percentage of cache occupancy +system.cpu3.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id +system.cpu3.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id system.cpu3.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id -system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id -system.cpu3.dcache.tags.tag_accesses 213096 # Number of tag accesses -system.cpu3.dcache.tags.data_accesses 213096 # Number of data accesses -system.cpu3.dcache.ReadReq_hits::cpu3.data 40712 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 40712 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 12155 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 12155 # number of WriteReq hits +system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id +system.cpu3.dcache.tags.tag_accesses 213856 # Number of tag accesses +system.cpu3.dcache.tags.data_accesses 213856 # Number of data accesses +system.cpu3.dcache.ReadReq_hits::cpu3.data 40892 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 40892 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 12169 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 12169 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 52867 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 52867 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 52867 # number of overall hits -system.cpu3.dcache.overall_hits::total 52867 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 53061 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 53061 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 53061 # number of overall hits +system.cpu3.dcache.overall_hits::total 53061 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 161 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 161 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 107 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 107 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 270 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 270 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 270 # number of overall misses -system.cpu3.dcache.overall_misses::total 270 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2676500 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2676500 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1989500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 1989500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 259000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 259000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4666000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4666000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4666000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 40875 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 40875 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 12262 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 12262 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 53137 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 53137 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 53137 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 53137 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003988 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003988 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008726 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.008726 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005081 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005081 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005081 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005081 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16420.245399 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16420.245399 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18593.457944 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 18593.457944 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4465.517241 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 4465.517241 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17281.481481 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17281.481481 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17281.481481 # average overall miss latency +system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 268 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 268 # number of overall misses +system.cpu3.dcache.overall_misses::total 268 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2856500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2856500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2210000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2210000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 258500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 258500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 5066500 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 5066500 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 5066500 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 5066500 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41053 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41053 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 12276 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 12276 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 53329 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 53329 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 53329 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 53329 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003922 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003922 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.008716 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.008716 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005025 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005025 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005025 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005025 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 17742.236025 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 17742.236025 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20654.205607 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20654.205607 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4535.087719 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 4535.087719 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18904.850746 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18904.850746 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18904.850746 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1004,99 +1010,99 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 161 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 107 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 270 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 270 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 270 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2513500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2513500 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1882500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1882500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4396000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4396000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4396000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4396000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003988 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003988 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008726 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005081 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005081 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005081 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15420.245399 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 15420.245399 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 17593.457944 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 17593.457944 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3465.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3465.517241 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 16281.481481 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 16281.481481 # average overall mshr miss latency +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2695500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2695500 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 2103000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 2103000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 201500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 201500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4798500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 4798500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4798500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 4798500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003922 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003922 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008716 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008716 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005025 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005025 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005025 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 16742.236025 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 16742.236025 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 19654.205607 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 19654.205607 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3535.087719 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3535.087719 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17904.850746 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17904.850746 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.icache.tags.replacements 281 # number of replacements -system.cpu3.icache.tags.tagsinuse 65.768661 # Cycle average of tags in use -system.cpu3.icache.tags.total_refs 168874 # Total number of references to valid blocks. +system.cpu3.icache.tags.tagsinuse 64.991831 # Cycle average of tags in use +system.cpu3.icache.tags.total_refs 169550 # Total number of references to valid blocks. system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.tags.avg_refs 460.147139 # Average number of references to valid blocks. +system.cpu3.icache.tags.avg_refs 461.989101 # Average number of references to valid blocks. system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.tags.occ_blocks::cpu3.inst 65.768661 # Average occupied blocks per requestor -system.cpu3.icache.tags.occ_percent::cpu3.inst 0.128454 # Average percentage of cache occupancy -system.cpu3.icache.tags.occ_percent::total 0.128454 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.991831 # Average occupied blocks per requestor +system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126937 # Average percentage of cache occupancy +system.cpu3.icache.tags.occ_percent::total 0.126937 # Average percentage of cache occupancy system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id +system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id -system.cpu3.icache.tags.tag_accesses 169608 # Number of tag accesses -system.cpu3.icache.tags.data_accesses 169608 # Number of data accesses -system.cpu3.icache.ReadReq_hits::cpu3.inst 168874 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 168874 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 168874 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 168874 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 168874 # number of overall hits -system.cpu3.icache.overall_hits::total 168874 # number of overall hits +system.cpu3.icache.tags.tag_accesses 170284 # Number of tag accesses +system.cpu3.icache.tags.data_accesses 170284 # Number of data accesses +system.cpu3.icache.ReadReq_hits::cpu3.inst 169550 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 169550 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 169550 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 169550 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 169550 # number of overall hits +system.cpu3.icache.overall_hits::total 169550 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5371500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5371500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5371500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5371500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5371500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5371500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 169241 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 169241 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 169241 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 169241 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 169241 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 169241 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002169 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002169 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002169 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002169 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002169 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002169 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14636.239782 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 14636.239782 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 14636.239782 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14636.239782 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 14636.239782 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5473500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5473500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5473500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5473500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5473500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5473500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 169917 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 169917 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 169917 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 169917 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 169917 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 169917 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002160 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002160 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002160 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002160 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002160 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002160 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14914.168937 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14914.168937 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14914.168937 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14914.168937 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14914.168937 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1105,71 +1111,75 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.writebacks::writebacks 281 # number of writebacks +system.cpu3.icache.writebacks::total 281 # number of writebacks system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5004500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 5004500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5004500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 5004500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5004500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 5004500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002169 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002169 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002169 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002169 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13636.239782 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13636.239782 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 13636.239782 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5106500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5106500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5106500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5106500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5106500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5106500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002160 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002160 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002160 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002160 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 13914.168937 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 13914.168937 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 13914.168937 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.tags.replacements 0 # number of replacements -system.l2c.tags.tagsinuse 349.411371 # Cycle average of tags in use -system.l2c.tags.total_refs 1716 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 347.318197 # Cycle average of tags in use +system.l2c.tags.total_refs 1714 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 429 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 4 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 3.995338 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 0.890694 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 231.985944 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 54.243981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 6.369557 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 0.864661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 47.217011 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 6.137141 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 0.888283 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 0.814098 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.003540 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.000828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.000097 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 0.882018 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 230.794628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 54.021394 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 6.166785 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 0.835671 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 46.779239 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 6.090035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 0.944334 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 0.804093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.003522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.000824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.000094 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.data 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.000720 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.000094 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.000714 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.000093 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.005332 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.005300 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1024 429 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::2 374 # Occupied blocks per task id system.l2c.tags.occ_task_id_percent::1024 0.006546 # Percentage of cache occupancy per task id system.l2c.tags.tag_accesses 19669 # Number of tag accesses system.l2c.tags.data_accesses 19669 # Number of data accesses -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits +system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits +system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits +system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.ReadCleanReq_hits::cpu0.inst 182 # number of ReadCleanReq hits system.l2c.ReadCleanReq_hits::cpu1.inst 352 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu2.inst 302 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::cpu3.inst 358 # number of ReadCleanReq hits -system.l2c.ReadCleanReq_hits::total 1194 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu2.inst 301 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::cpu3.inst 357 # number of ReadCleanReq hits +system.l2c.ReadCleanReq_hits::total 1192 # number of ReadCleanReq hits system.l2c.ReadSharedReq_hits::cpu0.data 5 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu1.data 9 # number of ReadSharedReq hits system.l2c.ReadSharedReq_hits::cpu2.data 3 # number of ReadSharedReq hits @@ -1179,23 +1189,23 @@ system.l2c.demand_hits::cpu0.inst 182 # nu system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 352 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 302 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 301 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits +system.l2c.demand_hits::total 1218 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 352 # number of overall hits system.l2c.overall_hits::cpu1.data 9 # number of overall hits -system.l2c.overall_hits::cpu2.inst 302 # number of overall hits +system.l2c.overall_hits::cpu2.inst 301 # number of overall hits system.l2c.overall_hits::cpu2.data 3 # number of overall hits -system.l2c.overall_hits::cpu3.inst 358 # number of overall hits +system.l2c.overall_hits::cpu3.inst 357 # number of overall hits system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits +system.l2c.overall_hits::total 1218 # number of overall hits system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 76 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses @@ -1205,9 +1215,9 @@ system.l2c.ReadExReq_misses::cpu3.data 14 # nu system.l2c.ReadExReq_misses::total 142 # number of ReadExReq misses system.l2c.ReadCleanReq_misses::cpu0.inst 285 # number of ReadCleanReq misses system.l2c.ReadCleanReq_misses::cpu1.inst 14 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu2.inst 64 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::cpu3.inst 9 # number of ReadCleanReq misses -system.l2c.ReadCleanReq_misses::total 372 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu2.inst 65 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::cpu3.inst 10 # number of ReadCleanReq misses +system.l2c.ReadCleanReq_misses::total 374 # number of ReadCleanReq misses system.l2c.ReadSharedReq_misses::cpu0.data 66 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu1.data 2 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu2.data 8 # number of ReadSharedReq misses @@ -1217,58 +1227,60 @@ system.l2c.demand_misses::cpu0.inst 285 # nu system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 14 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 64 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 65 # number of demand (read+write) misses system.l2c.demand_misses::cpu2.data 23 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 9 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 10 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 16 # 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number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackClean_accesses::writebacks 495 # number of WritebackClean accesses(hits+misses) +system.l2c.WritebackClean_accesses::total 495 # number of WritebackClean accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 78 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) @@ -1316,9 +1328,9 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadCleanReq accesses system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.038251 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.174863 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadCleanReq accesses -system.l2c.ReadCleanReq_miss_rate::total 0.237548 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.177596 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.027248 # miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_miss_rate::total 0.238825 # miss rate for ReadCleanReq accesses system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.181818 # miss rate for ReadSharedReq accesses system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.727273 # miss rate for ReadSharedReq accesses @@ -1328,53 +1340,53 @@ system.l2c.demand_miss_rate::cpu0.inst 0.610278 # mi system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.038251 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.174863 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.177596 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.884615 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.027248 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.327815 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42541.083916 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 50660.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 50833.200000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 50852.764706 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 50874.812500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 50782.789474 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 49515.151515 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50142.857143 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 49733.333333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 49647.887324 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 49750 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 49538.135593 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 49507.575758 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 49500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 49500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 49500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 49506.578947 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 49522.807018 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 49512.121212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 50214.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 49517.241379 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 49652.173913 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 49750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 49966.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 49561.188811 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadResp 430 # Transaction distribution system.membus.trans_dist::UpgradeReq 271 # Transaction distribution @@ -1563,62 +1578,63 @@ system.membus.pkt_count::total 1557 # Pa system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 261 # Total snoops (count) -system.membus.snoop_fanout::samples 913 # Request fanout histogram +system.membus.snoop_fanout::samples 915 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 913 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 915 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 913 # Request fanout histogram -system.membus.reqLayer0.occupancy 664148 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 915 # Request fanout histogram +system.membus.reqLayer0.occupancy 677632 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 2946008 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2936000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 1.1 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 3982 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 1114 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 1866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_requests 3980 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 1113 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadResp 2222 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 1 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 496 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2221 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution +system.toL2Bus.trans_dist::WritebackClean 495 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution system.toL2Bus.trans_dist::UpgradeReq 273 # Transaction distribution system.toL2Bus.trans_dist::UpgradeResp 273 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 429 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 429 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 428 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 428 # Transaction distribution system.toL2Bus.trans_dist::ReadCleanReq 1566 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 656 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 655 # Transaction distribution system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1077 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 580 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 848 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 579 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes) system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 849 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 367 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 853 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 369 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5311 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 29888 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 852 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5309 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 39040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 23424 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 30912 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 23488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 31040 # Cumulative packet size per connected master and slave (bytes) system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 116032 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 1034 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 3982 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.291562 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.219091 # Request fanout histogram +system.toL2Bus.pkt_size::total 147712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 1032 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 2922 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.269678 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.154527 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 1499 37.64% 37.64% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 871 21.87% 59.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 564 14.16% 73.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 1048 26.32% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 1002 34.29% 34.29% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 787 26.93% 61.23% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 476 16.29% 77.52% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 657 22.48% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram @@ -1627,24 +1643,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 3982 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1996990 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 2922 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 3050992 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 700999 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 501990 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 495500 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 549000 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 431977 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 432972 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 553988 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 427478 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 434474 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 554487 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 432477 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 427974 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%) ---------- End Simulation Statistics ---------- |