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authorAndreas Sandberg <andreas.sandberg@arm.com>2016-08-12 14:12:59 +0100
committerAndreas Sandberg <andreas.sandberg@arm.com>2016-08-12 14:12:59 +0100
commit55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch)
tree6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/40.m5threads-test-atomic
parentee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff)
downloadgem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/40.m5threads-test-atomic')
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt4545
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt82
-rw-r--r--tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt2013
3 files changed, 3282 insertions, 3358 deletions
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
index 8c3fa74c7..10d3d1f6f 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
@@ -1,79 +1,79 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000125 # Number of seconds simulated
-sim_ticks 124523000 # Number of ticks simulated
-final_tick 124523000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000124 # Number of seconds simulated
+sim_ticks 123936000 # Number of ticks simulated
+final_tick 123936000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 143029 # Simulator instruction rate (inst/s)
-host_op_rate 143029 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15434351 # Simulator tick rate (ticks/s)
-host_mem_usage 263456 # Number of bytes of host memory used
-host_seconds 8.07 # Real time elapsed on the host
-sim_insts 1153943 # Number of instructions simulated
-sim_ops 1153943 # Number of ops (including micro ops) simulated
+host_inst_rate 188054 # Simulator instruction rate (inst/s)
+host_op_rate 188053 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20091950 # Simulator tick rate (ticks/s)
+host_mem_usage 268856 # Number of bytes of host memory used
+host_seconds 6.17 # Real time elapsed on the host
+sim_insts 1159992 # Number of instructions simulated
+sim_ops 1159992 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu0.inst 24000 # Number of bytes read from this memory
+system.physmem.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.physmem.bytes_read::cpu0.inst 24064 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 5888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1408 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 5696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 896 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 704 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 896 # Number of bytes read from this memory
-system.physmem.bytes_read::total 45632 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 24000 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 5888 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 45376 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 24064 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 5696 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 896 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 704 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 31488 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu0.inst 375 # Number of read requests responded to by this memory
+system.physmem.bytes_inst_read::cpu3.inst 640 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 31296 # Number of instructions bytes read from this memory
+system.physmem.num_reads::cpu0.inst 376 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 170 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 92 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 22 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 89 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 14 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 11 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 14 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 713 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 192735479 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 87373417 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 47284437 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 11307148 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 7195458 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 7709419 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 5653574 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 7195458 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 366454390 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 192735479 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 47284437 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 7195458 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 5653574 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 252868948 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 192735479 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 87373417 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 47284437 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 11307148 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 7195458 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 7709419 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 5653574 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 7195458 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 366454390 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 713 # Number of read requests accepted
+system.physmem.num_reads::total 709 # Number of read requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 194164730 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 87787245 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 45959205 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 10844307 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 7229538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 7745933 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 5163956 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 7229538 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 366124451 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 194164730 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 45959205 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 7229538 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 5163956 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 252517428 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 194164730 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 87787245 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 45959205 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 10844307 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 7229538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 7745933 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 5163956 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 7229538 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 366124451 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 709 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 713 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 709 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 45632 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 45376 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 45632 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 45376 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 120 # Per bank write bursts
-system.physmem.perBankRdBursts::1 45 # Per bank write bursts
+system.physmem.perBankRdBursts::1 44 # Per bank write bursts
system.physmem.perBankRdBursts::2 31 # Per bank write bursts
system.physmem.perBankRdBursts::3 62 # Per bank write bursts
system.physmem.perBankRdBursts::4 69 # Per bank write bursts
@@ -84,8 +84,8 @@ system.physmem.perBankRdBursts::8 7 # Pe
system.physmem.perBankRdBursts::9 31 # Per bank write bursts
system.physmem.perBankRdBursts::10 23 # Per bank write bursts
system.physmem.perBankRdBursts::11 13 # Per bank write bursts
-system.physmem.perBankRdBursts::12 70 # Per bank write bursts
-system.physmem.perBankRdBursts::13 47 # Per bank write bursts
+system.physmem.perBankRdBursts::12 69 # Per bank write bursts
+system.physmem.perBankRdBursts::13 45 # Per bank write bursts
system.physmem.perBankRdBursts::14 19 # Per bank write bursts
system.physmem.perBankRdBursts::15 101 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
@@ -106,14 +106,14 @@ system.physmem.perBankWrBursts::14 0 # Pe
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 124288000 # Total gap between requests
+system.physmem.totGap 123701000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 713 # Read request sizes (log2)
+system.physmem.readPktSize::6 709 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
@@ -121,8 +121,8 @@ system.physmem.writePktSize::3 0 # Wr
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 433 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 430 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 203 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
@@ -217,29 +217,29 @@ system.physmem.wrQLenPdf::60 0 # Wh
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 171 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 249.637427 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 165.941235 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 244.016459 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 63 36.84% 36.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 41 23.98% 60.82% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 28 16.37% 77.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 13 7.60% 84.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 8 4.68% 89.47% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 8 4.68% 94.15% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3 1.75% 95.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 171 # Bytes accessed per row activation
-system.physmem.totQLat 6387250 # Total ticks spent queuing
-system.physmem.totMemAccLat 19756000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3565000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8958.27 # Average queueing delay per DRAM burst
+system.physmem.bytesPerActivate::samples 169 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 251.076923 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 166.451829 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 245.101340 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 63 37.28% 37.28% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39 23.08% 60.36% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 28 16.57% 76.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 13 7.69% 84.62% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 8 4.73% 89.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8 4.73% 94.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3 1.78% 95.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1 0.59% 96.45% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 6 3.55% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 169 # Bytes accessed per row activation
+system.physmem.totQLat 6766000 # Total ticks spent queuing
+system.physmem.totMemAccLat 20059750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3545000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 9543.02 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27708.27 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 366.45 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28293.02 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 366.12 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 366.45 # Average system read bandwidth in MiByte/s
+system.physmem.avgRdBWSys 366.12 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.86 # Data bus utilization in percentage
@@ -247,296 +247,297 @@ system.physmem.busUtilRead 2.86 # Da
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.23 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 530 # Number of row buffer hits during reads
+system.physmem.readRowHits 528 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.33 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 74.47 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 174316.97 # Average gap between requests
-system.physmem.pageHitRate 74.33 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 816480 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 445500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2917200 # Energy for read commands per rank (pJ)
+system.physmem.avgGap 174472.50 # Average gap between requests
+system.physmem.pageHitRate 74.47 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 831600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 453750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2925000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 46677870 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 29286750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 87772200 # Total energy per rank (pJ)
-system.physmem_0.averagePower 749.845263 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 50196500 # Time in different power states
+system.physmem_0.actBackEnergy 49377960 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 26918250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 88134960 # Total energy per rank (pJ)
+system.physmem_0.averagePower 752.944352 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 47288500 # Time in different power states
system.physmem_0.memoryStateTime::REF 3900000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 64717500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 68692500 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 430920 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 235125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2215200 # Energy for read commands per rank (pJ)
+system.physmem_1.actEnergy 408240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 222750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 7628400 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 50794695 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 25675500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 86979840 # Total energy per rank (pJ)
-system.physmem_1.averagePower 743.076065 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 46915750 # Time in different power states
+system.physmem_1.actBackEnergy 42901335 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 32591250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 85935975 # Total energy per rank (pJ)
+system.physmem_1.averagePower 734.244489 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 54352750 # Time in different power states
system.physmem_1.memoryStateTime::REF 3900000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 70805750 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 59251250 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.cpu0.branchPred.lookups 98739 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 94242 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1562 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 96047 # Number of BTB lookups
+system.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.cpu0.branchPred.lookups 98531 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 94014 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1575 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 95788 # Number of BTB lookups
system.cpu0.branchPred.BTBHits 0 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 1131 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.usedRAS 1142 # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect 128 # Number of incorrect RAS predictions.
-system.cpu0.branchPred.indirectLookups 96047 # Number of indirect predictor lookups.
-system.cpu0.branchPred.indirectHits 88694 # Number of indirect target hits.
-system.cpu0.branchPred.indirectMisses 7353 # Number of indirect misses.
-system.cpu0.branchPredindirectMispredicted 1035 # Number of mispredicted indirect branches.
+system.cpu0.branchPred.indirectLookups 95788 # Number of indirect predictor lookups.
+system.cpu0.branchPred.indirectHits 88519 # Number of indirect target hits.
+system.cpu0.branchPred.indirectMisses 7269 # Number of indirect misses.
+system.cpu0.branchPredindirectMispredicted 1054 # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 249047 # number of cpu cycles simulated
+system.cpu0.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 247873 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 23160 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 582455 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 98739 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 89825 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 194593 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3423 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.icacheStallCycles 23367 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 581451 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 98531 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 89661 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 193123 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3449 # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles 66 # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 2218 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingTrapStallCycles 2208 # Number of stall cycles due to pending traps
system.cpu0.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7952 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 853 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.CacheLines 7997 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 861 # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes 1 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 221760 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 2.626511 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.263155 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::samples 220500 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 2.636966 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.261585 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 34377 15.50% 15.50% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 91683 41.34% 56.85% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 679 0.31% 57.15% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 1006 0.45% 57.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 517 0.23% 57.84% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 87238 39.34% 97.18% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 730 0.33% 97.51% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 482 0.22% 97.72% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 5048 2.28% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 33425 15.16% 15.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 91538 41.51% 56.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 694 0.31% 56.99% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 1015 0.46% 57.45% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 497 0.23% 57.67% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 87060 39.48% 97.16% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 731 0.33% 97.49% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 514 0.23% 97.72% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 5026 2.28% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 221760 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.396467 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 2.338735 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 17619 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 19820 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 181778 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 832 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1711 # Number of cycles decode is squashing
-system.cpu0.decode.DecodedInsts 564879 # Number of instructions handled by decode
-system.cpu0.rename.SquashCycles 1711 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 18296 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 2376 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 16107 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 181922 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 1348 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 559910 # Number of instructions processed by rename
+system.cpu0.fetch.rateDist::total 220500 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.397506 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 2.345762 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 17843 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 18591 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 181526 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 816 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1724 # Number of cycles decode is squashing
+system.cpu0.decode.DecodedInsts 563984 # Number of instructions handled by decode
+system.cpu0.rename.SquashCycles 1724 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 18505 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 1935 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 15328 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 181668 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 1340 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 558880 # Number of instructions processed by rename
system.cpu0.rename.IQFullEvents 11 # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents 11 # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents 869 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 383145 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 1115796 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 842870 # Number of integer rename lookups
-system.cpu0.rename.CommittedMaps 364171 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 18974 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1067 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1095 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 5253 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 178633 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 90222 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 87104 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 86835 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 467056 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1095 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 463006 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 118 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 16506 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 13395 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 536 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 221760 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 2.087870 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.110825 # Number of insts issued each cycle
+system.cpu0.rename.RenamedOperands 382489 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 1113780 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 841332 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 2 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 363591 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 18898 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1094 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1121 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 5347 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 178321 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 90063 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 86944 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 86670 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 466208 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1118 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 462266 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 16406 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 13115 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 559 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 220500 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 2.096444 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.103875 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 37234 16.79% 16.79% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 4446 2.00% 18.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 88426 39.87% 58.67% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 88102 39.73% 98.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1676 0.76% 99.15% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 983 0.44% 99.60% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 568 0.26% 99.85% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 225 0.10% 99.95% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 100 0.05% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 36239 16.43% 16.43% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 4459 2.02% 18.46% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 88275 40.03% 58.49% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 87972 39.90% 98.39% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1699 0.77% 99.16% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 988 0.45% 99.61% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 572 0.26% 99.87% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 195 0.09% 99.95% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 101 0.05% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 221760 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 220500 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 134 40.48% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.48% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 76 22.96% 63.44% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 121 36.56% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 126 38.77% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 38.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 78 24.00% 62.77% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 121 37.23% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 195503 42.22% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 178044 38.45% 80.68% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 89459 19.32% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 195215 42.23% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.23% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 177740 38.45% 80.68% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 89311 19.32% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 463006 # Type of FU issued
-system.cpu0.iq.rate 1.859111 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 331 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.000715 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 1148221 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 484707 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 460421 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.FU_type_0::total 462266 # Type of FU issued
+system.cpu0.iq.rate 1.864931 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 325 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.000703 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 1145469 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 483779 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 459725 # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 463337 # Number of integer alu accesses
+system.cpu0.iq.int_alu_accesses 462591 # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 86583 # Number of loads that had data forwarded from stores
+system.cpu0.iew.lsq.thread0.forwLoads 86430 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2958 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 9 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 52 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1878 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2936 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 13 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 53 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1864 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked 11 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1711 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 2375 # Number of cycles IEW is blocking
+system.cpu0.iew.iewSquashCycles 1724 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1933 # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 555874 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 119 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 178633 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 90222 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 980 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewDispatchedInsts 554898 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 123 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 178321 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 90063 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1001 # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents 27 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 52 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 232 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 1679 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 1911 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 461536 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 177679 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1470 # Number of squashed instructions skipped in execute
+system.cpu0.iew.memOrderViolationEvents 53 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 229 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 1693 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 1922 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 460834 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 177384 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1432 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 87723 # number of nop insts executed
-system.cpu0.iew.exec_refs 266935 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 91696 # Number of branches executed
-system.cpu0.iew.exec_stores 89256 # Number of stores executed
-system.cpu0.iew.exec_rate 1.853208 # Inst execution rate
-system.cpu0.iew.wb_sent 460886 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 460421 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 273043 # num instructions producing a value
-system.cpu0.iew.wb_consumers 276596 # num instructions consuming a value
-system.cpu0.iew.wb_rate 1.848731 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.987155 # average fanout of values written-back
-system.cpu0.commit.commitSquashedInsts 17182 # The number of squashed insts skipped by commit
+system.cpu0.iew.exec_nop 87572 # number of nop insts executed
+system.cpu0.iew.exec_refs 266499 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 91565 # Number of branches executed
+system.cpu0.iew.exec_stores 89115 # Number of stores executed
+system.cpu0.iew.exec_rate 1.859154 # Inst execution rate
+system.cpu0.iew.wb_sent 460184 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 459725 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 272583 # num instructions producing a value
+system.cpu0.iew.wb_consumers 276120 # num instructions consuming a value
+system.cpu0.iew.wb_rate 1.854680 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.987190 # average fanout of values written-back
+system.cpu0.commit.commitSquashedInsts 17076 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 1562 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 218398 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 2.466176 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 2.142349 # Number of insts commited each cycle
+system.cpu0.commit.branchMispredicts 1575 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 217161 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 2.476218 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 2.140669 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 37197 17.03% 17.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 90473 41.43% 58.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 2051 0.94% 59.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 612 0.28% 59.68% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 499 0.23% 59.91% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 86381 39.55% 99.46% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 448 0.21% 99.66% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 288 0.13% 99.79% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 449 0.21% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 36214 16.68% 16.68% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 90367 41.61% 58.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 2049 0.94% 59.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 624 0.29% 59.52% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 510 0.23% 59.75% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 86212 39.70% 99.45% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 445 0.20% 99.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 289 0.13% 99.79% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 451 0.21% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 218398 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 538608 # Number of instructions committed
-system.cpu0.commit.committedOps 538608 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 217161 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 537738 # Number of instructions committed
+system.cpu0.commit.committedOps 537738 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 264019 # Number of memory references committed
-system.cpu0.commit.loads 175675 # Number of loads committed
+system.cpu0.commit.refs 263584 # Number of memory references committed
+system.cpu0.commit.loads 175385 # Number of loads committed
system.cpu0.commit.membars 84 # Number of memory barriers committed
-system.cpu0.commit.branches 90231 # Number of branches committed
+system.cpu0.commit.branches 90086 # Number of branches committed
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 362502 # Number of committed integer instructions.
+system.cpu0.commit.int_insts 361922 # Number of committed integer instructions.
system.cpu0.commit.function_calls 223 # Number of function calls committed.
-system.cpu0.commit.op_class_0::No_OpClass 86963 16.15% 16.15% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 187542 34.82% 50.97% # Class of committed instruction
+system.cpu0.commit.op_class_0::No_OpClass 86818 16.15% 16.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 187252 34.82% 50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.97% # Class of committed instruction
@@ -565,105 +566,105 @@ system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.97%
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.97% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.97% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 175759 32.63% 83.60% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 88344 16.40% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 175469 32.63% 83.60% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 88199 16.40% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 538608 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 449 # number cycles where commit BW limit reached
-system.cpu0.rob.rob_reads 772578 # The number of ROB reads
-system.cpu0.rob.rob_writes 1114998 # The number of ROB writes
-system.cpu0.timesIdled 315 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 27287 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.committedInsts 451561 # Number of Instructions Simulated
-system.cpu0.committedOps 451561 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 0.551525 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 0.551525 # CPI: Total CPI of All Threads
-system.cpu0.ipc 1.813156 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 1.813156 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 825039 # number of integer regfile reads
-system.cpu0.int_regfile_writes 371919 # number of integer regfile writes
+system.cpu0.commit.op_class_0::total 537738 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 451 # number cycles where commit BW limit reached
+system.cpu0.rob.rob_reads 770363 # The number of ROB reads
+system.cpu0.rob.rob_writes 1113018 # The number of ROB writes
+system.cpu0.timesIdled 321 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 27373 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.committedInsts 450836 # Number of Instructions Simulated
+system.cpu0.committedOps 450836 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 0.549807 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 0.549807 # CPI: Total CPI of All Threads
+system.cpu0.ipc 1.818819 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 1.818819 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 823745 # number of integer regfile reads
+system.cpu0.int_regfile_writes 371341 # number of integer regfile writes
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
-system.cpu0.misc_regfile_reads 269052 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 268638 # number of misc regfile reads
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 142.724931 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 178078 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse 142.669467 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 177790 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 172 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 1035.337209 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 1033.662791 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.724931 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278760 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.278760 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.669467 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278651 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.278651 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 170 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.332031 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 717658 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 717658 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 90413 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 90413 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 87748 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 87748 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits::cpu0.data 23 # number of SwapReq hits
-system.cpu0.dcache.SwapReq_hits::total 23 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 178161 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 178161 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 178161 # number of overall hits
-system.cpu0.dcache.overall_hits::total 178161 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 578 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 578 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 554 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 554 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses::cpu0.data 19 # number of SwapReq misses
-system.cpu0.dcache.SwapReq_misses::total 19 # number of SwapReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 1132 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 1132 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 1132 # number of overall misses
-system.cpu0.dcache.overall_misses::total 1132 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 18168000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 18168000 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36152490 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 36152490 # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 521000 # number of SwapReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency::total 521000 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 54320490 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.WriteReq_accesses::total 88302 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 31432.525952 # average ReadReq miss latency
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-system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 27421.052632 # average SwapReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 47986.298587 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 47986.298587 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 47986.298587 # average overall miss latency
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25868.965517 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 25868.965517 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 64903.793103 # average WriteReq miss latency
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+system.cpu0.dcache.SwapReq_avg_miss_latency::total 24375 # average SwapReq miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 44885.932803 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 44885.932803 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 44885.932803 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 832 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 22 # number of cycles access was blocked
@@ -672,2233 +673,2195 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 37.818182
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
system.cpu0.dcache.writebacks::total 1 # number of writebacks
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-system.cpu0.dcache.ReadReq_mshr_misses::total 193 # number of ReadReq MSHR misses
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-system.cpu0.icache.tags.avg_refs 10.130935 # Average number of references to valid blocks.
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system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.tags.age_task_id_blocks_1024::2 192 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 0.587891 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 8647 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 8647 # Number of data accesses
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-system.cpu0.icache.demand_accesses::cpu0.inst 7952 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7952 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7952 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7952 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.114562 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.114562 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.114562 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.114562 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.114562 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.114562 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47959.385291 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 47959.385291 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 47959.385291 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47959.385291 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 47959.385291 # average overall miss latency
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 250.106503 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.488489 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.488489 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 190 # Occupied blocks per task id
+system.cpu0.icache.tags.occ_task_id_percent::1024 0.583984 # Percentage of cache occupancy per task id
+system.cpu0.icache.tags.tag_accesses 8709 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 8709 # Number of data accesses
+system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.cpu0.icache.ReadReq_hits::cpu0.inst 7058 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 7058 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 7058 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 7058 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 7058 # number of overall hits
+system.cpu0.icache.overall_hits::total 7058 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 939 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 939 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 939 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 939 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 939 # number of overall misses
+system.cpu0.icache.overall_misses::total 939 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 44243500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 44243500 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 44243500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 44243500 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 44243500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 44243500 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 7997 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 7997 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 7997 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 7997 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 7997 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 7997 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.117419 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.117419 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.117419 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.117419 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.117419 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.117419 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47117.678381 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 47117.678381 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 47117.678381 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47117.678381 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 47117.678381 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 117 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 29.250000 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.writebacks::writebacks 394 # number of writebacks
-system.cpu0.icache.writebacks::total 394 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 215 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 215 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 215 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 215 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 696 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 696 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 696 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 696 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 696 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 696 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 33693000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 33693000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 33693000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 33693000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 33693000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 33693000 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.087525 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.087525 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.087525 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.087525 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 48409.482759 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 48409.482759 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 48409.482759 # average overall mshr miss latency
-system.cpu1.branchPred.lookups 70381 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 62763 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 2321 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 62113 # Number of BTB lookups
+system.cpu0.icache.writebacks::writebacks 413 # number of writebacks
+system.cpu0.icache.writebacks::total 413 # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 226 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 226 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 226 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 226 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 226 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 713 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 713 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 713 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 713 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 34164500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 34164500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 34164500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 34164500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 34164500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 34164500 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.089158 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.089158 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.089158 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.089158 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 47916.549790 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 47916.549790 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 47916.549790 # average overall mshr miss latency
+system.cpu1.branchPred.lookups 73042 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 65659 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 2238 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 64943 # Number of BTB lookups
system.cpu1.branchPred.BTBHits 0 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 1978 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu1.branchPred.indirectLookups 62113 # Number of indirect predictor lookups.
-system.cpu1.branchPred.indirectHits 52196 # Number of indirect target hits.
-system.cpu1.branchPred.indirectMisses 9917 # Number of indirect misses.
-system.cpu1.branchPredindirectMispredicted 1232 # Number of mispredicted indirect branches.
-system.cpu1.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
-system.cpu1.numCycles 193493 # number of cpu cycles simulated
+system.cpu1.branchPred.indirectLookups 64943 # Number of indirect predictor lookups.
+system.cpu1.branchPred.indirectHits 55241 # Number of indirect target hits.
+system.cpu1.branchPred.indirectMisses 9702 # Number of indirect misses.
+system.cpu1.branchPredindirectMispredicted 1128 # Number of mispredicted indirect branches.
+system.cpu1.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
+system.cpu1.numCycles 192502 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 35625 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 388406 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 70381 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 54174 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 147522 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 4799 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.icacheStallCycles 33710 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 406560 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 73042 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 57230 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 148689 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 4633 # Number of cycles fetch has spent squashing
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu1.fetch.PendingTrapStallCycles 1696 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingTrapStallCycles 1669 # Number of stall cycles due to pending traps
system.cpu1.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 23532 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 933 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 187271 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 2.074032 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.377312 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.CacheLines 22180 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 918 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 186413 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 2.180964 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.381342 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 61181 32.67% 32.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 61333 32.75% 65.42% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 6091 3.25% 68.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 3354 1.79% 70.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 663 0.35% 70.82% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 43826 23.40% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 1093 0.58% 94.80% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 1351 0.72% 95.53% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 8379 4.47% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 54977 29.49% 29.49% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 63721 34.18% 63.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 5493 2.95% 66.62% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 3499 1.88% 68.50% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 651 0.35% 68.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 47493 25.48% 94.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 995 0.53% 94.86% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 1355 0.73% 95.59% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 8229 4.41% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 187271 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.363739 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 2.007339 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 22629 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 55115 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 103585 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 3533 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 2399 # Number of cycles decode is squashing
-system.cpu1.decode.DecodedInsts 358317 # Number of instructions handled by decode
-system.cpu1.rename.SquashCycles 2399 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 23637 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 25102 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 14378 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 104390 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 17355 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 351725 # Number of instructions processed by rename
-system.cpu1.rename.IQFullEvents 14900 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 17 # Number of times rename has blocked due to LQ full
+system.cpu1.fetch.rateDist::total 186413 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.379435 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 2.111978 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 22012 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 48189 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 110683 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 3203 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 2316 # Number of cycles decode is squashing
+system.cpu1.decode.DecodedInsts 375249 # Number of instructions handled by decode
+system.cpu1.rename.SquashCycles 2316 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 23003 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 21046 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 13565 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 110960 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 15513 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 369118 # Number of instructions processed by rename
+system.cpu1.rename.IQFullEvents 12808 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 18 # Number of times rename has blocked due to LQ full
system.cpu1.rename.FullRegisterEvents 3 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 247787 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 679105 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 526513 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 34 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 220167 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 27620 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1612 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1735 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 22764 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 99432 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 48003 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 46782 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 41727 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 289849 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 6510 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 288395 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 24134 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 20047 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 1135 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 187271 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 1.539988 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.388620 # Number of insts issued each cycle
+system.cpu1.rename.RenamedOperands 260404 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 717496 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 555302 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 32 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 234261 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 26143 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1622 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1759 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 20875 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 105786 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 51568 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 49714 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 45358 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 305985 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 5880 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 304555 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 23105 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 18122 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 1124 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 186413 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 1.633765 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.368784 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 65886 35.18% 35.18% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 21449 11.45% 46.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 46526 24.84% 71.48% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 46214 24.68% 96.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 3599 1.92% 98.08% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1752 0.94% 99.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1124 0.60% 99.61% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 416 0.22% 99.84% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 59464 31.90% 31.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 19554 10.49% 42.39% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 50315 26.99% 69.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 50093 26.87% 96.25% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 3572 1.92% 98.17% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1698 0.91% 99.08% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1008 0.54% 99.62% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 406 0.22% 99.84% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 303 0.16% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 187271 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 186413 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 198 39.68% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 39.68% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 73 14.63% 54.31% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 228 45.69% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 182 38.89% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 58 12.39% 51.28% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 228 48.72% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 138505 48.03% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 102963 35.70% 83.73% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 46927 16.27% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 145063 47.63% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.63% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 108861 35.74% 83.38% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 50631 16.62% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 288395 # Type of FU issued
-system.cpu1.iq.rate 1.490467 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 499 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.001730 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 764671 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 320465 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 284383 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.FU_type_0::total 304555 # Type of FU issued
+system.cpu1.iq.rate 1.582087 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 468 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.001537 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 796075 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 334945 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 300973 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 68 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_writes 64 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 288894 # Number of integer alu accesses
+system.cpu1.iq.int_alu_accesses 305023 # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 41593 # Number of loads that had data forwarded from stores
+system.cpu1.iew.lsq.thread0.forwLoads 45252 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 4579 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 38 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 2647 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 4194 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 25 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 2536 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 2399 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 8044 # Number of cycles IEW is blocking
+system.cpu1.iew.iewSquashCycles 2316 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 6366 # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 344307 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 270 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 99432 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 48003 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 1487 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 36 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewDispatchedInsts 362764 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 272 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 105786 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 51568 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 1528 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2454 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 2900 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 285809 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 97701 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 2586 # Number of squashed instructions skipped in execute
+system.cpu1.iew.memOrderViolationEvents 39 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2397 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 2840 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 302276 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 104291 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 2279 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 47948 # number of nop insts executed
-system.cpu1.iew.exec_refs 144318 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 58093 # Number of branches executed
-system.cpu1.iew.exec_stores 46617 # Number of stores executed
-system.cpu1.iew.exec_rate 1.477103 # Inst execution rate
-system.cpu1.iew.wb_sent 284919 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 284383 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 161989 # num instructions producing a value
-system.cpu1.iew.wb_consumers 169394 # num instructions consuming a value
-system.cpu1.iew.wb_rate 1.469733 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.956285 # average fanout of values written-back
-system.cpu1.commit.commitSquashedInsts 25278 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 5375 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 2321 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 182469 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 1.748204 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 2.087021 # Number of insts commited each cycle
+system.cpu1.iew.exec_nop 50899 # number of nop insts executed
+system.cpu1.iew.exec_refs 154635 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 61121 # Number of branches executed
+system.cpu1.iew.exec_stores 50344 # Number of stores executed
+system.cpu1.iew.exec_rate 1.570249 # Inst execution rate
+system.cpu1.iew.wb_sent 301460 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 300973 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 172395 # num instructions producing a value
+system.cpu1.iew.wb_consumers 179828 # num instructions consuming a value
+system.cpu1.iew.wb_rate 1.563480 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.958666 # average fanout of values written-back
+system.cpu1.commit.commitSquashedInsts 24140 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 4756 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 2238 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 181815 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 1.862272 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 2.110451 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 70580 38.68% 38.68% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 54368 29.80% 68.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 5362 2.94% 71.41% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 6062 3.32% 74.74% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1316 0.72% 75.46% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 41726 22.87% 98.33% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 809 0.44% 98.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 1001 0.55% 99.32% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1245 0.68% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 63682 35.03% 35.03% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 57506 31.63% 66.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 5445 2.99% 69.65% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 5412 2.98% 72.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1312 0.72% 73.35% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 45472 25.01% 98.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 770 0.42% 98.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 999 0.55% 99.33% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1217 0.67% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 182469 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 318993 # Number of instructions committed
-system.cpu1.commit.committedOps 318993 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 181815 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 338589 # Number of instructions committed
+system.cpu1.commit.committedOps 338589 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 140209 # Number of memory references committed
-system.cpu1.commit.loads 94853 # Number of loads committed
-system.cpu1.commit.membars 4659 # Number of memory barriers committed
-system.cpu1.commit.branches 55980 # Number of branches committed
+system.cpu1.commit.refs 150624 # Number of memory references committed
+system.cpu1.commit.loads 101592 # Number of loads committed
+system.cpu1.commit.membars 4041 # Number of memory barriers committed
+system.cpu1.commit.branches 59040 # Number of branches committed
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 218308 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 231783 # Number of committed integer instructions.
system.cpu1.commit.function_calls 322 # Number of function calls committed.
-system.cpu1.commit.op_class_0::No_OpClass 46768 14.66% 14.66% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 127357 39.92% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 99512 31.20% 85.78% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 45356 14.22% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::No_OpClass 49829 14.72% 14.72% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 134095 39.60% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.32% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 105633 31.20% 85.52% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 49032 14.48% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 318993 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1245 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 524909 # The number of ROB reads
-system.cpu1.rob.rob_writes 693389 # The number of ROB writes
-system.cpu1.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 6222 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.commit.op_class_0::total 338589 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1217 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 542741 # The number of ROB reads
+system.cpu1.rob.rob_writes 730091 # The number of ROB writes
+system.cpu1.timesIdled 236 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 6089 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 47433 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 267566 # Number of Instructions Simulated
-system.cpu1.committedOps 267566 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 0.723160 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 0.723160 # CPI: Total CPI of All Threads
-system.cpu1.ipc 1.382820 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 1.382820 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 496242 # number of integer regfile reads
-system.cpu1.int_regfile_writes 230976 # number of integer regfile writes
+system.cpu1.committedInsts 284719 # Number of Instructions Simulated
+system.cpu1.committedOps 284719 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 0.676112 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 0.676112 # CPI: Total CPI of All Threads
+system.cpu1.ipc 1.479044 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 1.479044 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 527704 # number of integer regfile reads
+system.cpu1.int_regfile_writes 245054 # number of integer regfile writes
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 146210 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 156484 # number of misc regfile reads
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements 0 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 26.604916 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 52484 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 31 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 1693.032258 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.tagsinuse 26.869792 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 56025 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 1931.896552 # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.604916 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051963 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.051963 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 31 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 24 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.060547 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 405985 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 405985 # Number of data accesses
-system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.cpu1.dcache.ReadReq_hits::cpu1.data 55568 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 55568 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 45140 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 45140 # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
-system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 100708 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 100708 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 100708 # number of overall hits
-system.cpu1.dcache.overall_hits::total 100708 # number of overall hits
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.869792 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.052480 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.052480 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 432447 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 432447 # Number of data accesses
+system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.cpu1.dcache.ReadReq_hits::cpu1.data 58508 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 58508 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 48814 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 48814 # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data 11 # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total 11 # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 107322 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 107322 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 107322 # number of overall hits
+system.cpu1.dcache.overall_hits::total 107322 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 507 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 507 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 146 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 146 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 149 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 149 # number of WriteReq misses
system.cpu1.dcache.SwapReq_misses::cpu1.data 58 # number of SwapReq misses
system.cpu1.dcache.SwapReq_misses::total 58 # number of SwapReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 653 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 653 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 653 # number of overall misses
-system.cpu1.dcache.overall_misses::total 653 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9264000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 9264000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3726500 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 3726500 # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 796000 # number of SwapReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency::total 796000 # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 12990500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 12990500 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 12990500 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 12990500 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 56075 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 56075 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 45286 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 45286 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::cpu1.data 70 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 101361 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 101361 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 101361 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 101361 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009041 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.009041 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003224 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.003224 # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.828571 # miss rate for SwapReq accesses
-system.cpu1.dcache.SwapReq_miss_rate::total 0.828571 # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006442 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.006442 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006442 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.006442 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18272.189349 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 18272.189349 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25523.972603 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 25523.972603 # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 13724.137931 # average SwapReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency::total 13724.137931 # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19893.568147 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19893.568147 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
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system.cpu1.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 22451.724138 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 22451.724138 # average overall miss latency
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-system.cpu1.icache.overall_avg_miss_latency::total 22451.724138 # average overall miss latency
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+system.cpu1.icache.tags.occ_task_id_percent::1024 0.255859 # Percentage of cache occupancy per task id
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+system.cpu1.icache.tags.data_accesses 22867 # Number of data accesses
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+system.cpu1.icache.overall_miss_latency::total 18952000 # number of overall miss cycles
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+system.cpu1.icache.overall_accesses::total 22180 # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.038097 # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_miss_rate::total 0.038097 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.038097 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.038097 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.038097 # miss rate for overall accesses
+system.cpu1.icache.overall_miss_rate::total 0.038097 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22428.402367 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 22428.402367 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 22428.402367 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22428.402367 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 22428.402367 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 141 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs 35.250000 # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.icache.writebacks::writebacks 579 # number of writebacks
-system.cpu1.icache.writebacks::total 579 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 157 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 157 # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_hits::total 157 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits::cpu1.inst 157 # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_hits::total 157 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 713 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 713 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 713 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 713 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 713 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 713 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 15250000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 15250000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 15250000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 15250000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 15250000 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 15250000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030299 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.030299 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030299 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.030299 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21388.499299 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21388.499299 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 21388.499299 # average overall mshr miss latency
-system.cpu2.branchPred.lookups 63667 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 55684 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 2455 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 55606 # Number of BTB lookups
+system.cpu1.icache.writebacks::writebacks 556 # number of writebacks
+system.cpu1.icache.writebacks::total 556 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total 158 # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total 158 # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total 158 # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 687 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 687 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 687 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 687 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 687 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 687 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 14723000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 14723000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 14723000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 14723000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 14723000 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 14723000 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.030974 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.030974 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030974 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.030974 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 21430.858806 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 21430.858806 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 21430.858806 # average overall mshr miss latency
+system.cpu2.branchPred.lookups 66096 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 57926 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 2486 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 57464 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 0 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 2018 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.usedRAS 2115 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu2.branchPred.indirectLookups 55606 # Number of indirect predictor lookups.
-system.cpu2.branchPred.indirectHits 44645 # Number of indirect target hits.
-system.cpu2.branchPred.indirectMisses 10961 # Number of indirect misses.
-system.cpu2.branchPredindirectMispredicted 1342 # Number of mispredicted indirect branches.
-system.cpu2.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
-system.cpu2.numCycles 193104 # number of cpu cycles simulated
+system.cpu2.branchPred.indirectLookups 57464 # Number of indirect predictor lookups.
+system.cpu2.branchPred.indirectHits 46751 # Number of indirect target hits.
+system.cpu2.branchPred.indirectMisses 10713 # Number of indirect misses.
+system.cpu2.branchPredindirectMispredicted 1349 # Number of mispredicted indirect branches.
+system.cpu2.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
+system.cpu2.numCycles 192112 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 40968 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 342539 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 63667 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 46663 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 146022 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 5067 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.icacheStallCycles 39817 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 356778 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 66096 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 48866 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 146191 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 5129 # Number of cycles fetch has spent squashing
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu2.fetch.PendingTrapStallCycles 1848 # Number of stall cycles due to pending traps
-system.cpu2.fetch.IcacheWaitRetryStallCycles 13 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 29416 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 951 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.rateDist::samples 191398 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.789669 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.326327 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.PendingTrapStallCycles 1920 # Number of stall cycles due to pending traps
+system.cpu2.fetch.IcacheWaitRetryStallCycles 3 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 28579 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 972 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.rateDist::samples 190509 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.872762 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.344982 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 76889 40.17% 40.17% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 56601 29.57% 69.74% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 8825 4.61% 74.36% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 3447 1.80% 76.16% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 694 0.36% 76.52% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 33672 17.59% 94.11% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 980 0.51% 94.62% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 1389 0.73% 95.35% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 8901 4.65% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 72004 37.80% 37.80% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 58377 30.64% 68.44% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 8422 4.42% 72.86% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 3406 1.79% 74.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 670 0.35% 75.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 36267 19.04% 94.04% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 1053 0.55% 94.59% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 1474 0.77% 95.36% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 8836 4.64% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 191398 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.329703 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 1.773858 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 22836 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 76803 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 84446 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 4770 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 2533 # Number of cycles decode is squashing
-system.cpu2.decode.DecodedInsts 310490 # Number of instructions handled by decode
-system.cpu2.rename.SquashCycles 2533 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 23870 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 37657 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 14813 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 85216 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 27299 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 303538 # Number of instructions processed by rename
-system.cpu2.rename.IQFullEvents 23577 # Number of times rename has blocked due to IQ full
+system.cpu2.fetch.rateDist::total 190509 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.344049 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 1.857135 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 22990 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 70899 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 89451 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 4595 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 2564 # Number of cycles decode is squashing
+system.cpu2.decode.DecodedInsts 324452 # Number of instructions handled by decode
+system.cpu2.rename.SquashCycles 2564 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 24019 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 34614 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 13407 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 89996 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 25899 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 317685 # Number of instructions processed by rename
+system.cpu2.rename.IQFullEvents 22128 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full
system.cpu2.rename.FullRegisterEvents 2 # Number of times there has been no free registers
-system.cpu2.rename.RenamedOperands 211726 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 571973 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 446566 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 26 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 182781 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 28945 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 1674 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 1822 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 33085 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 82000 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 37987 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 39268 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 31634 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 245836 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 9182 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 247097 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 85 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 25038 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 19372 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 1244 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 191398 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 1.291011 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.381781 # Number of insts issued each cycle
+system.cpu2.rename.RenamedOperands 221990 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 601950 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 469192 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 40 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 192480 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 29510 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 1686 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 1819 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 31415 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 86703 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 40578 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 41384 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 34173 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 258235 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 8782 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 258833 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 83 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 25653 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 20039 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 1265 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 190509 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 1.358639 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.384430 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 81765 42.72% 42.72% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 29268 15.29% 58.01% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 36754 19.20% 77.21% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 36522 19.08% 96.30% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 3555 1.86% 98.15% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1723 0.90% 99.05% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 1061 0.55% 99.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 446 0.23% 99.84% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 304 0.16% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 76931 40.38% 40.38% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 28046 14.72% 55.10% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 39341 20.65% 75.75% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 39028 20.49% 96.24% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 3604 1.89% 98.13% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1759 0.92% 99.06% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 1073 0.56% 99.62% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 444 0.23% 99.85% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 283 0.15% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 191398 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 190509 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 203 40.76% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 64 12.85% 53.61% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 231 46.39% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 204 42.15% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntMult 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.15% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 51 10.54% 52.69% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 229 47.31% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 121951 49.35% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.35% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 88101 35.65% 85.01% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 37045 14.99% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 126867 49.02% 49.02% # Type of FU issued
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+system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.02% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 92395 35.70% 84.71% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 39571 15.29% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 247097 # Type of FU issued
-system.cpu2.iq.rate 1.279606 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 498 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.002015 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 686175 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 280041 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 243170 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.FU_type_0::total 258833 # Type of FU issued
+system.cpu2.iq.rate 1.347303 # Inst issue rate
+system.cpu2.iq.fu_busy_cnt 484 # FU busy when requested
+system.cpu2.iq.fu_busy_rate 0.001870 # FU busy rate (busy events/executed inst)
+system.cpu2.iq.int_inst_queue_reads 708742 # Number of integer instruction queue reads
+system.cpu2.iq.int_inst_queue_writes 292626 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 254835 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 52 # Number of floating instruction queue writes
+system.cpu2.iq.fp_inst_queue_writes 80 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 247595 # Number of integer alu accesses
+system.cpu2.iq.int_alu_accesses 259317 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 31591 # Number of loads that had data forwarded from stores
+system.cpu2.iew.lsq.thread0.forwLoads 34129 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 4554 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 4624 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 33 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 37 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 2621 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 36 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 2677 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 2533 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 10681 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 295617 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 336 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 82000 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 37987 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 1539 # Number of dispatched non-speculative instructions
+system.cpu2.iew.iewSquashCycles 2564 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 9290 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 55 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 309688 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 288 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 86703 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 40578 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 1561 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 34 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 37 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 446 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 2642 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 3088 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 244561 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 80330 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 2536 # Number of squashed instructions skipped in execute
+system.cpu2.iew.memOrderViolationEvents 36 # Number of memory order violations
+system.cpu2.iew.predictedTakenIncorrect 443 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 2684 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 3127 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 256258 # Number of executed instructions
+system.cpu2.iew.iewExecLoadInsts 85016 # Number of load instructions executed
+system.cpu2.iew.iewExecSquashedInsts 2575 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 40599 # number of nop insts executed
-system.cpu2.iew.exec_refs 117071 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 50931 # Number of branches executed
-system.cpu2.iew.exec_stores 36741 # Number of stores executed
-system.cpu2.iew.exec_rate 1.266473 # Inst execution rate
-system.cpu2.iew.wb_sent 243660 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 243170 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 134852 # num instructions producing a value
-system.cpu2.iew.wb_consumers 142392 # num instructions consuming a value
-system.cpu2.iew.wb_rate 1.259270 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.947048 # average fanout of values written-back
-system.cpu2.commit.commitSquashedInsts 26266 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 7938 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 2455 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 186363 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 1.445163 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.976076 # Number of insts commited each cycle
+system.cpu2.iew.exec_nop 42671 # number of nop insts executed
+system.cpu2.iew.exec_refs 124288 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 53042 # Number of branches executed
+system.cpu2.iew.exec_stores 39272 # Number of stores executed
+system.cpu2.iew.exec_rate 1.333899 # Inst execution rate
+system.cpu2.iew.wb_sent 255341 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 254835 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 142252 # num instructions producing a value
+system.cpu2.iew.wb_consumers 149928 # num instructions consuming a value
+system.cpu2.iew.wb_rate 1.326492 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.948802 # average fanout of values written-back
+system.cpu2.commit.commitSquashedInsts 26847 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 7517 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 2486 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 185379 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 1.525604 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 2.006612 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 89147 47.84% 47.84% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 47087 25.27% 73.10% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 5442 2.92% 76.02% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 8636 4.63% 80.66% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 1280 0.69% 81.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 31787 17.06% 98.40% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 722 0.39% 98.79% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 1037 0.56% 99.34% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1225 0.66% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 83888 45.25% 45.25% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 49216 26.55% 71.80% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 5545 2.99% 74.79% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 8151 4.40% 79.19% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 1274 0.69% 79.88% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 34338 18.52% 98.40% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 700 0.38% 98.78% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 1066 0.58% 99.35% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1201 0.65% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 186363 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 269325 # Number of instructions committed
-system.cpu2.commit.committedOps 269325 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 185379 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 282815 # Number of instructions committed
+system.cpu2.commit.committedOps 282815 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 112812 # Number of memory references committed
-system.cpu2.commit.loads 77446 # Number of loads committed
-system.cpu2.commit.membars 7225 # Number of memory barriers committed
-system.cpu2.commit.branches 48554 # Number of branches committed
+system.cpu2.commit.refs 119980 # Number of memory references committed
+system.cpu2.commit.loads 82079 # Number of loads committed
+system.cpu2.commit.membars 6800 # Number of memory barriers committed
+system.cpu2.commit.branches 50664 # Number of branches committed
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 183489 # Number of committed integer instructions.
+system.cpu2.commit.int_insts 192763 # Number of committed integer instructions.
system.cpu2.commit.function_calls 322 # Number of function calls committed.
-system.cpu2.commit.op_class_0::No_OpClass 39345 14.61% 14.61% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 109943 40.82% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.43% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 84671 31.44% 86.87% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 35366 13.13% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::No_OpClass 41451 14.66% 14.66% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 114584 40.52% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.17% # Class of committed instruction
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+system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.17% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 88879 31.43% 86.60% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 37901 13.40% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 269325 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1225 # number cycles where commit BW limit reached
-system.cpu2.rob.rob_reads 480143 # The number of ROB reads
-system.cpu2.rob.rob_writes 596277 # The number of ROB writes
-system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1706 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.commit.op_class_0::total 282815 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1201 # number cycles where commit BW limit reached
+system.cpu2.rob.rob_reads 493254 # The number of ROB reads
+system.cpu2.rob.rob_writes 624500 # The number of ROB writes
+system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1603 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 47823 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 222755 # Number of Instructions Simulated
-system.cpu2.committedOps 222755 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 0.866890 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 0.866890 # CPI: Total CPI of All Threads
-system.cpu2.ipc 1.153549 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 1.153549 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 415553 # number of integer regfile reads
-system.cpu2.int_regfile_writes 194388 # number of integer regfile writes
+system.cpu2.committedInsts 234564 # Number of Instructions Simulated
+system.cpu2.committedOps 234564 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 0.819017 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 0.819017 # CPI: Total CPI of All Threads
+system.cpu2.ipc 1.220975 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 1.220975 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 437605 # number of integer regfile reads
+system.cpu2.int_regfile_writes 204427 # number of integer regfile writes
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 119022 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 126238 # number of misc regfile reads
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 25.641689 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 42500 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 26.114184 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 45075 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 1416.666667 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 1502.500000 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 25.641689 # Average occupied blocks per requestor
-system.cpu2.dcache.tags.occ_percent::cpu2.data 0.050081 # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total 0.050081 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_blocks::cpu2.data 26.114184 # Average occupied blocks per requestor
+system.cpu2.dcache.tags.occ_percent::cpu2.data 0.051004 # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total 0.051004 # Average percentage of cache occupancy
system.cpu2.dcache.tags.occ_task_id_blocks::1024 30 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id
-system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 # Occupied blocks per task id
+system.cpu2.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 336580 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 336580 # Number of data accesses
-system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.cpu2.dcache.ReadReq_hits::cpu2.data 48215 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 48215 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 35154 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 35154 # number of WriteReq hits
+system.cpu2.dcache.tags.tag_accesses 355312 # Number of tag accesses
+system.cpu2.dcache.tags.data_accesses 355312 # Number of data accesses
+system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.cpu2.dcache.ReadReq_hits::cpu2.data 50364 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 50364 # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data 37691 # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total 37691 # number of WriteReq hits
system.cpu2.dcache.SwapReq_hits::cpu2.data 13 # number of SwapReq hits
system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 83369 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 83369 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 83369 # number of overall hits
-system.cpu2.dcache.overall_hits::total 83369 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 500 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 500 # number of ReadReq misses
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-system.cpu2.dcache.WriteReq_misses::total 145 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 645 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 645 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 645 # number of overall misses
-system.cpu2.dcache.overall_misses::total 645 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 8163500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 8163500 # number of ReadReq miss cycles
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-system.cpu2.dcache.WriteReq_miss_latency::total 3144500 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 806000 # number of SwapReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency::total 806000 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency::cpu2.data 11308000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.demand_miss_latency::total 11308000 # number of demand (read+write) miss cycles
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-system.cpu2.dcache.overall_miss_latency::total 11308000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 48715 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 48715 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 35299 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 35299 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 67 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses::cpu2.data 84014 # number of demand (read+write) accesses
-system.cpu2.dcache.demand_accesses::total 84014 # number of demand (read+write) accesses
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-system.cpu2.dcache.overall_accesses::total 84014 # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010264 # miss rate for ReadReq accesses
-system.cpu2.dcache.ReadReq_miss_rate::total 0.010264 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004108 # miss rate for WriteReq accesses
-system.cpu2.dcache.WriteReq_miss_rate::total 0.004108 # miss rate for WriteReq accesses
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-system.cpu2.dcache.SwapReq_miss_rate::total 0.805970 # miss rate for SwapReq accesses
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-system.cpu2.dcache.overall_miss_rate::total 0.007677 # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16327 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 16327 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 21686.206897 # average WriteReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency::total 21686.206897 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 14925.925926 # average SwapReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency::total 14925.925926 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency
-system.cpu2.dcache.demand_avg_miss_latency::total 17531.782946 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17531.782946 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency::total 17531.782946 # average overall miss latency
+system.cpu2.dcache.demand_hits::cpu2.data 88055 # number of demand (read+write) hits
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+system.cpu2.dcache.ReadReq_misses::total 498 # number of ReadReq misses
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+system.cpu2.dcache.WriteReq_misses::total 139 # number of WriteReq misses
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+system.cpu2.dcache.overall_misses::total 637 # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 3990000 # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total 3990000 # number of ReadReq miss cycles
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+system.cpu2.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses)
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+system.cpu2.dcache.demand_accesses::total 88692 # number of demand (read+write) accesses
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+system.cpu2.dcache.overall_accesses::total 88692 # number of overall (read+write) accesses
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+system.cpu2.dcache.ReadReq_miss_rate::total 0.009791 # miss rate for ReadReq accesses
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+system.cpu2.dcache.WriteReq_miss_rate::total 0.003674 # miss rate for WriteReq accesses
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+system.cpu2.dcache.SwapReq_miss_rate::total 0.816901 # miss rate for SwapReq accesses
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+system.cpu2.dcache.overall_miss_rate::total 0.007182 # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 8012.048193 # average ReadReq miss latency
+system.cpu2.dcache.ReadReq_avg_miss_latency::total 8012.048193 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20399.280576 # average WriteReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::total 20399.280576 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6318.965517 # average SwapReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::total 6318.965517 # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency
+system.cpu2.dcache.demand_avg_miss_latency::total 10715.070644 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10715.070644 # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::total 10715.070644 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 14869.713506 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14869.713506 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency::total 14869.713506 # average overall mshr miss latency
-system.cpu3.branchPred.lookups 61800 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 53939 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 2339 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 53501 # Number of BTB lookups
+system.cpu2.icache.writebacks::writebacks 578 # number of writebacks
+system.cpu2.icache.writebacks::total 578 # number of writebacks
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 127 # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total 127 # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst 127 # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total 127 # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst 127 # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total 127 # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 710 # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total 710 # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst 710 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total 710 # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst 710 # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total 710 # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10853000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total 10853000 # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10853000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total 10853000 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10853000 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 10853000 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.024843 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for demand accesses
+system.cpu2.icache.demand_mshr_miss_rate::total 0.024843 # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.024843 # mshr miss rate for overall accesses
+system.cpu2.icache.overall_mshr_miss_rate::total 0.024843 # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average ReadReq mshr miss latency
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 15285.915493 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 15285.915493 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::total 15285.915493 # average overall mshr miss latency
+system.cpu3.branchPred.lookups 58058 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 50256 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 2406 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 50211 # Number of BTB lookups
system.cpu3.branchPred.BTBHits 0 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu3.branchPred.BTBHitPct 0.000000 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 1989 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.usedRAS 1984 # Number of times the RAS was used to get a target.
system.cpu3.branchPred.RASInCorrect 231 # Number of incorrect RAS predictions.
-system.cpu3.branchPred.indirectLookups 53501 # Number of indirect predictor lookups.
-system.cpu3.branchPred.indirectHits 43109 # Number of indirect target hits.
-system.cpu3.branchPred.indirectMisses 10392 # Number of indirect misses.
-system.cpu3.branchPredindirectMispredicted 1225 # Number of mispredicted indirect branches.
-system.cpu3.pwrStateResidencyTicks::ON 124523000 # Cumulative time (in ticks) in various power states
-system.cpu3.numCycles 192748 # number of cpu cycles simulated
+system.cpu3.branchPred.indirectLookups 50211 # Number of indirect predictor lookups.
+system.cpu3.branchPred.indirectHits 39339 # Number of indirect target hits.
+system.cpu3.branchPred.indirectMisses 10872 # Number of indirect misses.
+system.cpu3.branchPredindirectMispredicted 1290 # Number of mispredicted indirect branches.
+system.cpu3.pwrStateResidencyTicks::ON 123936000 # Cumulative time (in ticks) in various power states
+system.cpu3.numCycles 191755 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 41262 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 329189 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 61800 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 45098 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 145688 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 4833 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.icacheStallCycles 44345 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 305380 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 58058 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 41323 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 141573 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 4965 # Number of cycles fetch has spent squashing
system.cpu3.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu3.fetch.NoActiveThreadStallCycles 10 # Number of stall cycles due to no active thread to fetch from
-system.cpu3.fetch.PendingTrapStallCycles 1762 # Number of stall cycles due to pending traps
-system.cpu3.fetch.CacheLines 30337 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 926 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.rateDist::samples 191141 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.722231 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.297340 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.PendingTrapStallCycles 1720 # Number of stall cycles due to pending traps
+system.cpu3.fetch.CacheLines 32940 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.rateDist::samples 190133 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.606139 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.261267 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 79632 41.66% 41.66% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 55527 29.05% 70.71% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 9457 4.95% 75.66% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3401 1.78% 77.44% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 679 0.36% 77.79% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 31347 16.40% 94.19% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 1154 0.60% 94.80% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 1382 0.72% 95.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 8562 4.48% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 84706 44.55% 44.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 53051 27.90% 72.45% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 10689 5.62% 78.07% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3433 1.81% 79.88% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 679 0.36% 80.24% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 26352 13.86% 94.10% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 1085 0.57% 94.67% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 1438 0.76% 95.42% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 8700 4.58% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 191141 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.320626 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 1.707872 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 22425 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 81552 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 79630 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 5108 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 2416 # Number of cycles decode is squashing
-system.cpu3.decode.DecodedInsts 297344 # Number of instructions handled by decode
-system.cpu3.rename.SquashCycles 2416 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 23427 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 40476 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 14673 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 80471 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 29668 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 290876 # Number of instructions processed by rename
-system.cpu3.rename.IQFullEvents 25659 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 14 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.RenamedOperands 201895 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 544124 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 425656 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 36 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 173837 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 28058 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 1657 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 1795 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 35428 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 77674 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 35638 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 37571 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 29275 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 234657 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 9848 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 236528 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 24579 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 19470 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 1266 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 191141 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 1.237453 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.372875 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 190133 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.302772 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 1.592553 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 22846 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 89002 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 70141 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 5652 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 2482 # Number of cycles decode is squashing
+system.cpu3.decode.DecodedInsts 273868 # Number of instructions handled by decode
+system.cpu3.rename.SquashCycles 2482 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 23847 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 45287 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 13384 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 70737 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 34386 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 267452 # Number of instructions processed by rename
+system.cpu3.rename.IQFullEvents 29592 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 13 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.RenamedOperands 184677 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 492576 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 387264 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 20 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 155405 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 29272 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 1682 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 1811 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 39856 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 69050 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 30771 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 33750 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 24332 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 213083 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 11008 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 216315 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 53 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 25213 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 19048 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 1289 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 190133 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 1.137704 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.357547 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 84630 44.28% 44.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 31019 16.23% 60.50% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 34273 17.93% 78.44% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 34156 17.87% 96.30% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 3613 1.89% 98.20% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 1675 0.88% 99.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 1066 0.56% 99.63% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 400 0.21% 99.84% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 309 0.16% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 89784 47.22% 47.22% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 34463 18.13% 65.35% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 29348 15.44% 80.78% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 29336 15.43% 96.21% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 3681 1.94% 98.15% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 1744 0.92% 99.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 1040 0.55% 99.61% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.84% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 305 0.16% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 191141 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 190133 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 176 38.18% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 38.18% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 50 10.85% 49.02% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 235 50.98% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 189 39.38% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 39.38% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 53 11.04% 50.42% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 238 49.58% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 117496 49.68% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.68% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 84415 35.69% 85.36% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 34617 14.64% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 109511 50.63% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 50.63% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 77010 35.60% 86.23% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 29794 13.77% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 236528 # Type of FU issued
-system.cpu3.iq.rate 1.227136 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 461 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.001949 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 664726 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 269047 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 232596 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.FU_type_0::total 216315 # Type of FU issued
+system.cpu3.iq.rate 1.128080 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 480 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.002219 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 623296 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 249298 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 212257 # Number of integer instruction queue wakeup accesses
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 72 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_writes 40 # Number of floating instruction queue writes
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 236989 # Number of integer alu accesses
+system.cpu3.iq.int_alu_accesses 216795 # Number of integer alu accesses
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 29180 # Number of loads that had data forwarded from stores
+system.cpu3.iew.lsq.thread0.forwLoads 24283 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 4384 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 35 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 2661 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 4403 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 27 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 34 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 2689 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 2416 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 11113 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 50 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 283276 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 77674 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 35638 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 1522 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 28 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewSquashCycles 2482 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 11408 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 259073 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 473 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 69050 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 30771 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 1541 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 26 # Number of times the IQ has become full, causing a stall
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 35 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 471 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 2483 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 2954 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 233943 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 76012 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 2585 # Number of squashed instructions skipped in execute
+system.cpu3.iew.memOrderViolationEvents 34 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 490 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 2580 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 3070 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 213662 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 67471 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 2653 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 38771 # number of nop insts executed
-system.cpu3.iew.exec_refs 110309 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 49060 # Number of branches executed
-system.cpu3.iew.exec_stores 34297 # Number of stores executed
-system.cpu3.iew.exec_rate 1.213725 # Inst execution rate
-system.cpu3.iew.wb_sent 233093 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 232596 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 128296 # num instructions producing a value
-system.cpu3.iew.wb_consumers 135910 # num instructions consuming a value
-system.cpu3.iew.wb_rate 1.206736 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.943978 # average fanout of values written-back
-system.cpu3.commit.commitSquashedInsts 25736 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 8582 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 2339 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 186297 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 1.382277 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.944418 # Number of insts commited each cycle
+system.cpu3.iew.exec_nop 34982 # number of nop insts executed
+system.cpu3.iew.exec_refs 96956 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 45328 # Number of branches executed
+system.cpu3.iew.exec_stores 29485 # Number of stores executed
+system.cpu3.iew.exec_rate 1.114245 # Inst execution rate
+system.cpu3.iew.wb_sent 212766 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 212257 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 115033 # num instructions producing a value
+system.cpu3.iew.wb_consumers 122695 # num instructions consuming a value
+system.cpu3.iew.wb_rate 1.106918 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.937552 # average fanout of values written-back
+system.cpu3.commit.commitSquashedInsts 26335 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 9719 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 2406 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 185183 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 1.256660 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.878907 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 92574 49.69% 49.69% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 45329 24.33% 74.02% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 5460 2.93% 76.95% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 9239 4.96% 81.91% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 1287 0.69% 82.60% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 29468 15.82% 98.42% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 712 0.38% 98.80% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 1036 0.56% 99.36% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 1192 0.64% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 99076 53.50% 53.50% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 41559 22.44% 75.94% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 5388 2.91% 78.85% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 10319 5.57% 84.43% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 1252 0.68% 85.10% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 24567 13.27% 98.37% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 787 0.42% 98.79% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 1025 0.55% 99.35% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 1210 0.65% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 186297 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 257514 # Number of instructions committed
-system.cpu3.commit.committedOps 257514 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 185183 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 232712 # Number of instructions committed
+system.cpu3.commit.committedOps 232712 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 106267 # Number of memory references committed
-system.cpu3.commit.loads 73290 # Number of loads committed
-system.cpu3.commit.membars 7865 # Number of memory barriers committed
-system.cpu3.commit.branches 46801 # Number of branches committed
+system.cpu3.commit.refs 92729 # Number of memory references committed
+system.cpu3.commit.loads 64647 # Number of loads committed
+system.cpu3.commit.membars 9005 # Number of memory barriers committed
+system.cpu3.commit.branches 43044 # Number of branches committed
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 175188 # Number of committed integer instructions.
+system.cpu3.commit.int_insts 157897 # Number of committed integer instructions.
system.cpu3.commit.function_calls 322 # Number of function calls committed.
-system.cpu3.commit.op_class_0::No_OpClass 37588 14.60% 14.60% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 105794 41.08% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.68% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 81155 31.51% 87.19% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 32977 12.81% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::No_OpClass 33834 14.54% 14.54% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 97144 41.74% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 0 0.00% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 0 0.00% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 56.28% # Class of committed instruction
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+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 56.28% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 56.28% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 56.28% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 56.28% # Class of committed instruction
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+system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 56.28% # Class of committed instruction
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+system.cpu3.commit.op_class_0::MemWrite 28082 12.07% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 257514 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 1192 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 467769 # The number of ROB reads
-system.cpu3.rob.rob_writes 571412 # The number of ROB writes
-system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1607 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.commit.op_class_0::total 232712 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 1210 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 442434 # The number of ROB reads
+system.cpu3.rob.rob_writes 523106 # The number of ROB writes
+system.cpu3.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1622 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 48179 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 212061 # Number of Instructions Simulated
-system.cpu3.committedOps 212061 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 0.908927 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 0.908927 # CPI: Total CPI of All Threads
-system.cpu3.ipc 1.100198 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 1.100198 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 395124 # number of integer regfile reads
-system.cpu3.int_regfile_writes 185063 # number of integer regfile writes
+system.cpu3.committedInsts 189873 # Number of Instructions Simulated
+system.cpu3.committedOps 189873 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.009912 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.009912 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.990185 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.990185 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 355771 # number of integer regfile reads
+system.cpu3.int_regfile_writes 167240 # number of integer regfile writes
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
-system.cpu3.misc_regfile_reads 112177 # number of misc regfile reads
+system.cpu3.misc_regfile_reads 98845 # number of misc regfile reads
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
-system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
system.cpu3.dcache.tags.replacements 0 # number of replacements
-system.cpu3.dcache.tags.tagsinuse 24.465247 # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs 40069 # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs 1381.689655 # Average number of references to valid blocks.
+system.cpu3.dcache.tags.tagsinuse 24.519752 # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs 35385 # Total number of references to valid blocks.
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+system.cpu3.dcache.tags.avg_refs 1179.500000 # Average number of references to valid blocks.
system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
-system.cpu3.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu3.dcache.tags.tag_accesses 319388 # Number of tag accesses
-system.cpu3.dcache.tags.data_accesses 319388 # Number of data accesses
-system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.ReadReq_hits::cpu3.data 46353 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 46353 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 32769 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 32769 # number of WriteReq hits
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-system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
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-system.cpu3.dcache.overall_hits::total 79122 # number of overall hits
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-system.cpu3.dcache.ReadReq_misses::total 454 # number of ReadReq misses
+system.cpu3.dcache.tags.occ_blocks::cpu3.data 24.519752 # Average occupied blocks per requestor
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system.cpu3.dcache.WriteReq_misses::total 137 # number of WriteReq misses
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-system.cpu3.dcache.SwapReq_miss_rate::total 0.788732 # miss rate for SwapReq accesses
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-system.cpu3.dcache.overall_miss_rate::total 0.007414 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 15410.792952 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 15410.792952 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 21587.591241 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 21587.591241 # average WriteReq miss latency
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-system.cpu3.dcache.SwapReq_avg_miss_latency::total 13758.928571 # average SwapReq miss latency
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-system.cpu3.dcache.demand_avg_miss_latency::total 16842.639594 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 16842.639594 # average overall miss latency
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system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses
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-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003461 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003461 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003100 # mshr miss rate for WriteReq accesses
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-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003312 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.003312 # mshr miss rate for demand accesses
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system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
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system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
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+system.membus.reqLayer0.occupancy 877500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
+system.membus.respLayer1.occupancy 3778750 # Layer occupancy (ticks)
+system.membus.respLayer1.utilization 3.0 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 6322 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 1727 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 3289 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 124523000 # Cumulative time (in ticks) in various power states
-system.toL2Bus.trans_dist::ReadResp 3517 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 9 # Transaction distribution
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 123936000 # Cumulative time (in ticks) in various power states
+system.toL2Bus.trans_dist::ReadResp 3509 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
-system.toL2Bus.trans_dist::WritebackClean 2134 # Transaction distribution
+system.toL2Bus.trans_dist::WritebackClean 2125 # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict 1 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 277 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 277 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 403 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 403 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 2843 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 684 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1785 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 593 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2005 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 2064 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1965 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 9526 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 69696 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.trans_dist::UpgradeReq 284 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 284 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 398 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 398 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 2823 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 690 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1838 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 602 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1930 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 372 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1998 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 378 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2004 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 362 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 9484 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 72000 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11264 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 82688 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1728 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 85184 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 79552 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 82432 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1664 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 80896 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 82624 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1600 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 334720 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1023 # Total snoops (count)
-system.toL2Bus.snoopTraffic 53376 # Total snoop traffic (bytes)
-system.toL2Bus.snoop_fanout::samples 4207 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.289042 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.099056 # Request fanout histogram
+system.toL2Bus.pkt_size::total 332800 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1032 # Total snoops (count)
+system.toL2Bus.snoopTraffic 53504 # Total snoop traffic (bytes)
+system.toL2Bus.snoop_fanout::samples 4195 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.291538 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.103863 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 1302 30.95% 30.95% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 1193 28.36% 59.31% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 906 21.54% 80.84% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 806 19.16% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 1306 31.13% 31.13% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1176 28.03% 59.17% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 897 21.38% 80.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 816 19.45% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
@@ -2907,24 +2870,24 @@ system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Re
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4207 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 5321969 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 4195 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 5296980 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1043498 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 522987 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1068997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.9 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 528987 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 1072493 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.9 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 443462 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 1032995 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.8 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 438456 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.4 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 1103489 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 1069486 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.9 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 430971 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 1053495 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 0.8 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 426466 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 439965 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 0.4 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 1070997 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 0.9 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 415480 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.3 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 5019ecb02..fb2ceaeb2 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu
sim_ticks 87707000 # Number of ticks simulated
final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 807732 # Simulator instruction rate (inst/s)
-host_op_rate 807715 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 104588000 # Simulator tick rate (ticks/s)
-host_mem_usage 259108 # Number of bytes of host memory used
-host_seconds 0.84 # Real time elapsed on the host
+host_inst_rate 428563 # Simulator instruction rate (inst/s)
+host_op_rate 428559 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55493138 # Simulator tick rate (ticks/s)
+host_mem_usage 263740 # Number of bytes of host memory used
+host_seconds 1.58 # Real time elapsed on the host
sim_insts 677333 # Number of instructions simulated
sim_ops 677333 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -749,43 +749,44 @@ system.cpu3.icache.writebacks::writebacks 279 # n
system.cpu3.icache.writebacks::total 279 # number of writebacks
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements 0 # number of replacements
-system.l2c.tags.tagsinuse 367.545675 # Cycle average of tags in use
-system.l2c.tags.total_refs 1716 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 422 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 4.066351 # Average number of references to valid blocks.
+system.l2c.tags.tagsinuse 498.606697 # Cycle average of tags in use
+system.l2c.tags.total_refs 1799 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 559 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 3.218247 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 56.170311 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 153.517433 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 59.512205 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 6.721185 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 19.205787 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1.942787 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 0.935416 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 12.182505 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu3.inst 0.965459 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 0.905646 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu3.data 11.854293 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.000857 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.002342 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.000293 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.000030 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.000186 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.005608 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1024 422 # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu3.data 0.000181 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.007608 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 559 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1024 0.006439 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 19424 # Number of tag accesses
-system.l2c.tags.data_accesses 19424 # Number of data accesses
+system.l2c.tags.age_task_id_blocks_1024::1 511 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.008530 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 19423 # Number of tag accesses
+system.l2c.tags.data_accesses 19423 # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks 1 # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total 1 # number of WritebackDirty hits
system.l2c.WritebackClean_hits::writebacks 495 # number of WritebackClean hits
system.l2c.WritebackClean_hits::total 495 # number of WritebackClean hits
-system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data 30 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 17 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data 19 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 82 # number of UpgradeReq hits
system.l2c.ReadCleanReq_hits::cpu0.inst 185 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu1.inst 296 # number of ReadCleanReq hits
system.l2c.ReadCleanReq_hits::cpu2.inst 355 # number of ReadCleanReq hits
@@ -814,11 +815,6 @@ system.l2c.overall_hits::cpu2.data 9 # nu
system.l2c.overall_hits::cpu3.inst 358 # number of overall hits
system.l2c.overall_hits::cpu3.data 9 # number of overall hits
system.l2c.overall_hits::total 1220 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 16 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
@@ -894,11 +890,6 @@ system.l2c.overall_accesses::cpu2.data 22 # nu
system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.975610 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
@@ -938,35 +929,34 @@ system.l2c.blocked::no_mshrs 0 # nu
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.membus.snoop_filter.tot_requests 879 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 320 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 799 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 240 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 87707000 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 423 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 273 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 80 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 193 # Transaction distribution
system.membus.trans_dist::ReadExReq 183 # Transaction distribution
system.membus.trans_dist::ReadExResp 136 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 423 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1518 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1518 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1358 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1358 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 35776 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 879 # Request fanout histogram
+system.membus.snoop_fanout::samples 799 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 879 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 799 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 879 # Request fanout histogram
+system.membus.snoop_fanout::total 799 # Request fanout histogram
system.toL2Bus.snoop_filter.tot_requests 3918 # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests 1221 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests 1709 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
index 78f5a0ee7..c1353f29d 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
@@ -1,94 +1,94 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000264 # Number of seconds simulated
-sim_ticks 264174500 # Number of ticks simulated
-final_tick 264174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000263 # Number of seconds simulated
+sim_ticks 263409500 # Number of ticks simulated
+final_tick 263409500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 538178 # Simulator instruction rate (inst/s)
-host_op_rate 538161 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 214299964 # Simulator tick rate (ticks/s)
-host_mem_usage 259104 # Number of bytes of host memory used
-host_seconds 1.23 # Real time elapsed on the host
-sim_insts 663394 # Number of instructions simulated
-sim_ops 663394 # Number of ops (including micro ops) simulated
+host_inst_rate 389943 # Simulator instruction rate (inst/s)
+host_op_rate 389940 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 154718592 # Simulator tick rate (ticks/s)
+host_mem_usage 263736 # Number of bytes of host memory used
+host_seconds 1.70 # Real time elapsed on the host
+sim_insts 663871 # Number of instructions simulated
+sim_ops 663871 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 3712 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1472 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 640 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 3712 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 58 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 23 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 572 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 69045271 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 39973578 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 1695849 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 3633962 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 14051318 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 5572075 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 969056 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 3633962 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 138575071 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 69045271 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 1695849 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 14051318 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 969056 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 85761495 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 69045271 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 39973578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 1695849 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 3633962 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 14051318 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 5572075 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 969056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 3633962 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 138575071 # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.physmem.bw_read::cpu0.inst 69245794 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 40089670 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 2429677 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 3644515 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 14092127 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 5588257 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 242968 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 3644515 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 138977524 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 69245794 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 2429677 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 14092127 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 242968 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 86010565 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 69245794 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 40089670 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 2429677 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 3644515 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 14092127 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 5588257 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 242968 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 3644515 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 138977524 # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.workload.num_syscalls 89 # Number of system calls
-system.cpu0.pwrStateResidencyTicks::ON 264174500 # Cumulative time (in ticks) in various power states
-system.cpu0.numCycles 528349 # number of cpu cycles simulated
+system.cpu0.pwrStateResidencyTicks::ON 263409500 # Cumulative time (in ticks) in various power states
+system.cpu0.numCycles 526819 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 158268 # Number of instructions committed
-system.cpu0.committedOps 158268 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 109004 # Number of integer alu accesses
+system.cpu0.committedInsts 158244 # Number of instructions committed
+system.cpu0.committedOps 158244 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 108988 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 25981 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 109004 # number of integer instructions
+system.cpu0.num_conditional_control_insts 25977 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 108988 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 315170 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 110610 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 315122 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 110594 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 73868 # number of memory refs
-system.cpu0.num_load_insts 48905 # Number of load instructions
-system.cpu0.num_store_insts 24963 # Number of store instructions
+system.cpu0.num_mem_refs 73856 # number of memory refs
+system.cpu0.num_load_insts 48897 # Number of load instructions
+system.cpu0.num_store_insts 24959 # Number of store instructions
system.cpu0.num_idle_cycles 0.002000 # Number of idle cycles
-system.cpu0.num_busy_cycles 528348.998000 # Number of busy cycles
+system.cpu0.num_busy_cycles 526818.998000 # Number of busy cycles
system.cpu0.not_idle_fraction 1.000000 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.000000 # Percentage of idle cycles
-system.cpu0.Branches 26846 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 23573 14.89% 14.89% # Class of executed instruction
-system.cpu0.op_class::IntAlu 60805 38.40% 53.29% # Class of executed instruction
+system.cpu0.Branches 26842 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 23569 14.89% 14.89% # Class of executed instruction
+system.cpu0.op_class::IntAlu 60797 38.40% 53.29% # Class of executed instruction
system.cpu0.op_class::IntMult 0 0.00% 53.29% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 53.29% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 53.29% # Class of executed instruction
@@ -117,38 +117,38 @@ system.cpu0.op_class::SimdFloatMisc 0 0.00% 53.29% # Cl
system.cpu0.op_class::SimdFloatMult 0 0.00% 53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 53.29% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 53.29% # Class of executed instruction
-system.cpu0.op_class::MemRead 48989 30.94% 84.23% # Class of executed instruction
-system.cpu0.op_class::MemWrite 24963 15.77% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 48981 30.94% 84.23% # Class of executed instruction
+system.cpu0.op_class::MemWrite 24959 15.77% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 158330 # Class of executed instruction
-system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.cpu0.op_class::total 158306 # Class of executed instruction
+system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements 2 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 144.970648 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 73336 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.tagsinuse 144.946606 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 73324 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 167 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 439.137725 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 439.065868 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.970648 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283146 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.283146 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 144.946606 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.283099 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.283099 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 165 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 149 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.322266 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 295705 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 295705 # Number of data accesses
-system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
-system.cpu0.dcache.ReadReq_hits::cpu0.data 48725 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 48725 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 24729 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 24729 # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses 295657 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 295657 # Number of data accesses
+system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
+system.cpu0.dcache.ReadReq_hits::cpu0.data 48717 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 48717 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 24725 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 24725 # number of WriteReq hits
system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits
system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 73454 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 73454 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 73454 # number of overall hits
-system.cpu0.dcache.overall_hits::total 73454 # number of overall hits
+system.cpu0.dcache.demand_hits::cpu0.data 73442 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 73442 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 73442 # number of overall hits
+system.cpu0.dcache.overall_hits::total 73442 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 170 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 170 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses
@@ -159,46 +159,46 @@ system.cpu0.dcache.demand_misses::cpu0.data 353 #
system.cpu0.dcache.demand_misses::total 353 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 353 # number of overall misses
system.cpu0.dcache.overall_misses::total 353 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4908500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4908500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7106500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 7106500 # number of WriteReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4701000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 4701000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 6585500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 6585500 # number of WriteReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 400000 # number of SwapReq miss cycles
system.cpu0.dcache.SwapReq_miss_latency::total 400000 # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 12015000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 12015000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 12015000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 12015000 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 48895 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 48895 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 24912 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 24912 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.demand_miss_latency::cpu0.data 11286500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 11286500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 11286500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 11286500 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 48887 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 48887 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 24908 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 73807 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 73807 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 73807 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 73807 # number of overall (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 73795 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 73795 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 73795 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 73795 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003477 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.003477 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007346 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.007346 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007347 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.007347 # miss rate for WriteReq accesses
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004783 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.004783 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004783 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.004783 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28873.529412 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 28873.529412 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38833.333333 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 38833.333333 # average WriteReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004784 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.004784 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004784 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.004784 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27652.941176 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 27652.941176 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35986.338798 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 35986.338798 # average WriteReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 15384.615385 # average SwapReq miss latency
system.cpu0.dcache.SwapReq_avg_miss_latency::total 15384.615385 # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 34036.827195 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34036.827195 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34036.827195 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 31973.087819 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 31973.087819 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 31973.087819 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -217,89 +217,89 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 353
system.cpu0.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 353 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4738500 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6402500 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 374000 # number of SwapReq MSHR miss cycles
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 374000 # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11662000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 11662000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11662000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 11662000 # number of overall MSHR miss cycles
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+system.cpu0.dcache.demand_mshr_miss_latency::total 10933500 # number of demand (read+write) MSHR miss cycles
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system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003477 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003477 # mshr miss rate for ReadReq accesses
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-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007346 # mshr miss rate for WriteReq accesses
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system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses
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-system.cpu0.dcache.demand_mshr_miss_rate::total 0.004783 # mshr miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27873.529412 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37833.333333 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 37833.333333 # average WriteReq mshr miss latency
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system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 14384.615385 # average SwapReq mshr miss latency
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 14384.615385 # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 33036.827195 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 33036.827195 # average overall mshr miss latency
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+system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements 215 # number of replacements
-system.cpu0.icache.tags.tagsinuse 211.220090 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 157864 # Total number of references to valid blocks.
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system.cpu0.icache.tags.sampled_refs 467 # Sample count of references to valid blocks.
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system.cpu0.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu0.icache.tags.occ_percent::total 0.412539 # Average percentage of cache occupancy
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system.cpu0.icache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 0.492188 # Percentage of cache occupancy per task id
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system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002950 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.002950 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002950 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.002950 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002950 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.002950 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 43739.828694 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 43739.828694 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 43739.828694 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 43739.828694 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 43739.828694 # average overall miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::total 43738.758030 # average ReadReq miss latency
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+system.cpu0.icache.overall_avg_miss_latency::total 43738.758030 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -314,260 +314,260 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467
system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
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system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002950 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.002950 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002950 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.002950 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42739.828694 # average ReadReq mshr miss latency
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-system.cpu1.numCycles 528348 # number of cpu cycles simulated
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42738.758030 # average ReadReq mshr miss latency
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 170000 # Number of instructions committed
-system.cpu1.committedOps 170000 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 111041 # Number of integer alu accesses
+system.cpu1.committedInsts 169340 # Number of instructions committed
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system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 637 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 33487 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 111041 # number of integer instructions
+system.cpu1.num_conditional_control_insts 32946 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 111465 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 272446 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 102959 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 276307 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 104671 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 53722 # number of memory refs
-system.cpu1.num_load_insts 41185 # Number of load instructions
-system.cpu1.num_store_insts 12537 # Number of store instructions
-system.cpu1.num_idle_cycles 74693.860345 # Number of idle cycles
-system.cpu1.num_busy_cycles 453654.139655 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.858628 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.141372 # Percentage of idle cycles
-system.cpu1.Branches 35142 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 25921 15.24% 15.24% # Class of executed instruction
-system.cpu1.op_class::IntAlu 74786 43.98% 59.23% # Class of executed instruction
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-system.cpu1.op_class::FloatAdd 0 0.00% 59.23% # Class of executed instruction
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-system.cpu1.op_class::FloatSqrt 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 59.23% # Class of executed instruction
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-system.cpu1.op_class::SimdMultAcc 0 0.00% 59.23% # Class of executed instruction
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-system.cpu1.op_class::SimdShiftAcc 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 59.23% # Class of executed instruction
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-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 59.23% # Class of executed instruction
-system.cpu1.op_class::MemRead 56788 33.40% 92.63% # Class of executed instruction
-system.cpu1.op_class::MemWrite 12537 7.37% 100.00% # Class of executed instruction
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+system.cpu1.num_busy_cycles 452159.140000 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.858283 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.141717 # Percentage of idle cycles
+system.cpu1.Branches 34599 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 25380 14.98% 14.98% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 170032 # Class of executed instruction
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+system.cpu1.op_class::total 169372 # Class of executed instruction
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system.cpu1.dcache.tags.replacements 0 # number of replacements
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-system.cpu1.dcache.tags.sampled_refs 30 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 915.766667 # Average number of references to valid blocks.
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system.cpu1.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
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system.cpu1.dcache.SwapReq_hits::cpu1.data 13 # number of SwapReq hits
system.cpu1.dcache.SwapReq_hits::total 13 # number of SwapReq hits
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system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses
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+system.cpu1.dcache.demand_avg_miss_latency::total 9511.152416 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 9511.152416 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
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-system.cpu1.dcache.overall_mshr_miss_latency::total 3360000 # number of overall MSHR miss cycles
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10301.775148 # average ReadReq mshr miss latency
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-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3491.379310 # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12262.773723 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12262.773723 # average overall mshr miss latency
-system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
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system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -582,260 +582,260 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366
system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
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system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written
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+system.cpu2.op_class::SimdFloatMultAcc 0 0.00% 59.45% # Class of executed instruction
+system.cpu2.op_class::SimdFloatSqrt 0 0.00% 59.45% # Class of executed instruction
+system.cpu2.op_class::MemRead 53070 31.98% 91.44% # Class of executed instruction
+system.cpu2.op_class::MemWrite 14205 8.56% 100.00% # Class of executed instruction
system.cpu2.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu2.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu2.op_class::total 165719 # Class of executed instruction
-system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.cpu2.op_class::total 165924 # Class of executed instruction
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system.cpu2.dcache.tags.replacements 0 # number of replacements
-system.cpu2.dcache.tags.tagsinuse 27.447331 # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs 30642 # Total number of references to valid blocks.
+system.cpu2.dcache.tags.tagsinuse 27.420509 # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs 30687 # Total number of references to valid blocks.
system.cpu2.dcache.tags.sampled_refs 29 # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs 1056.620690 # Average number of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs 1058.172414 # Average number of references to valid blocks.
system.cpu2.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.tags.occ_blocks::cpu2.data 27.447331 # Average occupied blocks per requestor
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-system.cpu2.dcache.tags.occ_percent::total 0.053608 # Average percentage of cache occupancy
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system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id
system.cpu2.dcache.tags.age_task_id_blocks_1024::2 26 # Occupied blocks per task id
system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 # Percentage of cache occupancy per task id
-system.cpu2.dcache.tags.tag_accesses 220669 # Number of tag accesses
-system.cpu2.dcache.tags.data_accesses 220669 # Number of data accesses
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-system.cpu2.dcache.ReadReq_hits::cpu2.data 40751 # number of ReadReq hits
-system.cpu2.dcache.ReadReq_hits::total 40751 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits::cpu2.data 14004 # number of WriteReq hits
-system.cpu2.dcache.WriteReq_hits::total 14004 # number of WriteReq hits
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-system.cpu2.dcache.SwapReq_hits::total 12 # number of SwapReq hits
-system.cpu2.dcache.demand_hits::cpu2.data 54755 # number of demand (read+write) hits
-system.cpu2.dcache.demand_hits::total 54755 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits::cpu2.data 54755 # number of overall hits
-system.cpu2.dcache.overall_hits::total 54755 # number of overall hits
-system.cpu2.dcache.ReadReq_misses::cpu2.data 169 # number of ReadReq misses
-system.cpu2.dcache.ReadReq_misses::total 169 # number of ReadReq misses
+system.cpu2.dcache.tags.tag_accesses 221019 # Number of tag accesses
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+system.cpu2.dcache.ReadReq_hits::cpu2.data 40826 # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total 40826 # number of ReadReq hits
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+system.cpu2.dcache.SwapReq_hits::total 13 # number of SwapReq hits
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+system.cpu2.dcache.overall_hits::total 54855 # number of overall hits
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system.cpu2.dcache.WriteReq_misses::cpu2.data 105 # number of WriteReq misses
system.cpu2.dcache.WriteReq_misses::total 105 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses::cpu2.data 60 # number of SwapReq misses
-system.cpu2.dcache.SwapReq_misses::total 60 # number of SwapReq misses
-system.cpu2.dcache.demand_misses::cpu2.data 274 # number of demand (read+write) misses
-system.cpu2.dcache.demand_misses::total 274 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses::cpu2.data 274 # number of overall misses
-system.cpu2.dcache.overall_misses::total 274 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2144500 # number of ReadReq miss cycles
-system.cpu2.dcache.ReadReq_miss_latency::total 2144500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1802500 # number of WriteReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency::total 1802500 # number of WriteReq miss cycles
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-system.cpu2.dcache.overall_miss_latency::total 3947000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses::cpu2.data 40920 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.ReadReq_accesses::total 40920 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::cpu2.data 14109 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses::total 14109 # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::cpu2.data 72 # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
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-system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12689.349112 # average ReadReq miss latency
-system.cpu2.dcache.ReadReq_avg_miss_latency::total 12689.349112 # average ReadReq miss latency
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-system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14405.109489 # average overall miss latency
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+system.cpu2.dcache.demand_avg_miss_latency::total 10838.951311 # average overall miss latency
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+system.cpu2.dcache.overall_avg_miss_latency::total 10838.951311 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu2.dcache.ReadReq_mshr_misses::total 169 # number of ReadReq MSHR misses
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system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses
system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
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-system.cpu2.dcache.SwapReq_mshr_misses::total 60 # number of SwapReq MSHR misses
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-system.cpu2.dcache.overall_mshr_misses::total 274 # number of overall MSHR misses
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-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16166.666667 # average WriteReq mshr miss latency
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-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3458.333333 # average SwapReq mshr miss latency
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-system.cpu2.dcache.demand_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 13405.109489 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency::total 13405.109489 # average overall mshr miss latency
-system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
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+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 7697.530864 # average ReadReq mshr miss latency
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+system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9838.951311 # average overall mshr miss latency
+system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.cpu2.icache.tags.replacements 280 # number of replacements
-system.cpu2.icache.tags.tagsinuse 69.258301 # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs 165354 # Total number of references to valid blocks.
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system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@@ -850,260 +850,260 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 366
system.cpu2.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses
system.cpu2.icache.overall_mshr_misses::cpu2.inst 366 # number of overall MSHR misses
system.cpu2.icache.overall_mshr_misses::total 366 # number of overall MSHR misses
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-system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average ReadReq mshr miss latency
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-system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21310.109290 # average overall mshr miss latency
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+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 21306.010929 # average overall mshr miss latency
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu3.num_func_calls 637 # number of times a function call or return occured
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system.cpu3.num_fp_insts 0 # number of float instructions
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system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu3.dcache.tags.replacements 0 # number of replacements
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system.cpu3.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
-system.cpu3.dcache.ReadReq_hits::cpu3.data 41179 # number of ReadReq hits
-system.cpu3.dcache.ReadReq_hits::total 41179 # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits::cpu3.data 12939 # number of WriteReq hits
-system.cpu3.dcache.WriteReq_hits::total 12939 # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits
-system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits
-system.cpu3.dcache.demand_hits::cpu3.data 54118 # number of demand (read+write) hits
-system.cpu3.dcache.demand_hits::total 54118 # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits::cpu3.data 54118 # number of overall hits
-system.cpu3.dcache.overall_hits::total 54118 # number of overall hits
-system.cpu3.dcache.ReadReq_misses::cpu3.data 151 # number of ReadReq misses
-system.cpu3.dcache.ReadReq_misses::total 151 # number of ReadReq misses
+system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 # Percentage of cache occupancy per task id
+system.cpu3.dcache.tags.tag_accesses 214417 # Number of tag accesses
+system.cpu3.dcache.tags.data_accesses 214417 # Number of data accesses
+system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.ReadReq_hits::cpu3.data 41020 # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total 41020 # number of ReadReq hits
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+system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
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+system.cpu3.dcache.overall_hits::total 53200 # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data 163 # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total 163 # number of ReadReq misses
system.cpu3.dcache.WriteReq_misses::cpu3.data 105 # number of WriteReq misses
system.cpu3.dcache.WriteReq_misses::total 105 # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses::cpu3.data 52 # number of SwapReq misses
-system.cpu3.dcache.SwapReq_misses::total 52 # number of SwapReq misses
-system.cpu3.dcache.demand_misses::cpu3.data 256 # number of demand (read+write) misses
-system.cpu3.dcache.demand_misses::total 256 # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses::cpu3.data 256 # number of overall misses
-system.cpu3.dcache.overall_misses::total 256 # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1675000 # number of ReadReq miss cycles
-system.cpu3.dcache.ReadReq_miss_latency::total 1675000 # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1736000 # number of WriteReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency::total 1736000 # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 234000 # number of SwapReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency::total 234000 # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency::cpu3.data 3411000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.demand_miss_latency::total 3411000 # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency::cpu3.data 3411000 # number of overall miss cycles
-system.cpu3.dcache.overall_miss_latency::total 3411000 # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses::cpu3.data 41330 # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.ReadReq_accesses::total 41330 # number of ReadReq accesses(hits+misses)
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-system.cpu3.dcache.WriteReq_accesses::total 13044 # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses::cpu3.data 54374 # number of demand (read+write) accesses
-system.cpu3.dcache.demand_accesses::total 54374 # number of demand (read+write) accesses
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-system.cpu3.dcache.overall_accesses::total 54374 # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003654 # miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_miss_rate::total 0.003654 # miss rate for ReadReq accesses
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-system.cpu3.dcache.WriteReq_miss_rate::total 0.008050 # miss rate for WriteReq accesses
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-system.cpu3.dcache.SwapReq_miss_rate::total 0.776119 # miss rate for SwapReq accesses
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-system.cpu3.dcache.demand_miss_rate::total 0.004708 # miss rate for demand accesses
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-system.cpu3.dcache.overall_miss_rate::total 0.004708 # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 11092.715232 # average ReadReq miss latency
-system.cpu3.dcache.ReadReq_avg_miss_latency::total 11092.715232 # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16533.333333 # average WriteReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency::total 16533.333333 # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 4500 # average SwapReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency::total 4500 # average SwapReq miss latency
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-system.cpu3.dcache.demand_avg_miss_latency::total 13324.218750 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13324.218750 # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency::total 13324.218750 # average overall miss latency
+system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
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+system.cpu3.dcache.demand_misses::total 268 # number of demand (read+write) misses
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+system.cpu3.dcache.overall_misses::total 268 # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 1141000 # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total 1141000 # number of ReadReq miss cycles
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+system.cpu3.dcache.WriteReq_miss_latency::total 1445000 # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 263000 # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total 263000 # number of SwapReq miss cycles
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+system.cpu3.dcache.demand_miss_latency::total 2586000 # number of demand (read+write) miss cycles
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+system.cpu3.dcache.overall_miss_latency::total 2586000 # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data 41183 # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total 41183 # number of ReadReq accesses(hits+misses)
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+system.cpu3.dcache.demand_accesses::total 53468 # number of demand (read+write) accesses
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+system.cpu3.dcache.overall_accesses::total 53468 # number of overall (read+write) accesses
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+system.cpu3.dcache.ReadReq_miss_rate::total 0.003958 # miss rate for ReadReq accesses
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+system.cpu3.dcache.WriteReq_miss_rate::total 0.008547 # miss rate for WriteReq accesses
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+system.cpu3.dcache.demand_miss_rate::total 0.005012 # miss rate for demand accesses
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+system.cpu3.dcache.overall_miss_rate::total 0.005012 # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7000 # average ReadReq miss latency
+system.cpu3.dcache.ReadReq_avg_miss_latency::total 7000 # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 13761.904762 # average WriteReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::total 13761.904762 # average WriteReq miss latency
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+system.cpu3.dcache.SwapReq_avg_miss_latency::total 4534.482759 # average SwapReq miss latency
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+system.cpu3.dcache.demand_avg_miss_latency::total 9649.253731 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 9649.253731 # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::total 9649.253731 # average overall miss latency
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 151 # number of ReadReq MSHR misses
-system.cpu3.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 105 # number of WriteReq MSHR misses
system.cpu3.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 52 # number of SwapReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses::cpu3.data 256 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses::cpu3.data 256 # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_misses::total 256 # number of overall MSHR misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1524000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1524000 # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1631000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1631000 # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 182000 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency::total 182000 # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3155000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency::total 3155000 # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3155000 # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency::total 3155000 # number of overall MSHR miss cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003654 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003654 # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008050 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.008050 # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.776119 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.776119 # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for demand accesses
-system.cpu3.dcache.demand_mshr_miss_rate::total 0.004708 # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004708 # mshr miss rate for overall accesses
-system.cpu3.dcache.overall_mshr_miss_rate::total 0.004708 # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 10092.715232 # average ReadReq mshr miss latency
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 10092.715232 # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15533.333333 # average WriteReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15533.333333 # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3500 # average SwapReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3500 # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12324.218750 # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12324.218750 # average overall mshr miss latency
-system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
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+system.cpu3.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses
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+system.cpu3.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 978000 # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total 978000 # number of ReadReq MSHR miss cycles
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+system.cpu3.dcache.SwapReq_mshr_miss_latency::total 205000 # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2318000 # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total 2318000 # number of demand (read+write) MSHR miss cycles
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+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003958 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003958 # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.008547 # mshr miss rate for WriteReq accesses
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+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005012 # mshr miss rate for demand accesses
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+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 6000 # average ReadReq mshr miss latency
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 6000 # average ReadReq mshr miss latency
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+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 12761.904762 # average WriteReq mshr miss latency
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+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 8649.253731 # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::total 8649.253731 # average overall mshr miss latency
+system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.cpu3.icache.tags.replacements 281 # number of replacements
-system.cpu3.icache.tags.tagsinuse 64.834449 # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs 169105 # Total number of references to valid blocks.
+system.cpu3.icache.tags.tagsinuse 64.803703 # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs 170061 # Total number of references to valid blocks.
system.cpu3.icache.tags.sampled_refs 367 # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs 460.776567 # Average number of references to valid blocks.
+system.cpu3.icache.tags.avg_refs 463.381471 # Average number of references to valid blocks.
system.cpu3.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.834449 # Average occupied blocks per requestor
-system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126630 # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total 0.126630 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_blocks::cpu3.inst 64.803703 # Average occupied blocks per requestor
+system.cpu3.icache.tags.occ_percent::cpu3.inst 0.126570 # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total 0.126570 # Average percentage of cache occupancy
system.cpu3.icache.tags.occ_task_id_blocks::1024 86 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
-system.cpu3.icache.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id
+system.cpu3.icache.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id
system.cpu3.icache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
system.cpu3.icache.tags.occ_task_id_percent::1024 0.167969 # Percentage of cache occupancy per task id
-system.cpu3.icache.tags.tag_accesses 169839 # Number of tag accesses
-system.cpu3.icache.tags.data_accesses 169839 # Number of data accesses
-system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
-system.cpu3.icache.ReadReq_hits::cpu3.inst 169105 # number of ReadReq hits
-system.cpu3.icache.ReadReq_hits::total 169105 # number of ReadReq hits
-system.cpu3.icache.demand_hits::cpu3.inst 169105 # number of demand (read+write) hits
-system.cpu3.icache.demand_hits::total 169105 # number of demand (read+write) hits
-system.cpu3.icache.overall_hits::cpu3.inst 169105 # number of overall hits
-system.cpu3.icache.overall_hits::total 169105 # number of overall hits
+system.cpu3.icache.tags.tag_accesses 170795 # Number of tag accesses
+system.cpu3.icache.tags.data_accesses 170795 # Number of data accesses
+system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
+system.cpu3.icache.ReadReq_hits::cpu3.inst 170061 # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total 170061 # number of ReadReq hits
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system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.158470 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.884615 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010899 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20035.714286 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19937.500000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 19794.117647 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20687.500000 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20097.402597 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 50515.151515 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 51142.857143 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 50821.428571 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 50733.333333 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51178.571429 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 51500 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 50665.492958 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000 # average ReadCleanReq mshr miss latency
system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50750 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50542.372881 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 50500 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 50539.548023 # average ReadCleanReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 50507.575758 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 50500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 50500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 50500 # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 50506.578947 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50531.578947 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 50529.824561 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 50512.121212 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51142.857143 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 51100 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 51000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 50800 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50508.620690 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 50652.173913 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50750 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51133.333333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 50568.181818 # average overall mshr miss latency
-system.membus.snoop_filter.tot_requests 916 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 338 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 50500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51433.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 50566.433566 # average overall mshr miss latency
+system.membus.snoop_filter.tot_requests 839 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 261 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.membus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp 430 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 272 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 195 # Transaction distribution
system.membus.trans_dist::ReadExReq 208 # Transaction distribution
system.membus.trans_dist::ReadExResp 142 # Transaction distribution
system.membus.trans_dist::ReadSharedReq 430 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1482 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1482 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1405 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1405 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 36608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36608 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 261 # Total snoops (count)
system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 916 # Request fanout histogram
+system.membus.snoop_fanout::samples 839 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 916 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 839 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 916 # Request fanout histogram
-system.membus.reqLayer0.occupancy 683633 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.3 # Layer utilization (%)
+system.membus.snoop_fanout::total 839 # Request fanout histogram
+system.membus.reqLayer0.occupancy 587124 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 2860000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.1 # Layer utilization (%)
system.toL2Bus.snoop_filter.tot_requests 3977 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 1110 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 1865 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.hit_single_requests 1097 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 1878 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 264174500 # Cumulative time (in ticks) in various power states
+system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 263409500 # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadResp 2225 # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty 1 # Transaction distribution
system.toL2Bus.trans_dist::WritebackClean 1056 # Transaction distribution
@@ -1616,11 +1587,11 @@ system.toL2Bus.trans_dist::ReadSharedReq 659 # Tr
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1149 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 581 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 373 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 366 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1012 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 377 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 365 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 1015 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 349 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 368 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 5868 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 43648 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 10944 # Cumulative packet size per connected master and slave (bytes)
@@ -1634,13 +1605,13 @@ system.toL2Bus.pkt_size::total 183616 # Cu
system.toL2Bus.snoops 1028 # Total snoops (count)
system.toL2Bus.snoopTraffic 53312 # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples 2919 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.272011 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.157273 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.282631 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.164624 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 1002 34.33% 34.33% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 784 26.86% 61.19% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 470 16.10% 77.29% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 663 22.71% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 771 26.41% 60.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 465 15.93% 76.67% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 681 23.33% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
@@ -1650,23 +1621,23 @@ system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Re
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::total 2919 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 3051987 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.occupancy 3053983 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 700500 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 501494 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 499498 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 552489 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 550995 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 440975 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 431976 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.2 # Layer utilization (%)
system.toL2Bus.respLayer4.occupancy 552491 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 442472 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 427974 # Layer occupancy (ticks)
system.toL2Bus.respLayer5.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 553492 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.occupancy 554986 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 403476 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 431477 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 0.2 # Layer utilization (%)
---------- End Simulation Statistics ----------