diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-06-10 06:46:20 -0500 |
commit | 247e4e9ab41bafcfcbde725bb40e6a7b5628f1de (patch) | |
tree | b4312f540772ef437b5b962cc1fff4bb54d90ce4 /tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats | |
parent | d32ee94231251b8d07bb811142f6759f8655962b (diff) | |
download | gem5-247e4e9ab41bafcfcbde725bb40e6a7b5628f1de.tar.xz |
stats: updates due to changes to ruby
Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats')
-rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats | 492 |
1 files changed, 17 insertions, 475 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index 864f22205..33cec94dc 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -1,26 +1,24 @@ -Real time: Apr/09/2013 02:05:31 +Real time: Jun/08/2013 14:13:51 Profiler Stats -------------- -Elapsed_time_in_seconds: 139 -Elapsed_time_in_minutes: 2.31667 -Elapsed_time_in_hours: 0.0386111 -Elapsed_time_in_days: 0.0016088 +Elapsed_time_in_seconds: 78 +Elapsed_time_in_minutes: 1.3 +Elapsed_time_in_hours: 0.0216667 +Elapsed_time_in_days: 0.000902778 -Virtual_time_in_seconds: 139.38 -Virtual_time_in_minutes: 2.323 -Virtual_time_in_hours: 0.0387167 -Virtual_time_in_days: 0.00161319 +Virtual_time_in_seconds: 78.87 +Virtual_time_in_minutes: 1.3145 +Virtual_time_in_hours: 0.0219083 +Virtual_time_in_days: 0.000912847 Ruby_current_time: 7257449 Ruby_start_time: 0 Ruby_cycles: 7257449 -mbytes_resident: 65.4102 -mbytes_total: 245.32 -resident_ratio: 0.266632 - -ruby_cycles_executed: [ 7257450 7257450 7257450 7257450 7257450 7257450 7257450 7257450 ] +mbytes_resident: 71.2383 +mbytes_total: 285.629 +resident_ratio: 0.249436 Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -60,7 +58,6 @@ Request vs. RubySystem State Profile -------------------------------- -filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] Message Delayed Cycles ---------------------- @@ -79,13 +76,13 @@ Total_delay_cycles: [binsize: 32 max: 952 count: 4856797 average: 43.4082 | stan Resource Usage -------------- page_size: 4096 -user_time: 139 +user_time: 78 system_time: 0 -page_reclaims: 17300 -page_faults: 7 +page_reclaims: 11392 +page_faults: 0 swaps: 0 -block_inputs: 1648 -block_outputs: 296 +block_inputs: 0 +block_outputs: 272 Network Stats ------------- @@ -293,458 +290,3 @@ links_utilized_percent_switch_10: 14.8743 outgoing_messages_switch_10_link_9_Response_Data: 212955 15332760 [ 0 212955 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Response_Control: 392034 3136272 [ 0 392034 0 0 0 0 0 0 0 0 ] base_latency: 1 - --- L1Cache --- - - Event Counts - -Load [49778 49377 49516 49381 49747 49368 50044 49642 ] 396853 -Ifetch [0 0 0 0 0 0 0 0 ] 0 -Store [26786 26679 26651 26574 26897 26600 26631 26746 ] 213564 -Inv [73735 73350 73434 73266 73836 73403 73975 73550 ] 588549 -L1_Replacement [533617 530929 531837 527767 533499 530493 533236 532831 ] 4254209 -Fwd_GETX [198 220 198 200 215 204 212 216 ] 1663 -Fwd_GETS [159 151 153 155 149 129 133 142 ] 1171 -Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -Data [1 2 1 0 3 2 1 1 ] 11 -Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624 -DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171 -Data_all_Acks [27420 27295 27237 27204 27578 27207 27259 27370 ] 218570 -Ack [1 2 1 0 3 2 1 1 ] 11 -Ack_all [1 2 1 0 3 2 1 1 ] 11 -WB_Ack [40110 39623 40034 39662 40309 39563 40425 40081 ] 319807 -PF_Load [0 0 0 0 0 0 0 0 ] 0 -PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 -PF_Store [0 0 0 0 0 0 0 0 ] 0 - - - Transitions - -NP Load [49768 49368 49506 49370 49736 49359 50040 49632 ] 396779 -NP Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP Store [26783 26673 26639 26570 26890 26593 26629 26744 ] 213521 -NP Inv [436 404 386 385 420 399 405 385 ] 3220 -NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -NP PF_Load [0 0 0 0 0 0 0 0 ] 0 -NP PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 -NP PF_Store [0 0 0 0 0 0 0 0 ] 0 - -I Load [8 9 9 9 9 8 4 8 ] 64 -I Ifetch [0 0 0 0 0 0 0 0 ] 0 -I Store [2 6 11 4 6 6 2 2 ] 39 -I Inv [0 0 0 0 0 0 0 0 ] 0 -I L1_Replacement [36061 36066 35776 35948 35950 36049 35879 35962 ] 287691 -I PF_Load [0 0 0 0 0 0 0 0 ] 0 -I PF_Ifetch [0 0 0 0 0 0 0 0 ] 0 -I PF_Store [0 0 0 0 0 0 0 0 ] 0 - -S Load [0 0 0 0 0 0 0 0 ] 0 -S Ifetch [0 0 0 0 0 0 0 0 ] 0 -S Store [0 0 0 0 0 0 0 0 ] 0 -S Inv [475 488 482 528 526 446 511 500 ] 3956 -S L1_Replacement [375 347 329 325 361 336 360 328 ] 2761 -S PF_Load [0 0 0 0 0 0 0 0 ] 0 -S PF_Store [0 0 0 0 0 0 0 0 ] 0 - -E Load [2 0 0 0 1 0 0 2 ] 5 -E Ifetch [0 0 0 0 0 0 0 0 ] 0 -E Store [0 0 0 0 0 0 0 0 ] 0 -E Inv [22855 23068 22724 22855 22694 23009 22944 22917 ] 183066 -E L1_Replacement [26080 25475 25987 25671 26159 25558 26202 25901 ] 207033 -E Fwd_GETX [47 55 52 62 56 56 77 52 ] 457 -E Fwd_GETS [7 9 12 5 14 7 7 7 ] 68 -E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -E PF_Load [0 0 0 0 0 0 0 0 ] 0 -E PF_Store [0 0 0 0 0 0 0 0 ] 0 - -M Load [0 0 0 1 1 1 0 0 ] 3 -M Ifetch [0 0 0 0 0 0 0 0 ] 0 -M Store [1 0 1 0 0 1 0 0 ] 3 -M Inv [12660 12445 12509 12484 12663 12517 12326 12472 ] 100076 -M L1_Replacement [14031 14149 14049 13992 14152 14005 14224 14181 ] 112783 -M Fwd_GETX [34 25 30 32 26 36 27 32 ] 242 -M Fwd_GETS [59 60 61 63 54 40 53 61 ] 451 -M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M PF_Load [0 0 0 0 0 0 0 0 ] 0 -M PF_Store [0 0 0 0 0 0 0 0 ] 0 - -IS Load [0 0 0 0 0 0 0 0 ] 0 -IS Ifetch [0 0 0 0 0 0 0 0 ] 0 -IS Store [0 0 0 0 0 0 0 0 ] 0 -IS Inv [0 0 0 0 0 0 1 1 ] 2 -IS L1_Replacement [297388 295578 296859 294148 297188 294582 298840 297864 ] 2372447 -IS Data_Exclusive [48989 48607 48775 48593 48923 48630 49230 48877 ] 390624 -IS DataS_fromL1 [147 148 149 152 133 124 182 136 ] 1171 -IS Data_all_Acks [637 618 589 633 686 611 629 624 ] 5027 -IS PF_Load [0 0 0 0 0 0 0 0 ] 0 -IS PF_Store [0 0 0 0 0 0 0 0 ] 0 - -IM Load [0 0 0 0 0 0 0 0 ] 0 -IM Ifetch [0 0 0 0 0 0 0 0 ] 0 -IM Store [0 0 0 0 0 0 0 0 ] 0 -IM Inv [0 0 0 0 0 0 0 0 ] 0 -IM L1_Replacement [159682 159314 158837 157683 159689 159963 157731 158595 ] 1271494 -IM Data [1 2 1 0 3 2 1 1 ] 11 -IM Data_all_Acks [26783 26677 26648 26571 26892 26596 26629 26745 ] 213541 -IM Ack [0 0 0 0 0 0 0 0 ] 0 -IM PF_Load [0 0 0 0 0 0 0 0 ] 0 -IM PF_Store [0 0 0 0 0 0 0 0 ] 0 - -SM Load [0 0 0 0 0 0 0 0 ] 0 -SM Ifetch [0 0 0 0 0 0 0 0 ] 0 -SM Store [0 0 0 0 0 0 0 0 ] 0 -SM Inv [0 0 0 0 0 0 0 0 ] 0 -SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SM Ack [1 2 1 0 3 2 1 1 ] 11 -SM Ack_all [1 2 1 0 3 2 1 1 ] 11 -SM PF_Load [0 0 0 0 0 0 0 0 ] 0 -SM PF_Store [0 0 0 0 0 0 0 0 ] 0 - -IS_I Load [0 0 0 0 0 0 0 0 ] 0 -IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0 -IS_I Store [0 0 0 0 0 0 0 0 ] 0 -IS_I Inv [0 0 0 0 0 0 0 0 ] 0 -IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 -IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -IS_I Data_all_Acks [0 0 0 0 0 0 1 1 ] 2 -IS_I PF_Load [0 0 0 0 0 0 0 0 ] 0 -IS_I PF_Store [0 0 0 0 0 0 0 0 ] 0 - -M_I Load [0 0 0 0 0 0 0 0 ] 0 -M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 -M_I Store [0 0 0 0 0 0 0 0 ] 0 -M_I Inv [37277 36920 37310 36987 37511 37013 37760 37258 ] 298036 -M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -M_I Fwd_GETX [117 140 116 106 133 112 108 132 ] 964 -M_I Fwd_GETS [93 82 80 87 81 82 73 74 ] 652 -M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M_I WB_Ack [2624 2482 2530 2483 2584 2356 2484 2618 ] 20161 -M_I PF_Load [0 0 0 0 0 0 0 0 ] 0 -M_I PF_Store [0 0 0 0 0 0 0 0 ] 0 - -SINK_WB_ACK Load [0 0 1 1 0 0 0 0 ] 2 -SINK_WB_ACK Ifetch [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK Store [0 0 0 0 1 0 0 0 ] 1 -SINK_WB_ACK Inv [32 25 23 27 22 19 28 17 ] 193 -SINK_WB_ACK L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK WB_Ack [37486 37141 37504 37179 37725 37207 37941 37463 ] 299646 -SINK_WB_ACK PF_Load [0 0 0 0 0 0 0 0 ] 0 -SINK_WB_ACK PF_Store [0 0 0 0 0 0 0 0 ] 0 - -PF_IS Load [0 0 0 0 0 0 0 0 ] 0 -PF_IS Ifetch [0 0 0 0 0 0 0 0 ] 0 -PF_IS Store [0 0 0 0 0 0 0 0 ] 0 -PF_IS Inv [0 0 0 0 0 0 0 0 ] 0 -PF_IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -PF_IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 -PF_IS DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -PF_IS Data_all_Acks [0 0 0 0 0 0 0 0 ] 0 -PF_IS PF_Load [0 0 0 0 0 0 0 0 ] 0 -PF_IS PF_Store [0 0 0 0 0 0 0 0 ] 0 - -PF_IM Load [0 0 0 0 0 0 0 0 ] 0 -PF_IM Ifetch [0 0 0 0 0 0 0 0 ] 0 -PF_IM Store [0 0 0 0 0 0 0 0 ] 0 -PF_IM Inv [0 0 0 0 0 0 0 0 ] 0 -PF_IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -PF_IM Data [0 0 0 0 0 0 0 0 ] 0 -PF_IM Data_all_Acks [0 0 0 0 0 0 0 0 ] 0 -PF_IM Ack [0 0 0 0 0 0 0 0 ] 0 -PF_IM PF_Load [0 0 0 0 0 0 0 0 ] 0 -PF_IM PF_Store [0 0 0 0 0 0 0 0 ] 0 - -PF_SM Load [0 0 0 0 0 0 0 0 ] 0 -PF_SM Ifetch [0 0 0 0 0 0 0 0 ] 0 -PF_SM Store [0 0 0 0 0 0 0 0 ] 0 -PF_SM Inv [0 0 0 0 0 0 0 0 ] 0 -PF_SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -PF_SM Ack [0 0 0 0 0 0 0 0 ] 0 -PF_SM Ack_all [0 0 0 0 0 0 0 0 ] 0 - -PF_IS_I Load [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I Store [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I Inv [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 -PF_IS_I Data_all_Acks [0 0 0 0 0 0 0 0 ] 0 - - --- L2Cache --- - - Event Counts - -L1_GET_INSTR [0 ] 0 -L1_GETS [398575 ] 398575 -L1_GETX [215875 ] 215875 -L1_UPGRADE [0 ] 0 -L1_PUTX [21987 ] 21987 -L1_PUTX_old [305455 ] 305455 -Fwd_L1_GETX [0 ] 0 -Fwd_L1_GETS [0 ] 0 -Fwd_L1_GET_INSTR [0 ] 0 -L2_Replacement [8554 ] 8554 -L2_Replacement_clean [4607156 ] 4607156 -Mem_Data [604993 ] 604993 -Mem_Ack [604984 ] 604984 -WB_Data [205698 ] 205698 -WB_Data_clean [193585 ] 193585 -Ack [3680 ] 3680 -Ack_all [186735 ] 186735 -Unblock [1171 ] 1171 -Unblock_Cancel [0 ] 0 -Exclusive_Unblock [604175 ] 604175 -MEM_Inv [0 ] 0 - - - Transitions - -NP L1_GET_INSTR [0 ] 0 -NP L1_GETS [393127 ] 393127 -NP L1_GETX [211871 ] 211871 -NP L1_PUTX [0 ] 0 -NP L1_PUTX_old [283962 ] 283962 - -SS L1_GET_INSTR [0 ] 0 -SS L1_GETS [4 ] 4 -SS L1_GETX [11 ] 11 -SS L1_UPGRADE [0 ] 0 -SS L1_PUTX [456 ] 456 -SS L1_PUTX_old [1 ] 1 -SS L2_Replacement [1087 ] 1087 -SS L2_Replacement_clean [2582 ] 2582 -SS MEM_Inv [0 ] 0 - -M L1_GET_INSTR [0 ] 0 -M L1_GETS [9 ] 9 -M L1_GETX [9 ] 9 -M L1_PUTX [0 ] 0 -M L1_PUTX_old [0 ] 0 -M L2_Replacement [7258 ] 7258 -M L2_Replacement_clean [12885 ] 12885 -M MEM_Inv [0 ] 0 - -MT L1_GET_INSTR [0 ] 0 -MT L1_GETS [1171 ] 1171 -MT L1_GETX [1663 ] 1663 -MT L1_PUTX [20161 ] 20161 -MT L1_PUTX_old [694 ] 694 -MT L2_Replacement [5 ] 5 -MT L2_Replacement_clean [581173 ] 581173 -MT MEM_Inv [0 ] 0 - -M_I L1_GET_INSTR [0 ] 0 -M_I L1_GETS [226 ] 226 -M_I L1_GETX [136 ] 136 -M_I L1_UPGRADE [0 ] 0 -M_I L1_PUTX [0 ] 0 -M_I L1_PUTX_old [13952 ] 13952 -M_I Mem_Ack [604984 ] 604984 -M_I MEM_Inv [0 ] 0 - -MT_I L1_GET_INSTR [0 ] 0 -MT_I L1_GETS [0 ] 0 -MT_I L1_GETX [0 ] 0 -MT_I L1_UPGRADE [0 ] 0 -MT_I L1_PUTX [0 ] 0 -MT_I L1_PUTX_old [0 ] 0 -MT_I WB_Data [3 ] 3 -MT_I WB_Data_clean [0 ] 0 -MT_I Ack_all [2 ] 2 -MT_I MEM_Inv [0 ] 0 - -MCT_I L1_GET_INSTR [0 ] 0 -MCT_I L1_GETS [67 ] 67 -MCT_I L1_GETX [78 ] 78 -MCT_I L1_UPGRADE [0 ] 0 -MCT_I L1_PUTX [0 ] 0 -MCT_I L1_PUTX_old [6266 ] 6266 -MCT_I WB_Data [204606 ] 204606 -MCT_I WB_Data_clean [193503 ] 193503 -MCT_I Ack_all [183064 ] 183064 - -I_I L1_GET_INSTR [0 ] 0 -I_I L1_GETS [0 ] 0 -I_I L1_GETX [0 ] 0 -I_I L1_UPGRADE [0 ] 0 -I_I L1_PUTX [0 ] 0 -I_I L1_PUTX_old [1 ] 1 -I_I Ack [2590 ] 2590 -I_I Ack_all [2582 ] 2582 - -S_I L1_GET_INSTR [0 ] 0 -S_I L1_GETS [0 ] 0 -S_I L1_GETX [0 ] 0 -S_I L1_UPGRADE [0 ] 0 -S_I L1_PUTX [0 ] 0 -S_I L1_PUTX_old [0 ] 0 -S_I Ack [1090 ] 1090 -S_I Ack_all [1087 ] 1087 -S_I MEM_Inv [0 ] 0 - -ISS L1_GET_INSTR [0 ] 0 -ISS L1_GETS [2509 ] 2509 -ISS L1_GETX [1307 ] 1307 -ISS L1_PUTX [0 ] 0 -ISS L1_PUTX_old [266 ] 266 -ISS L2_Replacement [0 ] 0 -ISS L2_Replacement_clean [2167226 ] 2167226 -ISS Mem_Data [390615 ] 390615 -ISS MEM_Inv [0 ] 0 - -IS L1_GET_INSTR [0 ] 0 -IS L1_GETS [7 ] 7 -IS L1_GETX [3 ] 3 -IS L1_PUTX [0 ] 0 -IS L1_PUTX_old [1 ] 1 -IS L2_Replacement [0 ] 0 -IS L2_Replacement_clean [14533 ] 14533 -IS Mem_Data [2509 ] 2509 -IS MEM_Inv [0 ] 0 - -IM L1_GET_INSTR [0 ] 0 -IM L1_GETS [1302 ] 1302 -IM L1_GETX [709 ] 709 -IM L1_PUTX [0 ] 0 -IM L1_PUTX_old [310 ] 310 -IM L2_Replacement [0 ] 0 -IM L2_Replacement_clean [1170224 ] 1170224 -IM Mem_Data [211869 ] 211869 -IM MEM_Inv [0 ] 0 - -SS_MB L1_GET_INSTR [0 ] 0 -SS_MB L1_GETS [0 ] 0 -SS_MB L1_GETX [0 ] 0 -SS_MB L1_UPGRADE [0 ] 0 -SS_MB L1_PUTX [0 ] 0 -SS_MB L1_PUTX_old [0 ] 0 -SS_MB L2_Replacement [5 ] 5 -SS_MB L2_Replacement_clean [10 ] 10 -SS_MB Unblock_Cancel [0 ] 0 -SS_MB Exclusive_Unblock [11 ] 11 -SS_MB MEM_Inv [0 ] 0 - -MT_MB L1_GET_INSTR [0 ] 0 -MT_MB L1_GETS [151 ] 151 -MT_MB L1_GETX [87 ] 87 -MT_MB L1_UPGRADE [0 ] 0 -MT_MB L1_PUTX [840 ] 840 -MT_MB L1_PUTX_old [1 ] 1 -MT_MB L2_Replacement [0 ] 0 -MT_MB L2_Replacement_clean [655321 ] 655321 -MT_MB Unblock_Cancel [0 ] 0 -MT_MB Exclusive_Unblock [604164 ] 604164 -MT_MB MEM_Inv [0 ] 0 - -MT_IIB L1_GET_INSTR [0 ] 0 -MT_IIB L1_GETS [2 ] 2 -MT_IIB L1_GETX [1 ] 1 -MT_IIB L1_UPGRADE [0 ] 0 -MT_IIB L1_PUTX [527 ] 527 -MT_IIB L1_PUTX_old [1 ] 1 -MT_IIB L2_Replacement [0 ] 0 -MT_IIB L2_Replacement_clean [3164 ] 3164 -MT_IIB WB_Data [727 ] 727 -MT_IIB WB_Data_clean [53 ] 53 -MT_IIB Unblock [391 ] 391 -MT_IIB MEM_Inv [0 ] 0 - -MT_IB L1_GET_INSTR [0 ] 0 -MT_IB L1_GETS [0 ] 0 -MT_IB L1_GETX [0 ] 0 -MT_IB L1_UPGRADE [0 ] 0 -MT_IB L1_PUTX [1 ] 1 -MT_IB L1_PUTX_old [0 ] 0 -MT_IB L2_Replacement [0 ] 0 -MT_IB L2_Replacement_clean [38 ] 38 -MT_IB WB_Data [362 ] 362 -MT_IB WB_Data_clean [29 ] 29 -MT_IB Unblock_Cancel [0 ] 0 -MT_IB MEM_Inv [0 ] 0 - -MT_SB L1_GET_INSTR [0 ] 0 -MT_SB L1_GETS [0 ] 0 -MT_SB L1_GETX [0 ] 0 -MT_SB L1_UPGRADE [0 ] 0 -MT_SB L1_PUTX [2 ] 2 -MT_SB L1_PUTX_old [0 ] 0 -MT_SB L2_Replacement [199 ] 199 -MT_SB L2_Replacement_clean [0 ] 0 -MT_SB Unblock [780 ] 780 -MT_SB MEM_Inv [0 ] 0 - -Memory controller: system.ruby.dir_cntrl0.memBuffer: - memory_total_requests: 817953 - memory_reads: 604997 - memory_writes: 212953 - memory_refreshes: 50399 - memory_total_request_delays: 5673617 - memory_delays_per_request: 6.93636 - memory_delays_in_input_queue: 172403 - memory_delays_behind_head_of_bank_queue: 411771 - memory_delays_stalled_at_head_of_bank_queue: 5089443 - memory_stalls_for_bank_busy: 991356 - memory_stalls_for_random_busy: 0 - memory_stalls_for_anti_starvation: 192369 - memory_stalls_for_arbitration: 976938 - memory_stalls_for_bus: 1587349 - memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 927948 - memory_stalls_for_read_read_turnaround: 413483 - accesses_per_bank: 25693 25309 25639 25493 25446 25240 25202 25657 25510 25612 25713 25863 25420 25756 25574 25666 25584 25558 25869 25665 25398 25614 25401 25740 25400 25542 25601 25502 25584 25779 25408 25515 - - --- Directory --- - - Event Counts - -Fetch [604998 ] 604998 -Data [212955 ] 212955 -Memory_Data [604995 ] 604995 -Memory_Ack [212951 ] 212951 -DMA_READ [0 ] 0 -DMA_WRITE [0 ] 0 -CleanReplacement [392034 ] 392034 - - - Transitions - -I Fetch [604998 ] 604998 -I DMA_READ [0 ] 0 -I DMA_WRITE [0 ] 0 - -ID Fetch [0 ] 0 -ID Data [0 ] 0 -ID Memory_Data [0 ] 0 -ID DMA_READ [0 ] 0 -ID DMA_WRITE [0 ] 0 - -ID_W Fetch [0 ] 0 -ID_W Data [0 ] 0 -ID_W Memory_Ack [0 ] 0 -ID_W DMA_READ [0 ] 0 -ID_W DMA_WRITE [0 ] 0 - -M Data [212955 ] 212955 -M DMA_READ [0 ] 0 -M DMA_WRITE [0 ] 0 -M CleanReplacement [392034 ] 392034 - -IM Fetch [0 ] 0 -IM Data [0 ] 0 -IM Memory_Data [604995 ] 604995 -IM DMA_READ [0 ] 0 -IM DMA_WRITE [0 ] 0 - -MI Fetch [0 ] 0 -MI Data [0 ] 0 -MI Memory_Ack [212951 ] 212951 -MI DMA_READ [0 ] 0 -MI DMA_WRITE [0 ] 0 - -M_DRD Data [0 ] 0 -M_DRD DMA_READ [0 ] 0 -M_DRD DMA_WRITE [0 ] 0 - -M_DRDI Fetch [0 ] 0 -M_DRDI Data [0 ] 0 -M_DRDI Memory_Ack [0 ] 0 -M_DRDI DMA_READ [0 ] 0 -M_DRDI DMA_WRITE [0 ] 0 - -M_DWR Data [0 ] 0 -M_DWR DMA_READ [0 ] 0 -M_DWR DMA_WRITE [0 ] 0 - -M_DWRI Fetch [0 ] 0 -M_DWRI Data [0 ] 0 -M_DWRI Memory_Ack [0 ] 0 -M_DWRI DMA_READ [0 ] 0 -M_DWRI DMA_WRITE [0 ] 0 - |