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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-15 19:13:59 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-15 19:13:59 -0500 |
commit | b6b5cde1321f1bd710463db8650b4485720e21bd (patch) | |
tree | 021fc6c2161ea5d52569ca08a3e128e406ccf34d /tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | |
parent | 5ffc16593997b35f4f1abbd149e01169e6bbcff5 (diff) | |
download | gem5-b6b5cde1321f1bd710463db8650b4485720e21bd.tar.xz |
regressions: update stats due to change to ruby memory system
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index c1652737d..ab2c911dd 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.007277 # Number of seconds simulated -sim_ticks 7277301 # Number of ticks simulated -final_tick 7277301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.007242 # Number of seconds simulated +sim_ticks 7241726 # Number of ticks simulated +final_tick 7241726 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 75137 # Simulator tick rate (ticks/s) -host_mem_usage 410244 # Number of bytes of host memory used -host_seconds 96.85 # Real time elapsed on the host +host_tick_rate 40867 # Simulator tick rate (ticks/s) +host_mem_usage 418748 # Number of bytes of host memory used +host_seconds 177.20 # Real time elapsed on the host system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -109,29 +109,29 @@ system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 98746 # number of read accesses completed -system.cpu0.num_writes 53285 # number of write accesses completed +system.cpu0.num_reads 99032 # number of read accesses completed +system.cpu0.num_writes 53300 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 98932 # number of read accesses completed -system.cpu1.num_writes 53387 # number of write accesses completed +system.cpu1.num_reads 99071 # number of read accesses completed +system.cpu1.num_writes 53375 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 53615 # number of write accesses completed +system.cpu2.num_reads 99029 # number of read accesses completed +system.cpu2.num_writes 53317 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99438 # number of read accesses completed -system.cpu3.num_writes 53391 # number of write accesses completed +system.cpu3.num_reads 98175 # number of read accesses completed +system.cpu3.num_writes 53115 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99851 # number of read accesses completed -system.cpu4.num_writes 53668 # number of write accesses completed +system.cpu4.num_reads 98923 # number of read accesses completed +system.cpu4.num_writes 53385 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99263 # number of read accesses completed -system.cpu5.num_writes 53077 # number of write accesses completed +system.cpu5.num_reads 98363 # number of read accesses completed +system.cpu5.num_writes 52848 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99775 # number of read accesses completed -system.cpu6.num_writes 53756 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53283 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98608 # number of read accesses completed -system.cpu7.num_writes 53419 # number of write accesses completed +system.cpu7.num_reads 99065 # number of read accesses completed +system.cpu7.num_writes 53415 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- |