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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-11-10 17:18:02 -0600 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-11-10 17:18:02 -0600 |
commit | 2680c827bee835175d780b82b93590e2b3467591 (patch) | |
tree | 40ca2659a13e7997a6143591de1917543bc51de4 /tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | |
parent | 90c45c29fe11b478ea20564b1f4a94614b03ec4e (diff) | |
download | gem5-2680c827bee835175d780b82b93590e2b3467591.tar.xz |
regressions: stats update due to ruby functional access patch
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt')
-rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | 42 |
1 files changed, 21 insertions, 21 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index de4675b40..3a076df54 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.008594 # Number of seconds simulated -sim_ticks 8594451 # Number of ticks simulated -final_tick 8594451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.008665 # Number of seconds simulated +sim_ticks 8664886 # Number of ticks simulated +final_tick 8664886 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 108749 # Simulator tick rate (ticks/s) -host_mem_usage 418376 # Number of bytes of host memory used -host_seconds 79.03 # Real time elapsed on the host +host_tick_rate 186194 # Simulator tick rate (ticks/s) +host_mem_usage 418708 # Number of bytes of host memory used +host_seconds 46.54 # Real time elapsed on the host system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0 system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99932 # number of read accesses completed -system.cpu0.num_writes 53945 # number of write accesses completed +system.cpu0.num_reads 99885 # number of read accesses completed +system.cpu0.num_writes 54375 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99540 # number of read accesses completed -system.cpu1.num_writes 53424 # number of write accesses completed +system.cpu1.num_reads 99537 # number of read accesses completed +system.cpu1.num_writes 53839 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99404 # number of read accesses completed -system.cpu2.num_writes 53533 # number of write accesses completed +system.cpu2.num_reads 99297 # number of read accesses completed +system.cpu2.num_writes 53929 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99305 # number of read accesses completed -system.cpu3.num_writes 53683 # number of write accesses completed +system.cpu3.num_reads 99124 # number of read accesses completed +system.cpu3.num_writes 54072 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99222 # number of read accesses completed -system.cpu4.num_writes 53970 # number of write accesses completed +system.cpu4.num_reads 99259 # number of read accesses completed +system.cpu4.num_writes 54427 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99453 # number of read accesses completed -system.cpu5.num_writes 53665 # number of write accesses completed +system.cpu5.num_reads 99389 # number of read accesses completed +system.cpu5.num_writes 54074 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99859 # number of read accesses completed -system.cpu6.num_writes 53616 # number of write accesses completed +system.cpu6.num_reads 99658 # number of read accesses completed +system.cpu6.num_writes 54033 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53297 # number of write accesses completed +system.cpu7.num_writes 53796 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- |