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author | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-15 19:13:59 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2012-10-15 19:13:59 -0500 |
commit | b6b5cde1321f1bd710463db8650b4485720e21bd (patch) | |
tree | 021fc6c2161ea5d52569ca08a3e128e406ccf34d /tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | |
parent | 5ffc16593997b35f4f1abbd149e01169e6bbcff5 (diff) | |
download | gem5-b6b5cde1321f1bd710463db8650b4485720e21bd.tar.xz |
regressions: update stats due to change to ruby memory system
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt')
-rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt | 44 |
1 files changed, 22 insertions, 22 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index a9a755cda..de4675b40 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -1,12 +1,12 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.008643 # Number of seconds simulated -sim_ticks 8642753 # Number of ticks simulated -final_tick 8642753 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.008594 # Number of seconds simulated +sim_ticks 8594451 # Number of ticks simulated +final_tick 8594451 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 200801 # Simulator tick rate (ticks/s) -host_mem_usage 409268 # Number of bytes of host memory used -host_seconds 43.04 # Real time elapsed on the host +host_tick_rate 108749 # Simulator tick rate (ticks/s) +host_mem_usage 418376 # Number of bytes of host memory used +host_seconds 79.03 # Real time elapsed on the host system.l1_cntrl4.cacheMemory.num_data_array_reads 0 # number of data array reads system.l1_cntrl4.cacheMemory.num_data_array_writes 0 # number of data array writes system.l1_cntrl4.cacheMemory.num_tag_array_reads 0 # number of tag array reads @@ -55,29 +55,29 @@ system.l1_cntrl3.cacheMemory.num_tag_array_reads 0 system.l1_cntrl3.cacheMemory.num_tag_array_writes 0 # number of tag array writes system.l1_cntrl3.cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array system.l1_cntrl3.cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.cpu0.num_reads 99336 # number of read accesses completed -system.cpu0.num_writes 53454 # number of write accesses completed +system.cpu0.num_reads 99932 # number of read accesses completed +system.cpu0.num_writes 53945 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99686 # number of read accesses completed -system.cpu1.num_writes 53261 # number of write accesses completed +system.cpu1.num_reads 99540 # number of read accesses completed +system.cpu1.num_writes 53424 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99694 # number of read accesses completed -system.cpu2.num_writes 53721 # number of write accesses completed +system.cpu2.num_reads 99404 # number of read accesses completed +system.cpu2.num_writes 53533 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98699 # number of read accesses completed -system.cpu3.num_writes 53080 # number of write accesses completed +system.cpu3.num_reads 99305 # number of read accesses completed +system.cpu3.num_writes 53683 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 54108 # number of write accesses completed +system.cpu4.num_reads 99222 # number of read accesses completed +system.cpu4.num_writes 53970 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99065 # number of read accesses completed -system.cpu5.num_writes 53284 # number of write accesses completed +system.cpu5.num_reads 99453 # number of read accesses completed +system.cpu5.num_writes 53665 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99678 # number of read accesses completed -system.cpu6.num_writes 53683 # number of write accesses completed +system.cpu6.num_reads 99859 # number of read accesses completed +system.cpu6.num_writes 53616 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98986 # number of read accesses completed -system.cpu7.num_writes 53291 # number of write accesses completed +system.cpu7.num_reads 100000 # number of read accesses completed +system.cpu7.num_writes 53297 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed ---------- End Simulation Statistics ---------- |