diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-30 09:35:32 -0400 |
| commit | 10b70d54529f0a44dc088c9271d9ecf3a8ffe68a (patch) | |
| tree | 482dff6407c0b1c8cf1711f33d8ecad6acbf6c7f /tests/quick/se/50.memtest/ref/alpha/linux | |
| parent | 9cbe1cb653428a2298644579ddf82c46272683d4 (diff) | |
| download | gem5-10b70d54529f0a44dc088c9271d9ecf3a8ffe68a.tar.xz | |
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Diffstat (limited to 'tests/quick/se/50.memtest/ref/alpha/linux')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt | 2844 |
1 files changed, 1422 insertions, 1422 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9268efa23..cd5a28936 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,634 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000753 # Number of seconds simulated -sim_ticks 753126500 # Number of ticks simulated -final_tick 753126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000759 # Number of seconds simulated +sim_ticks 758619000 # Number of ticks simulated +final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 111238456 # Simulator tick rate (ticks/s) -host_mem_usage 391924 # Number of bytes of host memory used -host_seconds 6.77 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 90167 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 90714 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 93247 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 94741 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 86405 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 91776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 89783 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 85071 # Number of bytes read from this memory -system.physmem.bytes_read::total 721904 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 471360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5341 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5319 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5446 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5378 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5389 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5299 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5260 # Number of bytes written to this memory -system.physmem.bytes_written::total 514024 # Number of bytes written to this memory +host_tick_rate 151805189 # Simulator tick rate (ticks/s) +host_mem_usage 345224 # Number of bytes of host memory used +host_seconds 5.00 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory +system.physmem.bytes_read::total 738527 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory +system.physmem.bytes_written::total 528067 # Number of bytes written to this memory system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11284 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10805 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88502 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7365 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5341 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5232 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5319 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5378 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5389 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5299 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5260 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 119723579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 120449885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 123813197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 125796928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 114728402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121860006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 119213704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 112957119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 958542821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 625870953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7091770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6947040 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7062559 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7231189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7140899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7155504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7036003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6984218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 682520134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 625870953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 126815349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 127396925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130875756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 133028117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 121869301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129015511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 126249707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 119941338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1641062956 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15498 # number of replacements -system.l2c.tagsinuse 803.451409 # Cycle average of tags in use -system.l2c.total_refs 150823 # Total number of references to valid blocks. -system.l2c.sampled_refs 16301 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.252377 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15559 # number of replacements +system.l2c.tagsinuse 800.707629 # Cycle average of tags in use +system.l2c.total_refs 151038 # Total number of references to valid blocks. +system.l2c.sampled_refs 16357 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.233845 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 740.977974 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.980396 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.585151 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 8.326366 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.791550 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.277354 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.805973 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.956689 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.749957 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.723611 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007793 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007407 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.008131 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007609 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007107 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007623 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007568 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784621 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10791 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10648 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10876 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10892 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86047 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76684 # number of Writeback hits -system.l2c.Writeback_hits::total 76684 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 327 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 379 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 352 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 359 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 389 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2869 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2049 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2057 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2058 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16288 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12638 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12950 # number of demand (read+write) hits -system.l2c.demand_hits::total 102335 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12740 # number of overall hits -system.l2c.overall_hits::cpu1 12617 # number of overall hits -system.l2c.overall_hits::cpu2 12949 # number of overall hits -system.l2c.overall_hits::cpu3 12848 # number of overall hits -system.l2c.overall_hits::cpu4 12644 # number of overall hits -system.l2c.overall_hits::cpu5 12949 # number of overall hits -system.l2c.overall_hits::cpu6 12638 # number of overall hits -system.l2c.overall_hits::cpu7 12950 # number of overall hits -system.l2c.overall_hits::total 102335 # number of overall hits -system.l2c.ReadReq_misses::cpu0 829 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 817 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 838 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 845 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 778 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 763 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6542 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1857 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1862 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1833 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14915 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4259 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4029 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4260 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4087 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4203 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4290 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4312 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 33728 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5088 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4846 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5133 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 4865 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5039 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5075 # number of demand (read+write) misses -system.l2c.demand_misses::total 40270 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5088 # number of overall misses -system.l2c.overall_misses::cpu1 4846 # number of overall misses -system.l2c.overall_misses::cpu2 5098 # number of overall misses -system.l2c.overall_misses::cpu3 5133 # number of overall misses -system.l2c.overall_misses::cpu4 4865 # number of overall misses -system.l2c.overall_misses::cpu5 5039 # number of overall misses -system.l2c.overall_misses::cpu6 5126 # number of overall misses -system.l2c.overall_misses::cpu7 5075 # number of overall misses -system.l2c.overall_misses::total 40270 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 72627487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 68308474 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 75006474 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 70533471 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 66613974 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 67813479 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 73978476 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 69040973 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 563922808 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54756455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 53319972 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53416959 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57331458 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53682456 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 54000963 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 51801955 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 51941959 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 430252177 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 241663349 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231681341 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 241380832 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 244014828 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 232261321 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 242148860 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 245082818 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 243371325 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1921604674 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 314290836 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 299989815 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 316387306 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 314548299 # 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number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2233 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2212 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2250 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2221 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2195 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2173 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17784 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6281 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6309 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17764 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18025 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142605 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17828 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18047 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17981 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17509 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17988 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17764 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18025 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142605 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071794 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.071410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.071392 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.072619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068090 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.071380 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.073115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.065465 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.070656 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.853560 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.830501 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.843128 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.843556 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.838361 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.828180 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.835080 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.837092 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.838675 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.678077 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.669047 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.675226 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.675808 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.671872 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.669694 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.677725 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.676923 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.674344 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285394 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.277501 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.282485 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.285468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.277857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.280131 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.281553 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.282388 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285394 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.277501 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.282485 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.285468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.277857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.280131 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.281553 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.282388 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 87608.548854 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 83608.903305 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 89506.532220 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 83471.563314 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 85622.074550 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 81116.601675 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 88491 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 90486.203145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 86200.368083 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28728.465373 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28712.962843 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28641.801072 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30206.247629 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28830.534909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28800.513600 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28260.750136 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28555.227598 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28846.944485 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 56741.805353 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 57503.435344 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 56662.167136 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56906.443097 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 56829.293125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 57613.338092 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 57128.862005 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56440.474258 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56973.573114 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61770.997642 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61904.625464 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 62061.064339 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61279.621859 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61433.770812 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61512.668982 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 62243.717128 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 61559.073498 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61721.566476 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61770.997642 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61904.625464 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 62061.064339 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61279.621859 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61433.770812 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61512.668982 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 62243.717128 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 61559.073498 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61721.566476 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 205 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 736.955948 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.896049 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.875266 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.499139 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.819632 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 8.127236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.346952 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.379667 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.807741 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.719684 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007711 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007691 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007323 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007636 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007937 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.008151 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008183 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.007625 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781941 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10425 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10868 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10623 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86293 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76698 # number of Writeback hits +system.l2c.Writeback_hits::total 76698 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 360 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 388 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 365 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 360 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 369 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2938 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2007 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2070 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2061 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1961 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2103 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16299 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12432 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12832 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 13006 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12735 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12726 # number of demand (read+write) hits +system.l2c.demand_hits::total 102592 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12432 # number of overall hits +system.l2c.overall_hits::cpu1 12963 # number of overall hits +system.l2c.overall_hits::cpu2 12832 # number of overall hits +system.l2c.overall_hits::cpu3 12949 # number of overall hits +system.l2c.overall_hits::cpu4 12949 # number of overall hits +system.l2c.overall_hits::cpu5 13006 # number of overall hits +system.l2c.overall_hits::cpu6 12735 # number of overall hits +system.l2c.overall_hits::cpu7 12726 # number of overall hits +system.l2c.overall_hits::total 102592 # number of overall hits +system.l2c.ReadReq_misses::cpu0 852 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 872 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 800 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 819 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 876 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 871 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 869 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 848 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6807 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1804 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1923 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1810 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1803 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1840 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1866 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1868 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14835 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4250 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4213 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4295 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4281 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4294 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4308 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34265 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5102 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5245 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5013 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5114 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5157 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5122 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5156 # number of demand (read+write) misses +system.l2c.demand_misses::total 41072 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5102 # number of overall misses +system.l2c.overall_misses::cpu1 5245 # number of overall misses +system.l2c.overall_misses::cpu2 5013 # number of overall misses +system.l2c.overall_misses::cpu3 5114 # number of overall misses +system.l2c.overall_misses::cpu4 5157 # number of overall misses +system.l2c.overall_misses::cpu5 5122 # number of overall misses +system.l2c.overall_misses::cpu6 5163 # number of overall misses +system.l2c.overall_misses::cpu7 5156 # number of overall misses +system.l2c.overall_misses::total 41072 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50457953 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 52232944 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 47803944 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 49059449 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 51558931 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 52310430 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 51043945 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 50050941 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 404518537 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54750899 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 49983404 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 56149902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53493906 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 50935912 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 51769923 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 53458903 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54181398 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 424724247 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 228244633 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234983117 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 226986626 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 231330611 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 230611636 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 229068598 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 231365116 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232157113 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1844747450 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 278702586 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 287216061 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 274790570 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 280390060 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 282170567 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 281379028 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 282409061 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282208054 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2249265987 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 278702586 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 287216061 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 274790570 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 280390060 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 282170567 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 281379028 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 282409061 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282208054 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2249265987 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11277 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11740 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11652 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11698 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11803 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11643 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11471 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 93100 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76698 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76698 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2283 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2164 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2311 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2182 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2205 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2237 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17773 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6257 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6468 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6193 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6365 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6303 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6312 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6411 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50564 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17534 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18063 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18106 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18128 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17898 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17882 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143664 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17534 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18063 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18106 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18128 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17898 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17882 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143664 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.075552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.074276 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.068658 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.070012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.074218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.073714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.074637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.073926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.073115 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.841437 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.833641 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.832107 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.829514 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.832794 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.834467 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.838275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.835047 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.834693 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.679239 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.676098 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.680284 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.674784 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.679200 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.673479 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.686491 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.671970 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.677656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.290978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.288060 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.280919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283120 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.284823 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.282546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.288468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288335 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285889 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.290978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.288060 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.280919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283120 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.284823 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.282546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.288468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288335 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285889 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 59222.949531 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 59900.165138 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 59754.930000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59901.647131 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 58857.227169 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 60057.898967 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 58738.716916 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59022.336085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59426.845453 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28501.248829 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27706.986696 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29199.117005 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29554.644199 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28250.644481 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28135.827717 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28648.929796 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29005.031049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28629.878463 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53704.619529 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53734.991310 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53877.670544 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.444936 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53868.637234 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53885.814632 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53881.023754 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53889.766249 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53837.660878 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54626.143865 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54759.973499 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54815.593457 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54827.935080 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54716.030056 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54935.382273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54698.636645 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54733.912723 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54763.975141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54626.143865 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54759.973499 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54815.593457 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54827.935080 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54716.030056 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54935.382273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54698.636645 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54733.912723 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54763.975141 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10793 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 34 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1480 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.029412 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.292568 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7365 # number of writebacks -system.l2c.writebacks::total 7365 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7587 # number of writebacks +system.l2c.writebacks::total 7587 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 22 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 7 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 817 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 811 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 833 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 837 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 768 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 832 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 831 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 756 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6485 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1857 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1865 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1897 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1862 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1833 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1819 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14913 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4027 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4258 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4285 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4083 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4201 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4288 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 33706 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5072 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4838 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5091 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5122 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 4851 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5033 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5119 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5065 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40191 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5072 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4838 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5122 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 4851 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5033 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5119 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5065 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40191 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 62233988 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 58293474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 64591474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 59635471 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 57012474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 57238479 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 63446976 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 59031473 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 481483809 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78461421 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76760937 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77303426 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78549924 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76789922 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77341424 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75742929 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75130926 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 616080909 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 189411849 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 182830341 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 189356832 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 191977328 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 182678822 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 190853860 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 192540318 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 191094825 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1510744175 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 251645837 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 241123815 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 253948306 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 251612799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 239691296 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 248092339 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 255987294 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 250126298 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1992227984 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 251645837 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 241123815 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 253948306 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 251612799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 239691296 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 248092339 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 255987294 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 250126298 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1992227984 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 411426099 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414392619 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419713103 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412462117 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406761621 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421965569 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407663587 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419790595 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3314175310 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 231152983 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 227958986 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 229754991 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 235704484 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 234071489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230948990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 231546487 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 229152485 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1850290895 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 642579082 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 642351605 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 649468094 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 648166601 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 640833110 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 652914559 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 639210074 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 648943080 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5164466205 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071932 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067215 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.071038 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072678 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.064865 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.070041 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.853112 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.830501 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.843128 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.843111 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838361 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.828180 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835080 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837092 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.838563 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677440 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.668715 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.674909 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.675335 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.671215 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.669375 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.677409 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.676452 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.673904 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281834 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281834 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 76173.791922 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 71878.512947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 77540.785114 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 71249.069295 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74234.992188 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 68796.248798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 76350.151625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78083.958995 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 74245.768543 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41187.097638 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41335.991922 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41449.558177 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41407.445440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41240.559613 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41248.759467 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41321.837971 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41303.422760 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41311.668276 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44515.123149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45401.127638 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44470.838891 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44802.176896 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44741.323047 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45430.578434 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44902.126399 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44347.835925 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44821.223966 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 92 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 845 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 865 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 809 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 871 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 865 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 839 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6747 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1804 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1923 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1809 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1803 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1840 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1865 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1868 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14833 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4243 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4367 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4211 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4291 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4278 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4245 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4291 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4307 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34233 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5088 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5005 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5100 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5149 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5110 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5146 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40980 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5088 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5005 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5100 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5149 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5110 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5146 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40980 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 39952953 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 41536444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37955945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 38925950 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 40835431 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 41565931 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 40269445 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 39637942 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 320680041 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78868808 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73978329 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78794825 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74230834 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 74073835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75455362 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76452812 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 76637320 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 608492125 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 176592133 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181884117 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 175861127 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 179102612 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 178683137 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 177427598 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 179259117 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 179911613 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1428721454 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 216545086 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 223420561 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 213817072 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 218028562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 219518568 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 218993529 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 219528562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 219549555 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1749401495 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 216545086 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 223420561 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 213817072 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 218028562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 219518568 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 218993529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 219528562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 219549555 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1749401495 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 402081632 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 400575089 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409123618 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 408517090 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 408283130 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 406615614 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405150633 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 405778615 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3246125421 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 225621486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222590493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 219789492 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227766486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225717983 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 229461987 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226436485 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231064489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1808448901 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 627703118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 623165582 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 628913110 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 636283576 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634001113 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 636077601 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 631587118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 636843104 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5054574322 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.074931 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.073680 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.073795 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.073206 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073141 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.072470 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.841437 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.833641 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832107 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.829056 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.832794 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.834467 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.837826 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.835047 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.834581 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.678121 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.675170 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679961 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.674156 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678724 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.686011 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.671814 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.677023 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285249 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285249 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 47281.601183 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48019.010405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 47803.457179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 48116.131026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46883.388060 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48053.099422 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46879.447031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47244.269368 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47529.278346 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.120770 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41007.942905 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40974.947998 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41034.181316 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41083.657793 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41008.348913 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40993.464879 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41026.402570 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41022.862873 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41619.640113 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41649.671857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41762.319402 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41739.131205 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41767.914212 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41796.842874 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41775.604055 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41771.909218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41735.210294 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -657,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98761 # number of read accesses completed -system.cpu0.num_writes 53242 # number of write accesses completed +system.cpu0.num_reads 97622 # number of read accesses completed +system.cpu0.num_writes 53016 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22316 # number of replacements -system.cpu0.l1c.tagsinuse 389.737995 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13032 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22724 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.573491 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21387 # number of replacements +system.cpu0.l1c.tagsinuse 393.959213 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13124 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 21798 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.602074 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 389.737995 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.761207 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.761207 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8451 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8451 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1130 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9581 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9581 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9581 # number of overall hits -system.cpu0.l1c.overall_hits::total 9581 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35764 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35764 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22786 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22786 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58550 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58550 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58550 # number of overall misses -system.cpu0.l1c.overall_misses::total 58550 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4595217343 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4595217343 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3140614125 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3140614125 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7735831468 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7735831468 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7735831468 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7735831468 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44215 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44215 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23916 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23916 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68131 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68131 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68131 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68131 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808866 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.808866 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952751 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952751 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859374 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859374 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859374 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859374 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 128487.231378 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 128487.231378 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 137830.866541 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 137830.866541 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 132123.509274 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 132123.509274 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 132123.509274 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 132123.509274 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1390817 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 393.959213 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.769452 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.769452 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8513 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8513 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1098 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1098 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9611 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9611 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9611 # number of overall hits +system.cpu0.l1c.overall_hits::total 9611 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35379 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35379 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 22892 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 22892 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58271 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58271 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58271 # number of overall misses +system.cpu0.l1c.overall_misses::total 58271 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1332854037 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1332854037 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1090035309 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1090035309 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2422889346 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2422889346 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2422889346 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2422889346 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 43892 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 43892 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 23990 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 23990 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 67882 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 67882 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 67882 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 67882 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806047 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806047 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954231 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954231 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858416 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858416 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858416 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858416 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37673.592724 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37673.592724 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47616.429713 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 47616.429713 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 41579.676786 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 41579.676786 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 41579.676786 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 41579.676786 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1432667 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63512 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66221 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.898492 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.634633 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks -system.cpu0.l1c.writebacks::total 9722 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35764 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35764 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22786 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22786 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58550 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58550 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58550 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58550 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4523701343 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4523701343 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3095050125 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3095050125 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7618751468 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7618751468 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7618751468 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7618751468 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1332951909 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1332951909 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 956448961 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 956448961 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2289400870 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2289400870 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808866 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808866 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952751 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952751 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859374 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859374 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 126487.566911 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 126487.566911 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 135831.217634 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 135831.217634 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9284 # number of writebacks +system.cpu0.l1c.writebacks::total 9284 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35379 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35379 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22892 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 22892 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58271 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58271 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58271 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58271 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262100037 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262100037 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1044251309 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1044251309 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2306351346 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2306351346 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2306351346 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2306351346 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 709848172 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 709848172 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 441878494 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 441878494 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1151726666 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1151726666 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806047 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806047 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954231 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954231 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858416 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858416 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35673.705786 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35673.705786 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45616.429713 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45616.429713 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -772,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 96397 # number of read accesses completed -system.cpu1.num_writes 52047 # number of write accesses completed +system.cpu1.num_reads 98743 # number of read accesses completed +system.cpu1.num_writes 53079 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21248 # number of replacements -system.cpu1.l1c.tagsinuse 388.599667 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12959 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 21596 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.600065 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 22269 # number of replacements +system.cpu1.l1c.tagsinuse 395.693103 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13156 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22645 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.580967 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 388.599667 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.758984 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.758984 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1037 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1037 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9558 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9558 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9558 # number of overall hits -system.cpu1.l1c.overall_hits::total 9558 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 34759 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 34759 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22425 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22425 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 57184 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 57184 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 57184 # number of overall misses -system.cpu1.l1c.overall_misses::total 57184 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4505667082 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4505667082 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3159000290 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3159000290 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7664667372 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7664667372 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7664667372 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7664667372 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43280 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43280 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23462 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23462 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 66742 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 66742 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 66742 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 66742 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803119 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.803119 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955801 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955801 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.856792 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.856792 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.856792 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.856792 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129625.912195 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 129625.912195 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140869.578149 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 140869.578149 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 134035.173685 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 134035.173685 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 134035.173685 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 134035.173685 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1387894 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 395.693103 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.772838 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.772838 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8677 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8677 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1112 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9789 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9789 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9789 # number of overall hits +system.cpu1.l1c.overall_hits::total 9789 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35979 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22841 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22841 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58820 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58820 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58820 # number of overall misses +system.cpu1.l1c.overall_misses::total 58820 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1346712982 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1346712982 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1084415887 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1084415887 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2431128869 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2431128869 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2431128869 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2431128869 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44656 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44656 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23953 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23953 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68609 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68609 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68609 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68609 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805692 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805692 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953576 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953576 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857322 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857322 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857322 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857322 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37430.528419 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37430.528419 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47476.725494 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47476.725494 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41331.670673 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41331.670673 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41331.670673 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41331.670673 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1432282 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62397 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66708 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.242960 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.470918 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9378 # number of writebacks -system.cpu1.l1c.writebacks::total 9378 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 34759 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 34759 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22425 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22425 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 57184 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 57184 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 57184 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 57184 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4436169082 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4436169082 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3114154290 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3114154290 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7550323372 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7550323372 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7550323372 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7550323372 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1384263931 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1384263931 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 908274469 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 908274469 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2292538400 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2292538400 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803119 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803119 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955801 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955801 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.856792 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.856792 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127626.487586 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127626.487586 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138869.756522 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138869.756522 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9759 # number of writebacks +system.cpu1.l1c.writebacks::total 9759 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35979 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22841 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22841 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58820 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58820 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58820 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58820 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1274756982 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1274756982 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1038739887 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1038739887 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2313496869 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2313496869 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2313496869 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2313496869 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702867762 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702867762 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 426288670 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 426288670 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1129156432 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1129156432 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805692 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805692 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953576 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953576 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857322 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857322 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35430.584007 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45476.988179 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53454 # number of write accesses completed +system.cpu2.num_reads 98534 # number of read accesses completed +system.cpu2.num_writes 52787 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22874 # number of replacements -system.cpu2.l1c.tagsinuse 393.105668 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13406 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 23291 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.575587 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21873 # number of replacements +system.cpu2.l1c.tagsinuse 394.149978 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13285 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22270 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.596542 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 393.105668 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.767785 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.767785 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8773 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8773 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1158 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1158 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9931 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9931 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9931 # number of overall hits -system.cpu2.l1c.overall_hits::total 9931 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36255 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36255 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22757 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22757 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59012 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59012 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59012 # number of overall misses -system.cpu2.l1c.overall_misses::total 59012 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4588921928 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4588921928 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3096881635 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3096881635 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7685803563 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7685803563 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7685803563 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7685803563 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45028 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45028 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23915 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23915 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68943 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68943 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68943 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68943 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805166 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805166 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951579 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.951579 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.855953 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.855953 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.855953 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.855953 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 126573.491325 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 126573.491325 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 136084.793031 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 136084.793031 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 130241.367230 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 130241.367230 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 130241.367230 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 130241.367230 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1394100 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.149978 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.769824 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.769824 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8620 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8620 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1112 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9732 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9732 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9732 # number of overall hits +system.cpu2.l1c.overall_hits::total 9732 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35901 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35901 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22666 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22666 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58567 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58567 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58567 # number of overall misses +system.cpu2.l1c.overall_misses::total 58567 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1333102057 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1333102057 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1080309021 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1080309021 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2413411078 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2413411078 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2413411078 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2413411078 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44521 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23778 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23778 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68299 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68299 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68299 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68299 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806384 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806384 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953234 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953234 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857509 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857509 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857509 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857509 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37132.727696 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37132.727696 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47662.093929 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47662.093929 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41207.695084 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41207.695084 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41207.695084 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41207.695084 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1432337 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 64388 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66669 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.651550 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.484303 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9909 # number of writebacks -system.cpu2.l1c.writebacks::total 9909 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36255 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22757 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22757 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59012 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59012 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59012 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59012 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4516419928 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4516419928 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3051379635 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3051379635 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7567799563 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7567799563 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7567799563 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7567799563 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1394051277 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1394051277 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 902954372 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 902954372 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2297005649 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2297005649 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805166 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805166 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951579 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951579 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.855953 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.855953 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 124573.711985 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 124573.711985 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 134085.320341 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 134085.320341 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9470 # number of writebacks +system.cpu2.l1c.writebacks::total 9470 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35901 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35901 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22666 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22666 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58567 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58567 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58567 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58567 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1261304057 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1261304057 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1034981021 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1034981021 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2296285078 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2296285078 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2296285078 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2296285078 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 719957534 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 719957534 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 417914602 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 417914602 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1137872136 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1137872136 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806384 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806384 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953234 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953234 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857509 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857509 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35132.839113 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35132.839113 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45662.270405 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45662.270405 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1002,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98905 # number of read accesses completed -system.cpu3.num_writes 53947 # number of write accesses completed +system.cpu3.num_reads 99583 # number of read accesses completed +system.cpu3.num_writes 53448 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22486 # number of replacements -system.cpu3.l1c.tagsinuse 391.587362 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13348 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22882 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.583341 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22221 # number of replacements +system.cpu3.l1c.tagsinuse 395.683952 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13227 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.584903 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 391.587362 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.764819 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.764819 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8745 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8745 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1178 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1178 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9923 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9923 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9923 # number of overall hits -system.cpu3.l1c.overall_hits::total 9923 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36044 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36044 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22870 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22870 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58914 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58914 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58914 # number of overall misses -system.cpu3.l1c.overall_misses::total 58914 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4630744245 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4630744245 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3061222174 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3061222174 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7691966419 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7691966419 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7691966419 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7691966419 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44789 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44789 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24048 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24048 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68837 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68837 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68837 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68837 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804751 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.804751 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951015 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.951015 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.855848 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.855848 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.855848 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.855848 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 128474.759877 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 128474.759877 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 133853.177700 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 133853.177700 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 130562.623808 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 130562.623808 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 130562.623808 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 130562.623808 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1375135 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.683952 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.772820 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.772820 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8699 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8699 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1092 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1092 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9791 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9791 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9791 # number of overall hits +system.cpu3.l1c.overall_hits::total 9791 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35935 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35935 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23086 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23086 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59021 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59021 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59021 # number of overall misses +system.cpu3.l1c.overall_misses::total 59021 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1329205475 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1329205475 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1090244238 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1090244238 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2419449713 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2419449713 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2419449713 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2419449713 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44634 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44634 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24178 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24178 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68812 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68812 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68812 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68812 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805104 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805104 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954835 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954835 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857714 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857714 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857714 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857714 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 36989.160289 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 36989.160289 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47225.341679 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47225.341679 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 40993.031514 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 40993.031514 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 40993.031514 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 40993.031514 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1431757 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63801 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67125 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.553502 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.329713 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9848 # number of writebacks -system.cpu3.l1c.writebacks::total 9848 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36044 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36044 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22870 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22870 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58914 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58914 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4558664245 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4558664245 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3015496174 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3015496174 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7574160419 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7574160419 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7574160419 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7574160419 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1332002539 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1332002539 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 965663255 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 965663255 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2297665794 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2297665794 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804751 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804751 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951015 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951015 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.855848 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.855848 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 126474.981828 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 126474.981828 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 131853.789856 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 131853.789856 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9875 # number of writebacks +system.cpu3.l1c.writebacks::total 9875 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35935 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35935 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23086 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23086 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59021 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59021 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59021 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59021 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1257339475 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1257339475 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1044074238 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1044074238 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2301413713 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2301413713 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2301413713 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2301413713 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 714868620 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 714868620 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 436247033 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 436247033 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1151115653 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1151115653 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805104 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805104 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954835 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954835 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857714 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857714 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34989.271602 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34989.271602 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45225.428312 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45225.428312 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1117,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 96174 # number of read accesses completed -system.cpu4.num_writes 51853 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 53418 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 21569 # number of replacements -system.cpu4.l1c.tagsinuse 388.492426 # Cycle average of tags in use -system.cpu4.l1c.total_refs 12628 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 21966 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.574888 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22068 # number of replacements +system.cpu4.l1c.tagsinuse 394.143159 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13375 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22471 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 388.492426 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.758774 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.758774 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8239 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8239 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 990 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 990 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9229 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9229 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9229 # number of overall hits -system.cpu4.l1c.overall_hits::total 9229 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 34929 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 34929 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22565 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22565 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 57494 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 57494 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 57494 # number of overall misses -system.cpu4.l1c.overall_misses::total 57494 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4583503891 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4583503891 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3126262139 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3126262139 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7709766030 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7709766030 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7709766030 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7709766030 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 43168 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 43168 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 23555 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 23555 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 66723 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 66723 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 66723 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 66723 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809141 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809141 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957971 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.957971 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.861682 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.861682 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.861682 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.861682 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 131223.450170 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 131223.450170 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 138544.743585 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 138544.743585 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 134096.880196 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 134096.880196 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 134096.880196 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 134096.880196 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1393760 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 394.143159 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.769811 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.769811 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8810 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8810 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1141 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1141 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9951 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9951 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9951 # number of overall hits +system.cpu4.l1c.overall_hits::total 9951 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36179 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36179 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22735 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22735 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58914 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58914 # number of overall misses +system.cpu4.l1c.overall_misses::total 58914 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1352891584 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1352891584 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1067419012 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1067419012 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2420310596 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2420310596 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2420310596 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2420310596 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44989 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44989 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 23876 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 23876 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68865 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68865 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68865 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68865 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804174 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804174 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952211 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952211 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.855500 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.855500 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.855500 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.855500 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37394.388568 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 37394.388568 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 46950.473367 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 46950.473367 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 41082.095869 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 41082.095869 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 41082.095869 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 41082.095869 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1431267 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62546 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66934 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 22.283759 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.383258 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9434 # number of writebacks -system.cpu4.l1c.writebacks::total 9434 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 34929 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 34929 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22565 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22565 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 57494 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 57494 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 57494 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 57494 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4513651891 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4513651891 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3081144139 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3081144139 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7594796030 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7594796030 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7594796030 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7594796030 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1346430009 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1346430009 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 963144394 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 963144394 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2309574403 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2309574403 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809141 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809141 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957971 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957971 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.861682 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.861682 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 129223.621947 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 129223.621947 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 136545.275382 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 136545.275382 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9521 # number of writebacks +system.cpu4.l1c.writebacks::total 9521 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36179 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36179 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22735 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22735 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58914 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58914 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1280533584 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1280533584 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1021953012 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1021953012 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2302486596 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2302486596 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2302486596 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2302486596 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 712917081 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 712917081 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 441958565 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 441958565 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1154875646 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1154875646 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804174 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804174 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952211 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952211 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.855500 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.855500 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35394.388568 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35394.388568 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 44950.649307 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 44950.649307 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1232,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98962 # number of read accesses completed -system.cpu5.num_writes 53362 # number of write accesses completed +system.cpu5.num_reads 99061 # number of read accesses completed +system.cpu5.num_writes 53322 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22485 # number of replacements -system.cpu5.l1c.tagsinuse 390.064411 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13538 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22892 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.591386 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22382 # number of replacements +system.cpu5.l1c.tagsinuse 394.919460 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13094 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22775 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.574929 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 390.064411 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.761845 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.761845 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8808 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8808 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1142 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9950 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9950 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9950 # number of overall hits -system.cpu5.l1c.overall_hits::total 9950 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35846 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35846 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22890 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22890 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58736 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58736 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58736 # number of overall misses -system.cpu5.l1c.overall_misses::total 58736 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4553672386 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4553672386 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3119643153 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3119643153 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7673315539 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7673315539 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7673315539 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7673315539 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44654 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44654 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24032 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24032 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68686 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68686 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68686 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68686 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802750 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.802750 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952480 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952480 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.855138 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.855138 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.855138 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.855138 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127034.324220 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 127034.324220 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136288.473263 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 136288.473263 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 130640.757610 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 130640.757610 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 130640.757610 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 130640.757610 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1393328 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 394.919460 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771327 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771327 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8623 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8623 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1083 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9706 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9706 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9706 # number of overall hits +system.cpu5.l1c.overall_hits::total 9706 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35968 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35968 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22960 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22960 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58928 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58928 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58928 # number of overall misses +system.cpu5.l1c.overall_misses::total 58928 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1339036093 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1339036093 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1083656826 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1083656826 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2422692919 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2422692919 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2422692919 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2422692919 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44591 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44591 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24043 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24043 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68634 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68634 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68634 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806620 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806620 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954956 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954956 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858583 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858583 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37228.539062 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47197.596951 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47197.596951 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41112.763355 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41112.763355 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41112.763355 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1432391 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63640 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66951 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.893903 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9848 # number of writebacks -system.cpu5.l1c.writebacks::total 9848 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35846 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35846 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22890 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22890 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58736 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58736 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58736 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58736 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4481994386 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4481994386 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3073871153 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3073871153 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7555865539 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7555865539 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7555865539 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7555865539 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1395127827 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1395127827 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 940338919 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 940338919 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2335466746 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2335466746 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802750 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802750 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952480 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952480 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.855138 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.855138 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125034.714780 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125034.714780 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134288.822761 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134288.822761 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9691 # number of writebacks +system.cpu5.l1c.writebacks::total 9691 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35968 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22960 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22960 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58928 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58928 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58928 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58928 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1267104093 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1267104093 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1037740826 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1037740826 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2304844919 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2304844919 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2304844919 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2304844919 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 711626590 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 711626590 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 438340423 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 438340423 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1149967013 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1149967013 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806620 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806620 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954956 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954956 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35228.650272 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45197.771167 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45197.771167 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1347,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 97085 # number of read accesses completed -system.cpu6.num_writes 52397 # number of write accesses completed +system.cpu6.num_reads 98175 # number of read accesses completed +system.cpu6.num_writes 52998 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21752 # number of replacements -system.cpu6.l1c.tagsinuse 389.740766 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13001 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22153 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586873 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21915 # number of replacements +system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13077 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22297 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 389.740766 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.761212 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.761212 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8437 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8437 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9519 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9519 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9519 # number of overall hits -system.cpu6.l1c.overall_hits::total 9519 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35128 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35128 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22626 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22626 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 57754 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 57754 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 57754 # number of overall misses -system.cpu6.l1c.overall_misses::total 57754 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4550980379 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4550980379 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3080862665 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3080862665 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7631843044 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7631843044 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7631843044 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7631843044 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 43565 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 43565 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23708 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23708 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 67273 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 67273 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 67273 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 67273 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806335 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806335 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954361 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954361 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858502 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858502 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858502 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858502 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129554.212565 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 129554.212565 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136164.707195 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 136164.707195 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132143.973474 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132143.973474 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132143.973474 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132143.973474 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1372349 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 395.370816 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.772209 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.772209 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8591 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8591 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1078 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1078 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9669 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9669 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9669 # number of overall hits +system.cpu6.l1c.overall_hits::total 9669 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35673 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35673 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22773 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22773 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58446 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58446 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58446 # number of overall misses +system.cpu6.l1c.overall_misses::total 58446 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1336174857 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1336174857 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1084897863 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1084897863 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2421072720 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2421072720 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2421072720 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2421072720 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44264 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44264 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23851 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68115 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68115 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68115 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68115 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805915 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805915 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954803 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954803 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858049 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858049 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858049 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858049 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37456.195358 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37456.195358 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47639.654986 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 47639.654986 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 41424.096089 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 41424.096089 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 41424.096089 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 41424.096089 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1432460 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62634 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66523 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.910608 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.533304 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9668 # number of writebacks -system.cpu6.l1c.writebacks::total 9668 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35128 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35128 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22626 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22626 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 57754 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 57754 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 57754 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 57754 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4480736379 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4480736379 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3035616665 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3035616665 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7516353044 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7516353044 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7516353044 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7516353044 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1387372518 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1387372518 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 999274904 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 999274904 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2386647422 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2386647422 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806335 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806335 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954361 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954361 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858502 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858502 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127554.554173 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127554.554173 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134164.972377 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134164.972377 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9553 # number of writebacks +system.cpu6.l1c.writebacks::total 9553 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35673 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35673 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22773 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22773 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58446 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58446 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58446 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58446 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1264832857 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1264832857 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1039353863 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1039353863 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2304186720 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2304186720 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2304186720 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2304186720 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 711871628 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 711871628 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 446494550 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 446494550 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1158366178 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1158366178 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954803 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954803 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858049 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858049 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35456.307487 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35456.307487 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45639.742809 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45639.742809 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1462,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98863 # number of read accesses completed -system.cpu7.num_writes 52856 # number of write accesses completed +system.cpu7.num_reads 98453 # number of read accesses completed +system.cpu7.num_writes 53303 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22616 # number of replacements -system.cpu7.l1c.tagsinuse 391.615445 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13178 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 23003 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.572882 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22126 # number of replacements +system.cpu7.l1c.tagsinuse 394.997672 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13256 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.588006 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 391.615445 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.764874 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.764874 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8679 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8679 # number of ReadReq hits +system.cpu7.l1c.occ_blocks::cpu7 394.997672 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.771480 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.771480 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8720 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8720 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9777 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9777 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9777 # number of overall hits -system.cpu7.l1c.overall_hits::total 9777 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35968 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35968 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22753 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22753 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58721 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58721 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58721 # number of overall misses -system.cpu7.l1c.overall_misses::total 58721 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4555865271 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4555865271 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3104187449 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3104187449 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7660052720 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7660052720 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7660052720 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7660052720 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44647 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44647 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 23851 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68498 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68498 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68498 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68498 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805608 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805608 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953964 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953964 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857266 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857266 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857266 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857266 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 126664.403664 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 126664.403664 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136429.809212 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 136429.809212 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 130448.267570 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 130448.267570 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 130448.267570 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 130448.267570 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1381368 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 9818 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9818 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9818 # number of overall hits +system.cpu7.l1c.overall_hits::total 9818 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35443 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35443 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23039 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23039 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58482 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58482 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58482 # number of overall misses +system.cpu7.l1c.overall_misses::total 58482 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1325635544 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1325635544 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1095033308 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1095033308 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2420668852 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2420668852 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2420668852 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2420668852 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44163 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44163 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24137 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68300 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68300 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68300 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68300 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.802550 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.802550 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954510 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954510 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.856252 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.856252 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.856252 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.856252 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37401.900065 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 37401.900065 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47529.550241 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47529.550241 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 41391.690640 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 41391.690640 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 41391.690640 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 41391.690640 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1432038 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63977 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66517 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.591634 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.528902 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9880 # number of writebacks -system.cpu7.l1c.writebacks::total 9880 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35968 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22753 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22753 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58721 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58721 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58721 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58721 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4483949271 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4483949271 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3058683449 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3058683449 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7542632720 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7542632720 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7542632720 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7542632720 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1380003854 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1380003854 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 891969960 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 891969960 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2271973814 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2271973814 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805608 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805608 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857266 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857266 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 124664.959714 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 124664.959714 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134429.897112 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134429.897112 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks +system.cpu7.l1c.writebacks::total 9733 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |