diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-22 10:49:09 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-22 10:49:09 +0100 |
| commit | d0ffd2f9b88d6abb29ed861deec12b40bdb7419f (patch) | |
| tree | a7ef700a3fd665d825752ae17799b4f1c46bd0cd /tests/quick/se/50.memtest/ref/null/none | |
| parent | 39663dc77c5e74a21b92c9347553ea0c5a302e2e (diff) | |
| download | gem5-d0ffd2f9b88d6abb29ed861deec12b40bdb7419f.tar.xz | |
test: Make the memtest and memcheck tests functional only
The memtest and memcheck are not designed to test timing. Make them
functional only to make ref diffs less noisy in the future.
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'tests/quick/se/50.memtest/ref/null/none')
10 files changed, 0 insertions, 5202 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/EMPTY b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/EMPTY diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini deleted file mode 100644 index a2f7231b1..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini +++ /dev/null @@ -1,742 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu0.l1c.cpu_side - -[system.cpu0.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu1.l1c.cpu_side - -[system.cpu1.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.port -mem_side=system.toL2Bus.slave[1] - -[system.cpu1.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu2] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu2.l1c.cpu_side - -[system.cpu2.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu2.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu2.port -mem_side=system.toL2Bus.slave[2] - -[system.cpu2.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu3] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu3.l1c.cpu_side - -[system.cpu3.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu3.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu3.port -mem_side=system.toL2Bus.slave[3] - -[system.cpu3.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu4] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu4.l1c.cpu_side - -[system.cpu4.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu4.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu4.port -mem_side=system.toL2Bus.slave[4] - -[system.cpu4.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu5] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu5.l1c.cpu_side - -[system.cpu5.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu5.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu5.port -mem_side=system.toL2Bus.slave[5] - -[system.cpu5.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu6] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu6.l1c.cpu_side - -[system.cpu6.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu6.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu6.port -mem_side=system.toL2Bus.slave[6] - -[system.cpu6.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu7] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu7.l1c.cpu_side - -[system.cpu7.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu7.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu7.port -mem_side=system.toL2Bus.slave[7] - -[system.cpu7.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=65536 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=65536 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.l2c.mem_side system.system_port - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr deleted file mode 100755 index 01d1cac03..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr +++ /dev/null @@ -1,73 +0,0 @@ -system.cpu3: completed 10000 read, 5503 write accesses @55915500 -system.cpu4: completed 10000 read, 5302 write accesses @55980000 -system.cpu7: completed 10000 read, 5500 write accesses @56129000 -system.cpu2: completed 10000 read, 5342 write accesses @56146500 -system.cpu6: completed 10000 read, 5358 write accesses @56494500 -system.cpu0: completed 10000 read, 5493 write accesses @56861500 -system.cpu1: completed 10000 read, 5676 write accesses @57033500 -system.cpu5: completed 10000 read, 5528 write accesses @57497500 -system.cpu4: completed 20000 read, 10871 write accesses @105086000 -system.cpu7: completed 20000 read, 11018 write accesses @105227000 -system.cpu6: completed 20000 read, 10904 write accesses @105245500 -system.cpu0: completed 20000 read, 10841 write accesses @105416500 -system.cpu3: completed 20000 read, 11147 write accesses @105878500 -system.cpu2: completed 20000 read, 10930 write accesses @106485500 -system.cpu5: completed 20000 read, 10954 write accesses @106687000 -system.cpu1: completed 20000 read, 11324 write accesses @107095000 -system.cpu4: completed 30000 read, 16387 write accesses @154433500 -system.cpu6: completed 30000 read, 16529 write accesses @154891500 -system.cpu2: completed 30000 read, 16387 write accesses @154906000 -system.cpu3: completed 30000 read, 16756 write accesses @155604500 -system.cpu7: completed 30000 read, 16642 write accesses @155734000 -system.cpu5: completed 30000 read, 16445 write accesses @156039500 -system.cpu0: completed 30000 read, 16469 write accesses @156104500 -system.cpu1: completed 30000 read, 16825 write accesses @156708500 -system.cpu6: completed 40000 read, 21980 write accesses @203895500 -system.cpu4: completed 40000 read, 22029 write accesses @204285000 -system.cpu3: completed 40000 read, 22257 write accesses @204704000 -system.cpu7: completed 40000 read, 22193 write accesses @205001500 -system.cpu2: completed 40000 read, 22047 write accesses @205470000 -system.cpu5: completed 40000 read, 22004 write accesses @206055000 -system.cpu0: completed 40000 read, 21987 write accesses @206174000 -system.cpu1: completed 40000 read, 22532 write accesses @206732500 -system.cpu4: completed 50000 read, 27591 write accesses @253615500 -system.cpu6: completed 50000 read, 27369 write accesses @253616500 -system.cpu2: completed 50000 read, 27561 write accesses @254261500 -system.cpu7: completed 50000 read, 27945 write accesses @254398000 -system.cpu5: completed 50000 read, 27346 write accesses @254644500 -system.cpu3: completed 50000 read, 27794 write accesses @254687000 -system.cpu0: completed 50000 read, 27491 write accesses @255540000 -system.cpu1: completed 50000 read, 28147 write accesses @256393500 -system.cpu4: completed 60000 read, 33155 write accesses @302912000 -system.cpu6: completed 60000 read, 33024 write accesses @303044500 -system.cpu5: completed 60000 read, 32819 write accesses @303948500 -system.cpu7: completed 60000 read, 33412 write accesses @304003500 -system.cpu2: completed 60000 read, 33183 write accesses @305097000 -system.cpu3: completed 60000 read, 33603 write accesses @305311500 -system.cpu1: completed 60000 read, 33393 write accesses @305569000 -system.cpu0: completed 60000 read, 33038 write accesses @305621500 -system.cpu4: completed 70000 read, 38636 write accesses @352443000 -system.cpu5: completed 70000 read, 38516 write accesses @353701000 -system.cpu6: completed 70000 read, 38725 write accesses @353942000 -system.cpu7: completed 70000 read, 39072 write accesses @354424000 -system.cpu2: completed 70000 read, 38818 write accesses @354701000 -system.cpu1: completed 70000 read, 38717 write accesses @354858500 -system.cpu3: completed 70000 read, 39274 write accesses @355379500 -system.cpu0: completed 70000 read, 38744 write accesses @355617500 -system.cpu4: completed 80000 read, 44404 write accesses @402767500 -system.cpu2: completed 80000 read, 44188 write accesses @403291500 -system.cpu5: completed 80000 read, 44099 write accesses @403371500 -system.cpu7: completed 80000 read, 44629 write accesses @403854500 -system.cpu6: completed 80000 read, 44307 write accesses @404062000 -system.cpu0: completed 80000 read, 44206 write accesses @404147000 -system.cpu1: completed 80000 read, 44256 write accesses @404649000 -system.cpu3: completed 80000 read, 44966 write accesses @406154000 -system.cpu4: completed 90000 read, 49951 write accesses @452283500 -system.cpu5: completed 90000 read, 49582 write accesses @452363500 -system.cpu2: completed 90000 read, 49727 write accesses @452365500 -system.cpu6: completed 90000 read, 49789 write accesses @453642000 -system.cpu0: completed 90000 read, 49883 write accesses @453665500 -system.cpu7: completed 90000 read, 50370 write accesses @454276500 -system.cpu1: completed 90000 read, 49817 write accesses @454621500 -system.cpu3: completed 90000 read, 50461 write accesses @455559000 -system.cpu5: completed 100000 read, 55110 write accesses @501584000 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout deleted file mode 100755 index ee02aa361..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout +++ /dev/null @@ -1,13 +0,0 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 21 2016 14:24:31 -gem5 started Jul 21 2016 14:24:50 -gem5 executing on e108600-lin, pid 18184 -command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest-filter - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 501584000 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt deleted file mode 100644 index 4b7a057ad..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ /dev/null @@ -1,1777 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000520 # Number of seconds simulated -sim_ticks 519755500 # Number of ticks simulated -final_tick 519755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 97602781 # Simulator tick rate (ticks/s) -host_mem_usage 236356 # Number of bytes of host memory used -host_seconds 5.33 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 252685 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 258147 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 248443 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 257431 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 256206 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 249786 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 257817 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 255503 # Number of bytes read from this memory -system.physmem.bytes_read::total 2036018 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 1421696 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5545 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5403 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5468 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5504 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5430 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5562 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5554 # Number of bytes written to this memory -system.physmem.bytes_written::total 1465524 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 13663 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 13833 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 13579 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 13621 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 13782 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 13599 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 13692 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 13646 # Number of read requests responded to by this memory -system.physmem.num_reads::total 109415 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 22214 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5545 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5403 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5468 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5504 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5430 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5562 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5554 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66042 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 486161282 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 496670069 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 477999752 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 495292498 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 492935621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 480583659 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 496035155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 491583062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3917261097 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2735316894 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10668478 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10395272 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10520331 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10589595 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10447220 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10316389 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10701185 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10685794 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2819641158 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2735316894 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 496829759 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 507065341 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 488520083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 505882093 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 503382841 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 490900048 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 506736340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 502268855 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6736902255 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99523 # number of read accesses completed -system.cpu0.num_writes 55175 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22190 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.732266 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13637 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22577 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.604022 # Average number of references to valid blocks. -system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.732266 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.765102 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.765102 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338094 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338094 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8745 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8745 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1203 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1203 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9948 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9948 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9948 # number of overall hits -system.cpu0.l1c.overall_hits::total 9948 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36338 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36338 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24073 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24073 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60411 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60411 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60411 # number of overall misses -system.cpu0.l1c.overall_misses::total 60411 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 720327390 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 720327390 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 585363499 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 585363499 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1305690889 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1305690889 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1305690889 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1305690889 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45083 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45083 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25276 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25276 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70359 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70359 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70359 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70359 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806024 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806024 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952405 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952405 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858611 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858611 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858611 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858611 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19822.978425 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 19822.978425 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24316.184065 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 24316.184065 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21613.462598 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21613.462598 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21613.462598 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21613.462598 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 881814 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67116 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.138655 # average number of cycles each access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 9797 # number of writebacks -system.cpu0.l1c.writebacks::total 9797 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36338 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36338 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24073 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24073 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60411 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60411 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60411 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60411 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5547 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5547 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15416 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15416 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 683989390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 683989390 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 561290499 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 561290499 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245279889 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1245279889 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245279889 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1245279889 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 771084187 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 771084187 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 771084187 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 771084187 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806024 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806024 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952405 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952405 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858611 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858611 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18822.978425 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18822.978425 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23316.184065 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23316.184065 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78131.947208 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78131.947208 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50018.434549 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50018.434549 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99560 # number of read accesses completed -system.cpu1.num_writes 54738 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22160 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.166928 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13521 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22561 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.599309 # Average number of references to valid blocks. -system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.166928 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.765951 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.765951 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 337076 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 337076 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8807 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8807 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1218 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1218 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10025 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10025 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10025 # number of overall hits -system.cpu1.l1c.overall_hits::total 10025 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36399 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36399 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23708 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23708 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60107 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60107 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60107 # number of overall misses -system.cpu1.l1c.overall_misses::total 60107 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 728138208 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 728138208 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 572668423 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 572668423 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1300806631 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1300806631 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1300806631 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1300806631 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45206 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45206 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24926 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24926 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70132 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70132 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70132 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70132 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805181 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805181 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.951135 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.951135 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857055 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857055 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857055 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857055 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 20004.346493 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 20004.346493 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24155.070989 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 24155.070989 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21641.516479 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21641.516479 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21641.516479 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21641.516479 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 883013 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66936 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.191900 # average number of cycles each access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9595 # number of writebacks -system.cpu1.l1c.writebacks::total 9595 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36399 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36399 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23708 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23708 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60107 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60107 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60107 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60107 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9955 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5404 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15359 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15359 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 691742208 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 691742208 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 548961423 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 548961423 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1240703631 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1240703631 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1240703631 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1240703631 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 776683501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 776683501 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 776683501 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 776683501 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805181 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.951135 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.951135 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857055 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857055 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 19004.428913 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 19004.428913 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23155.113169 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23155.113169 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78019.437569 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78019.437569 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50568.624325 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50568.624325 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 98983 # number of read accesses completed -system.cpu2.num_writes 55204 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22113 # number of replacements -system.cpu2.l1c.tags.tagsinuse 391.892697 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13532 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. -system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 391.892697 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.765415 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.765415 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337818 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337818 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1144 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1144 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9934 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9934 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9934 # number of overall hits -system.cpu2.l1c.overall_hits::total 9934 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36176 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36176 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24169 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24169 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses -system.cpu2.l1c.overall_misses::total 60345 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 716181593 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 716181593 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 589266088 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 589266088 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1305447681 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1305447681 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1305447681 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1305447681 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44966 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25313 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25313 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70279 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70279 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70279 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70279 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804519 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.804519 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954806 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954806 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858649 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858649 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858649 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858649 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19797.147086 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 19797.147086 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24381.070297 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 24381.070297 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21633.071191 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21633.071191 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21633.071191 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21633.071191 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 879879 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66865 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.159037 # average number of cycles each access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks -system.cpu2.l1c.writebacks::total 9745 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36176 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36176 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24169 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24169 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9851 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5469 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15320 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15320 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 680005593 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 680005593 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 565098088 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 565098088 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245103681 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1245103681 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245103681 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1245103681 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769729433 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769729433 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769729433 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769729433 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804519 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804519 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954806 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954806 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858649 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858649 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18797.147086 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18797.147086 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23381.111672 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23381.111672 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78137.187392 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78137.187392 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50243.435574 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50243.435574 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 100000 # number of read accesses completed -system.cpu3.num_writes 55136 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22201 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.334218 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13633 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22606 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.603070 # Average number of references to valid blocks. -system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.334218 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766278 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766278 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 339332 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 339332 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8805 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8805 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1190 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1190 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9995 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9995 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9995 # number of overall hits -system.cpu3.l1c.overall_hits::total 9995 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36852 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36852 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23757 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23757 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60609 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60609 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60609 # number of overall misses -system.cpu3.l1c.overall_misses::total 60609 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 737200497 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 737200497 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 577684792 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 577684792 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1314885289 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1314885289 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1314885289 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1314885289 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45657 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45657 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24947 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24947 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70604 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70604 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70604 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70604 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807149 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807149 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952299 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.952299 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858436 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858436 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858436 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858436 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 20004.355177 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 20004.355177 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24316.403250 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 24316.403250 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21694.555083 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21694.555083 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21694.555083 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21694.555083 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 880663 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67164 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.112129 # average number of cycles each access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 9556 # number of writebacks -system.cpu3.l1c.writebacks::total 9556 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36852 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36852 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23757 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23757 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60609 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60609 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60609 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60609 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9752 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9752 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5506 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15258 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15258 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 700349497 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 700349497 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 553928792 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 553928792 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1254278289 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1254278289 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1254278289 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1254278289 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 761853080 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 761853080 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 761853080 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 761853080 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807149 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807149 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952299 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952299 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858436 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858436 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 19004.382313 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 19004.382313 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23316.445342 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23316.445342 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78122.752256 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78122.752256 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 49931.385503 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 49931.385503 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 99808 # number of read accesses completed -system.cpu4.num_writes 55157 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22030 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.026241 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13726 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22418 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.612276 # Average number of references to valid blocks. -system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.026241 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765676 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765676 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 338084 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 338084 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8869 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8869 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1181 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1181 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10050 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10050 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10050 # number of overall hits -system.cpu4.l1c.overall_hits::total 10050 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36458 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36458 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23868 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23868 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60326 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60326 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60326 # number of overall misses -system.cpu4.l1c.overall_misses::total 60326 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 723342269 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 723342269 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 578669341 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 578669341 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1302011610 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1302011610 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1302011610 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1302011610 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45327 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45327 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25049 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70376 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70376 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70376 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70376 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804333 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804333 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952852 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.952852 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857196 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857196 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857196 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857196 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19840.426491 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 19840.426491 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24244.567664 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 24244.567664 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21582.926267 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21582.926267 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21582.926267 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21582.926267 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 883463 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67109 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.164598 # average number of cycles each access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9613 # number of writebacks -system.cpu4.l1c.writebacks::total 9613 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36458 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23868 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23868 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60326 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60326 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60326 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60326 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5430 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15364 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 686885269 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 686885269 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 554802341 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 554802341 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1241687610 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1241687610 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1241687610 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1241687610 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 775754665 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 775754665 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 775754665 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 775754665 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804333 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804333 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952852 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952852 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857196 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857196 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18840.453920 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18840.453920 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23244.609561 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23244.609561 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78090.866217 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78090.866217 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50491.712119 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50491.712119 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 99404 # number of read accesses completed -system.cpu5.num_writes 55162 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22439 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.788419 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13514 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22846 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.591526 # Average number of references to valid blocks. -system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.788419 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765212 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765212 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338295 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338295 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8686 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8686 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1223 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1223 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9909 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9909 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9909 # number of overall hits -system.cpu5.l1c.overall_hits::total 9909 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36676 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36676 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23788 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23788 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60464 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60464 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60464 # number of overall misses -system.cpu5.l1c.overall_misses::total 60464 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 728782621 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 728782621 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 575848202 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 575848202 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1304630823 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1304630823 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1304630823 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1304630823 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45362 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45362 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25011 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70373 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70373 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70373 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70373 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808518 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808518 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951102 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951102 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859193 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859193 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859193 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859193 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19870.831634 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 19870.831634 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24207.508071 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 24207.508071 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21576.985032 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21576.985032 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21576.985032 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21576.985032 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 880240 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 67028 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.132422 # average number of cycles each access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 9753 # number of writebacks -system.cpu5.l1c.writebacks::total 9753 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36676 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23788 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60464 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60464 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60464 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60464 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9850 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5362 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15212 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 692108621 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 692108621 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 552061202 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 552061202 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1244169823 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1244169823 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1244169823 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1244169823 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 771042075 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 771042075 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 771042075 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 771042075 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808518 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808518 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951102 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951102 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859193 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859193 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18870.886165 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18870.886165 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23207.550109 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23207.550109 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78278.383249 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78278.383249 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50686.436695 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50686.436695 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 99584 # number of read accesses completed -system.cpu6.num_writes 55158 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22137 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.593819 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13609 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22548 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.603557 # Average number of references to valid blocks. -system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.593819 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.764832 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.764832 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338403 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338403 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8781 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8781 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1188 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1188 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9969 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9969 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9969 # number of overall hits -system.cpu6.l1c.overall_hits::total 9969 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36497 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36497 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23948 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23948 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60445 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60445 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60445 # number of overall misses -system.cpu6.l1c.overall_misses::total 60445 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 730258004 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 730258004 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 580007386 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 580007386 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1310265390 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1310265390 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1310265390 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1310265390 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45278 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45278 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25136 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70414 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70414 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806065 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806065 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952737 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.952737 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858423 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858423 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 20008.713155 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 20008.713155 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24219.449891 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 24219.449891 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21676.985524 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21676.985524 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21676.985524 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21676.985524 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 882368 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 67127 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.144755 # average number of cycles each access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9587 # number of writebacks -system.cpu6.l1c.writebacks::total 9587 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36497 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36497 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23948 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23948 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60445 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60445 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9817 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5564 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5564 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15381 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 693763004 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 693763004 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 556061386 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 556061386 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1249824390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1249824390 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1249824390 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1249824390 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767059984 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767059984 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 767059984 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 767059984 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806065 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806065 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952737 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952737 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 19008.767954 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 19008.767954 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23219.533406 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23219.533406 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78135.885097 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78135.885097 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 49870.618555 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 49870.618555 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 98890 # number of read accesses completed -system.cpu7.num_writes 55602 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 22121 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.886114 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13491 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22504 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.599493 # Average number of references to valid blocks. -system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.886114 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765403 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765403 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 383 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.748047 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 336547 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 336547 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8615 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8615 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1223 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1223 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9838 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9838 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9838 # number of overall hits -system.cpu7.l1c.overall_hits::total 9838 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36077 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36077 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24110 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24110 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60187 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60187 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60187 # number of overall misses -system.cpu7.l1c.overall_misses::total 60187 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 719876948 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 719876948 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 591584960 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 591584960 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1311461908 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1311461908 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1311461908 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1311461908 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44692 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25333 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25333 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70025 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70025 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70025 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70025 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807236 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807236 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951723 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.951723 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859507 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859507 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859507 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859507 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19953.902708 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 19953.902708 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24536.912484 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 24536.912484 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21789.786964 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21789.786964 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21789.786964 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21789.786964 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 881767 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66704 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.219102 # average number of cycles each access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9764 # number of writebacks -system.cpu7.l1c.writebacks::total 9764 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36077 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36077 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24110 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24110 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60187 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60187 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60187 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60187 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5554 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15362 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 683799948 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 683799948 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 567476960 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 567476960 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1251276908 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1251276908 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1251276908 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1251276908 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 764550984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 764550984 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 764550984 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 764550984 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807236 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807236 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951723 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951723 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859507 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859507 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18953.902708 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18953.902708 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23536.995438 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23536.995438 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 77951.772431 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 77951.772431 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49768.974352 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49768.974352 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 90719 # number of replacements -system.l2c.tags.tagsinuse 1018.150991 # Cycle average of tags in use -system.l2c.tags.total_refs 149983 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 91743 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.634817 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 9046000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 702.470265 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 39.119320 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 40.193520 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 38.067708 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 40.504400 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 39.836129 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 39.104490 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 39.067369 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 39.787790 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.686006 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.038202 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.039251 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.037175 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.039555 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.038902 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.038188 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.038152 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.038855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994288 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 929 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2127679 # Number of tag accesses -system.l2c.tags.data_accesses 2127679 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 76258 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 76258 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 455 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 421 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 452 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 407 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 451 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 439 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 454 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 475 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3554 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1826 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1861 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1960 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1829 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1856 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1881 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14892 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 9343 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 9296 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 9301 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 9456 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 9362 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 9172 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 9284 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 9134 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 74348 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 11169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 11157 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 11261 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 11285 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 11233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 10980 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 11140 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 11015 # number of demand (read+write) hits -system.l2c.demand_hits::total 89240 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 11169 # number of overall hits -system.l2c.overall_hits::cpu1 11157 # number of overall hits -system.l2c.overall_hits::cpu2 11261 # number of overall hits -system.l2c.overall_hits::cpu3 11285 # number of overall hits -system.l2c.overall_hits::cpu4 11233 # number of overall hits -system.l2c.overall_hits::cpu5 10980 # number of overall hits -system.l2c.overall_hits::cpu6 11140 # number of overall hits -system.l2c.overall_hits::cpu7 11015 # number of overall hits -system.l2c.overall_hits::total 89240 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1925 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1836 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1914 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1942 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1877 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1911 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15209 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4693 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4629 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4644 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4614 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4607 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4628 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4562 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4784 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37161 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 2455 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 2583 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 2376 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 2554 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 2482 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 2499 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 2567 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 2497 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 20013 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 7148 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 7212 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 7020 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 7168 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 7089 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 7127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 7129 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 7281 # number of demand (read+write) misses -system.l2c.demand_misses::total 57174 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 7148 # number of overall misses -system.l2c.overall_misses::cpu1 7212 # number of overall misses -system.l2c.overall_misses::cpu2 7020 # number of overall misses -system.l2c.overall_misses::cpu3 7168 # number of overall misses -system.l2c.overall_misses::cpu4 7089 # number of overall misses -system.l2c.overall_misses::cpu5 7127 # number of overall misses -system.l2c.overall_misses::cpu6 7129 # number of overall misses -system.l2c.overall_misses::cpu7 7281 # number of overall misses -system.l2c.overall_misses::total 57174 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 32240808 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 31334307 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 31443971 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 32481798 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 31939294 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 32487949 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 32438947 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 31458982 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 255826056 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 205522581 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 201589053 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 204096506 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 201630443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 202953396 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 200092863 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 200475342 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 208573158 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1624933342 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 170016591 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 178762923 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 164403073 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 176363992 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 171439292 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 173166429 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 177285527 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 173293048 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1384730875 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 375539172 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 380351976 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 368499579 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 377994435 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 374392688 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 373259292 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 377760869 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 381866206 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 3009664217 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 375539172 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 380351976 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 368499579 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 377994435 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 374392688 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 373259292 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 377760869 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 381866206 # number of overall miss cycles -system.l2c.overall_miss_latency::total 3009664217 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 76258 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 76258 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2380 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2257 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2366 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2393 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2352 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2386 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18763 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6519 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6490 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6604 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6443 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6478 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6418 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6665 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 52053 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11798 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11879 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11677 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 12010 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11844 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11671 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11851 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11631 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 94361 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18317 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18369 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18281 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18453 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18322 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18107 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18269 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18296 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 146414 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18317 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18369 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18281 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18453 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18322 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18107 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18269 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18296 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 146414 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.808824 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.813469 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.808960 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.824038 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.811534 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.810449 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.806973 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.800922 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.810585 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.719896 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.713251 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.703210 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.716126 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.711176 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.719080 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.710813 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.717779 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.713907 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.208086 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.217443 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.203477 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.212656 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.209558 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.214120 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.216606 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.214685 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.212090 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.390239 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.392618 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.384005 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.388446 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.386912 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.393605 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.390224 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.397956 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.390495 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.390239 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.392618 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.384005 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.388446 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.386912 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.393605 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.390224 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.397956 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.390495 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16748.471688 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 17066.616013 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16428.407001 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 17041.866737 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 16446.598352 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 17308.443793 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 17091.120653 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 16462.052329 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16820.701953 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 43793.432985 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 43549.158134 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 43948.429371 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 43699.705895 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 44053.265900 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 43235.277226 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 43944.616835 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 43598.068144 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 43726.846479 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 69253.193890 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69207.480836 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69193.212542 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69054.029757 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69073.042707 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69294.289316 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69063.313985 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69400.499800 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 69191.569230 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 52537.656967 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 52738.765391 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 52492.817521 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 52733.598633 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 52813.187756 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 52372.567981 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 52989.320943 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 52446.944925 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52640.434761 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 52537.656967 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 52738.765391 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 52492.817521 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 52733.598633 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 52813.187756 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 52372.567981 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 52989.320943 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 52446.944925 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52640.434761 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 47178 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 7722 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.109557 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 22214 # number of writebacks -system.l2c.writebacks::total 22214 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 3 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 3 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 18 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 16 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 18 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 19 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 22 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 24 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 19 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 17 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 18 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 153 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 39 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 35 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 40 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 33 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 29 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 39 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 37 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 32 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 284 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 55 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 53 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 59 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 55 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 53 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 58 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 54 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 50 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 437 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 55 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 53 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 59 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 55 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 53 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 58 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 54 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 50 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 437 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4803 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4803 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1924 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1833 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1913 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1903 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1939 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1897 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1907 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15191 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4677 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4611 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4625 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4592 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4583 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4609 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4545 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4766 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37008 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 2416 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 2548 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 2336 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 2521 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 2453 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 2460 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 2530 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 2465 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 19729 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 7093 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 7159 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 6961 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 7113 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 7036 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 7069 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 7075 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 7231 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 56737 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 7093 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 7159 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 6961 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 7113 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 7036 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 7069 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 7075 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 7231 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 56737 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9751 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78835 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5546 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5403 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5468 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5504 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5563 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43830 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15415 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15358 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15319 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15255 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15380 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122665 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 44370463 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900556 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43952891 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 43546523 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44916850 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43178222 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 43968016 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 43732622 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 349566143 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 157972902 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 154816531 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 157133230 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 154812258 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 156142960 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 152972566 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 154139305 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 159984433 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1247974185 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 144081359 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 151505606 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 139163869 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 149583647 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 145392585 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146682187 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 150257353 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 146960130 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1173626736 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 302054261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 306322137 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 296297099 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 304395905 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 301535545 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 299654753 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 304396658 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 306944563 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2421600921 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 302054261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 306322137 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 296297099 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 304395905 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 301535545 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 299654753 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 304396658 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 306944563 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2421600921 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 562092060 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 566771491 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 561276835 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 555967979 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 566543445 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 562440249 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 559671781 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 557696401 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 4492460241 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 562092060 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 566771491 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 561276835 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 555967979 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 566543445 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 562440249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 559671781 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 557696401 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4492460241 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.808403 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.812140 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.808538 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.822741 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810280 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.809585 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.806548 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.799246 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.809625 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.717441 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.710478 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.700333 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.712711 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.707471 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.716128 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708165 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.715079 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.710968 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.204780 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.214496 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.200051 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.209908 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.207109 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.210779 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.213484 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.211934 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209080 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.387511 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.387511 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 23061.571206 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22859.004910 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22975.897020 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22883.091435 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 23164.956163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 23028.385067 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 23177.657354 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22932.680650 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23011.397736 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 33776.545221 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33575.478421 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33974.752432 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33713.470819 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 34070.032730 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33189.968757 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33914.038504 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33567.862568 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33721.740840 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59636.324089 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59460.598901 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59573.574058 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59335.044427 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59271.335100 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59626.905285 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59390.258103 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59618.713996 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59487.390947 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56955.320701 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56933.349171 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56976.635367 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 57016.508973 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 57030.747433 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 57100.532893 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 57010.469695 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56861.378569 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56985.605898 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36463.967564 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36903.990819 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36639.260722 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36444.967486 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36874.736071 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36973.458388 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36389.582640 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36303.632405 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 36623.814788 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 164288 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 148961 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78834 # Transaction distribution -system.membus.trans_dist::ReadResp 98509 # Transaction distribution -system.membus.trans_dist::WriteReq 43828 # Transaction distribution -system.membus.trans_dist::WriteResp 43821 # Transaction distribution -system.membus.trans_dist::WritebackDirty 22214 # Transaction distribution -system.membus.trans_dist::CleanEvict 4965 # Transaction distribution -system.membus.trans_dist::UpgradeReq 52120 # Transaction distribution -system.membus.trans_dist::ReadExReq 56238 # Transaction distribution -system.membus.trans_dist::ReadExResp 10901 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 19680 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 431110 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 431110 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3501537 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 3501537 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56051 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 276559 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 276559 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 276559 # Request fanout histogram -system.membus.reqLayer0.occupancy 402118445 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 77.4 # Layer utilization (%) -system.membus.respLayer0.occupancy 354384000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 68.2 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 665414 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 284013 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 85048 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 42676 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 42372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78835 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370283 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43830 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43821 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 98472 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 166953 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29477 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161940 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161937 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 291468 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133769 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133274 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133373 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133750 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133407 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133623 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133404 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1068068 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1804723 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795646 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1797908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1798742 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1795138 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1788203 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1789204 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1803712 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14373276 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 408427 # Total snoops (count) -system.toL2Bus.snoopTraffic 21069312 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 705291 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.195765 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.989501 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 180431 25.58% 25.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 295517 41.90% 67.48% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 157808 22.37% 89.86% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 56265 7.98% 97.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 13098 1.86% 99.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1998 0.28% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 166 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 8 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 705291 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 498497896 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102236927 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 101928534 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102159135 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102401165 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102112987 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102230994 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102247991 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101908995 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/EMPTY b/tests/quick/se/50.memtest/ref/null/none/memtest/EMPTY new file mode 100644 index 000000000..e69de29bb --- /dev/null +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/EMPTY diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini deleted file mode 100644 index cdf2da963..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini +++ /dev/null @@ -1,734 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain dvfs_handler l2c membus physmem toL2Bus voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[1] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu0] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu0.l1c.cpu_side - -[system.cpu0.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu0.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu0.port -mem_side=system.toL2Bus.slave[0] - -[system.cpu0.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu1] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu1.l1c.cpu_side - -[system.cpu1.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu1.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu1.port -mem_side=system.toL2Bus.slave[1] - -[system.cpu1.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu2] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu2.l1c.cpu_side - -[system.cpu2.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu2.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu2.port -mem_side=system.toL2Bus.slave[2] - -[system.cpu2.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu3] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu3.l1c.cpu_side - -[system.cpu3.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu3.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu3.port -mem_side=system.toL2Bus.slave[3] - -[system.cpu3.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu4] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu4.l1c.cpu_side - -[system.cpu4.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu4.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu4.port -mem_side=system.toL2Bus.slave[4] - -[system.cpu4.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu5] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu5.l1c.cpu_side - -[system.cpu5.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu5.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu5.port -mem_side=system.toL2Bus.slave[5] - -[system.cpu5.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu6] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu6.l1c.cpu_side - -[system.cpu6.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu6.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu6.port -mem_side=system.toL2Bus.slave[6] - -[system.cpu6.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu7] -type=MemTest -children=l1c -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -interval=1 -max_loads=100000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -percent_functional=50 -percent_reads=65 -percent_uncacheable=10 -power_model=Null -progress_check=5000000 -progress_interval=10000 -size=65536 -suppress_func_warnings=false -system=system -port=system.cpu7.l1c.cpu_side - -[system.cpu7.l1c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=4 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=2 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=32768 -system=system -tags=system.cpu7.l1c.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu7.port -mem_side=system.toL2Bus.slave[7] - -[system.cpu7.l1c.tags] -type=LRU -assoc=4 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=2 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=32768 - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.l2c] -type=Cache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -hit_latency=20 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=65536 -system=system -tags=system.l2c.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[0] - -[system.l2c.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -hit_latency=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=65536 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=Null -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port -slave=system.l2c.mem_side system.system_port - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727 -port=system.membus.master[0] - -[system.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.l2c.cpu_side -slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side - -[system.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr deleted file mode 100755 index 2b36322d9..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr +++ /dev/null @@ -1,73 +0,0 @@ -system.cpu2: completed 10000 read, 5501 write accesses @55798000 -system.cpu1: completed 10000 read, 5520 write accesses @55942500 -system.cpu4: completed 10000 read, 5672 write accesses @55948000 -system.cpu0: completed 10000 read, 5544 write accesses @56022500 -system.cpu6: completed 10000 read, 5523 write accesses @56194500 -system.cpu5: completed 10000 read, 5576 write accesses @56196500 -system.cpu3: completed 10000 read, 5638 write accesses @56648500 -system.cpu7: completed 10000 read, 5609 write accesses @56820000 -system.cpu6: completed 20000 read, 11092 write accesses @104740000 -system.cpu4: completed 20000 read, 11217 write accesses @105227500 -system.cpu0: completed 20000 read, 11130 write accesses @105598500 -system.cpu5: completed 20000 read, 11119 write accesses @105604000 -system.cpu2: completed 20000 read, 11021 write accesses @105822000 -system.cpu7: completed 20000 read, 11085 write accesses @105988500 -system.cpu3: completed 20000 read, 11232 write accesses @106234000 -system.cpu1: completed 20000 read, 11093 write accesses @106248000 -system.cpu6: completed 30000 read, 16618 write accesses @154364000 -system.cpu4: completed 30000 read, 16727 write accesses @154528000 -system.cpu5: completed 30000 read, 16661 write accesses @154991500 -system.cpu0: completed 30000 read, 16578 write accesses @155150000 -system.cpu7: completed 30000 read, 16597 write accesses @155572000 -system.cpu3: completed 30000 read, 16777 write accesses @155692000 -system.cpu2: completed 30000 read, 16783 write accesses @155741500 -system.cpu1: completed 30000 read, 16605 write accesses @155757500 -system.cpu4: completed 40000 read, 22227 write accesses @203532500 -system.cpu0: completed 40000 read, 22094 write accesses @203735500 -system.cpu2: completed 40000 read, 22329 write accesses @204034500 -system.cpu6: completed 40000 read, 22323 write accesses @204341500 -system.cpu5: completed 40000 read, 22093 write accesses @204530500 -system.cpu3: completed 40000 read, 22449 write accesses @204979500 -system.cpu7: completed 40000 read, 22085 write accesses @205200000 -system.cpu1: completed 40000 read, 22157 write accesses @205324500 -system.cpu2: completed 50000 read, 27810 write accesses @252814500 -system.cpu0: completed 50000 read, 27524 write accesses @252975000 -system.cpu4: completed 50000 read, 27619 write accesses @253195000 -system.cpu6: completed 50000 read, 27815 write accesses @253668000 -system.cpu5: completed 50000 read, 27749 write accesses @254286500 -system.cpu3: completed 50000 read, 28015 write accesses @254662000 -system.cpu1: completed 50000 read, 27700 write accesses @255277000 -system.cpu7: completed 50000 read, 27537 write accesses @255788500 -system.cpu2: completed 60000 read, 33479 write accesses @302616500 -system.cpu4: completed 60000 read, 33151 write accesses @302639500 -system.cpu0: completed 60000 read, 33158 write accesses @302949000 -system.cpu5: completed 60000 read, 33293 write accesses @303327000 -system.cpu6: completed 60000 read, 33367 write accesses @303498500 -system.cpu3: completed 60000 read, 33551 write accesses @304167000 -system.cpu1: completed 60000 read, 33190 write accesses @304842500 -system.cpu7: completed 60000 read, 33105 write accesses @305455501 -system.cpu4: completed 70000 read, 38677 write accesses @351659000 -system.cpu0: completed 70000 read, 38797 write accesses @352214500 -system.cpu2: completed 70000 read, 39135 write accesses @352355500 -system.cpu6: completed 70000 read, 38839 write accesses @353200500 -system.cpu5: completed 70000 read, 38774 write accesses @353284000 -system.cpu3: completed 70000 read, 38980 write accesses @353497000 -system.cpu1: completed 70000 read, 38895 write accesses @355264000 -system.cpu7: completed 70000 read, 38703 write accesses @355598500 -system.cpu2: completed 80000 read, 44512 write accesses @400360000 -system.cpu4: completed 80000 read, 44241 write accesses @401405500 -system.cpu0: completed 80000 read, 44424 write accesses @401492500 -system.cpu6: completed 80000 read, 44426 write accesses @402695000 -system.cpu5: completed 80000 read, 44250 write accesses @402938000 -system.cpu3: completed 80000 read, 44495 write accesses @403103500 -system.cpu1: completed 80000 read, 44343 write accesses @403920500 -system.cpu7: completed 80000 read, 44194 write accesses @404626000 -system.cpu0: completed 90000 read, 49874 write accesses @450153000 -system.cpu2: completed 90000 read, 50018 write accesses @450453000 -system.cpu4: completed 90000 read, 49959 write accesses @452038500 -system.cpu3: completed 90000 read, 50050 write accesses @452249000 -system.cpu5: completed 90000 read, 49902 write accesses @452294500 -system.cpu6: completed 90000 read, 50125 write accesses @453074500 -system.cpu1: completed 90000 read, 49995 write accesses @453105500 -system.cpu7: completed 90000 read, 49805 write accesses @454516500 -system.cpu2: completed 100000 read, 55556 write accesses @500337000 diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout deleted file mode 100755 index b287697fe..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout +++ /dev/null @@ -1,13 +0,0 @@ -Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout -Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jul 21 2016 14:24:31 -gem5 started Jul 21 2016 14:24:50 -gem5 executing on e108600-lin, pid 18186 -command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.memtest/null/none/memtest - -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 500337000 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt deleted file mode 100644 index 797f06fbf..000000000 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ /dev/null @@ -1,1777 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000522 # Number of seconds simulated -sim_ticks 521659000 # Number of ticks simulated -final_tick 521659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 99821577 # Simulator tick rate (ticks/s) -host_mem_usage 236108 # Number of bytes of host memory used -host_seconds 5.23 # Real time elapsed on the host -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 261574 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 259726 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 254844 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 256223 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 261709 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 259188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 257071 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 253171 # Number of bytes read from this memory -system.physmem.bytes_read::total 2063506 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 1454400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5412 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5468 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5497 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5381 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5437 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5503 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5505 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5688 # Number of bytes written to this memory -system.physmem.bytes_written::total 1498291 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 13795 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 13774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 13680 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 13673 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 13678 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 13740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 13765 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 13771 # Number of read requests responded to by this memory -system.physmem.num_reads::total 109876 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 22725 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5412 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5468 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5497 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5381 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5437 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5503 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5505 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5688 # Number of write requests responded to by this memory -system.physmem.num_writes::total 66616 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 501427178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 497884633 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 488526029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 491169519 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 501685967 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 496853308 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 492795102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 485318954 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3955660690 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2788028195 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10374593 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10481943 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10537535 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 10315168 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10422517 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10549037 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10552871 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10903675 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2872165533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2788028195 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 511801771 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 508366577 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 499063565 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 501484686 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 512108485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 507402345 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 503347973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 496222628 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6827826224 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99316 # number of read accesses completed -system.cpu0.num_writes 55523 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22284 # number of replacements -system.cpu0.l1c.tags.tagsinuse 390.956341 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13404 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.590667 # Average number of references to valid blocks. -system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 390.956341 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.763587 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.763587 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 337730 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 337730 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8729 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8729 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1158 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1158 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9887 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9887 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9887 # number of overall hits -system.cpu0.l1c.overall_hits::total 9887 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36226 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36226 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24124 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24124 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60350 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60350 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60350 # number of overall misses -system.cpu0.l1c.overall_misses::total 60350 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 712731918 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 712731918 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 593276823 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 593276823 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1306008741 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1306008741 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1306008741 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1306008741 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44955 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44955 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25282 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25282 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70237 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70237 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805828 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805828 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954197 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954197 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859234 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859234 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859234 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859234 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19674.596091 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 19674.596091 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24592.804800 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 24592.804800 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 21640.575659 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 21640.575659 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 21640.575659 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 21640.575659 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 872655 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66710 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.081322 # average number of cycles each access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 9923 # number of writebacks -system.cpu0.l1c.writebacks::total 9923 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36226 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36226 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24124 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60350 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60350 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60350 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60350 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9863 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5414 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15277 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 676507918 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 676507918 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 569152823 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 569152823 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245660741 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1245660741 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245660741 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1245660741 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 770027425 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 770027425 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 770027425 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 770027425 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805828 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805828 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954197 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954197 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859234 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859234 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18674.651300 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18674.651300 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23592.804800 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23592.804800 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78072.333469 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78072.333469 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50404.361131 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50404.361131 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99894 # number of read accesses completed -system.cpu1.num_writes 55231 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22436 # number of replacements -system.cpu1.l1c.tags.tagsinuse 391.315294 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13542 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.593609 # Average number of references to valid blocks. -system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 391.315294 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.764288 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.764288 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.736328 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338824 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338824 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8855 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8855 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10004 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10004 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10004 # number of overall hits -system.cpu1.l1c.overall_hits::total 10004 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36651 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36651 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23831 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23831 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60482 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60482 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60482 # number of overall misses -system.cpu1.l1c.overall_misses::total 60482 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 724296905 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 724296905 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 578481683 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 578481683 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1302778588 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1302778588 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1302778588 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1302778588 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45506 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45506 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24980 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70486 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70486 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70486 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70486 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805410 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.805410 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954003 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954003 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.858071 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.858071 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.858071 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.858071 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 19761.995716 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 19761.995716 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24274.335236 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 24274.335236 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 21539.938957 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 21539.938957 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 21539.938957 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 21539.938957 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 869423 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66885 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.998774 # average number of cycles each access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9819 # number of writebacks -system.cpu1.l1c.writebacks::total 9819 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36651 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36651 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23831 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60482 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60482 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60482 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60482 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9872 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15341 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 687646905 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 687646905 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 554650683 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 554650683 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1242297588 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1242297588 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1242297588 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1242297588 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 771585814 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 771585814 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 771585814 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 771585814 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805410 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805410 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954003 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954003 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.858071 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.858071 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 18762.023001 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 18762.023001 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23274.335236 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23274.335236 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78159.016815 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78159.016815 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50295.666123 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50295.666123 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 99314 # number of read accesses completed -system.cpu2.num_writes 55477 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22237 # number of replacements -system.cpu2.l1c.tags.tagsinuse 390.931192 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.596086 # Average number of references to valid blocks. -system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 390.931192 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.763537 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.763537 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 337492 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 337492 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8705 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8705 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1188 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1188 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9893 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9893 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9893 # number of overall hits -system.cpu2.l1c.overall_hits::total 9893 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36190 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36190 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60319 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60319 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60319 # number of overall misses -system.cpu2.l1c.overall_misses::total 60319 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 713868287 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 713868287 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 591883556 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 591883556 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1305751843 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1305751843 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1305751843 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1305751843 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44895 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44895 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25317 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25317 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70212 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70212 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70212 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70212 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806103 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806103 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953075 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953075 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859098 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859098 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859098 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859098 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19725.567477 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 19725.567477 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24529.966265 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 24529.966265 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 21647.438502 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 21647.438502 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 21647.438502 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 21647.438502 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 871392 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66762 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.052215 # average number of cycles each access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9753 # number of writebacks -system.cpu2.l1c.writebacks::total 9753 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36190 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60319 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60319 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60319 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60319 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9852 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15350 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 677680287 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 677680287 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 567754556 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 567754556 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245434843 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1245434843 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245434843 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1245434843 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769926007 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769926007 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769926007 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769926007 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806103 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806103 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953075 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953075 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859098 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859098 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18725.622741 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18725.622741 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23529.966265 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23529.966265 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78149.208993 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78149.208993 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50158.046059 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50158.046059 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 99963 # number of read accesses completed -system.cpu3.num_writes 54829 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22502 # number of replacements -system.cpu3.l1c.tags.tagsinuse 392.266593 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13442 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22904 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.586884 # Average number of references to valid blocks. -system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 392.266593 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.766146 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.766146 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338127 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338127 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8758 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8758 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1160 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1160 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9918 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9918 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9918 # number of overall hits -system.cpu3.l1c.overall_hits::total 9918 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36654 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36654 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23751 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23751 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60405 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60405 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60405 # number of overall misses -system.cpu3.l1c.overall_misses::total 60405 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 726630781 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 726630781 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 580088175 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 580088175 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1306718956 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1306718956 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1306718956 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1306718956 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45412 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45412 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24911 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24911 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70323 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70323 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70323 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70323 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807143 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807143 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953434 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953434 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.858965 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.858965 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.858965 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.858965 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 19824.051427 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 19824.051427 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24423.736895 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 24423.736895 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 21632.629021 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 21632.629021 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 21632.629021 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 21632.629021 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 870625 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66788 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.035650 # average number of cycles each access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 9808 # number of writebacks -system.cpu3.l1c.writebacks::total 9808 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36654 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36654 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23751 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23751 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60405 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60405 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60405 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60405 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9824 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9824 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5382 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15206 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15206 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 689977781 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 689977781 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 556338175 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 556338175 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1246315956 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1246315956 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1246315956 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1246315956 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 768661965 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 768661965 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 768661965 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 768661965 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807143 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807143 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953434 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953434 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.858965 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.858965 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 18824.078709 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 18824.078709 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23423.778999 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23423.778999 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78243.278196 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78243.278196 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 50549.912206 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 50549.912206 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 98794 # number of read accesses completed -system.cpu4.num_writes 54937 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22508 # number of replacements -system.cpu4.l1c.tags.tagsinuse 392.668091 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13409 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22922 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.584984 # Average number of references to valid blocks. -system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 392.668091 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.766930 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.766930 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.808594 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337369 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337369 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1134 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1134 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9873 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9873 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9873 # number of overall hits -system.cpu4.l1c.overall_hits::total 9873 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36311 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36311 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23983 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23983 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60294 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60294 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60294 # number of overall misses -system.cpu4.l1c.overall_misses::total 60294 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 724331862 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 724331862 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 586488864 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 586488864 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1310820726 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1310820726 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1310820726 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1310820726 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45050 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45050 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25117 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25117 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70167 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70167 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70167 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70167 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806016 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.806016 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954851 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954851 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859293 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859293 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859293 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859293 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19948.000936 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 19948.000936 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24454.357837 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 24454.357837 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 21740.483730 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 21740.483730 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 21740.483730 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 21740.483730 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 869421 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66532 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.067712 # average number of cycles each access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9883 # number of writebacks -system.cpu4.l1c.writebacks::total 9883 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36311 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36311 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23983 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60294 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60294 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5439 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5439 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15180 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15180 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 688022862 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 688022862 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 562507864 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 562507864 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1250530726 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1250530726 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1250530726 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1250530726 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 763019844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 763019844 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 763019844 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 763019844 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806016 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806016 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954851 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954851 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859293 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859293 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18948.056016 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18948.056016 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23454.441229 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23454.441229 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78330.750847 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78330.750847 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50264.811858 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50264.811858 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 99762 # number of read accesses completed -system.cpu5.num_writes 55488 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22372 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.676077 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13488 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22774 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592254 # Average number of references to valid blocks. -system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.676077 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.764992 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.764992 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338416 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338416 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8728 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8728 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1164 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1164 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9892 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9892 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9892 # number of overall hits -system.cpu5.l1c.overall_hits::total 9892 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36506 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36506 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60501 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60501 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60501 # number of overall misses -system.cpu5.l1c.overall_misses::total 60501 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 721706442 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 721706442 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 584665158 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 584665158 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1306371600 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1306371600 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1306371600 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1306371600 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45234 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25159 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25159 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70393 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70393 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70393 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70393 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807048 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807048 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953734 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953734 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859475 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859475 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859475 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859475 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19769.529447 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 19769.529447 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24366.124526 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 24366.124526 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 21592.562106 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 21592.562106 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 21592.562106 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 21592.562106 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 870792 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66903 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.015739 # average number of cycles each access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 9839 # number of writebacks -system.cpu5.l1c.writebacks::total 9839 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36506 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36506 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60501 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60501 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60501 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60501 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9845 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9845 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5507 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15352 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15352 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 685200442 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 685200442 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 560672158 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 560672158 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1245872600 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1245872600 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1245872600 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1245872600 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 769357074 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 769357074 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 769357074 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 769357074 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807048 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807048 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953734 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953734 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859475 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859475 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18769.529447 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18769.529447 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23366.207877 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23366.207877 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78146.985678 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78146.985678 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50114.452449 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50114.452449 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 55102 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22254 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.922561 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13477 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22655 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.594880 # Average number of references to valid blocks. -system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.922561 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765474 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765474 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337953 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337953 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8677 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8677 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1226 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1226 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9903 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9903 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9903 # number of overall hits -system.cpu6.l1c.overall_hits::total 9903 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36565 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36565 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23825 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23825 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60390 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60390 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60390 # number of overall misses -system.cpu6.l1c.overall_misses::total 60390 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 723690383 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 723690383 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 577264297 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 577264297 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1300954680 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1300954680 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1300954680 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1300954680 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45242 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45242 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25051 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25051 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70293 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70293 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808209 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808209 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951060 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951060 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859118 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859118 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859118 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859118 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 19791.887953 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 19791.887953 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24229.351396 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 24229.351396 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 21542.551416 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 21542.551416 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 21542.551416 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 21542.551416 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 870051 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66789 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.026861 # average number of cycles each access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9787 # number of writebacks -system.cpu6.l1c.writebacks::total 9787 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36565 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36565 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23825 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23825 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60390 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60390 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5506 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15410 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15410 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 687127383 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 687127383 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 553439297 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 553439297 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1240566680 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1240566680 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1240566680 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1240566680 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 773835448 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 773835448 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 773835448 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 773835448 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808209 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808209 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951060 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951060 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859118 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859118 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 18791.942650 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 18791.942650 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23229.351396 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23229.351396 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78133.627625 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78133.627625 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 50216.446982 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 50216.446982 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 99606 # number of read accesses completed -system.cpu7.num_writes 54773 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 21949 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.189669 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13361 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22347 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.597888 # Average number of references to valid blocks. -system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.189669 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.764042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.764042 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 335877 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 335877 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8692 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8692 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9840 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9840 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9840 # number of overall hits -system.cpu7.l1c.overall_hits::total 9840 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36424 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36424 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23598 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23598 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60022 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60022 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60022 # number of overall misses -system.cpu7.l1c.overall_misses::total 60022 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 721113865 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 721113865 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 575330708 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 575330708 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1296444573 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1296444573 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1296444573 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1296444573 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45116 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45116 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24746 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24746 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69862 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69862 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69862 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69862 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807341 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953609 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953609 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859151 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859151 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859151 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859151 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19797.766994 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 19797.766994 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24380.485973 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 24380.485973 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 21599.489737 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 21599.489737 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 21599.489737 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 21599.489737 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 871786 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66469 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.115678 # average number of cycles each access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9508 # number of writebacks -system.cpu7.l1c.writebacks::total 9508 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36424 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36424 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23598 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23598 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60022 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60022 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60022 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60022 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9972 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9972 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5689 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15661 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15661 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 684690865 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 684690865 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 551733708 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 551733708 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1236424573 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1236424573 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1236424573 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1236424573 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 778989868 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 778989868 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 778989868 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 778989868 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807341 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953609 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953609 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859151 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859151 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18797.794449 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18797.794449 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23380.528350 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23380.528350 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78117.716406 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78117.716406 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49740.748867 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49740.748867 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 91944 # number of replacements -system.l2c.tags.tagsinuse 1018.135199 # Cycle average of tags in use -system.l2c.tags.total_refs 150035 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 92968 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.613835 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 8704000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 700.601873 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 40.249147 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 40.174988 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 39.327766 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 40.057426 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 39.781379 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 39.374996 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 39.797467 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 38.770159 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.684182 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.039306 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.039233 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.038406 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.039119 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.038849 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.038452 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.038865 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.037861 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994273 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 947 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2139200 # Number of tag accesses -system.l2c.tags.data_accesses 2139200 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 77024 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77024 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 414 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 433 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 398 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 417 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 426 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 450 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 421 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 435 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3394 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1862 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1934 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1949 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1865 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1828 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1873 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1869 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1854 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15034 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 9356 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 9333 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 9371 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 9291 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 9201 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 9292 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 9177 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 9226 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 74247 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 11218 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 11267 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 11320 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 11156 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 11029 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 11165 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 11046 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 11080 # number of demand (read+write) hits -system.l2c.demand_hits::total 89281 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 11218 # number of overall hits -system.l2c.overall_hits::cpu1 11267 # number of overall hits -system.l2c.overall_hits::cpu2 11320 # number of overall hits -system.l2c.overall_hits::cpu3 11156 # number of overall hits -system.l2c.overall_hits::cpu4 11029 # number of overall hits -system.l2c.overall_hits::cpu5 11165 # number of overall hits -system.l2c.overall_hits::cpu6 11046 # number of overall hits -system.l2c.overall_hits::cpu7 11080 # number of overall hits -system.l2c.overall_hits::total 89281 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1872 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1844 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1947 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1836 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1852 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1900 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1862 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1851 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14964 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4900 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4669 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4784 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4718 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4791 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4701 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4630 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4626 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37819 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 2463 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 2553 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 2469 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 2512 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 2543 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 2510 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 2544 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 2476 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 20070 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 7363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 7222 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 7253 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 7230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 7334 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 7211 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 7174 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 7102 # number of demand (read+write) misses -system.l2c.demand_misses::total 57889 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 7363 # number of overall misses -system.l2c.overall_misses::cpu1 7222 # number of overall misses -system.l2c.overall_misses::cpu2 7253 # number of overall misses -system.l2c.overall_misses::cpu3 7230 # number of overall misses -system.l2c.overall_misses::cpu4 7334 # number of overall misses -system.l2c.overall_misses::cpu5 7211 # number of overall misses -system.l2c.overall_misses::cpu6 7174 # number of overall misses -system.l2c.overall_misses::cpu7 7102 # number of overall misses -system.l2c.overall_misses::total 57889 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 31234104 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 31358138 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 32572788 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 30120451 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 30799263 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 31792446 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 30352791 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 30383968 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 248613949 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 215803873 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 203805632 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 208081416 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 204329473 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 209030536 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 205216215 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 201405883 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 201887028 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1649560056 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 169116609 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 174843463 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 170153096 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 173149203 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 175448063 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 172961782 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 175284714 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 170387602 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 1381344532 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 384920482 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 378649095 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 378234512 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 377478676 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 384478599 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 378177997 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 376690597 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 372274630 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 3030904588 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 384920482 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 378649095 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 378234512 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 377478676 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 384478599 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 378177997 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 376690597 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 372274630 # number of overall miss cycles -system.l2c.overall_miss_latency::total 3030904588 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77024 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77024 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2277 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2345 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2253 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2278 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2283 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2286 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18358 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6762 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6603 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6733 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6583 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6619 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6574 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6499 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6480 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 52853 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11819 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11886 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11840 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11803 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11744 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11802 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11721 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11702 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 94317 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18581 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18489 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18573 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18386 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18363 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18376 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18220 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18182 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 147170 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18581 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18489 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18573 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18386 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18363 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18376 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18220 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18182 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 147170 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.818898 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.809838 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.830277 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.814913 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.812994 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.808511 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.815594 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.809711 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.815121 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.724638 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.707103 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.710530 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.716695 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.723825 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.715090 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.712417 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.713889 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.715551 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.208393 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.214791 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.208530 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.212827 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.216536 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.212676 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.217046 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.211588 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.212793 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.396265 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.390611 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.390513 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.393234 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.399390 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.392414 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.393743 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.390606 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.393348 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.396265 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.390611 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.390513 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.393234 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.399390 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.392414 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.393743 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.390606 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.393348 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16684.884615 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 17005.497831 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16729.731895 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16405.474401 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 16630.271598 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 16732.866316 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16301.176692 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 16414.893571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16614.137196 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 44041.606735 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 43650.810024 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 43495.279264 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 43308.493641 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 43629.834273 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 43653.736439 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 43500.190713 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 43641.813230 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 43617.230916 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68662.853837 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68485.492754 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68915.794249 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68928.822850 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68992.553284 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68909.076494 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68901.224057 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68815.671244 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 68826.334429 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 52277.669700 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 52429.949460 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 52148.698745 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 52210.052006 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 52424.134033 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 52444.598114 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 52507.749791 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 52418.280766 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52357.176458 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 52277.669700 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 52429.949460 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 52148.698745 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 52210.052006 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 52424.134033 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 52444.598114 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 52507.749791 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 52418.280766 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52357.176458 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 46726 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 7668 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.093636 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 22726 # number of writebacks -system.l2c.writebacks::total 22726 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu0 3 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 5 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 5 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 25 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 20 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 17 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 18 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 21 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 18 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 25 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 26 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 21 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 166 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 33 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 30 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 30 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 27 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 34 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 37 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 35 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 41 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 267 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 53 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 47 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 48 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 48 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 52 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 61 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 62 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 433 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 53 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 47 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 48 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 48 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 52 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 61 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 62 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 433 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 4900 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 4900 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1840 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1945 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1833 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1847 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1898 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1861 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1846 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14939 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4880 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4652 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4766 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4697 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4773 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4676 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4604 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4605 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37653 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 2430 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 2523 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 2439 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 2485 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 2509 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 2473 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 2509 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 2435 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 19803 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 7310 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 7175 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 7205 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 7182 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 7282 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 7149 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 7113 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 7040 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 57456 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 7310 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 7175 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 7205 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 7182 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 7282 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 7149 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 7113 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 7040 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 57456 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9823 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9844 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9971 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78870 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5413 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5381 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5438 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5504 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5505 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43897 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15276 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15204 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15179 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15348 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15409 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15660 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122767 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 42798637 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 41900379 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 44540803 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 41317767 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 42296498 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43188221 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 42540949 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 41448863 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 340032117 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 166179988 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 156537743 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 159697945 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 156613177 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 160372266 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 157473921 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 154279145 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 154804178 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1265958363 # number of ReadExReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu0 143336439 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu1 148034574 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu2 144250348 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu3 146721083 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu4 148442317 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu5 146274036 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu6 148395292 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::cpu7 144143903 # number of ReadSharedReq MSHR miss cycles -system.l2c.ReadSharedReq_mshr_miss_latency::total 1169597992 # number of ReadSharedReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 309516427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 304572317 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 303948293 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 303334260 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 308814583 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 303747957 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 302674437 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 298948081 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 2435556355 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 309516427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 304572317 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 303948293 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 303334260 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 308814583 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 303747957 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 302674437 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 298948081 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 2435556355 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 558924481 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 559228006 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 558782791 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 556927201 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 552042138 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 557542912 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 561245949 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 564245669 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 4468939147 # number of ReadReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 558924481 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 559228006 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 558782791 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 556927201 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 552042138 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 557542912 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 561245949 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 564245669 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4468939147 # number of overall MSHR uncacheable cycles -system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses -system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.817585 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.808081 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.829424 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.813582 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810799 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.807660 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.815155 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.807524 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.813760 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.721680 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.704528 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.707857 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.713504 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721106 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.711287 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708417 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710648 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.712410 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.205601 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.212267 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.205997 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.210540 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.213641 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.209541 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.214060 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.208084 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209962 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.390406 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.390406 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 22899.217228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22771.945109 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22900.155784 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22541.062193 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 22900.107201 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 22754.594837 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 22859.188071 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22453.338570 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22761.370708 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 34053.276230 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33649.557825 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33507.751783 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33343.235469 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 33599.888121 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33677.057528 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33509.805604 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33616.542454 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 33621.713091 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58986.188889 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58674.028537 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59143.234112 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59042.689336 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59163.936628 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59148.417307 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59145.194101 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59196.674743 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59061.656921 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56668.810808 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56647.893639 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56717.701076 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 56696.243612 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 56672.019095 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 56637.841528 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 56668.613590 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56588.674055 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56662.091378 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36588.405407 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36453.165113 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36402.787687 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36630.307880 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36368.808090 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36326.746938 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36423.255825 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36031.013346 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 36401.794839 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 165129 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 149421 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. -system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78866 # Transaction distribution -system.membus.trans_dist::ReadResp 98603 # Transaction distribution -system.membus.trans_dist::WriteReq 43891 # Transaction distribution -system.membus.trans_dist::WriteResp 43890 # Transaction distribution -system.membus.trans_dist::WritebackDirty 22725 # Transaction distribution -system.membus.trans_dist::CleanEvict 5096 # Transaction distribution -system.membus.trans_dist::UpgradeReq 51962 # Transaction distribution -system.membus.trans_dist::ReadExReq 56321 # Transaction distribution -system.membus.trans_dist::ReadExResp 11265 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 19745 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 432364 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 432364 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3561537 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 3561537 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 55548 # Total snoops (count) -system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 277065 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 277065 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 277065 # Request fanout histogram -system.membus.reqLayer0.occupancy 406206026 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 77.9 # Layer utilization (%) -system.membus.respLayer0.occupancy 356644000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 68.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 666785 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283960 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 335937 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 86136 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 43107 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 43029 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78870 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370375 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43897 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43890 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 99750 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 167866 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 28850 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 28850 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162383 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162380 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 291522 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133688 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 134001 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133796 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133576 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133426 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133904 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133634 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133439 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1069464 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1829226 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1815722 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1817716 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1809443 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1812235 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1808884 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1798064 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1779371 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14470661 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 409171 # Total snoops (count) -system.toL2Bus.snoopTraffic 21085504 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 706797 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.196447 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.990756 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 181481 25.68% 25.68% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 294628 41.68% 67.36% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 158602 22.44% 89.80% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 56776 8.03% 97.83% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 13243 1.87% 99.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1898 0.27% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 160 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 9 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 706797 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 500161714 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102256739 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102545160 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 19.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102125332 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102285646 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102013056 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102427641 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102433420 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 101994041 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |