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authorAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:27:03 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-09-25 07:27:03 -0400
commit806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6 (patch)
treebf8944a02c194cb657534276190f2a17859b3675 /tests/quick/se/50.memtest/ref
parenta9a7002a3b3ad1e423d16ace826e80574d4ddc4f (diff)
downloadgem5-806e1fbf0f63d386d4ae80ff0d4ab77e6c37f9d6.tar.xz
stats: Update stats to reflect snoop-filter changes
Diffstat (limited to 'tests/quick/se/50.memtest/ref')
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt3452
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt3417
2 files changed, 3438 insertions, 3431 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index 96f88f923..61ea5a710 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,1817 +1,1819 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000889 # Number of seconds simulated
-sim_ticks 888991000 # Number of ticks simulated
-final_tick 888991000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000518 # Number of seconds simulated
+sim_ticks 518362500 # Number of ticks simulated
+final_tick 518362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 170326912 # Simulator tick rate (ticks/s)
-host_mem_usage 278304 # Number of bytes of host memory used
-host_seconds 5.22 # Real time elapsed on the host
+host_tick_rate 97254136 # Simulator tick rate (ticks/s)
+host_mem_usage 280792 # Number of bytes of host memory used
+host_seconds 5.33 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 77301 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 77008 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 78427 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 77571 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 81605 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77234 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 80454 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78765 # Number of bytes read from this memory
-system.physmem.bytes_read::total 628365 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 396032 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5354 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5486 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5463 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5457 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5585 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5519 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::total 439804 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10773 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10795 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10954 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11043 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11171 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10895 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10839 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10977 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87447 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6188 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5354 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5486 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5463 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5457 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5585 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5519 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49960 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 86953636 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 86624049 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 88220241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 87257351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 91795080 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 86878270 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 90500354 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 88600447 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 706829428 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 445484825 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 6022558 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 6171041 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 6145169 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 6138420 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 6146294 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 6282403 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 6208162 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 6123797 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 494722669 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 445484825 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 92976194 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 92795090 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 94365410 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 93395771 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 97941374 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 93160673 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 96708516 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 94724244 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1201552097 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 83556 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 80496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 82210 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 83458 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 79724 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 80437 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 82031 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 84431 # Number of bytes read from this memory
+system.physmem.bytes_read::total 656343 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 416960 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5428 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5478 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5268 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5521 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5505 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5477 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5442 # Number of bytes written to this memory
+system.physmem.bytes_written::total 460429 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10980 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10944 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11020 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10882 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10676 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11030 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10910 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87516 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6515 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5428 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5478 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5268 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5521 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5505 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5477 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5442 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49984 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 161192216 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 155289011 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 158595577 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 161003159 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 153799706 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 155175191 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 158250259 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 162880224 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1266185343 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 804379175 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 10320963 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 10471436 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 10567894 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 10162772 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 10650848 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 10619981 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 10565965 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 10498445 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 888237479 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 804379175 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 171513179 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 165760448 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 169163472 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 171165931 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 164450553 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 165795172 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 168816224 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 173378668 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2154422822 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 99131 # number of read accesses completed
-system.cpu0.num_writes 55164 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22535 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 395.025918 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13450 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.586338 # Average number of references to valid blocks.
+system.cpu0.num_reads 99891 # number of read accesses completed
+system.cpu0.num_writes 54838 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22327 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 391.597191 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13273 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22716 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.584302 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 395.025918 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.771535 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.771535 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 341 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338659 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338659 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8591 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8591 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1192 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1192 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9783 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9783 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9783 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9783 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36665 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36665 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23983 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23983 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60648 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60648 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60648 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60648 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 1205183022 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 1205183022 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1064148669 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1064148669 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 2269331691 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 2269331691 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 2269331691 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 2269331691 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45256 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45256 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 25175 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 25175 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70431 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70431 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70431 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70431 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.810169 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.810169 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952651 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.952651 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.861098 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.861098 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.861098 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.861098 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 32870.121969 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 32870.121969 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 44370.957303 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 44370.957303 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 37418.079590 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 37418.079590 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 37418.079590 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 37418.079590 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1129963 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 391.597191 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.764838 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.764838 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 337776 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 337776 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8714 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8714 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1148 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1148 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9862 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9862 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9862 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9862 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36629 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36629 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 23739 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 23739 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60368 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60368 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60368 # number of overall misses
+system.cpu0.l1c.overall_misses::total 60368 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 614304512 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 614304512 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 680799251 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 680799251 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 1295103763 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 1295103763 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1295103763 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1295103763 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 45343 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 45343 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 24887 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 24887 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 70230 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 70230 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 70230 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 70230 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807820 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.807820 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953871 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.953871 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.859576 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.859576 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.859576 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.859576 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16770.987797 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 16770.987797 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 28678.514301 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 28678.514301 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 21453.481364 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 21453.481364 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 21453.481364 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 21453.481364 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 764972 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 56549 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 61598 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 19.982016 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.418780 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9979 # number of writebacks
-system.cpu0.l1c.writebacks::total 9979 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36665 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36665 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23983 # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses::cpu0 60648 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses::cpu0 60648 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9718 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9718 # number of ReadReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5355 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5355 # number of WriteReq MSHR uncacheable
-system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15073 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15073 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1168518022 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1168518022 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1040166669 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1040166669 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2208684691 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency::total 2208684691 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2208684691 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 2208684691 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 789521900 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 789521900 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1493953369 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1493953369 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2283475269 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2283475269 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.810169 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.810169 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952651 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952651 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.861098 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861098 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.861098 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 31870.121969 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 31870.121969 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 43370.998999 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 43370.998999 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 36418.096079 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 81243.249640 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81243.249640 # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 278982.888702 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 278982.888702 # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 151494.411796 # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 151494.411796 # average overall mshr uncacheable latency
+system.cpu0.l1c.writebacks::writebacks 9814 # number of writebacks
+system.cpu0.l1c.writebacks::total 9814 # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36629 # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total 36629 # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23739 # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total 23739 # number of WriteReq MSHR misses
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+system.cpu0.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0 60368 # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses
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+system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9828 # number of ReadReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5350 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5350 # number of WriteReq MSHR uncacheable
+system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15178 # number of overall MSHR uncacheable misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15178 # number of overall MSHR uncacheable misses
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+system.cpu0.l1c.ReadReq_mshr_miss_latency::total 577676512 # number of ReadReq MSHR miss cycles
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+system.cpu0.l1c.WriteReq_mshr_miss_latency::total 657061251 # number of WriteReq MSHR miss cycles
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+system.cpu0.l1c.demand_mshr_miss_latency::total 1234737763 # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1234737763 # number of overall MSHR miss cycles
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+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 645410094 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1466796887 # number of overall MSHR uncacheable cycles
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+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807820 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953871 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953871 # mshr miss rate for WriteReq accesses
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+system.cpu0.l1c.demand_mshr_miss_rate::total 0.859576 # mshr miss rate for demand accesses
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+system.cpu0.l1c.overall_mshr_miss_rate::total 0.859576 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 15771.015097 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 15771.015097 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 27678.556426 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 27678.556426 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20453.514494 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20453.514494 # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 65670.542735 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65670.542735 # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 153530.241682 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total 153530.241682 # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 96639.668402 # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 96639.668402 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99860 # number of read accesses completed
-system.cpu1.num_writes 55211 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22541 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 395.711444 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13500 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22934 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.588646 # Average number of references to valid blocks.
+system.cpu1.num_reads 99259 # number of read accesses completed
+system.cpu1.num_writes 55194 # number of write accesses completed
+system.cpu1.l1c.tags.replacements 22288 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 392.187813 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13481 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.594322 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 395.711444 # Average occupied blocks per requestor
-system.cpu1.l1c.tags.occ_percent::cpu1 0.772874 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_percent::total 0.772874 # Average percentage of cache occupancy
-system.cpu1.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 55 # Occupied blocks per task id
-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id
-system.cpu1.l1c.tags.tag_accesses 338432 # Number of tag accesses
-system.cpu1.l1c.tags.data_accesses 338432 # Number of data accesses
-system.cpu1.l1c.ReadReq_hits::cpu1 8752 # number of ReadReq hits
-system.cpu1.l1c.ReadReq_hits::total 8752 # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits::cpu1 1139 # number of WriteReq hits
-system.cpu1.l1c.WriteReq_hits::total 1139 # number of WriteReq hits
-system.cpu1.l1c.demand_hits::cpu1 9891 # number of demand (read+write) hits
-system.cpu1.l1c.demand_hits::total 9891 # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits::cpu1 9891 # number of overall hits
-system.cpu1.l1c.overall_hits::total 9891 # number of overall hits
-system.cpu1.l1c.ReadReq_misses::cpu1 36537 # number of ReadReq misses
-system.cpu1.l1c.ReadReq_misses::total 36537 # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses::cpu1 23971 # number of WriteReq misses
-system.cpu1.l1c.WriteReq_misses::total 23971 # number of WriteReq misses
-system.cpu1.l1c.demand_misses::cpu1 60508 # number of demand (read+write) misses
-system.cpu1.l1c.demand_misses::total 60508 # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses::cpu1 60508 # number of overall misses
-system.cpu1.l1c.overall_misses::total 60508 # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency::cpu1 1195916774 # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_latency::total 1195916774 # number of ReadReq miss cycles
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-system.cpu1.l1c.WriteReq_miss_latency::total 1059745891 # number of WriteReq miss cycles
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-system.cpu1.l1c.demand_miss_latency::total 2255662665 # number of demand (read+write) miss cycles
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-system.cpu1.l1c.overall_miss_latency::total 2255662665 # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses::cpu1 45289 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_accesses::total 45289 # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::cpu1 25110 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses::total 25110 # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses::cpu1 70399 # number of demand (read+write) accesses
-system.cpu1.l1c.demand_accesses::total 70399 # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses::cpu1 70399 # number of overall (read+write) accesses
-system.cpu1.l1c.overall_accesses::total 70399 # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806752 # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_miss_rate::total 0.806752 # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954640 # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_miss_rate::total 0.954640 # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate::cpu1 0.859501 # miss rate for demand accesses
-system.cpu1.l1c.demand_miss_rate::total 0.859501 # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate::cpu1 0.859501 # miss rate for overall accesses
-system.cpu1.l1c.overall_miss_rate::total 0.859501 # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 32731.663081 # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_miss_latency::total 32731.663081 # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 44209.498602 # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency::total 44209.498602 # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency::cpu1 37278.750992 # average overall miss latency
-system.cpu1.l1c.demand_avg_miss_latency::total 37278.750992 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::cpu1 37278.750992 # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency::total 37278.750992 # average overall miss latency
-system.cpu1.l1c.blocked_cycles::no_mshrs 1120827 # number of cycles access was blocked
+system.cpu1.l1c.tags.occ_blocks::cpu1 392.187813 # Average occupied blocks per requestor
+system.cpu1.l1c.tags.occ_percent::cpu1 0.765992 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total 0.765992 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 17 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 337082 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 337082 # Number of data accesses
+system.cpu1.l1c.ReadReq_hits::cpu1 8742 # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total 8742 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1127 # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total 1127 # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1 9869 # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total 9869 # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1 9869 # number of overall hits
+system.cpu1.l1c.overall_hits::total 9869 # number of overall hits
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+system.cpu1.l1c.ReadReq_misses::total 36456 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 23797 # number of WriteReq misses
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+system.cpu1.l1c.demand_misses::total 60253 # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1 60253 # number of overall misses
+system.cpu1.l1c.overall_misses::total 60253 # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1 609449513 # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total 609449513 # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1 681132433 # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total 681132433 # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1 1290581946 # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total 1290581946 # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1 1290581946 # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total 1290581946 # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1 45198 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total 45198 # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1 24924 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total 24924 # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1 70122 # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total 70122 # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1 70122 # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total 70122 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806584 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.806584 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954783 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.954783 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.859260 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.859260 # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1 0.859260 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.859260 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16717.399413 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16717.399413 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 28622.617683 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 28622.617683 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 21419.380711 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 21419.380711 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 21419.380711 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 21419.380711 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 761379 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 56192 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 61322 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 19.946380 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.416082 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9897 # number of writebacks
-system.cpu1.l1c.writebacks::total 9897 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36537 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36537 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23971 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses::cpu1 60508 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.demand_mshr_misses::total 60508 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60508 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60508 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9744 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9744 # number of ReadReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5487 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5487 # number of WriteReq MSHR uncacheable
-system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15231 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15231 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1159382774 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1159382774 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1035775891 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1035775891 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2195158665 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency::total 2195158665 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2195158665 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 2195158665 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 792485431 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 792485431 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1532713252 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1532713252 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2325198683 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2325198683 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.806752 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806752 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954640 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954640 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859501 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859501 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859501 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 31731.745190 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 31731.745190 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 43209.540320 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 43209.540320 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 36278.817099 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 81330.606630 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81330.606630 # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 279335.383999 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279335.383999 # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 152662.246931 # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 152662.246931 # average overall mshr uncacheable latency
+system.cpu1.l1c.writebacks::writebacks 9824 # number of writebacks
+system.cpu1.l1c.writebacks::total 9824 # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36456 # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23797 # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1 60253 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total 60253 # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1 60253 # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total 60253 # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9840 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9840 # number of ReadReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5428 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5428 # number of WriteReq MSHR uncacheable
+system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15268 # number of overall MSHR uncacheable misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15268 # number of overall MSHR uncacheable misses
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+system.cpu1.l1c.ReadReq_mshr_miss_latency::total 572994513 # number of ReadReq MSHR miss cycles
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+system.cpu1.l1c.WriteReq_mshr_miss_latency::total 657337433 # number of WriteReq MSHR miss cycles
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+system.cpu1.l1c.demand_mshr_miss_latency::total 1230331946 # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1230331946 # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total 1230331946 # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 646152701 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 646152701 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 842788738 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1488941439 # number of overall MSHR uncacheable cycles
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+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.806584 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954783 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954783 # mshr miss rate for WriteReq accesses
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+system.cpu1.l1c.demand_mshr_miss_rate::total 0.859260 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859260 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.859260 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 15717.426843 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 15717.426843 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 27622.701727 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 27622.701727 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20419.430501 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20419.430501 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 65665.924898 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65665.924898 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 155266.900884 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155266.900884 # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 97520.398153 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 97520.398153 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu2.num_reads 99820 # number of read accesses completed
-system.cpu2.num_writes 54950 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22307 # number of replacements
-system.cpu2.l1c.tags.tagsinuse 395.344704 # Cycle average of tags in use
-system.cpu2.l1c.tags.total_refs 13648 # Total number of references to valid blocks.
-system.cpu2.l1c.tags.sampled_refs 22708 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks.
+system.cpu2.num_reads 99508 # number of read accesses completed
+system.cpu2.num_writes 54525 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22121 # number of replacements
+system.cpu2.l1c.tags.tagsinuse 392.684502 # Cycle average of tags in use
+system.cpu2.l1c.tags.total_refs 13597 # Total number of references to valid blocks.
+system.cpu2.l1c.tags.sampled_refs 22507 # Sample count of references to valid blocks.
+system.cpu2.l1c.tags.avg_refs 0.604123 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.tags.occ_blocks::cpu2 395.344704 # Average occupied blocks per requestor
-system.cpu2.l1c.tags.occ_percent::cpu2 0.772158 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_percent::total 0.772158 # Average percentage of cache occupancy
-system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::0 349 # Occupied blocks per task id
-system.cpu2.l1c.tags.age_task_id_blocks_1024::1 52 # Occupied blocks per task id
-system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id
-system.cpu2.l1c.tags.tag_accesses 339436 # Number of tag accesses
-system.cpu2.l1c.tags.data_accesses 339436 # Number of data accesses
-system.cpu2.l1c.ReadReq_hits::cpu2 8860 # number of ReadReq hits
-system.cpu2.l1c.ReadReq_hits::total 8860 # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits::cpu2 1133 # number of WriteReq hits
-system.cpu2.l1c.WriteReq_hits::total 1133 # number of WriteReq hits
-system.cpu2.l1c.demand_hits::cpu2 9993 # number of demand (read+write) hits
-system.cpu2.l1c.demand_hits::total 9993 # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits::cpu2 9993 # number of overall hits
-system.cpu2.l1c.overall_hits::total 9993 # number of overall hits
-system.cpu2.l1c.ReadReq_misses::cpu2 36664 # number of ReadReq misses
-system.cpu2.l1c.ReadReq_misses::total 36664 # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses::cpu2 23971 # number of WriteReq misses
-system.cpu2.l1c.WriteReq_misses::total 23971 # number of WriteReq misses
-system.cpu2.l1c.demand_misses::cpu2 60635 # number of demand (read+write) misses
-system.cpu2.l1c.demand_misses::total 60635 # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses::cpu2 60635 # number of overall misses
-system.cpu2.l1c.overall_misses::total 60635 # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency::cpu2 1194013761 # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_latency::total 1194013761 # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::cpu2 1064419870 # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency::total 1064419870 # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency::cpu2 2258433631 # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_latency::total 2258433631 # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency::cpu2 2258433631 # number of overall miss cycles
-system.cpu2.l1c.overall_miss_latency::total 2258433631 # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses::cpu2 45524 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_accesses::total 45524 # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::cpu2 25104 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses::total 25104 # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses::cpu2 70628 # number of demand (read+write) accesses
-system.cpu2.l1c.demand_accesses::total 70628 # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses::cpu2 70628 # number of overall (read+write) accesses
-system.cpu2.l1c.overall_accesses::total 70628 # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805377 # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_miss_rate::total 0.805377 # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954868 # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_miss_rate::total 0.954868 # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate::cpu2 0.858512 # miss rate for demand accesses
-system.cpu2.l1c.demand_miss_rate::total 0.858512 # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate::cpu2 0.858512 # miss rate for overall accesses
-system.cpu2.l1c.overall_miss_rate::total 0.858512 # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 32566.380128 # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_miss_latency::total 32566.380128 # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 44404.483334 # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency::total 44404.483334 # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency::cpu2 37246.369770 # average overall miss latency
-system.cpu2.l1c.demand_avg_miss_latency::total 37246.369770 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 37246.369770 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 37246.369770 # average overall miss latency
-system.cpu2.l1c.blocked_cycles::no_mshrs 1131174 # number of cycles access was blocked
+system.cpu2.l1c.tags.occ_blocks::cpu2 392.684502 # Average occupied blocks per requestor
+system.cpu2.l1c.tags.occ_percent::cpu2 0.766962 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_percent::total 0.766962 # Average percentage of cache occupancy
+system.cpu2.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
+system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu2.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
+system.cpu2.l1c.tags.tag_accesses 338301 # Number of tag accesses
+system.cpu2.l1c.tags.data_accesses 338301 # Number of data accesses
+system.cpu2.l1c.ReadReq_hits::cpu2 8815 # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total 8815 # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2 1121 # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total 1121 # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits
+system.cpu2.l1c.overall_hits::total 9936 # number of overall hits
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+system.cpu2.l1c.ReadReq_misses::total 36608 # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2 23851 # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total 23851 # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2 60459 # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total 60459 # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2 60459 # number of overall misses
+system.cpu2.l1c.overall_misses::total 60459 # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2 611593894 # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total 611593894 # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2 682333894 # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total 682333894 # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2 1293927788 # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total 1293927788 # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2 1293927788 # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total 1293927788 # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2 45423 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total 45423 # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2 24972 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2 70395 # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total 70395 # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2 70395 # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total 70395 # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805935 # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_miss_rate::total 0.805935 # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955110 # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::total 0.955110 # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2 0.858854 # miss rate for demand accesses
+system.cpu2.l1c.demand_miss_rate::total 0.858854 # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2 0.858854 # miss rate for overall accesses
+system.cpu2.l1c.overall_miss_rate::total 0.858854 # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16706.563975 # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_miss_latency::total 16706.563975 # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 28608.188084 # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::total 28608.188084 # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 21401.739824 # average overall miss latency
+system.cpu2.l1c.demand_avg_miss_latency::total 21401.739824 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 21401.739824 # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::total 21401.739824 # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs 766345 # number of cycles access was blocked
system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.blocked::no_mshrs 56579 # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs 61950 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu2.l1c.avg_blocked_cycles::no_mshrs 19.992824 # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.370379 # average number of cycles each access was blocked
system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks
-system.cpu2.l1c.writebacks::total 9745 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36664 # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_misses::total 36664 # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23971 # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses::total 23971 # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses::cpu2 60635 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.demand_mshr_misses::total 60635 # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses::cpu2 60635 # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_misses::total 60635 # number of overall MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9885 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9885 # number of ReadReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5464 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable
-system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15349 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15349 # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1157350761 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1157350761 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040448870 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040448870 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2197799631 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency::total 2197799631 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2197799631 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 2197799631 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 800475880 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 800475880 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1507844825 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1507844825 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2308320705 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2308320705 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805377 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805377 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954868 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954868 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858512 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858512 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858512 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 31566.407402 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 31566.407402 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 43404.483334 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 43404.483334 # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 36246.386262 # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 80978.844714 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80978.844714 # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 275959.887445 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 275959.887445 # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 150388.996352 # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 150388.996352 # average overall mshr uncacheable latency
+system.cpu2.l1c.writebacks::writebacks 9721 # number of writebacks
+system.cpu2.l1c.writebacks::total 9721 # number of writebacks
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+system.cpu2.l1c.ReadReq_mshr_misses::total 36608 # number of ReadReq MSHR misses
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+system.cpu2.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses
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+system.cpu2.l1c.demand_mshr_misses::total 60459 # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2 60459 # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total 60459 # number of overall MSHR misses
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+system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9890 # number of ReadReq MSHR uncacheable
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+system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5479 # number of WriteReq MSHR uncacheable
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+system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15369 # number of overall MSHR uncacheable misses
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+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 648669577 # number of ReadReq MSHR uncacheable cycles
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+system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1496985288 # number of overall MSHR uncacheable cycles
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+system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805935 # mshr miss rate for ReadReq accesses
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+system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955110 # mshr miss rate for WriteReq accesses
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+system.cpu2.l1c.demand_mshr_miss_rate::total 0.858854 # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858854 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total 0.858854 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 15706.618608 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 15706.618608 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 27608.230011 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 27608.230011 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20401.789444 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20401.789444 # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 65588.430435 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65588.430435 # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154830.390765 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154830.390765 # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 97402.907671 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97402.907671 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu3.num_reads 99181 # number of read accesses completed
-system.cpu3.num_writes 54913 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22385 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 394.599023 # Cycle average of tags in use
-system.cpu3.l1c.tags.total_refs 13320 # Total number of references to valid blocks.
-system.cpu3.l1c.tags.sampled_refs 22779 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.584749 # Average number of references to valid blocks.
+system.cpu3.num_reads 100000 # number of read accesses completed
+system.cpu3.num_writes 55096 # number of write accesses completed
+system.cpu3.l1c.tags.replacements 22478 # number of replacements
+system.cpu3.l1c.tags.tagsinuse 393.167313 # Cycle average of tags in use
+system.cpu3.l1c.tags.total_refs 13728 # Total number of references to valid blocks.
+system.cpu3.l1c.tags.sampled_refs 22864 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.600420 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.tags.occ_blocks::cpu3 394.599023 # Average occupied blocks per requestor
-system.cpu3.l1c.tags.occ_percent::cpu3 0.770701 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_percent::total 0.770701 # Average percentage of cache occupancy
-system.cpu3.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::0 338 # Occupied blocks per task id
-system.cpu3.l1c.tags.age_task_id_blocks_1024::1 56 # Occupied blocks per task id
-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id
-system.cpu3.l1c.tags.tag_accesses 337671 # Number of tag accesses
-system.cpu3.l1c.tags.data_accesses 337671 # Number of data accesses
-system.cpu3.l1c.ReadReq_hits::cpu3 8526 # number of ReadReq hits
-system.cpu3.l1c.ReadReq_hits::total 8526 # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits::cpu3 1172 # number of WriteReq hits
-system.cpu3.l1c.WriteReq_hits::total 1172 # number of WriteReq hits
-system.cpu3.l1c.demand_hits::cpu3 9698 # number of demand (read+write) hits
-system.cpu3.l1c.demand_hits::total 9698 # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits::cpu3 9698 # number of overall hits
-system.cpu3.l1c.overall_hits::total 9698 # number of overall hits
-system.cpu3.l1c.ReadReq_misses::cpu3 36662 # number of ReadReq misses
-system.cpu3.l1c.ReadReq_misses::total 36662 # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses::cpu3 23851 # number of WriteReq misses
-system.cpu3.l1c.WriteReq_misses::total 23851 # number of WriteReq misses
-system.cpu3.l1c.demand_misses::cpu3 60513 # number of demand (read+write) misses
-system.cpu3.l1c.demand_misses::total 60513 # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses::cpu3 60513 # number of overall misses
-system.cpu3.l1c.overall_misses::total 60513 # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency::cpu3 1194465114 # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_latency::total 1194465114 # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::cpu3 1056306776 # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency::total 1056306776 # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency::cpu3 2250771890 # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_latency::total 2250771890 # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency::cpu3 2250771890 # number of overall miss cycles
-system.cpu3.l1c.overall_miss_latency::total 2250771890 # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses::cpu3 45188 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_accesses::total 45188 # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::cpu3 25023 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses::total 25023 # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses::cpu3 70211 # number of demand (read+write) accesses
-system.cpu3.l1c.demand_accesses::total 70211 # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses::cpu3 70211 # number of overall (read+write) accesses
-system.cpu3.l1c.overall_accesses::total 70211 # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811322 # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_miss_rate::total 0.811322 # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953163 # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_miss_rate::total 0.953163 # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate::cpu3 0.861873 # miss rate for demand accesses
-system.cpu3.l1c.demand_miss_rate::total 0.861873 # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate::cpu3 0.861873 # miss rate for overall accesses
-system.cpu3.l1c.overall_miss_rate::total 0.861873 # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 32580.467896 # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_miss_latency::total 32580.467896 # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 44287.735357 # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency::total 44287.735357 # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency::cpu3 37194.848875 # average overall miss latency
-system.cpu3.l1c.demand_avg_miss_latency::total 37194.848875 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::cpu3 37194.848875 # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency::total 37194.848875 # average overall miss latency
-system.cpu3.l1c.blocked_cycles::no_mshrs 1130263 # number of cycles access was blocked
+system.cpu3.l1c.tags.occ_blocks::cpu3 393.167313 # Average occupied blocks per requestor
+system.cpu3.l1c.tags.occ_percent::cpu3 0.767905 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_percent::total 0.767905 # Average percentage of cache occupancy
+system.cpu3.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::0 380 # Occupied blocks per task id
+system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
+system.cpu3.l1c.tags.occ_task_id_percent::1024 0.753906 # Percentage of cache occupancy per task id
+system.cpu3.l1c.tags.tag_accesses 339546 # Number of tag accesses
+system.cpu3.l1c.tags.data_accesses 339546 # Number of data accesses
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+system.cpu3.l1c.ReadReq_hits::total 8879 # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3 1139 # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total 1139 # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3 10018 # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total 10018 # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3 10018 # number of overall hits
+system.cpu3.l1c.overall_hits::total 10018 # number of overall hits
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+system.cpu3.l1c.ReadReq_misses::total 36721 # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3 23927 # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total 23927 # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3 60648 # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total 60648 # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3 60648 # number of overall misses
+system.cpu3.l1c.overall_misses::total 60648 # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3 620124867 # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total 620124867 # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3 683533364 # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total 683533364 # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3 1303658231 # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total 1303658231 # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3 1303658231 # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total 1303658231 # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3 45600 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total 45600 # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3 25066 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total 25066 # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3 70666 # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total 70666 # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3 70666 # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total 70666 # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805285 # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_miss_rate::total 0.805285 # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954560 # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::total 0.954560 # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3 0.858235 # miss rate for demand accesses
+system.cpu3.l1c.demand_miss_rate::total 0.858235 # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3 0.858235 # miss rate for overall accesses
+system.cpu3.l1c.overall_miss_rate::total 0.858235 # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16887.472209 # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_miss_latency::total 16887.472209 # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 28567.449492 # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::total 28567.449492 # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 21495.485935 # average overall miss latency
+system.cpu3.l1c.demand_avg_miss_latency::total 21495.485935 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 21495.485935 # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::total 21495.485935 # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs 763846 # number of cycles access was blocked
system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.blocked::no_mshrs 56535 # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs 61681 # number of cycles access was blocked
system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu3.l1c.avg_blocked_cycles::no_mshrs 19.992270 # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.383813 # average number of cycles each access was blocked
system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
-system.cpu3.l1c.writebacks::writebacks 9719 # number of writebacks
-system.cpu3.l1c.writebacks::total 9719 # number of writebacks
-system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36662 # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_misses::total 36662 # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23851 # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses::total 23851 # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses::cpu3 60513 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.demand_mshr_misses::total 60513 # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses::cpu3 60513 # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_misses::total 60513 # number of overall MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9988 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9988 # number of ReadReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5458 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5458 # number of WriteReq MSHR uncacheable
-system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15446 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15446 # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1157803114 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1157803114 # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1032457776 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1032457776 # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2190260890 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency::total 2190260890 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2190260890 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 2190260890 # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 807637161 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 807637161 # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1532365329 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1532365329 # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2340002490 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2340002490 # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811322 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811322 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953163 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953163 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_miss_rate::total 0.861873 # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861873 # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_miss_rate::total 0.861873 # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 31580.467896 # average ReadReq mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 31580.467896 # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 43287.819211 # average WriteReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 43287.819211 # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::total 36194.881926 # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 80860.748999 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80860.748999 # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 280755.831623 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 280755.831623 # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 151495.694031 # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 151495.694031 # average overall mshr uncacheable latency
+system.cpu3.l1c.writebacks::writebacks 10011 # number of writebacks
+system.cpu3.l1c.writebacks::total 10011 # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36721 # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total 36721 # number of ReadReq MSHR misses
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+system.cpu3.l1c.WriteReq_mshr_misses::total 23927 # number of WriteReq MSHR misses
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+system.cpu3.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3 60648 # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9730 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9730 # number of ReadReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5269 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5269 # number of WriteReq MSHR uncacheable
+system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 14999 # number of overall MSHR uncacheable misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses::total 14999 # number of overall MSHR uncacheable misses
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+system.cpu3.l1c.WriteReq_mshr_miss_latency::total 659607364 # number of WriteReq MSHR miss cycles
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+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 639132205 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 639132205 # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 818596366 # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 818596366 # number of WriteReq MSHR uncacheable cycles
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+system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1457728571 # number of overall MSHR uncacheable cycles
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+system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805285 # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954560 # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954560 # mshr miss rate for WriteReq accesses
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+system.cpu3.l1c.demand_mshr_miss_rate::total 0.858235 # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858235 # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_miss_rate::total 0.858235 # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 15887.553906 # average ReadReq mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 15887.553906 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27567.491286 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27567.491286 # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20495.551890 # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20495.551890 # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 65686.763104 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65686.763104 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 155360.858987 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155360.858987 # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97188.383959 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97188.383959 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu4.num_reads 99531 # number of read accesses completed
-system.cpu4.num_writes 55217 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22414 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 393.784167 # Cycle average of tags in use
+system.cpu4.num_reads 98810 # number of read accesses completed
+system.cpu4.num_writes 55636 # number of write accesses completed
+system.cpu4.l1c.tags.replacements 22565 # number of replacements
+system.cpu4.l1c.tags.tagsinuse 393.118080 # Cycle average of tags in use
system.cpu4.l1c.tags.total_refs 13493 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22803 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.591720 # Average number of references to valid blocks.
+system.cpu4.l1c.tags.sampled_refs 22961 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.587649 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.tags.occ_blocks::cpu4 393.784167 # Average occupied blocks per requestor
-system.cpu4.l1c.tags.occ_percent::cpu4 0.769110 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_percent::total 0.769110 # Average percentage of cache occupancy
-system.cpu4.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::0 342 # Occupied blocks per task id
-system.cpu4.l1c.tags.age_task_id_blocks_1024::1 47 # Occupied blocks per task id
-system.cpu4.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
-system.cpu4.l1c.tags.tag_accesses 337660 # Number of tag accesses
-system.cpu4.l1c.tags.data_accesses 337660 # Number of data accesses
-system.cpu4.l1c.ReadReq_hits::cpu4 8661 # number of ReadReq hits
-system.cpu4.l1c.ReadReq_hits::total 8661 # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits::cpu4 1197 # number of WriteReq hits
-system.cpu4.l1c.WriteReq_hits::total 1197 # number of WriteReq hits
-system.cpu4.l1c.demand_hits::cpu4 9858 # number of demand (read+write) hits
-system.cpu4.l1c.demand_hits::total 9858 # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits::cpu4 9858 # number of overall hits
-system.cpu4.l1c.overall_hits::total 9858 # number of overall hits
-system.cpu4.l1c.ReadReq_misses::cpu4 36381 # number of ReadReq misses
-system.cpu4.l1c.ReadReq_misses::total 36381 # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses::cpu4 24008 # number of WriteReq misses
-system.cpu4.l1c.WriteReq_misses::total 24008 # number of WriteReq misses
-system.cpu4.l1c.demand_misses::cpu4 60389 # number of demand (read+write) misses
-system.cpu4.l1c.demand_misses::total 60389 # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses::cpu4 60389 # number of overall misses
-system.cpu4.l1c.overall_misses::total 60389 # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency::cpu4 1185615268 # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_latency::total 1185615268 # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::cpu4 1062060825 # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency::total 1062060825 # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency::cpu4 2247676093 # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_latency::total 2247676093 # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency::cpu4 2247676093 # number of overall miss cycles
-system.cpu4.l1c.overall_miss_latency::total 2247676093 # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses::cpu4 45042 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_accesses::total 45042 # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::cpu4 25205 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses::total 25205 # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses::cpu4 70247 # number of demand (read+write) accesses
-system.cpu4.l1c.demand_accesses::total 70247 # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses::cpu4 70247 # number of overall (read+write) accesses
-system.cpu4.l1c.overall_accesses::total 70247 # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807713 # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_miss_rate::total 0.807713 # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952509 # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_miss_rate::total 0.952509 # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate::cpu4 0.859667 # miss rate for demand accesses
-system.cpu4.l1c.demand_miss_rate::total 0.859667 # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate::cpu4 0.859667 # miss rate for overall accesses
-system.cpu4.l1c.overall_miss_rate::total 0.859667 # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 32588.858690 # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_miss_latency::total 32588.858690 # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 44237.788446 # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency::total 44237.788446 # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency::cpu4 37219.958817 # average overall miss latency
-system.cpu4.l1c.demand_avg_miss_latency::total 37219.958817 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::cpu4 37219.958817 # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency::total 37219.958817 # average overall miss latency
-system.cpu4.l1c.blocked_cycles::no_mshrs 1133314 # number of cycles access was blocked
+system.cpu4.l1c.tags.occ_blocks::cpu4 393.118080 # Average occupied blocks per requestor
+system.cpu4.l1c.tags.occ_percent::cpu4 0.767809 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_percent::total 0.767809 # Average percentage of cache occupancy
+system.cpu4.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id
+system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id
+system.cpu4.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
+system.cpu4.l1c.tags.tag_accesses 338158 # Number of tag accesses
+system.cpu4.l1c.tags.data_accesses 338158 # Number of data accesses
+system.cpu4.l1c.ReadReq_hits::cpu4 8694 # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total 8694 # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4 1170 # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total 1170 # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4 9864 # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total 9864 # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4 9864 # number of overall hits
+system.cpu4.l1c.overall_hits::total 9864 # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4 36355 # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total 36355 # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4 24124 # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total 24124 # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4 60479 # number of demand (read+write) misses
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+system.cpu4.l1c.overall_misses::total 60479 # number of overall misses
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+system.cpu4.l1c.ReadReq_miss_latency::total 612629802 # number of ReadReq miss cycles
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+system.cpu4.l1c.WriteReq_miss_latency::total 686589261 # number of WriteReq miss cycles
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+system.cpu4.l1c.demand_miss_latency::total 1299219063 # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4 1299219063 # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total 1299219063 # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4 25294 # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total 25294 # number of WriteReq accesses(hits+misses)
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+system.cpu4.l1c.demand_accesses::total 70343 # number of demand (read+write) accesses
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+system.cpu4.l1c.overall_accesses::total 70343 # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807010 # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_miss_rate::total 0.807010 # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953744 # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::total 0.953744 # miss rate for WriteReq accesses
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+system.cpu4.l1c.overall_miss_rate::total 0.859773 # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16851.321744 # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_miss_latency::total 16851.321744 # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 28460.838211 # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::total 28460.838211 # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 21482.151871 # average overall miss latency
+system.cpu4.l1c.demand_avg_miss_latency::total 21482.151871 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 21482.151871 # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::total 21482.151871 # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs 755009 # number of cycles access was blocked
system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.blocked::no_mshrs 56676 # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs 61034 # number of cycles access was blocked
system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu4.l1c.avg_blocked_cycles::no_mshrs 19.996365 # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.370302 # average number of cycles each access was blocked
system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
-system.cpu4.l1c.writebacks::writebacks 9784 # number of writebacks
-system.cpu4.l1c.writebacks::total 9784 # number of writebacks
-system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36381 # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_misses::total 36381 # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24008 # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses::total 24008 # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses::cpu4 60389 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.demand_mshr_misses::total 60389 # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses::cpu4 60389 # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_misses::total 60389 # number of overall MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 10053 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.ReadReq_mshr_uncacheable::total 10053 # number of ReadReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5464 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5464 # number of WriteReq MSHR uncacheable
-system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15517 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15517 # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1149238268 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1149238268 # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1038052825 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1038052825 # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2187291093 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency::total 2187291093 # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2187291093 # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency::total 2187291093 # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 813079130 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 813079130 # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1517158795 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1517158795 # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2330237925 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2330237925 # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807713 # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952509 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952509 # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859667 # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859667 # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859667 # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 31588.968637 # average ReadReq mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 31588.968637 # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 43237.788446 # average WriteReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 43237.788446 # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency::total 36220.025054 # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 80879.252959 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 80879.252959 # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 277664.493960 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 277664.493960 # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 150173.224528 # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 150173.224528 # average overall mshr uncacheable latency
+system.cpu4.l1c.writebacks::writebacks 10039 # number of writebacks
+system.cpu4.l1c.writebacks::total 10039 # number of writebacks
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+system.cpu4.l1c.overall_mshr_misses::total 60479 # number of overall MSHR misses
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+system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9580 # number of ReadReq MSHR uncacheable
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+system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5521 # number of WriteReq MSHR uncacheable
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+system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15101 # number of overall MSHR uncacheable misses
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+system.cpu4.l1c.WriteReq_mshr_miss_latency::total 662467261 # number of WriteReq MSHR miss cycles
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+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 630980804 # number of ReadReq MSHR uncacheable cycles
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+system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1498157002 # number of overall MSHR uncacheable cycles
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+system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953744 # mshr miss rate for WriteReq accesses
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+system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859773 # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_miss_rate::total 0.859773 # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 15851.321744 # average ReadReq mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 15851.321744 # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 27460.921116 # average WriteReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 27460.921116 # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20482.184940 # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20482.184940 # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 65864.384551 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65864.384551 # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 157068.682847 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157068.682847 # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 99209.125356 # average overall mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 99209.125356 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu5.num_reads 100000 # number of read accesses completed
-system.cpu5.num_writes 55296 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22532 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 395.145821 # Cycle average of tags in use
-system.cpu5.l1c.tags.total_refs 13497 # Total number of references to valid blocks.
-system.cpu5.l1c.tags.sampled_refs 22906 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.589234 # Average number of references to valid blocks.
+system.cpu5.num_reads 98552 # number of read accesses completed
+system.cpu5.num_writes 54926 # number of write accesses completed
+system.cpu5.l1c.tags.replacements 22151 # number of replacements
+system.cpu5.l1c.tags.tagsinuse 392.121942 # Cycle average of tags in use
+system.cpu5.l1c.tags.total_refs 13428 # Total number of references to valid blocks.
+system.cpu5.l1c.tags.sampled_refs 22535 # Sample count of references to valid blocks.
+system.cpu5.l1c.tags.avg_refs 0.595873 # Average number of references to valid blocks.
system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.tags.occ_blocks::cpu5 395.145821 # Average occupied blocks per requestor
-system.cpu5.l1c.tags.occ_percent::cpu5 0.771769 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_percent::total 0.771769 # Average percentage of cache occupancy
-system.cpu5.l1c.tags.occ_task_id_blocks::1024 374 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::0 335 # Occupied blocks per task id
-system.cpu5.l1c.tags.age_task_id_blocks_1024::1 39 # Occupied blocks per task id
-system.cpu5.l1c.tags.occ_task_id_percent::1024 0.730469 # Percentage of cache occupancy per task id
-system.cpu5.l1c.tags.tag_accesses 337979 # Number of tag accesses
-system.cpu5.l1c.tags.data_accesses 337979 # Number of data accesses
-system.cpu5.l1c.ReadReq_hits::cpu5 8739 # number of ReadReq hits
-system.cpu5.l1c.ReadReq_hits::total 8739 # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits::cpu5 1202 # number of WriteReq hits
-system.cpu5.l1c.WriteReq_hits::total 1202 # number of WriteReq hits
-system.cpu5.l1c.demand_hits::cpu5 9941 # number of demand (read+write) hits
-system.cpu5.l1c.demand_hits::total 9941 # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits::cpu5 9941 # number of overall hits
-system.cpu5.l1c.overall_hits::total 9941 # number of overall hits
-system.cpu5.l1c.ReadReq_misses::cpu5 36450 # number of ReadReq misses
-system.cpu5.l1c.ReadReq_misses::total 36450 # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses::cpu5 23918 # number of WriteReq misses
-system.cpu5.l1c.WriteReq_misses::total 23918 # number of WriteReq misses
-system.cpu5.l1c.demand_misses::cpu5 60368 # number of demand (read+write) misses
-system.cpu5.l1c.demand_misses::total 60368 # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses::cpu5 60368 # number of overall misses
-system.cpu5.l1c.overall_misses::total 60368 # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency::cpu5 1193062548 # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_latency::total 1193062548 # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::cpu5 1058341769 # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency::total 1058341769 # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency::cpu5 2251404317 # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_latency::total 2251404317 # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency::cpu5 2251404317 # number of overall miss cycles
-system.cpu5.l1c.overall_miss_latency::total 2251404317 # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses::cpu5 45189 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_accesses::total 45189 # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::cpu5 25120 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses::total 25120 # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses::cpu5 70309 # number of demand (read+write) accesses
-system.cpu5.l1c.demand_accesses::total 70309 # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses::cpu5 70309 # number of overall (read+write) accesses
-system.cpu5.l1c.overall_accesses::total 70309 # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806612 # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_miss_rate::total 0.806612 # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952150 # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_miss_rate::total 0.952150 # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate::cpu5 0.858610 # miss rate for demand accesses
-system.cpu5.l1c.demand_miss_rate::total 0.858610 # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate::cpu5 0.858610 # miss rate for overall accesses
-system.cpu5.l1c.overall_miss_rate::total 0.858610 # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 32731.482798 # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_miss_latency::total 32731.482798 # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 44248.756961 # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency::total 44248.756961 # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency::cpu5 37294.664673 # average overall miss latency
-system.cpu5.l1c.demand_avg_miss_latency::total 37294.664673 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::cpu5 37294.664673 # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency::total 37294.664673 # average overall miss latency
-system.cpu5.l1c.blocked_cycles::no_mshrs 1121436 # number of cycles access was blocked
+system.cpu5.l1c.tags.occ_blocks::cpu5 392.121942 # Average occupied blocks per requestor
+system.cpu5.l1c.tags.occ_percent::cpu5 0.765863 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_percent::total 0.765863 # Average percentage of cache occupancy
+system.cpu5.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id
+system.cpu5.l1c.tags.age_task_id_blocks_1024::1 13 # Occupied blocks per task id
+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id
+system.cpu5.l1c.tags.tag_accesses 336693 # Number of tag accesses
+system.cpu5.l1c.tags.data_accesses 336693 # Number of data accesses
+system.cpu5.l1c.ReadReq_hits::cpu5 8529 # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total 8529 # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5 1201 # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total 1201 # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5 9730 # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total 9730 # number of demand (read+write) hits
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+system.cpu5.l1c.overall_hits::total 9730 # number of overall hits
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+system.cpu5.l1c.overall_misses::total 60307 # number of overall misses
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+system.cpu5.l1c.ReadReq_miss_latency::total 609487073 # number of ReadReq miss cycles
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+system.cpu5.l1c.WriteReq_miss_latency::total 677626855 # number of WriteReq miss cycles
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+system.cpu5.l1c.demand_miss_latency::total 1287113928 # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5 1287113928 # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total 1287113928 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 44892 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total 44892 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5 25145 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total 25145 # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5 70037 # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total 70037 # number of demand (read+write) accesses
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+system.cpu5.l1c.overall_accesses::total 70037 # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.810011 # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_miss_rate::total 0.810011 # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952237 # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::total 0.952237 # miss rate for WriteReq accesses
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+system.cpu5.l1c.demand_miss_rate::total 0.861073 # miss rate for demand accesses
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+system.cpu5.l1c.overall_miss_rate::total 0.861073 # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16761.187828 # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_miss_latency::total 16761.187828 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 28300.486761 # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::total 28300.486761 # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 21342.695342 # average overall miss latency
+system.cpu5.l1c.demand_avg_miss_latency::total 21342.695342 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 21342.695342 # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::total 21342.695342 # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs 765746 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.blocked::no_mshrs 56172 # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs 61759 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu5.l1c.avg_blocked_cycles::no_mshrs 19.964324 # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.398938 # average number of cycles each access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks::writebacks 9981 # number of writebacks
-system.cpu5.l1c.writebacks::total 9981 # number of writebacks
-system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36450 # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_misses::total 36450 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23918 # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses::total 23918 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses::cpu5 60368 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses::cpu5 60368 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9842 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9842 # number of ReadReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5587 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5587 # number of WriteReq MSHR uncacheable
-system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15429 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15429 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1156614548 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1156614548 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1034424769 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1034424769 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2191039317 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency::total 2191039317 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2191039317 # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency::total 2191039317 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 798681353 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 798681353 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1559836698 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1559836698 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2358518051 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2358518051 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806612 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806612 # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952150 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952150 # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_miss_rate::total 0.858610 # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858610 # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_miss_rate::total 0.858610 # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 31731.537668 # average ReadReq mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 31731.537668 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 43248.798771 # average WriteReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 43248.798771 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36294.714369 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 81150.310201 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81150.310201 # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 279190.388044 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279190.388044 # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 152862.664528 # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 152862.664528 # average overall mshr uncacheable latency
+system.cpu5.l1c.writebacks::writebacks 9825 # number of writebacks
+system.cpu5.l1c.writebacks::total 9825 # number of writebacks
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+system.cpu5.l1c.WriteReq_mshr_misses::total 23944 # number of WriteReq MSHR misses
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+system.cpu5.l1c.demand_mshr_misses::total 60307 # number of demand (read+write) MSHR misses
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+system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9974 # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9974 # number of ReadReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5505 # number of WriteReq MSHR uncacheable
+system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5505 # number of WriteReq MSHR uncacheable
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+system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15479 # number of overall MSHR uncacheable misses
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+system.cpu5.l1c.ReadReq_mshr_miss_latency::total 573124073 # number of ReadReq MSHR miss cycles
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+system.cpu5.l1c.WriteReq_mshr_miss_latency::total 653684855 # number of WriteReq MSHR miss cycles
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+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 653819057 # number of ReadReq MSHR uncacheable cycles
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+system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1510172238 # number of overall MSHR uncacheable cycles
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+system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.810011 # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952237 # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952237 # mshr miss rate for WriteReq accesses
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+system.cpu5.l1c.demand_mshr_miss_rate::total 0.861073 # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.861073 # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_miss_rate::total 0.861073 # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 15761.187828 # average ReadReq mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 15761.187828 # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 27300.570289 # average WriteReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27300.570289 # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20342.728506 # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20342.728506 # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 65552.341789 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65552.341789 # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 155559.160945 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total 155559.160945 # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 97562.648621 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 97562.648621 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu6.num_reads 99879 # number of read accesses completed
-system.cpu6.num_writes 55426 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22371 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 395.326557 # Cycle average of tags in use
-system.cpu6.l1c.tags.total_refs 13543 # Total number of references to valid blocks.
-system.cpu6.l1c.tags.sampled_refs 22792 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.594200 # Average number of references to valid blocks.
+system.cpu6.num_reads 98949 # number of read accesses completed
+system.cpu6.num_writes 55414 # number of write accesses completed
+system.cpu6.l1c.tags.replacements 22111 # number of replacements
+system.cpu6.l1c.tags.tagsinuse 389.931977 # Cycle average of tags in use
+system.cpu6.l1c.tags.total_refs 13393 # Total number of references to valid blocks.
+system.cpu6.l1c.tags.sampled_refs 22506 # Sample count of references to valid blocks.
+system.cpu6.l1c.tags.avg_refs 0.595086 # Average number of references to valid blocks.
system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.tags.occ_blocks::cpu6 395.326557 # Average occupied blocks per requestor
-system.cpu6.l1c.tags.occ_percent::cpu6 0.772122 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_percent::total 0.772122 # Average percentage of cache occupancy
-system.cpu6.l1c.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::0 355 # Occupied blocks per task id
-system.cpu6.l1c.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
-system.cpu6.l1c.tags.occ_task_id_percent::1024 0.822266 # Percentage of cache occupancy per task id
-system.cpu6.l1c.tags.tag_accesses 339285 # Number of tag accesses
-system.cpu6.l1c.tags.data_accesses 339285 # Number of data accesses
-system.cpu6.l1c.ReadReq_hits::cpu6 8751 # number of ReadReq hits
-system.cpu6.l1c.ReadReq_hits::total 8751 # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits::cpu6 1170 # number of WriteReq hits
-system.cpu6.l1c.WriteReq_hits::total 1170 # number of WriteReq hits
-system.cpu6.l1c.demand_hits::cpu6 9921 # number of demand (read+write) hits
-system.cpu6.l1c.demand_hits::total 9921 # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits::cpu6 9921 # number of overall hits
-system.cpu6.l1c.overall_hits::total 9921 # number of overall hits
-system.cpu6.l1c.ReadReq_misses::cpu6 36633 # number of ReadReq misses
-system.cpu6.l1c.ReadReq_misses::total 36633 # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses::cpu6 24021 # number of WriteReq misses
-system.cpu6.l1c.WriteReq_misses::total 24021 # number of WriteReq misses
-system.cpu6.l1c.demand_misses::cpu6 60654 # number of demand (read+write) misses
-system.cpu6.l1c.demand_misses::total 60654 # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses::cpu6 60654 # number of overall misses
-system.cpu6.l1c.overall_misses::total 60654 # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency::cpu6 1194061806 # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_latency::total 1194061806 # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::cpu6 1068136243 # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency::total 1068136243 # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency::cpu6 2262198049 # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_latency::total 2262198049 # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency::cpu6 2262198049 # number of overall miss cycles
-system.cpu6.l1c.overall_miss_latency::total 2262198049 # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses::cpu6 45384 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_accesses::total 45384 # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::cpu6 25191 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses::total 25191 # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses::cpu6 70575 # number of demand (read+write) accesses
-system.cpu6.l1c.demand_accesses::total 70575 # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses::cpu6 70575 # number of overall (read+write) accesses
-system.cpu6.l1c.overall_accesses::total 70575 # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807179 # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_miss_rate::total 0.807179 # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953555 # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_miss_rate::total 0.953555 # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate::cpu6 0.859426 # miss rate for demand accesses
-system.cpu6.l1c.demand_miss_rate::total 0.859426 # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate::cpu6 0.859426 # miss rate for overall accesses
-system.cpu6.l1c.overall_miss_rate::total 0.859426 # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 32595.250348 # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_miss_latency::total 32595.250348 # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 44466.768369 # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency::total 44466.768369 # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency::cpu6 37296.766067 # average overall miss latency
-system.cpu6.l1c.demand_avg_miss_latency::total 37296.766067 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::cpu6 37296.766067 # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency::total 37296.766067 # average overall miss latency
-system.cpu6.l1c.blocked_cycles::no_mshrs 1121671 # number of cycles access was blocked
+system.cpu6.l1c.tags.occ_blocks::cpu6 389.931977 # Average occupied blocks per requestor
+system.cpu6.l1c.tags.occ_percent::cpu6 0.761586 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_percent::total 0.761586 # Average percentage of cache occupancy
+system.cpu6.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id
+system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id
+system.cpu6.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id
+system.cpu6.l1c.tags.tag_accesses 337246 # Number of tag accesses
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+system.cpu6.l1c.WriteReq_miss_latency::total 684112648 # number of WriteReq miss cycles
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+system.cpu6.l1c.demand_miss_latency::total 1291646289 # number of demand (read+write) miss cycles
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+system.cpu6.l1c.overall_miss_latency::total 1291646289 # number of overall miss cycles
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+system.cpu6.l1c.WriteReq_accesses::total 25179 # number of WriteReq accesses(hits+misses)
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+system.cpu6.l1c.demand_accesses::total 70136 # number of demand (read+write) accesses
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+system.cpu6.l1c.overall_accesses::total 70136 # number of overall (read+write) accesses
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+system.cpu6.l1c.ReadReq_miss_rate::total 0.808461 # miss rate for ReadReq accesses
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+system.cpu6.l1c.overall_miss_rate::total 0.860913 # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16715.282039 # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_miss_latency::total 16715.282039 # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 28463.184855 # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::total 28463.184855 # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 21391.601481 # average overall miss latency
+system.cpu6.l1c.demand_avg_miss_latency::total 21391.601481 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 21391.601481 # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::total 21391.601481 # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs 766078 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.blocked::no_mshrs 56232 # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs 61691 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu6.l1c.avg_blocked_cycles::no_mshrs 19.947201 # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.417986 # average number of cycles each access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
-system.cpu6.l1c.writebacks::writebacks 9808 # number of writebacks
-system.cpu6.l1c.writebacks::total 9808 # number of writebacks
-system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36633 # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_misses::total 36633 # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24021 # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses::total 24021 # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses::cpu6 60654 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.demand_mshr_misses::total 60654 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses::cpu6 60654 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_misses::total 60654 # number of overall MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9734 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9734 # number of ReadReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5519 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5519 # number of WriteReq MSHR uncacheable
-system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15253 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15253 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1157429806 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1157429806 # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1044117243 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1044117243 # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2201547049 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency::total 2201547049 # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2201547049 # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency::total 2201547049 # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 789209928 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 789209928 # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1545234814 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1545234814 # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2334444742 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2334444742 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807179 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807179 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953555 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953555 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_miss_rate::total 0.859426 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859426 # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_miss_rate::total 0.859426 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 31595.277646 # average ReadReq mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 31595.277646 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 43466.851630 # average WriteReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 43466.851630 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency::total 36296.815527 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 81077.658517 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 81077.658517 # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 279984.564957 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 279984.564957 # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 153048.235888 # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 153048.235888 # average overall mshr uncacheable latency
+system.cpu6.l1c.writebacks::writebacks 9648 # number of writebacks
+system.cpu6.l1c.writebacks::total 9648 # number of writebacks
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+system.cpu6.l1c.ReadReq_mshr_misses::total 36346 # number of ReadReq MSHR misses
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+system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15382 # number of overall MSHR uncacheable misses
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+system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1494418764 # number of overall MSHR uncacheable cycles
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+system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860913 # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_miss_rate::total 0.860913 # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 15715.309553 # average ReadReq mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 15715.309553 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 27463.268067 # average WriteReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 27463.268067 # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20391.651165 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20391.651165 # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 65702.450323 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65702.450323 # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 154016.373859 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total 154016.373859 # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 97153.735795 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 97153.735795 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu7.num_reads 99237 # number of read accesses completed
-system.cpu7.num_writes 54706 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22568 # number of replacements
-system.cpu7.l1c.tags.tagsinuse 396.130968 # Cycle average of tags in use
-system.cpu7.l1c.tags.total_refs 13545 # Total number of references to valid blocks.
-system.cpu7.l1c.tags.sampled_refs 22967 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.589759 # Average number of references to valid blocks.
+system.cpu7.num_reads 99388 # number of read accesses completed
+system.cpu7.num_writes 55153 # number of write accesses completed
+system.cpu7.l1c.tags.replacements 22255 # number of replacements
+system.cpu7.l1c.tags.tagsinuse 390.416736 # Cycle average of tags in use
+system.cpu7.l1c.tags.total_refs 13442 # Total number of references to valid blocks.
+system.cpu7.l1c.tags.sampled_refs 22659 # Sample count of references to valid blocks.
+system.cpu7.l1c.tags.avg_refs 0.593230 # Average number of references to valid blocks.
system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.tags.occ_blocks::cpu7 396.130968 # Average occupied blocks per requestor
-system.cpu7.l1c.tags.occ_percent::cpu7 0.773693 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_percent::total 0.773693 # Average percentage of cache occupancy
-system.cpu7.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::0 336 # Occupied blocks per task id
-system.cpu7.l1c.tags.age_task_id_blocks_1024::1 63 # Occupied blocks per task id
-system.cpu7.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
-system.cpu7.l1c.tags.tag_accesses 337631 # Number of tag accesses
-system.cpu7.l1c.tags.data_accesses 337631 # Number of data accesses
-system.cpu7.l1c.ReadReq_hits::cpu7 8763 # number of ReadReq hits
-system.cpu7.l1c.ReadReq_hits::total 8763 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits::cpu7 1110 # number of WriteReq hits
-system.cpu7.l1c.WriteReq_hits::total 1110 # number of WriteReq hits
-system.cpu7.l1c.demand_hits::cpu7 9873 # number of demand (read+write) hits
-system.cpu7.l1c.demand_hits::total 9873 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits::cpu7 9873 # number of overall hits
-system.cpu7.l1c.overall_hits::total 9873 # number of overall hits
-system.cpu7.l1c.ReadReq_misses::cpu7 36422 # number of ReadReq misses
-system.cpu7.l1c.ReadReq_misses::total 36422 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses::cpu7 23951 # number of WriteReq misses
-system.cpu7.l1c.WriteReq_misses::total 23951 # number of WriteReq misses
-system.cpu7.l1c.demand_misses::cpu7 60373 # number of demand (read+write) misses
-system.cpu7.l1c.demand_misses::total 60373 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses::cpu7 60373 # number of overall misses
-system.cpu7.l1c.overall_misses::total 60373 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency::cpu7 1187262746 # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_latency::total 1187262746 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::cpu7 1066556279 # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency::total 1066556279 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency::cpu7 2253819025 # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_latency::total 2253819025 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency::cpu7 2253819025 # number of overall miss cycles
-system.cpu7.l1c.overall_miss_latency::total 2253819025 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses::cpu7 45185 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_accesses::total 45185 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::cpu7 25061 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses::total 25061 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses::cpu7 70246 # number of demand (read+write) accesses
-system.cpu7.l1c.demand_accesses::total 70246 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses::cpu7 70246 # number of overall (read+write) accesses
-system.cpu7.l1c.overall_accesses::total 70246 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806064 # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_miss_rate::total 0.806064 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955708 # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_miss_rate::total 0.955708 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate::cpu7 0.859451 # miss rate for demand accesses
-system.cpu7.l1c.demand_miss_rate::total 0.859451 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate::cpu7 0.859451 # miss rate for overall accesses
-system.cpu7.l1c.overall_miss_rate::total 0.859451 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 32597.406677 # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_miss_latency::total 32597.406677 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 44530.761931 # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency::total 44530.761931 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency::cpu7 37331.572474 # average overall miss latency
-system.cpu7.l1c.demand_avg_miss_latency::total 37331.572474 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::cpu7 37331.572474 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency::total 37331.572474 # average overall miss latency
-system.cpu7.l1c.blocked_cycles::no_mshrs 1126172 # number of cycles access was blocked
+system.cpu7.l1c.tags.occ_blocks::cpu7 390.416736 # Average occupied blocks per requestor
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu7.l1c.writebacks::total 9950 # number of writebacks
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-system.cpu7.l1c.WriteReq_mshr_misses::total 23951 # number of WriteReq MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::total 60373 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9901 # number of ReadReq MSHR uncacheable
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-system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15345 # number of overall MSHR uncacheable misses
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-system.cpu7.l1c.demand_mshr_miss_latency::total 2193450025 # number of demand (read+write) MSHR miss cycles
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-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2305520252 # number of overall MSHR uncacheable cycles
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-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 31597.434133 # average ReadReq mshr miss latency
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-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 43530.887186 # average WriteReq mshr miss latency
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-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 36331.638729 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 36331.638729 # average overall mshr miss latency
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-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 150245.699055 # average overall mshr uncacheable latency
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 97110.168741 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 13238 # number of replacements
-system.l2c.tags.tagsinuse 783.486176 # Cycle average of tags in use
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-system.l2c.tags.sampled_refs 14027 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 11.673843 # Average number of references to valid blocks.
+system.l2c.tags.replacements 14059 # number of replacements
+system.l2c.tags.tagsinuse 786.833616 # Cycle average of tags in use
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+system.l2c.tags.avg_refs 11.006336 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0 6.423018 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.356158 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.459637 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.505664 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.498026 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.297131 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.613319 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.425290 # Average occupied blocks per requestor
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-system.l2c.tags.occ_task_id_percent::1024 0.770508 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 2093442 # Number of tag accesses
-system.l2c.tags.data_accesses 2093442 # Number of data accesses
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-system.l2c.Writeback_hits::total 77141 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0 278 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1 288 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 234 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 250 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 237 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 267 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 288 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 265 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2107 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu5 1866 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1759 # number of ReadExReq hits
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-system.l2c.ReadSharedReq_hits::cpu0 10764 # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu3 10852 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu4 10715 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu5 10815 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu6 10778 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu7 10709 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 86309 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0 12509 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu2 12615 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3 12626 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu4 12498 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12681 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12537 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12439 # number of demand (read+write) hits
-system.l2c.demand_hits::total 100545 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0 12509 # number of overall hits
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system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
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-system.l2c.demand_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 45331.650518 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1 45382.595389 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2 45361.723111 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3 45368.818508 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu4 45470.031250 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu5 45437.866056 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu6 45471.103480 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu7 45414.426095 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 45405.077704 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44221.156633 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44202.582307 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44181.167156 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44181.716159 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44166.713618 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44121.720992 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44175.413191 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44200.616200 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44181.280211 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45634.662682 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45295.386256 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45128.316493 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45396.736119 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45350.016654 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45451.832050 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45361.385758 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45227.220610 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45355.293452 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44723.307213 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44596.221339 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44518.341457 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44611.004856 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44583.390024 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44603.257924 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44604.534190 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44564.828283 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 44600.323116 # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.888939 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883173 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.888430 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.880371 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.875592 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.879303 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.882018 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.871274 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.881128 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.732007 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.730787 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.720839 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.723676 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.716926 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.718440 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.723198 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.724731 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.723817 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.064364 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060598 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.063139 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062229 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.061786 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.063510 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064653 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.065930 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063277 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.299237 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.304319 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.300185 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.296150 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.293975 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.298531 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.296626 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.305067 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.299170 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.299237 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 45450.420840 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 45460.256170 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 45384.873953 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 45421.041148 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 45371.430678 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 45448.514258 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 45378.159125 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 45405.790778 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 45414.855258 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 46229.221491 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 46032.345591 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 46000.198523 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 46190.566761 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 46073.560902 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 46021.316411 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 46020.856869 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45971.206079 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 46067.626088 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52281.249322 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 53772.607504 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 53044.776871 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52136.500000 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 52982.239774 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 53144.868673 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52161.531507 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52767.411688 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52778.681055 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 47049.195153 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 47036.276249 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 46969.999063 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 47008.230321 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 46986.732662 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 47003.643652 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 46847.159631 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 46938.682196 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 46979.808316 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44927.218559 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 45002.272561 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 45006.490495 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 45019.805550 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 45047.220146 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44972.916082 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 45028.391963 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44938.341544 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44992.694522 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 46260.365421 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46369.461496 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 46373.118474 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 46391.945900 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 46368.309183 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46372.920254 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46332.743655 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46551.714627 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 46377.702156 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 45397.131308 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45488.328465 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 45493.631832 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 45501.765502 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 45530.216807 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45470.817947 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45492.856836 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45516.504083 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 45486.343181 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 253876 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 250804 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 127987 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 121935 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 78861 # Transaction distribution
-system.membus.trans_dist::ReadResp 84355 # Transaction distribution
-system.membus.trans_dist::WriteReq 43772 # Transaction distribution
-system.membus.trans_dist::WriteResp 43770 # Transaction distribution
-system.membus.trans_dist::Writeback 6188 # Transaction distribution
-system.membus.trans_dist::CleanEvict 1234 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 61487 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 50676 # Transaction distribution
-system.membus.trans_dist::ReadExReq 49401 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3090 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 5496 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 428330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 428330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1068167 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1068167 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57121 # Total snoops (count)
-system.membus.snoop_fanout::samples 253876 # Request fanout histogram
+system.membus.trans_dist::ReadReq 78487 # Transaction distribution
+system.membus.trans_dist::ReadResp 84311 # Transaction distribution
+system.membus.trans_dist::WriteReq 43469 # Transaction distribution
+system.membus.trans_dist::WriteResp 43465 # Transaction distribution
+system.membus.trans_dist::Writeback 6515 # Transaction distribution
+system.membus.trans_dist::CleanEvict 1324 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 61199 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 50308 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49356 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3201 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 5828 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427463 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 427463 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1116768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1116768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57043 # Total snoops (count)
+system.membus.snoop_fanout::samples 255514 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 253876 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 255514 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 253876 # Request fanout histogram
-system.membus.reqLayer0.occupancy 481009549 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 54.1 # Layer utilization (%)
-system.membus.respLayer0.occupancy 317350499 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 35.7 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 783985 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 389410 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 391503 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.snoop_filter.tot_snoops 13238 # Total number of snoops made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_snoops 4575 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_snoops 8663 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 78862 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371257 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43772 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43769 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 83329 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 20018 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29498 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29497 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162169 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162167 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 292402 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122283 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122529 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122863 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122791 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122820 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122959 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122669 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122503 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 981417 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781215 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778494 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776817 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1770963 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1771805 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1794946 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778453 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1777585 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14230278 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoop_fanout::total 255514 # Request fanout histogram
+system.membus.reqLayer0.occupancy 292277246 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 56.4 # Layer utilization (%)
+system.membus.respLayer0.occupancy 310111858 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 59.8 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 663155 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 282754 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 334620 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 12643 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 6068 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 6575 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 78490 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370569 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43469 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43464 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 83812 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 20730 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29471 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29469 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161822 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161815 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 292094 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122083 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122289 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122819 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122567 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122495 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122827 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122357 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122446 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 979883 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1778056 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1772835 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1781127 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1803862 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1797691 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1778038 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1761236 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1781905 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14254750 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 335326 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 797223 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.523507 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.320965 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 800967 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.187618 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.006332 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 184121 23.10% 23.10% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 277567 34.82% 57.91% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 172653 21.66% 79.57% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 93165 11.69% 91.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 44731 5.61% 96.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 17914 2.25% 99.11% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 5826 0.73% 99.84% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 1211 0.15% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 35 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 216572 27.04% 27.04% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 322054 40.21% 67.25% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 178446 22.28% 89.53% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 65924 8.23% 97.76% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 15526 1.94% 99.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2251 0.28% 99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 192 0.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 2 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 797223 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 882991225 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 99.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100686388 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100571959 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 100903359 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 11.4 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100786975 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100705827 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100586898 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 100884775 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 11.3 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100465612 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 11.3 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 800967 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 495267856 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 95.5 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101287347 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 101004376 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101361922 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 101351771 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101153250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 101246693 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101297808 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 101337760 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 19.5 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index d439f20bd..76540bca6 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,1806 +1,1811 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000517 # Number of seconds simulated
-sim_ticks 516502000 # Number of ticks simulated
-final_tick 516502000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000518 # Number of seconds simulated
+sim_ticks 517786000 # Number of ticks simulated
+final_tick 517786000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 87177041 # Simulator tick rate (ticks/s)
-host_mem_usage 277532 # Number of bytes of host memory used
-host_seconds 5.92 # Real time elapsed on the host
+host_tick_rate 99723528 # Simulator tick rate (ticks/s)
+host_mem_usage 280036 # Number of bytes of host memory used
+host_seconds 5.19 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 77818 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 80958 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 77616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 81564 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 77320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77018 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 77760 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78103 # Number of bytes read from this memory
-system.physmem.bytes_read::total 628157 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 397760 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5585 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5520 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5375 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5416 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5446 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5475 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5563 # Number of bytes written to this memory
-system.physmem.bytes_written::total 441591 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10975 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10902 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10962 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11130 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10918 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10679 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10980 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10819 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87365 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6215 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5585 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5520 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5375 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5416 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5446 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5475 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5563 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50046 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 150663502 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 156742859 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 150272409 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 157916136 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 149699324 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 149114621 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 150551208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 151215291 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1216175349 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 770103504 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 10813124 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 10687277 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 10406542 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 10553686 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 10485923 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 10544006 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 10600153 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 10770529 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 854964744 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 770103504 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 161476625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 167430136 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 160678952 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 168469822 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 160185246 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 159658627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 161151360 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 161985820 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2071140092 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 82733 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82298 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 83808 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 81707 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 79210 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 80419 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 83957 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 82578 # Number of bytes read from this memory
+system.physmem.bytes_read::total 656710 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 415488 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5449 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5329 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5533 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5454 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5382 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5483 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5404 # Number of bytes written to this memory
+system.physmem.bytes_written::total 459030 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10913 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10856 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10917 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10895 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10981 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10993 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11003 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10884 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87442 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6492 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5449 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5329 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5533 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5454 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5382 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5483 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5404 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50034 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 159782227 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 158942111 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 161858374 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 157800713 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 152978257 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 155313199 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 162146138 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 159482875 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1268303894 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 802431893 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 10523653 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 10291897 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 10685882 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 10533309 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 10394256 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 10589317 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 10637599 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 10436744 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 886524549 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 802431893 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 170305879 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 169234008 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 172544256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 168334022 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 163372513 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 165902516 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 172783737 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 169919619 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2154828443 # Total bandwidth to/from this memory (bytes/s)
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+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 154751.605321 # average WriteReq mshr uncacheable latency
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+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 97319.786967 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.num_reads 99343 # number of read accesses completed
-system.cpu1.num_writes 54840 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22376 # number of replacements
-system.cpu1.l1c.tags.tagsinuse 393.102021 # Cycle average of tags in use
-system.cpu1.l1c.tags.total_refs 13319 # Total number of references to valid blocks.
-system.cpu1.l1c.tags.sampled_refs 22762 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.585142 # Average number of references to valid blocks.
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+system.cpu1.l1c.tags.replacements 22526 # number of replacements
+system.cpu1.l1c.tags.tagsinuse 393.510444 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13408 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22912 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.585196 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.tags.occ_blocks::cpu1 393.102021 # Average occupied blocks per requestor
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-system.cpu1.l1c.tags.occ_percent::total 0.767777 # Average percentage of cache occupancy
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system.cpu1.l1c.tags.occ_task_id_blocks::1024 386 # Occupied blocks per task id
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-system.cpu1.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
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+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 98171.195708 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 54722 # number of write accesses completed
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system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20219.093910 # average overall mshr miss latency
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+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 154209.329539 # average WriteReq mshr uncacheable latency
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+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 97547.526970 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 54933 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22211 # number of replacements
-system.cpu3.l1c.tags.tagsinuse 391.604025 # Cycle average of tags in use
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-system.cpu3.l1c.tags.sampled_refs 22604 # Sample count of references to valid blocks.
-system.cpu3.l1c.tags.avg_refs 0.591090 # Average number of references to valid blocks.
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+system.cpu3.l1c.tags.sampled_refs 22840 # Sample count of references to valid blocks.
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 27323.663996 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 27323.663996 # average WriteReq mshr miss latency
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+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65391.953127 # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 156269.610082 # average WriteReq mshr uncacheable latency
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 97950.577762 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 97950.577762 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu4.num_reads 100000 # number of read accesses completed
-system.cpu4.num_writes 55127 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22421 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 392.948683 # Cycle average of tags in use
-system.cpu4.l1c.tags.total_refs 13931 # Total number of references to valid blocks.
-system.cpu4.l1c.tags.sampled_refs 22818 # Sample count of references to valid blocks.
-system.cpu4.l1c.tags.avg_refs 0.610527 # Average number of references to valid blocks.
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+system.cpu4.l1c.tags.sampled_refs 22499 # Sample count of references to valid blocks.
+system.cpu4.l1c.tags.avg_refs 0.602160 # Average number of references to valid blocks.
system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 97747.307395 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 55138 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22475 # number of replacements
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-system.cpu5.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks.
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 27168.552073 # average WriteReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20182.962436 # average overall mshr miss latency
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+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65537.830149 # average ReadReq mshr uncacheable latency
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 98132.815728 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 55267 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22184 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 392.209079 # Cycle average of tags in use
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-system.cpu6.l1c.tags.sampled_refs 22573 # Sample count of references to valid blocks.
-system.cpu6.l1c.tags.avg_refs 0.601382 # Average number of references to valid blocks.
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu6.l1c.overall_avg_miss_latency::cpu6 21045.924371 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 55134 # number of write accesses completed
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 568436547 # number of ReadReq MSHR miss cycles
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+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 658518760 # number of WriteReq MSHR miss cycles
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+system.cpu7.l1c.demand_mshr_miss_latency::total 1226955307 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1226955307 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 1226955307 # number of overall MSHR miss cycles
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+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 638135236 # number of ReadReq MSHR uncacheable cycles
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+system.cpu7.l1c.overall_mshr_miss_rate::total 0.861604 # mshr miss rate for overall accesses
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+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 15549.321525 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 27438.281667 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 27438.281667 # average WriteReq mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20261.163978 # average overall mshr miss latency
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+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 65469.912383 # average ReadReq mshr uncacheable latency
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+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 157579.709660 # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 98323.278133 # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 98323.278133 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 13635 # number of replacements
-system.l2c.tags.tagsinuse 787.795797 # Cycle average of tags in use
-system.l2c.tags.total_refs 163881 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 14421 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 11.364052 # Average number of references to valid blocks.
+system.l2c.tags.replacements 14184 # number of replacements
+system.l2c.tags.tagsinuse 788.596931 # Cycle average of tags in use
+system.l2c.tags.total_refs 165124 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14990 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 11.015610 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 732.377461 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.931961 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.975655 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.944636 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 7.398268 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.695089 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.188919 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.047720 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 7.236089 # Average occupied blocks per requestor
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-system.l2c.tags.occ_percent::cpu6 0.006883 # Average percentage of cache occupancy
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-system.l2c.Writeback_hits::total 77190 # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu1 278 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2 290 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 299 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 286 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 279 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 254 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 287 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu3 1725 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu4 1792 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1760 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1718 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1773 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 14082 # number of ReadExReq hits
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-system.l2c.ReadSharedReq_hits::cpu5 10917 # number of ReadSharedReq hits
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-system.l2c.ReadSharedReq_hits::cpu7 10921 # number of ReadSharedReq hits
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-system.l2c.demand_hits::cpu4 12597 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu5 12677 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu6 12453 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu7 12694 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu4 12597 # number of overall hits
-system.l2c.overall_hits::cpu5 12677 # number of overall hits
-system.l2c.overall_hits::cpu6 12453 # number of overall hits
-system.l2c.overall_hits::cpu7 12694 # number of overall hits
-system.l2c.overall_hits::total 100838 # number of overall hits
-system.l2c.UpgradeReq_misses::cpu0 2065 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1 2004 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2 2022 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3 2044 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 2054 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 2029 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 2097 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 2076 # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::cpu6 4720 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4602 # number of ReadExReq misses
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-system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses
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-system.l2c.ReadSharedReq_misses::cpu6 677 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu7 715 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 5548 # number of ReadSharedReq misses
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-system.l2c.demand_misses::cpu7 5317 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu4 5257 # number of overall misses
-system.l2c.overall_misses::cpu5 5212 # number of overall misses
-system.l2c.overall_misses::cpu6 5397 # number of overall misses
-system.l2c.overall_misses::cpu7 5317 # number of overall misses
-system.l2c.overall_misses::total 42396 # number of overall misses
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-system.l2c.UpgradeReq_miss_latency::total 489028425 # number of UpgradeReq miss cycles
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-system.l2c.ReadExReq_miss_latency::cpu7 252050416 # number of ReadExReq miss cycles
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-system.l2c.demand_miss_latency::cpu4 292444355 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu5 289897340 # number of demand (read+write) miss cycles
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-system.l2c.demand_miss_latency::cpu7 296548322 # number of demand (read+write) miss cycles
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-system.l2c.Writeback_accesses::total 77190 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu1 2282 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu3 2343 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu4 2340 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu5 2308 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu7 2363 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 18606 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.ReadExReq_accesses::total 50930 # number of ReadExReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu3 11654 # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.ReadSharedReq_accesses::cpu7 11636 # number of ReadSharedReq accesses(hits+misses)
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-system.l2c.overall_accesses::cpu7 18011 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 143234 # number of overall (read+write) accesses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.878177 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.874567 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.872386 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.877778 # miss rate for UpgradeReq accesses
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 253706432 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 248671425 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 2001789449 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0 683260307 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1 678998159 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2 687935300 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3 685025157 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4 687382947 # number of overall MSHR uncacheable cycles
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+system.l2c.overall_mshr_uncacheable_latency::cpu7 682192804 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 5488835125 # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.894668 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.878177 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.874567 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.872386 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.877350 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878683 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.891961 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878544 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.880791 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.724213 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.722363 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.716051 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.727803 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717937 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720772 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.732370 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721412 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.722875 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059844 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.059777 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.061384 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062039 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057598 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.055671 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058885 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.060846 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.059510 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.295384 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0 0.298281 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1 0.292103 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2 0.295463 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3 0.296638 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu4 0.293492 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu5 0.290681 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu6 0.301793 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu7 0.294653 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.295384 # mshr miss rate for overall accesses
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44153.813953 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44143.207086 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44154.787339 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44162.909002 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44126.387725 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44141.018245 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44148.535527 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44114.156069 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44143.052905 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44845.994381 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 44851.673483 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44703.501857 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44814.176381 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44823.200262 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 44734.180202 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44683.120679 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44790.805827 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 44780.567362 # average ReadExReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 52327.836018 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51742.355811 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52404.123404 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 51409.993084 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51785.054463 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52146.608696 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52778.891369 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52485.744350 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52131.499181 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1 45767.365682 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2 45731.320523 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3 45707.540090 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu4 45701.403626 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu6 45693.025617 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu7 45817.377614 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0 45808.348023 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::total 45734.942754 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44434.574642 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44385.022778 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44375.893074 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44381.776768 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44449.804846 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44425.871923 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44369.744556 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44358.191365 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44397.556218 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45566.328559 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 45522.452536 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45629.941953 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45783.280264 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45522.884970 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 45504.485678 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 45710.947032 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 45702.306849 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45617.859258 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44842.397445 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 44795.121555 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44817.054977 # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44830.158377 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 44815.584024 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 44846.723027 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 44846.457947 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 44833.789624 # average overall mshr uncacheable latency
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.883059 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.894691 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.889223 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882581 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.894333 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.883731 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.886295 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.880591 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.886807 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.729228 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.725950 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.730991 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721161 # mshr miss rate for ReadExReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::total 0.724646 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.062894 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.062264 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.065186 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.064352 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.059903 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.062139 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.064884 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.062484 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.063010 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.297431 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.298419 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.297083 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.296479 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.302012 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.291981 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.295687 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.298923 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.298846 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.297431 # mshr miss rate for overall accesses
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 44922.610775 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 44954.132418 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 44938.666828 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 44950.770468 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 44833.006193 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 44949.669121 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 44860.720976 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 44964.533301 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44921.573351 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 45682.110945 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45612.025856 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 45452.439268 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 45550.203282 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 45535.266950 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 45553.240165 # average ReadExReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 51925.344173 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 51508.154058 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 52511.027523 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 52582.218206 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 51819.692308 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 52725.951456 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 52163.453457 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 52454.054720 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 52214.900357 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency
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+system.l2c.demand_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu0 46532.832164 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 46410.551416 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 46536.438003 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 46430.035609 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 46385.025228 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 46510.774436 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 46443.804864 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 46465.663171 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 46464.486730 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 44420.329070 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 44451.631081 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 44461.256660 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 44495.280217 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 44517.718428 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 44486.777070 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 44473.425597 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 44477.416538 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 44473.085348 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 45722.229950 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 46311.681366 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 45905.193385 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 45877.502108 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 45846.631364 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 46046.768557 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 46061.443718 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 46016.177831 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 45972.703971 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 44886.368874 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 45110.162038 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 44983.672268 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 44990.487127 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 44985.794961 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 45043.134123 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 45043.138605 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 45026.255957 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 45008.529040 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 78781 # Transaction distribution
-system.membus.trans_dist::ReadResp 84254 # Transaction distribution
-system.membus.trans_dist::WriteReq 43831 # Transaction distribution
-system.membus.trans_dist::WriteResp 43828 # Transaction distribution
-system.membus.trans_dist::Writeback 6215 # Transaction distribution
-system.membus.trans_dist::CleanEvict 1216 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 61094 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 50117 # Transaction distribution
-system.membus.trans_dist::ReadExReq 49522 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3101 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 5483 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427442 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 427442 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1069738 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1069738 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57394 # Total snoops (count)
-system.membus.snoop_fanout::samples 254906 # Request fanout histogram
+system.membus.trans_dist::ReadReq 78406 # Transaction distribution
+system.membus.trans_dist::ReadResp 84270 # Transaction distribution
+system.membus.trans_dist::WriteReq 43542 # Transaction distribution
+system.membus.trans_dist::WriteResp 43539 # Transaction distribution
+system.membus.trans_dist::Writeback 6492 # Transaction distribution
+system.membus.trans_dist::CleanEvict 1226 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 61182 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 50391 # Transaction distribution
+system.membus.trans_dist::ReadExReq 49587 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3167 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 5869 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 427671 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 427671 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1115735 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1115735 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57207 # Total snoops (count)
+system.membus.snoop_fanout::samples 255615 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 254906 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 255615 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 254906 # Request fanout histogram
-system.membus.reqLayer0.occupancy 291050214 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 56.4 # Layer utilization (%)
-system.membus.respLayer0.occupancy 309370624 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 59.9 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 78782 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371328 # Transaction distribution
+system.membus.snoop_fanout::total 255615 # Request fanout histogram
+system.membus.reqLayer0.occupancy 293172648 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 56.6 # Layer utilization (%)
+system.membus.respLayer0.occupancy 310812284 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 60.0 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 663719 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 283046 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 335146 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 12757 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 5920 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 6837 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.trans_dist::ReadReq 78408 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 370885 # Transaction distribution
system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43832 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43827 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 83405 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 20435 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29579 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29579 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161223 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161218 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 292561 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122545 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122537 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122267 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122810 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122614 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122506 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122579 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122756 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 980614 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1769994 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1778957 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1770860 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783783 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1787183 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1781792 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1778656 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1778193 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14229418 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 335158 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 800908 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 7.017024 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.129362 # Request fanout histogram
+system.toL2Bus.trans_dist::WriteReq 43543 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43537 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 83883 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 20723 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29304 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29302 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162111 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162107 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 292494 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 122467 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 122636 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 122530 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 122578 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 122681 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 122805 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 122788 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 981273 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1801396 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1791690 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1789116 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1791289 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1784816 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780428 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1784184 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1802670 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14325589 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 335027 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 801595 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.188537 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.005333 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 787273 98.30% 98.30% # Request fanout histogram
-system.toL2Bus.snoop_fanout::8 13635 1.70% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 216155 26.97% 26.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 322197 40.19% 67.16% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 179904 22.44% 89.60% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 65286 8.14% 97.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 15605 1.95% 99.69% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 2259 0.28% 99.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 176 0.02% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 13 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 8 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 800908 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 495395322 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 101110391 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 801595 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 495500281 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 95.7 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101557213 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101309873 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 101587169 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101121441 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101199500 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 101172758 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 19.5 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 101251086 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 101216377 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.occupancy 101367103 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 101535375 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101020631 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 101469413 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101588792 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101318353 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 101399821 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%)
---------- End Simulation Statistics ----------