SE/FS: Make both SE and FS tests available all the time.

--HG--
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simerr
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
rename : tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal => tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/status => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/config.ini => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simerr => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/simout => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/stats.txt => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
rename : tests/long/10.linux-boot/ref/arm/linux/realview-o3/system.terminal => tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
rename : tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal => tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
rename : tests/long/10.linux-boot/test.py => tests/long/fs/10.linux-boot/test.py
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.hterm
rename : tests/long/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm => tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/system.t1000.pterm
rename : tests/long/80.solaris-boot/test.py => tests/long/fs/80.solaris-boot/test.py
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simerr => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
rename : tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/simout => tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/simout => tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/arm/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/simout => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/simout => tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/simout => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/config.ini => tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simerr => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simerr
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/simout => tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
rename : tests/long/00.gzip/ref/x86/linux/simple-timing/stats.txt => tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/00.gzip/test.py => tests/long/se/00.gzip/test.py
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/o3-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/simout => tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm => tests/long/se/10.mcf/ref/arm/linux/simple-timing/chair.cook.ppm
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/arm/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/simout => tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/simout => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/o3-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/simout => tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/simout => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/config.ini => tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/mcf.out => tests/long/se/10.mcf/ref/x86/linux/simple-timing/mcf.out
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simerr => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simerr
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/simout => tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
rename : tests/long/10.mcf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/10.mcf/test.py => tests/long/se/10.mcf/test.py
rename : tests/long/20.parser/ref/alpha/tru64/NOTE => tests/long/se/20.parser/ref/alpha/tru64/NOTE
rename : tests/long/20.parser/ref/arm/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simerr => tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/o3-timing/simout => tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
rename : tests/long/20.parser/ref/arm/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/simout => tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/arm/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simerr => tests/long/se/20.parser/ref/arm/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/arm/linux/simple-timing/simout => tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
rename : tests/long/20.parser/ref/arm/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/o3-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simerr => tests/long/se/20.parser/ref/x86/linux/o3-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/o3-timing/simout => tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
rename : tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simerr => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/simout => tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
rename : tests/long/20.parser/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/20.parser/ref/x86/linux/simple-timing/config.ini => tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
rename : tests/long/20.parser/ref/x86/linux/simple-timing/simerr => tests/long/se/20.parser/ref/x86/linux/simple-timing/simerr
rename : tests/long/20.parser/ref/x86/linux/simple-timing/simout => tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
rename : tests/long/20.parser/ref/x86/linux/simple-timing/stats.txt => tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/20.parser/test.py => tests/long/se/20.parser/test.py
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simerr => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/simout => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
rename : tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/30.eon/ref/arm/linux/o3-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
rename : tests/long/30.eon/ref/arm/linux/o3-timing/simerr => tests/long/se/30.eon/ref/arm/linux/o3-timing/simerr
rename : tests/long/30.eon/ref/arm/linux/o3-timing/simout => tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
rename : tests/long/30.eon/ref/arm/linux/o3-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simerr => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simerr
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/simout => tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
rename : tests/long/30.eon/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/30.eon/ref/arm/linux/simple-timing/config.ini => tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
rename : tests/long/30.eon/ref/arm/linux/simple-timing/simerr => tests/long/se/30.eon/ref/arm/linux/simple-timing/simerr
rename : tests/long/30.eon/ref/arm/linux/simple-timing/simout => tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
rename : tests/long/30.eon/ref/arm/linux/simple-timing/stats.txt => tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/30.eon/test.py => tests/long/se/30.eon/test.py
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simerr => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
rename : tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
rename : tests/long/40.perlbmk/ref/arm/linux/o3-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
rename : tests/long/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/config.ini => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simerr => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simerr
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/simout => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
rename : tests/long/40.perlbmk/ref/arm/linux/simple-timing/stats.txt => tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/40.perlbmk/test.py => tests/long/se/40.perlbmk/test.py
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simerr => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.msg => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.msg
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simerr
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/simout => tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/o3-timing/smred.out
rename : tests/long/50.vortex/ref/arm/linux/o3-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/simout => tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/arm/linux/simple-timing/smred.out
rename : tests/long/50.vortex/ref/arm/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.msg
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/50.vortex/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/config.ini => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simerr => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simerr
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/simout => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.msg => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.msg
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/smred.out => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/50.vortex/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/50.vortex/test.py => tests/long/se/50.vortex/test.py
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simerr => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
rename : tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simerr
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
rename : tests/long/60.bzip2/ref/arm/linux/o3-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/arm/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/config.ini => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simerr => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simerr
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/simout => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
rename : tests/long/60.bzip2/ref/x86/linux/simple-timing/stats.txt => tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/60.bzip2/test.py => tests/long/se/60.bzip2/test.py
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simerr => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simerr
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.out => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.out
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pin => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sav => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/smred.twf => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt => tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simerr
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/simout => tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/o3-timing/smred.out
rename : tests/long/70.twolf/ref/arm/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/arm/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/simout => tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/arm/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/arm/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/sparc/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/simout => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/sparc/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/simout => tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.out
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/o3-timing/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/simout => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.out
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/simple-atomic/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/config.ini => tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simerr => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simerr
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/simout => tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.out => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.out
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pin => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pin
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl1 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.pl2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sav => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sav
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.sv2 => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/smred.twf => tests/long/se/70.twolf/ref/x86/linux/simple-timing/smred.twf
rename : tests/long/70.twolf/ref/x86/linux/simple-timing/stats.txt => tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
rename : tests/long/70.twolf/test.py => tests/long/se/70.twolf/test.py
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/status => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
rename : tests/quick/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal => tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/system.pc.terminal
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simerr
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/simout => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
rename : tests/quick/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal => tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/system.pc.terminal
rename : tests/quick/10.linux-boot/test.py => tests/quick/fs/10.linux-boot/test.py
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simerr
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
rename : tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal => tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
rename : tests/quick/80.netperf-stream/test.py => tests/quick/fs/80.netperf-stream/test.py
rename : tests/quick/00.hello.mp/test.py => tests/quick/se/00.hello.mp/test.py
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simerr => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simerr
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/simout => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
rename : tests/quick/00.hello/ref/alpha/tru64/simple-timing/stats.txt => tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/simout => tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/simout => tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/arm/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/simout => tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/simout => tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/mips/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/power/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/power/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/power/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/power/linux/o3-timing/simout => tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/power/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/power/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/simout => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/simout => tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/o3-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/simout => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-atomic/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/config.ini => tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simerr => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simerr
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/simout => tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
rename : tests/quick/00.hello/ref/x86/linux/simple-timing/stats.txt => tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
rename : tests/quick/00.hello/test.py => tests/quick/se/00.hello/test.py
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simerr
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
rename : tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt => tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
rename : tests/quick/01.hello-2T-smt/test.py => tests/quick/se/01.hello-2T-smt/test.py
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/inorder-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/o3-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/config.ini => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simerr => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simerr
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/simout => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
rename : tests/quick/02.insttest/ref/sparc/linux/simple-timing/stats.txt => tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
rename : tests/quick/02.insttest/test.py => tests/quick/se/02.insttest/test.py
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/simout => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/detailed/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/detailed/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/config.ini => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simerr
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
rename : tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt => tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/stats.txt
rename : tests/quick/20.eio-short/test.py => tests/quick/se/20.eio-short/test.py
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
rename : tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt => tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt
rename : tests/quick/30.eio-mp/test.py => tests/quick/se/30.eio-mp/test.py
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/skip
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp-ruby/stats.txt
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simerr
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
rename : tests/quick/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt => tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
rename : tests/quick/40.m5threads-test-atomic/test.py => tests/quick/se/40.m5threads-test-atomic/test.py
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
rename : tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
rename : tests/quick/50.memtest/test.py => tests/quick/se/50.memtest/test.py
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
rename : tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt => tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
rename : tests/quick/60.rubytest/test.py => tests/quick/se/60.rubytest/test.py

29 files changed, 12731 insertions, 0 deletions

diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
new file mode 100644
index 000000000..b96bfd745
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
@@ -0,0 +1,928 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
+
+[system.cpu0]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.l1_cntrl0.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.l1_cntrl1.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.l1_cntrl2.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.l1_cntrl3.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.l1_cntrl4.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.l1_cntrl5.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.l1_cntrl6.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.l1_cntrl7.sequencer.port[0]
+
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+cntrl_id=9
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+to_mem_ctrl_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+buffer_size=0
+cntrl_id=0
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.l1_cntrl1]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
+buffer_size=0
+cntrl_id=1
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl1.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=1
+
+[system.l1_cntrl1.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl1.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl1.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=1
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.l1_cntrl2]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
+buffer_size=0
+cntrl_id=2
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl2.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=2
+
+[system.l1_cntrl2.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl2.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl2.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=2
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.l1_cntrl3]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
+buffer_size=0
+cntrl_id=3
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl3.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=3
+
+[system.l1_cntrl3.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl3.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl3.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=3
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.l1_cntrl4]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
+buffer_size=0
+cntrl_id=4
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl4.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=4
+
+[system.l1_cntrl4.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl4.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl4.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=4
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.l1_cntrl5]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
+buffer_size=0
+cntrl_id=5
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl5.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=5
+
+[system.l1_cntrl5.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl5.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl5.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=5
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.l1_cntrl6]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
+buffer_size=0
+cntrl_id=6
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl6.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=6
+
+[system.l1_cntrl6.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl6.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl6.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=6
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.l1_cntrl7]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
+buffer_size=0
+cntrl_id=7
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl7.sequencer
+to_l2_latency=1
+transitions_per_cycle=32
+version=7
+
+[system.l1_cntrl7.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl7.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl7.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=7
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+cntrl_id=8
+l2_request_latency=2
+l2_response_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+to_l1_latency=1
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=network profiler
+block_size_bytes=64
+clock=1
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=false
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=1000
+number_of_virtual_networks=10
+ruby_system=system.ruby
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
+description=Crossbar
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+print_config=false
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
+
+[system.ruby.network.topology.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl0
+int_node=system.ruby.network.topology.routers00
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.topology.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl1
+int_node=system.ruby.network.topology.routers01
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.topology.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl2
+int_node=system.ruby.network.topology.routers02
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.topology.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl3
+int_node=system.ruby.network.topology.routers03
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.topology.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl4
+int_node=system.ruby.network.topology.routers04
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.topology.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl5
+int_node=system.ruby.network.topology.routers05
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.topology.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl6
+int_node=system.ruby.network.topology.routers06
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.topology.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl7
+int_node=system.ruby.network.topology.routers07
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.topology.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l2_cntrl0
+int_node=system.ruby.network.topology.routers08
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.topology.ext_links9]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.dir_cntrl0
+int_node=system.ruby.network.topology.routers09
+latency=1
+link_id=9
+weight=1
+
+[system.ruby.network.topology.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=18
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=19
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
new file mode 100644
index 000000000..83d47d194
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -0,0 +1,910 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 1
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/23/2012 04:26:12
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 251
+Elapsed_time_in_minutes: 4.18333
+Elapsed_time_in_hours: 0.0697222
+Elapsed_time_in_days: 0.00290509
+
+Virtual_time_in_seconds: 250.81
+Virtual_time_in_minutes: 4.18017
+Virtual_time_in_hours:   0.0696694
+Virtual_time_in_days:    0.00290289
+
+Ruby_current_time: 22570074
+Ruby_start_time: 0
+Ruby_cycles: 22570074
+
+mbytes_resident: 41.8906
+mbytes_total: 339.688
+resident_ratio: 0.123321
+
+ruby_cycles_executed: [ 22570075 22570075 22570075 22570075 22570075 22570075 22570075 22570075 ]
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
+
+L2Cache-0:0  
+Directory-0:0  
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 607977 average: 15.9984 | standard deviation: 0.127729 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 607857 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 4096 max: 496494 count: 607849 average: 4750.99 | standard deviation: 9556.54 | 355105 169191 59645 14289 3099 901 533 416 339 360 301 307 272 222 195 214 182 182 146 147 133 117 100 98 103 77 85 58 69 51 57 65 48 59 50 44 45 36 43 28 31 29 24 23 23 19 19 22 17 13 14 15 12 8 6 15 10 7 8 9 7 9 6 5 9 4 6 4 3 3 3 1 1 6 2 4 5 2 1 3 0 1 3 0 1 1 2 1 0 1 0 0 1 3 0 2 0 2 0 1 0 0 0 0 0 1 0 1 0 2 0 0 0 1 2 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 4096 max: 490436 count: 394834 average: 4762.86 | standard deviation: 9711.77 | 230455 110075 38816 9210 2008 585 365 253 208 244 197 195 174 145 133 148 107 123 104 108 87 77 61 55 64 55 53 44 49 35 37 39 30 46 33 26 25 24 35 18 23 18 20 11 13 15 9 15 11 8 8 9 6 4 4 7 7 5 5 7 5 5 4 4 7 4 4 4 2 3 2 0 1 2 1 2 4 2 0 3 0 1 3 0 0 1 2 1 0 1 0 0 1 2 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 0 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 4096 max: 496494 count: 213015 average: 4728.98 | standard deviation: 9261.9 | 124650 59116 20829 5079 1091 316 168 163 131 116 104 112 98 77 62 66 75 59 42 39 46 40 39 43 39 22 32 14 20 16 20 26 18 13 17 18 20 12 8 10 8 11 4 12 10 4 10 7 6 5 6 6 6 4 2 8 3 2 3 2 2 4 2 1 2 0 2 0 1 0 1 1 0 4 1 2 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 4096 max: 496494 count: 607849 average: 4750.99 | standard deviation: 9556.54 | 355105 169191 59645 14289 3099 901 533 416 339 360 301 307 272 222 195 214 182 182 146 147 133 117 100 98 103 77 85 58 69 51 57 65 48 59 50 44 45 36 43 28 31 29 24 23 23 19 19 22 17 13 14 15 12 8 6 15 10 7 8 9 7 9 6 5 9 4 6 4 3 3 3 1 1 6 2 4 5 2 1 3 0 1 3 0 1 1 2 1 0 1 0 0 1 3 0 2 0 2 0 1 0 0 0 0 0 1 0 1 0 2 0 0 0 1 2 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_NULL: [binsize: 4096 max: 490436 count: 394834 average: 4762.86 | standard deviation: 9711.77 | 230455 110075 38816 9210 2008 585 365 253 208 244 197 195 174 145 133 148 107 123 104 108 87 77 61 55 64 55 53 44 49 35 37 39 30 46 33 26 25 24 35 18 23 18 20 11 13 15 9 15 11 8 8 9 6 4 4 7 7 5 5 7 5 5 4 4 7 4 4 4 2 3 2 0 1 2 1 2 4 2 0 3 0 1 3 0 0 1 2 1 0 1 0 0 1 2 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 2 0 0 0 1 2 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 4096 max: 496494 count: 213015 average: 4728.98 | standard deviation: 9261.9 | 124650 59116 20829 5079 1091 316 168 163 131 116 104 112 98 77 62 66 75 59 42 39 46 40 39 43 39 22 32 14 20 16 20 26 18 13 17 18 20 12 8 10 8 11 4 12 10 4 10 7 6 5 6 6 6 4 2 8 3 2 3 2 2 4 2 1 2 0 2 0 1 0 1 1 0 4 1 2 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 512 max: 14615 count: 4591131 average: 71.483 | standard deviation: 382.552 | 4445303 71429 25716 13355 8643 6710 5118 4179 3087 2370 1645 1185 778 570 386 232 170 104 53 31 26 11 12 5 2 5 3 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 20 count: 3083256 average: 0.208137 | standard deviation: 0.796792 | 2751370 221517 30254 20578 22740 19744 14634 794 583 437 475 70 19 8 21 6 2 0 2 1 1 ]
+  virtual_network_0_delay_cycles: [binsize: 512 max: 14615 count: 1507875 average: 217.224 | standard deviation: 643.398 | 1362047 71429 25716 13355 8643 6710 5118 4179 3087 2370 1645 1185 778 570 386 232 170 104 53 31 26 11 12 5 2 5 3 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 20 count: 485327 average: 0.227906 | standard deviation: 0.828193 | 420344 48971 6701 1578 1851 2838 1762 436 88 273 369 61 15 7 21 6 2 0 2 1 1 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 13 count: 2597929 average: 0.204444 | standard deviation: 0.790733 | 2331026 172546 23553 19000 20889 16906 12872 358 495 164 106 9 4 1 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 250
+system_time: 0
+page_reclaims: 11074
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 208
+
+Network Stats
+-------------
+
+total_msg_count_Control: 3637485 29099880
+total_msg_count_Request_Control: 1453647 11629176
+total_msg_count_Response_Data: 4275051 307803672
+total_msg_count_Response_Control: 6300513 50404104
+total_msg_count_Writeback_Data: 1156890 83296080
+total_msg_count_Writeback_Control: 573396 4587168
+total_msgs: 17396982 total_bytes: 486820080
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 1.58871
+  links_utilized_percent_switch_0_link_0: 1.75155 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 1.42586 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 61316 490528 [ 61316 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 76858 5533776 [ 0 76858 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 37620 300960 [ 0 37620 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 76861 614888 [ 76861 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 168 12096 [ 0 168 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 102017 816136 [ 0 25650 76367 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 48759 3510648 [ 13206 35553 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 24414 195312 [ 24414 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 1.57407
+  links_utilized_percent_switch_1_link_0: 1.73518 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 1.41296 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 60819 486552 [ 60819 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 76153 5483016 [ 0 76153 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 37066 296528 [ 0 37066 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 76155 609240 [ 76155 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 171 12312 [ 0 171 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 101164 809312 [ 0 25505 75659 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 48336 3480192 [ 13138 35198 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 23928 191424 [ 23928 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 1.55874
+  links_utilized_percent_switch_2_link_0: 1.71975 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 1.39772 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 60425 483400 [ 60425 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 75466 5433552 [ 0 75466 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 36678 293424 [ 0 36678 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 75468 603744 [ 75468 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 185 13320 [ 0 185 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 100414 803312 [ 0 25436 74978 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 47731 3436632 [ 12870 34861 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 23809 190472 [ 23809 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 1.57195
+  links_utilized_percent_switch_3_link_0: 1.73065 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 1.41325 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Request_Control: 60661 485288 [ 60661 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 75942 5467824 [ 0 75942 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 37080 296640 [ 0 37080 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Control: 75945 607560 [ 75945 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 156 11232 [ 0 156 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 100823 806584 [ 0 25377 75446 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 48440 3487680 [ 13266 35174 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Control: 23813 190504 [ 23813 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 1.56082
+  links_utilized_percent_switch_4_link_0: 1.72098 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 1.40066 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Request_Control: 60424 483392 [ 60424 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 75520 5437440 [ 0 75520 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 36748 293984 [ 0 36748 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Control: 75521 604168 [ 75521 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 150 10800 [ 0 150 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 100453 803624 [ 0 25381 75072 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 47907 3449304 [ 12973 34934 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 23775 190200 [ 23775 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 1.56684
+  links_utilized_percent_switch_5_link_0: 1.73026 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 1.40342 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Request_Control: 60530 484240 [ 60530 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 75951 5468472 [ 0 75951 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 36954 295632 [ 0 36954 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Control: 75953 607624 [ 75953 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 151 10872 [ 0 151 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 101090 808720 [ 0 25567 75523 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 47912 3449664 [ 13060 34852 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Control: 23894 191152 [ 23894 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 1.56294
+  links_utilized_percent_switch_6_link_0: 1.72248 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 1.40339 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Request_Control: 60256 482048 [ 60256 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 75607 5443704 [ 0 75607 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 36813 294504 [ 0 36813 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Control: 75611 604888 [ 75611 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 190 13680 [ 0 190 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 100454 803632 [ 0 25339 75115 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 48015 3457080 [ 13233 34782 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Control: 23582 188656 [ 23582 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 1.57836
+  links_utilized_percent_switch_7_link_0: 1.73917 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 1.41756 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Request_Control: 60896 487168 [ 60896 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 76341 5496552 [ 0 76341 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 37097 296776 [ 0 37097 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Control: 76345 610760 [ 76345 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 180 12960 [ 0 180 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 101238 809904 [ 0 25420 75818 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 48530 3494160 [ 13181 35349 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 23917 191336 [ 23917 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 22.444
+  links_utilized_percent_switch_8_link_0: 24.6504 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 20.2375 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Control: 607859 4862872 [ 607859 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Data: 605033 43562376 [ 0 605033 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Control: 1412277 11298216 [ 0 808299 603978 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 385630 27765360 [ 104927 280703 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Control: 191132 1529056 [ 191132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Control: 604636 4837088 [ 604636 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 482993 3863944 [ 482993 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 817747 58877784 [ 0 817747 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Control: 687892 5503136 [ 0 687892 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 9.92231
+  links_utilized_percent_switch_9_link_0: 6.4501 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 13.3945 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Control: 604636 4837088 [ 604636 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Data: 212790 15320880 [ 0 212790 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 391838 3134704 [ 0 391838 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 604631 43533432 [ 0 604631 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 604626 4837008 [ 0 604626 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 4.49505
+  links_utilized_percent_switch_10_link_0: 1.75156 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 1.73518 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 1.71975 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 1.73065 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 1.72098 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 1.73026 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 1.72248 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 1.73917 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 24.6504 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 6.4501 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Request_Control: 61316 490528 [ 61316 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Response_Data: 76858 5533776 [ 0 76858 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Response_Control: 37620 300960 [ 0 37620 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Request_Control: 60819 486552 [ 60819 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 76153 5483016 [ 0 76153 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Control: 37066 296528 [ 0 37066 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Request_Control: 60425 483400 [ 60425 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Data: 75466 5433552 [ 0 75466 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Control: 36678 293424 [ 0 36678 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Request_Control: 60661 485288 [ 60661 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Data: 75942 5467824 [ 0 75942 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Control: 37080 296640 [ 0 37080 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Request_Control: 60424 483392 [ 60424 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Data: 75520 5437440 [ 0 75520 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Control: 36748 293984 [ 0 36748 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Request_Control: 60530 484240 [ 60530 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Data: 75951 5468472 [ 0 75951 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Control: 36954 295632 [ 0 36954 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Request_Control: 60256 482048 [ 60256 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Data: 75607 5443704 [ 0 75607 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 36813 294504 [ 0 36813 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Request_Control: 60896 487168 [ 60896 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Data: 76341 5496552 [ 0 76341 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Control: 37097 296776 [ 0 37097 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Control: 607859 4862872 [ 607859 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Data: 605033 43562376 [ 0 605033 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Control: 1412277 11298216 [ 0 808299 603978 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Writeback_Data: 385630 27765360 [ 104927 280703 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Writeback_Control: 191132 1529056 [ 191132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Control: 604636 4837088 [ 604636 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Response_Data: 212790 15320880 [ 0 212790 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Response_Control: 391838 3134704 [ 0 391838 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 76861
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76861
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.1254%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.8746%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76861    100%
+
+ --- L1Cache ---
+ - Event Counts -
+Load [49165 49521 48931 49371 50057 49427 49260 49197 ] 394929
+Ifetch [0 0 0 0 0 0 0 0 ] 0
+Store [26362 26470 26682 27010 26838 26732 26219 26752 ] 213065
+Inv [60315 60419 60121 60769 61203 60703 60297 60551 ] 484378
+L1_Replacement [31022878 30992943 30998511 31011137 30978735 31015750 31000258 30989218 ] 248009430
+Fwd_GETX [68 71 80 74 58 61 71 64 ] 547
+Fwd_GETS [41 40 55 53 55 55 57 46 ] 402
+Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
+Data [0 0 0 0 0 0 0 1 ] 1
+Data_Exclusive [48660 48995 48393 48761 49518 48885 48703 48651 ] 390566
+DataS_fromL1 [51 61 42 54 47 45 58 44 ] 402
+Data_all_Acks [26809 26895 27172 27526 27293 27223 26705 27246 ] 216869
+Ack [0 0 0 0 0 0 0 1 ] 1
+Ack_all [0 0 0 0 0 0 0 1 ] 1
+WB_Ack [36748 36954 36813 37097 37620 37066 36678 37078 ] 296054
+
+ - Transitions -
+NP  Load [49142 49463 48921 49325 50043 49409 49240 49171 ] 394714
+NP  Ifetch [0 0 0 0 0 0 0 0 ] 0
+NP  Store [26354 26461 26670 26992 26798 26723 26210 26739 ] 212947
+NP  Inv [259 267 325 321 292 299 308 289 ] 2360
+NP  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+
+I  Load [18 22 9 14 13 16 9 22 ] 123
+I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I  Store [7 7 11 14 7 7 9 13 ] 75
+I  Inv [0 0 0 0 0 0 0 0 ] 0
+I  L1_Replacement [38492 38706 38461 38904 38940 38776 38480 38549 ] 309308
+
+S  Load [0 0 0 0 0 0 0 0 ] 0
+S  Ifetch [0 0 0 0 0 0 0 0 ] 0
+S  Store [0 0 0 0 0 0 0 0 ] 0
+S  Inv [279 262 261 309 300 295 294 297 ] 2297
+S  L1_Replacement [252 260 311 311 277 286 287 278 ] 2262
+
+E  Load [2 1 1 0 0 0 1 0 ] 5
+E  Ifetch [0 0 0 0 0 0 0 0 ] 0
+E  Store [0 0 1 0 0 1 0 0 ] 2
+E  Inv [24841 25038 24750 24790 25058 24911 24833 24791 ] 199012
+E  L1_Replacement [23788 23910 23588 23928 24424 23937 23820 23820 ] 191215
+E  Fwd_GETX [26 36 46 35 28 30 46 34 ] 281
+E  Fwd_GETS [5 11 8 8 7 6 4 6 ] 55
+E  Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
+
+M  Load [0 1 0 0 1 0 0 0 ] 2
+M  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M  Store [0 1 0 0 0 1 0 0 ] 2
+M  Inv [13349 13381 13403 13783 13564 13551 13314 13451 ] 107796
+M  L1_Replacement [12960 13044 13227 13170 13196 13129 12859 13259 ] 104844
+M  Fwd_GETX [24 20 20 15 10 14 13 12 ] 128
+M  Fwd_GETS [28 22 31 35 33 36 31 29 ] 245
+M  Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
+
+IS  Load [0 0 0 0 0 0 0 0 ] 0
+IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS  Store [0 0 0 0 0 0 0 0 ] 0
+IS  Inv [1 0 1 0 0 0 0 0 ] 2
+IS  L1_Replacement [20157546 20081658 19830753 19901991 20110300 19902485 20045187 19917415 ] 159947335
+IS  Data_Exclusive [48660 48995 48393 48761 49518 48885 48703 48651 ] 390566
+IS  DataS_fromL1 [51 61 42 54 47 45 58 44 ] 402
+IS  Data_all_Acks [447 428 491 523 490 494 488 496 ] 3857
+
+IM  Load [0 0 0 0 0 0 0 0 ] 0
+IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM  Store [0 0 0 0 0 0 0 0 ] 0
+IM  Inv [0 0 0 0 0 0 0 0 ] 0
+IM  L1_Replacement [10789830 10835365 11092162 11032833 10791598 11037137 10879625 10995881 ] 87454431
+IM  Data [0 0 0 0 0 0 0 1 ] 1
+IM  Data_all_Acks [26361 26467 26680 27003 26803 26729 26217 26750 ] 213010
+IM  Ack [0 0 0 0 0 0 0 0 ] 0
+
+SM  Load [0 0 0 0 0 0 0 0 ] 0
+SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM  Store [0 0 0 0 0 0 0 0 ] 0
+SM  Inv [0 0 0 0 0 0 0 0 ] 0
+SM  L1_Replacement [0 0 0 0 0 0 0 16 ] 16
+SM  Ack [0 0 0 0 0 0 0 1 ] 1
+SM  Ack_all [0 0 0 0 0 0 0 1 ] 1
+
+IS_I  Load [0 0 0 0 0 0 0 0 ] 0
+IS_I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS_I  Store [0 0 0 0 0 0 0 0 ] 0
+IS_I  Inv [0 0 0 0 0 0 0 0 ] 0
+IS_I  L1_Replacement [10 0 9 0 0 0 0 0 ] 19
+IS_I  Data_Exclusive [0 0 0 0 0 0 0 0 ] 0
+IS_I  DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0
+IS_I  Data_all_Acks [1 0 1 0 0 0 0 0 ] 2
+
+M_I  Load [0 0 0 0 0 0 0 0 ] 0
+M_I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M_I  Store [0 0 0 0 0 0 0 0 ] 0
+M_I  Inv [21585 21471 21379 21566 21989 21647 21547 21723 ] 172907
+M_I  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+M_I  Fwd_GETX [18 15 14 24 20 17 12 18 ] 138
+M_I  Fwd_GETS [8 7 16 10 15 13 22 11 ] 102
+M_I  Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0
+M_I  WB_Ack [15137 15461 15406 15498 15596 15389 15098 15327 ] 122912
+
+E_I  Load [0 0 0 0 0 0 0 0 ] 0
+E_I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+E_I  Store [0 0 0 0 0 0 0 0 ] 0
+E_I  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+
+SINK_WB_ACK  Load [3 34 0 32 0 2 10 4 ] 85
+SINK_WB_ACK  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  Store [1 1 0 4 33 0 0 0 ] 39
+SINK_WB_ACK  Inv [1 0 2 0 0 0 1 0 ] 4
+SINK_WB_ACK  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SINK_WB_ACK  WB_Ack [21611 21493 21407 21599 22024 21677 21580 21751 ] 173142
+
+Cache Stats: system.l1_cntrl1.L1IcacheMemory
+  system.l1_cntrl1.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl1.L1DcacheMemory
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 76155
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 76155
+  system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   64.9005%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   35.0995%
+
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   76155    100%
+
+Cache Stats: system.l1_cntrl2.L1IcacheMemory
+  system.l1_cntrl2.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl2.L1DcacheMemory
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 75468
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 75468
+  system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   65.2581%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   34.7419%
+
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   75468    100%
+
+Cache Stats: system.l1_cntrl3.L1IcacheMemory
+  system.l1_cntrl3.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl3.L1DcacheMemory
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 75945
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 75945
+  system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7745%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2255%
+
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   75945    100%
+
+Cache Stats: system.l1_cntrl4.L1IcacheMemory
+  system.l1_cntrl4.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl4.L1DcacheMemory
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 75521
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 75521
+  system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   65.0945%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   34.9055%
+
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   75521    100%
+
+Cache Stats: system.l1_cntrl5.L1IcacheMemory
+  system.l1_cntrl5.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl5.L1DcacheMemory
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 75953
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 75953
+  system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.1521%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.8479%
+
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   75953    100%
+
+Cache Stats: system.l1_cntrl6.L1IcacheMemory
+  system.l1_cntrl6.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl6.L1DcacheMemory
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 75611
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 75611
+  system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.7128%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.2872%
+
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   75611    100%
+
+Cache Stats: system.l1_cntrl7.L1IcacheMemory
+  system.l1_cntrl7.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl7.L1DcacheMemory
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 76345
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76345
+  system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.6264%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.3736%
+
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76345    100%
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+  system.l2_cntrl0.L2cacheMemory_total_misses: 607517
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 607517
+  system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   64.962%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   35.038%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   607517    100%
+
+ --- L2Cache ---
+ - Event Counts -
+L1_GET_INSTR [0 ] 0
+L1_GETS [422091 ] 422091
+L1_GETX [248760 ] 248760
+L1_UPGRADE [0 ] 0
+L1_PUTX [123601 ] 123601
+L1_PUTX_old [208407 ] 208407
+Fwd_L1_GETX [0 ] 0
+Fwd_L1_GETS [0 ] 0
+Fwd_L1_GET_INSTR [0 ] 0
+L2_Replacement [43801 ] 43801
+L2_Replacement_clean [33104485 ] 33104485
+Mem_Data [604631 ] 604631
+Mem_Ack [604626 ] 604626
+WB_Data [169468 ] 169468
+WB_Data_clean [111637 ] 111637
+Ack [2333 ] 2333
+Ack_all [201340 ] 201340
+Unblock [402 ] 402
+Unblock_Cancel [0 ] 0
+Exclusive_Unblock [603576 ] 603576
+MEM_Inv [0 ] 0
+
+ - Transitions -
+NP  L1_GET_INSTR [0 ] 0
+NP  L1_GETS [392321 ] 392321
+NP  L1_GETX [212315 ] 212315
+NP  L1_PUTX [0 ] 0
+NP  L1_PUTX_old [117846 ] 117846
+
+SS  L1_GET_INSTR [0 ] 0
+SS  L1_GETS [0 ] 0
+SS  L1_GETX [1 ] 1
+SS  L1_UPGRADE [0 ] 0
+SS  L1_PUTX [18 ] 18
+SS  L1_PUTX_old [0 ] 0
+SS  L2_Replacement [344 ] 344
+SS  L2_Replacement_clean [1984 ] 1984
+SS  MEM_Inv [0 ] 0
+
+M  L1_GET_INSTR [0 ] 0
+M  L1_GETS [174 ] 174
+M  L1_GETX [151 ] 151
+M  L1_PUTX [0 ] 0
+M  L1_PUTX_old [4 ] 4
+M  L2_Replacement [43275 ] 43275
+M  L2_Replacement_clean [79310 ] 79310
+M  MEM_Inv [0 ] 0
+
+MT  L1_GET_INSTR [0 ] 0
+MT  L1_GETS [402 ] 402
+MT  L1_GETX [547 ] 547
+MT  L1_PUTX [122912 ] 122912
+MT  L1_PUTX_old [89 ] 89
+MT  L2_Replacement [72 ] 72
+MT  L2_Replacement_clean [479643 ] 479643
+MT  MEM_Inv [0 ] 0
+
+M_I  L1_GET_INSTR [0 ] 0
+M_I  L1_GETS [3243 ] 3243
+M_I  L1_GETX [1799 ] 1799
+M_I  L1_UPGRADE [0 ] 0
+M_I  L1_PUTX [0 ] 0
+M_I  L1_PUTX_old [54713 ] 54713
+M_I  Mem_Ack [604626 ] 604626
+M_I  MEM_Inv [0 ] 0
+
+MT_I  L1_GET_INSTR [0 ] 0
+MT_I  L1_GETS [0 ] 0
+MT_I  L1_GETX [0 ] 0
+MT_I  L1_UPGRADE [0 ] 0
+MT_I  L1_PUTX [0 ] 0
+MT_I  L1_PUTX_old [2 ] 2
+MT_I  WB_Data [25 ] 25
+MT_I  WB_Data_clean [0 ] 0
+MT_I  Ack_all [47 ] 47
+MT_I  MEM_Inv [0 ] 0
+
+MCT_I  L1_GET_INSTR [0 ] 0
+MCT_I  L1_GETS [106 ] 106
+MCT_I  L1_GETX [144 ] 144
+MCT_I  L1_UPGRADE [0 ] 0
+MCT_I  L1_PUTX [0 ] 0
+MCT_I  L1_PUTX_old [35361 ] 35361
+MCT_I  WB_Data [169099 ] 169099
+MCT_I  WB_Data_clean [111579 ] 111579
+MCT_I  Ack_all [198965 ] 198965
+
+I_I  L1_GET_INSTR [0 ] 0
+I_I  L1_GETS [0 ] 0
+I_I  L1_GETX [0 ] 0
+I_I  L1_UPGRADE [0 ] 0
+I_I  L1_PUTX [0 ] 0
+I_I  L1_PUTX_old [0 ] 0
+I_I  Ack [1989 ] 1989
+I_I  Ack_all [1984 ] 1984
+
+S_I  L1_GET_INSTR [0 ] 0
+S_I  L1_GETS [0 ] 0
+S_I  L1_GETX [0 ] 0
+S_I  L1_UPGRADE [0 ] 0
+S_I  L1_PUTX [0 ] 0
+S_I  L1_PUTX_old [0 ] 0
+S_I  Ack [344 ] 344
+S_I  Ack_all [344 ] 344
+S_I  MEM_Inv [0 ] 0
+
+ISS  L1_GET_INSTR [0 ] 0
+ISS  L1_GETS [1927 ] 1927
+ISS  L1_GETX [20828 ] 20828
+ISS  L1_PUTX [0 ] 0
+ISS  L1_PUTX_old [212 ] 212
+ISS  L2_Replacement [0 ] 0
+ISS  L2_Replacement_clean [19036421 ] 19036421
+ISS  Mem_Data [390392 ] 390392
+ISS  MEM_Inv [0 ] 0
+
+IS  L1_GET_INSTR [0 ] 0
+IS  L1_GETS [5 ] 5
+IS  L1_GETX [143 ] 143
+IS  L1_PUTX [0 ] 0
+IS  L1_PUTX_old [0 ] 0
+IS  L2_Replacement [0 ] 0
+IS  L2_Replacement_clean [97464 ] 97464
+IS  Mem_Data [1927 ] 1927
+IS  MEM_Inv [0 ] 0
+
+IM  L1_GET_INSTR [0 ] 0
+IM  L1_GETS [22267 ] 22267
+IM  L1_GETX [10554 ] 10554
+IM  L1_PUTX [0 ] 0
+IM  L1_PUTX_old [180 ] 180
+IM  L2_Replacement [0 ] 0
+IM  L2_Replacement_clean [10368191 ] 10368191
+IM  Mem_Data [212312 ] 212312
+IM  MEM_Inv [0 ] 0
+
+SS_MB  L1_GET_INSTR [0 ] 0
+SS_MB  L1_GETS [0 ] 0
+SS_MB  L1_GETX [0 ] 0
+SS_MB  L1_UPGRADE [0 ] 0
+SS_MB  L1_PUTX [0 ] 0
+SS_MB  L1_PUTX_old [0 ] 0
+SS_MB  L2_Replacement [0 ] 0
+SS_MB  L2_Replacement_clean [0 ] 0
+SS_MB  Unblock_Cancel [0 ] 0
+SS_MB  Exclusive_Unblock [1 ] 1
+SS_MB  MEM_Inv [0 ] 0
+
+MT_MB  L1_GET_INSTR [0 ] 0
+MT_MB  L1_GETS [1646 ] 1646
+MT_MB  L1_GETX [2278 ] 2278
+MT_MB  L1_UPGRADE [0 ] 0
+MT_MB  L1_PUTX [388 ] 388
+MT_MB  L1_PUTX_old [0 ] 0
+MT_MB  L2_Replacement [19 ] 19
+MT_MB  L2_Replacement_clean [3040991 ] 3040991
+MT_MB  Unblock_Cancel [0 ] 0
+MT_MB  Exclusive_Unblock [603575 ] 603575
+MT_MB  MEM_Inv [0 ] 0
+
+M_MB  L1_GET_INSTR [0 ] 0
+M_MB  L1_GETS [0 ] 0
+M_MB  L1_GETX [0 ] 0
+M_MB  L1_UPGRADE [0 ] 0
+M_MB  L1_PUTX [0 ] 0
+M_MB  L1_PUTX_old [0 ] 0
+M_MB  L2_Replacement [0 ] 0
+M_MB  L2_Replacement_clean [0 ] 0
+M_MB  Exclusive_Unblock [0 ] 0
+M_MB  MEM_Inv [0 ] 0
+
+MT_IIB  L1_GET_INSTR [0 ] 0
+MT_IIB  L1_GETS [0 ] 0
+MT_IIB  L1_GETX [0 ] 0
+MT_IIB  L1_UPGRADE [0 ] 0
+MT_IIB  L1_PUTX [203 ] 203
+MT_IIB  L1_PUTX_old [0 ] 0
+MT_IIB  L2_Replacement [0 ] 0
+MT_IIB  L2_Replacement_clean [480 ] 480
+MT_IIB  WB_Data [343 ] 343
+MT_IIB  WB_Data_clean [58 ] 58
+MT_IIB  Unblock [1 ] 1
+MT_IIB  MEM_Inv [0 ] 0
+
+MT_IB  L1_GET_INSTR [0 ] 0
+MT_IB  L1_GETS [0 ] 0
+MT_IB  L1_GETX [0 ] 0
+MT_IB  L1_UPGRADE [0 ] 0
+MT_IB  L1_PUTX [0 ] 0
+MT_IB  L1_PUTX_old [0 ] 0
+MT_IB  L2_Replacement [0 ] 0
+MT_IB  L2_Replacement_clean [0 ] 0
+MT_IB  WB_Data [1 ] 1
+MT_IB  WB_Data_clean [0 ] 0
+MT_IB  Unblock_Cancel [0 ] 0
+MT_IB  MEM_Inv [0 ] 0
+
+MT_SB  L1_GET_INSTR [0 ] 0
+MT_SB  L1_GETS [0 ] 0
+MT_SB  L1_GETX [0 ] 0
+MT_SB  L1_UPGRADE [0 ] 0
+MT_SB  L1_PUTX [80 ] 80
+MT_SB  L1_PUTX_old [0 ] 0
+MT_SB  L2_Replacement [91 ] 91
+MT_SB  L2_Replacement_clean [1 ] 1
+MT_SB  Unblock [401 ] 401
+MT_SB  MEM_Inv [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 817426
+  memory_reads: 604635
+  memory_writes: 212789
+  memory_refreshes: 47021
+  memory_total_request_delays: 10414985
+  memory_delays_per_request: 12.7412
+  memory_delays_in_input_queue: 359587
+  memory_delays_behind_head_of_bank_queue: 1350935
+  memory_delays_stalled_at_head_of_bank_queue: 8704463
+  memory_stalls_for_bank_busy: 1530499
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 674659
+  memory_stalls_for_arbitration: 1774410
+  memory_stalls_for_bus: 2738438
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 1415262
+  memory_stalls_for_read_read_turnaround: 571195
+  accesses_per_bank: 25739  25325  25438  25683  25679  25637  25766  25555  25740  25505  25578  25662  25344  25393  25488  25442  25462  25509  25568  25516  25705  25537  25668  25458  25453  25173  25551  25126  25479  25713  25863  25671  
+
+ --- Directory ---
+ - Event Counts -
+Fetch [604636 ] 604636
+Data [212790 ] 212790
+Memory_Data [604631 ] 604631
+Memory_Ack [212788 ] 212788
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+CleanReplacement [391838 ] 391838
+
+ - Transitions -
+I  Fetch [604636 ] 604636
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+ID  Fetch [0 ] 0
+ID  Data [0 ] 0
+ID  Memory_Data [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+
+ID_W  Fetch [0 ] 0
+ID_W  Data [0 ] 0
+ID_W  Memory_Ack [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+
+M  Data [212790 ] 212790
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+M  CleanReplacement [391838 ] 391838
+
+IM  Fetch [0 ] 0
+IM  Data [0 ] 0
+IM  Memory_Data [604631 ] 604631
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+
+MI  Fetch [0 ] 0
+MI  Data [0 ] 0
+MI  Memory_Ack [212788 ] 212788
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+
+M_DRD  Data [0 ] 0
+M_DRD  DMA_READ [0 ] 0
+M_DRD  DMA_WRITE [0 ] 0
+
+M_DRDI  Fetch [0 ] 0
+M_DRDI  Data [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+M_DRDI  DMA_READ [0 ] 0
+M_DRDI  DMA_WRITE [0 ] 0
+
+M_DWR  Data [0 ] 0
+M_DWR  DMA_READ [0 ] 0
+M_DWR  DMA_WRITE [0 ] 0
+
+M_DWRI  Fetch [0 ] 0
+M_DWRI  Data [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+M_DWRI  DMA_READ [0 ] 0
+M_DWRI  DMA_WRITE [0 ] 0
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
new file mode 100755
index 000000000..c4fb7c226
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
@@ -0,0 +1,74 @@
+system.cpu7: completed 10000 read, 5407 write accesses @2193104
+system.cpu5: completed 10000 read, 5417 write accesses @2227894
+system.cpu3: completed 10000 read, 5304 write accesses @2241899
+system.cpu0: completed 10000 read, 5406 write accesses @2286999
+system.cpu6: completed 10000 read, 5500 write accesses @2314615
+system.cpu2: completed 10000 read, 5192 write accesses @2332464
+system.cpu4: completed 10000 read, 5484 write accesses @2351825
+system.cpu1: completed 10000 read, 5601 write accesses @2421215
+system.cpu7: completed 20000 read, 10600 write accesses @4362574
+system.cpu2: completed 20000 read, 10442 write accesses @4540254
+system.cpu5: completed 20000 read, 10862 write accesses @4558355
+system.cpu3: completed 20000 read, 10634 write accesses @4562696
+system.cpu0: completed 20000 read, 10789 write accesses @4572225
+system.cpu6: completed 20000 read, 10964 write accesses @4613315
+system.cpu4: completed 20000 read, 10859 write accesses @4624135
+system.cpu1: completed 20000 read, 10860 write accesses @4669865
+system.cpu7: completed 30000 read, 16054 write accesses @6655525
+system.cpu0: completed 30000 read, 16092 write accesses @6770115
+system.cpu1: completed 30000 read, 16284 write accesses @6828865
+system.cpu3: completed 30000 read, 16125 write accesses @6864285
+system.cpu4: completed 30000 read, 16227 write accesses @6890965
+system.cpu6: completed 30000 read, 16336 write accesses @6904064
+system.cpu2: completed 30000 read, 15932 write accesses @6953085
+system.cpu5: completed 30000 read, 16240 write accesses @6957625
+system.cpu7: completed 40000 read, 21410 write accesses @8901178
+system.cpu0: completed 40000 read, 21509 write accesses @9069465
+system.cpu1: completed 40000 read, 21632 write accesses @9091094
+system.cpu3: completed 40000 read, 21475 write accesses @9116195
+system.cpu4: completed 40000 read, 21761 write accesses @9209395
+system.cpu5: completed 40000 read, 21553 write accesses @9245188
+system.cpu6: completed 40000 read, 21832 write accesses @9310296
+system.cpu2: completed 40000 read, 21265 write accesses @9325324
+system.cpu7: completed 50000 read, 26853 write accesses @11255815
+system.cpu0: completed 50000 read, 26977 write accesses @11286865
+system.cpu1: completed 50000 read, 27136 write accesses @11385455
+system.cpu5: completed 50000 read, 26999 write accesses @11446175
+system.cpu4: completed 50000 read, 27138 write accesses @11497105
+system.cpu3: completed 50000 read, 26925 write accesses @11513845
+system.cpu6: completed 50000 read, 27245 write accesses @11629194
+system.cpu2: completed 50000 read, 26613 write accesses @11642405
+system.cpu0: completed 60000 read, 32322 write accesses @13513714
+system.cpu7: completed 60000 read, 32300 write accesses @13580354
+system.cpu5: completed 60000 read, 32335 write accesses @13650056
+system.cpu1: completed 60000 read, 32734 write accesses @13710275
+system.cpu4: completed 60000 read, 32403 write accesses @13735965
+system.cpu2: completed 60000 read, 31942 write accesses @13824435
+system.cpu6: completed 60000 read, 32511 write accesses @13871344
+system.cpu3: completed 60000 read, 32324 write accesses @13913205
+system.cpu0: completed 70000 read, 37723 write accesses @15813186
+system.cpu7: completed 70000 read, 37805 write accesses @15917425
+system.cpu5: completed 70000 read, 37663 write accesses @15942505
+system.cpu4: completed 70000 read, 37631 write accesses @16028785
+system.cpu1: completed 70000 read, 38017 write accesses @16031454
+system.cpu3: completed 70000 read, 37707 write accesses @16112322
+system.cpu6: completed 70000 read, 37910 write accesses @16120997
+system.cpu2: completed 70000 read, 37183 write accesses @16150764
+system.cpu0: completed 80000 read, 42908 write accesses @18001745
+system.cpu5: completed 80000 read, 42901 write accesses @18163144
+system.cpu4: completed 80000 read, 42765 write accesses @18206905
+system.cpu7: completed 80000 read, 43338 write accesses @18261574
+system.cpu6: completed 80000 read, 43257 write accesses @18334555
+system.cpu1: completed 80000 read, 43298 write accesses @18408395
+system.cpu3: completed 80000 read, 43106 write accesses @18453978
+system.cpu2: completed 80000 read, 42466 write accesses @18467507
+system.cpu0: completed 90000 read, 48230 write accesses @20259175
+system.cpu5: completed 90000 read, 48356 write accesses @20526365
+system.cpu7: completed 90000 read, 48874 write accesses @20532605
+system.cpu4: completed 90000 read, 48159 write accesses @20555334
+system.cpu1: completed 90000 read, 48676 write accesses @20572365
+system.cpu6: completed 90000 read, 48688 write accesses @20703625
+system.cpu2: completed 90000 read, 47767 write accesses @20716675
+system.cpu3: completed 90000 read, 48620 write accesses @20769265
+system.cpu0: completed 100000 read, 53615 write accesses @22570074
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
new file mode 100755
index 000000000..20caf030d
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:44:57
+gem5 started Jan 23 2012 04:22:01
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 22570074 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
new file mode 100644
index 000000000..bb265760e
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -0,0 +1,47 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.022570                       # Number of seconds simulated
+sim_ticks                                    22570074                       # Number of ticks simulated
+final_tick                                   22570074                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                  89999                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347844                       # Number of bytes of host memory used
+host_seconds                                   250.78                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          53615                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           98926                       # number of read accesses completed
+system.cpu1.num_writes                          53490                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           98053                       # number of read accesses completed
+system.cpu2.num_writes                          52227                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           98222                       # number of read accesses completed
+system.cpu3.num_writes                          53057                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                           98292                       # number of read accesses completed
+system.cpu4.num_writes                          52603                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                           98988                       # number of read accesses completed
+system.cpu5.num_writes                          53055                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           98007                       # number of read accesses completed
+system.cpu6.num_writes                          53041                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           99081                       # number of read accesses completed
+system.cpu7.num_writes                          53785                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
new file mode 100644
index 000000000..e0267adf3
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini
@@ -0,0 +1,910 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
+
+[system.cpu0]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.l1_cntrl0.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.l1_cntrl1.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.l1_cntrl2.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.l1_cntrl3.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.l1_cntrl4.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.l1_cntrl5.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.l1_cntrl6.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.l1_cntrl7.sequencer.port[0]
+
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+cntrl_id=9
+directory=system.dir_cntrl0.directory
+directory_latency=6
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+buffer_size=0
+cntrl_id=0
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.l1_cntrl1]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
+buffer_size=0
+cntrl_id=1
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl1.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.l1_cntrl1.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl1.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl1.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=1
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.l1_cntrl2]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
+buffer_size=0
+cntrl_id=2
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl2.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.l1_cntrl2.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl2.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl2.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=2
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.l1_cntrl3]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
+buffer_size=0
+cntrl_id=3
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl3.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.l1_cntrl3.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl3.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl3.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=3
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.l1_cntrl4]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
+buffer_size=0
+cntrl_id=4
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl4.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.l1_cntrl4.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl4.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl4.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=4
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.l1_cntrl5]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
+buffer_size=0
+cntrl_id=5
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl5.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.l1_cntrl5.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl5.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl5.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=5
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.l1_cntrl6]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
+buffer_size=0
+cntrl_id=6
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl6.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.l1_cntrl6.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl6.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl6.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=6
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.l1_cntrl7]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
+buffer_size=0
+cntrl_id=7
+l2_select_num_bits=0
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+ruby_system=system.ruby
+sequencer=system.l1_cntrl7.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.l1_cntrl7.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl7.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl7.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=7
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+buffer_size=0
+cntrl_id=8
+number_of_TBEs=256
+recycle_latency=10
+request_latency=2
+response_latency=2
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=15
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=network profiler
+block_size_bytes=64
+clock=1
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=false
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=1000
+number_of_virtual_networks=10
+ruby_system=system.ruby
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
+description=Crossbar
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+print_config=false
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
+
+[system.ruby.network.topology.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl0
+int_node=system.ruby.network.topology.routers00
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.topology.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl1
+int_node=system.ruby.network.topology.routers01
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.topology.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl2
+int_node=system.ruby.network.topology.routers02
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.topology.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl3
+int_node=system.ruby.network.topology.routers03
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.topology.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl4
+int_node=system.ruby.network.topology.routers04
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.topology.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl5
+int_node=system.ruby.network.topology.routers05
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.topology.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl6
+int_node=system.ruby.network.topology.routers06
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.topology.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl7
+int_node=system.ruby.network.topology.routers07
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.topology.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l2_cntrl0
+int_node=system.ruby.network.topology.routers08
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.topology.ext_links9]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.dir_cntrl0
+int_node=system.ruby.network.topology.routers09
+latency=1
+link_id=9
+weight=1
+
+[system.ruby.network.topology.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=18
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=19
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
new file mode 100644
index 000000000..78fcf4ec9
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -0,0 +1,1794 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 1
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, unordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: inactive
+virtual_net_4: inactive
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/23/2012 04:26:05
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 233
+Elapsed_time_in_minutes: 3.88333
+Elapsed_time_in_hours: 0.0647222
+Elapsed_time_in_days: 0.00269676
+
+Virtual_time_in_seconds: 232.61
+Virtual_time_in_minutes: 3.87683
+Virtual_time_in_hours:   0.0646139
+Virtual_time_in_days:    0.00269225
+
+Ruby_current_time: 19400856
+Ruby_start_time: 0
+Ruby_cycles: 19400856
+
+mbytes_resident: 42.1172
+mbytes_total: 339.848
+resident_ratio: 0.12393
+
+ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ]
+
+Busy Controller Counts:
+L2Cache-0:0  
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
+
+
+Directory-0:0  
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 611543 average: 15.9984 | standard deviation: 0.127356 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 611423 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 4096 max: 471736 count: 611415 average: 4056.74 | standard deviation: 10848.1 | 482227 61326 33739 15196 5426 2164 1259 902 879 774 686 670 594 495 501 448 405 337 306 341 282 251 215 201 194 156 143 114 117 112 82 83 79 67 51 42 52 28 41 40 26 25 30 22 20 22 16 14 10 11 13 11 17 11 13 8 4 14 5 8 6 3 5 5 7 6 2 4 0 7 4 4 5 3 4 3 6 1 0 1 2 0 0 2 3 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 4096 max: 429244 count: 397143 average: 4044.81 | standard deviation: 10853.8 | 313465 39785 21824 9849 3461 1435 819 560 574 508 445 442 372 328 331 292 273 221 187 211 183 160 125 135 128 109 87 75 72 68 51 60 53 37 33 28 32 15 27 25 16 16 16 16 14 15 12 8 7 6 6 7 10 7 9 6 2 8 4 4 5 3 4 4 7 3 1 4 0 6 4 4 4 2 1 1 6 1 0 1 1 0 0 1 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 4096 max: 471736 count: 214272 average: 4078.85 | standard deviation: 10837.5 | 168762 21541 11915 5347 1965 729 440 342 305 266 241 228 222 167 170 156 132 116 119 130 99 91 90 66 66 47 56 39 45 44 31 23 26 30 18 14 20 13 14 15 10 9 14 6 6 7 4 6 3 5 7 4 7 4 4 2 2 6 1 4 1 0 1 1 0 3 1 0 0 1 0 0 1 1 3 2 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_NULL: [binsize: 4096 max: 471736 count: 611415 average: 4056.74 | standard deviation: 10848.1 | 482227 61326 33739 15196 5426 2164 1259 902 879 774 686 670 594 495 501 448 405 337 306 341 282 251 215 201 194 156 143 114 117 112 82 83 79 67 51 42 52 28 41 40 26 25 30 22 20 22 16 14 10 11 13 11 17 11 13 8 4 14 5 8 6 3 5 5 7 6 2 4 0 7 4 4 5 3 4 3 6 1 0 1 2 0 0 2 3 1 0 0 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 0
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_NULL: [binsize: 4096 max: 429244 count: 397143 average: 4044.81 | standard deviation: 10853.8 | 313465 39785 21824 9849 3461 1435 819 560 574 508 445 442 372 328 331 292 273 221 187 211 183 160 125 135 128 109 87 75 72 68 51 60 53 37 33 28 32 15 27 25 16 16 16 16 14 15 12 8 7 6 6 7 10 7 9 6 2 8 4 4 5 3 4 4 7 3 1 4 0 6 4 4 4 2 1 1 6 1 0 1 1 0 0 1 2 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 4096 max: 471736 count: 214272 average: 4078.85 | standard deviation: 10837.5 | 168762 21541 11915 5347 1965 729 440 342 305 266 241 228 222 167 170 156 132 116 119 130 99 91 90 66 66 47 56 39 45 44 31 23 26 30 18 14 20 13 14 15 10 9 14 6 6 7 4 6 3 5 7 4 7 4 4 2 2 6 1 4 1 0 1 1 0 3 1 0 0 1 0 0 1 1 3 2 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 232
+system_time: 0
+page_reclaims: 11111
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 192
+
+Network Stats
+-------------
+
+total_msg_count_Request_Control: 3636039 29088312
+total_msg_count_Response_Data: 3604368 259514496
+total_msg_count_ResponseL2hit_Data: 6678 480816
+total_msg_count_ResponseLocal_Data: 24849 1789128
+total_msg_count_Response_Control: 8658 69264
+total_msg_count_Writeback_Data: 2451477 176506344
+total_msg_count_Writeback_Control: 8399094 67192752
+total_msg_count_Forwarded_Control: 24849 198792
+total_msg_count_Invalidate_Control: 69 552
+total_msg_count_Unblock_Control: 3647493 29179944
+total_msgs: 21803574 total_bytes: 564020400
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 30.1872
+  links_utilized_percent_switch_0_link_0: 34.22 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 26.1544 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 611261 4890088 [ 611261 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 600728 43252416 [ 0 0 600728 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Data: 604218 43503696 [ 0 0 604218 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 1207058 9656464 [ 608536 598522 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Unblock_Control: 615104 4920832 [ 0 0 615104 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 600752 4806016 [ 0 600752 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 600728 43252416 [ 0 0 600728 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_ResponseL2hit_Data: 2226 160272 [ 0 0 2226 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 2863 22904 [ 0 0 2863 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 212941 15331752 [ 0 0 212941 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 1592640 12741120 [ 608536 598523 385581 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Forwarded_Control: 8283 66264 [ 8283 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Invalidate_Control: 23 184 [ 23 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 600727 4805816 [ 0 0 600727 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 2.17097
+  links_utilized_percent_switch_1_link_0: 1.97262 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.36932 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 75227 5416344 [ 0 0 75227 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 255 18360 [ 0 0 255 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 952 68544 [ 0 0 952 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 354 2832 [ 0 0 354 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 76111 608888 [ 76111 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Forwarded_Control: 1038 8304 [ 1038 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 76437 611496 [ 76437 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 1038 74736 [ 0 0 1038 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 75619 5444568 [ 0 0 75619 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 76111 608888 [ 76111 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 76875 615000 [ 0 0 76875 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 2.1575
+  links_utilized_percent_switch_2_link_0: 1.96119 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.35381 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 74689 5377608 [ 0 0 74689 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 273 19656 [ 0 0 273 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 1033 74376 [ 0 0 1033 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 342 2736 [ 0 0 342 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 75651 605208 [ 75651 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Forwarded_Control: 1024 8192 [ 1024 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 75997 607976 [ 75997 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 1024 73728 [ 0 0 1024 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 75108 5407776 [ 0 0 75108 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 75651 605208 [ 75651 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 76480 611840 [ 0 0 76480 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 2.17414
+  links_utilized_percent_switch_3_link_0: 1.9761 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.37218 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 75255 5418360 [ 0 0 75255 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 285 20520 [ 0 0 285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 1029 74088 [ 0 0 1029 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 359 2872 [ 0 0 359 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 76220 609760 [ 76220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Forwarded_Control: 1058 8464 [ 1058 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 76573 612584 [ 76573 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 1058 76176 [ 0 0 1058 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 4 32 [ 0 0 4 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 75674 5448528 [ 0 0 75674 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Control: 76220 609760 [ 76220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 77063 616504 [ 0 0 77063 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 2.15519
+  links_utilized_percent_switch_4_link_0: 1.95871 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.35166 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Response_Data: 74576 5369472 [ 0 0 74576 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 275 19800 [ 0 0 275 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 1044 75168 [ 0 0 1044 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 347 2776 [ 0 0 347 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 75587 604696 [ 75587 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Forwarded_Control: 1023 8184 [ 1023 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 75899 607192 [ 75899 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 1023 73656 [ 0 0 1023 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 1 8 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 75045 5403240 [ 0 0 75045 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 75587 604696 [ 75587 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 76387 611096 [ 0 0 76387 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 2.17809
+  links_utilized_percent_switch_5_link_0: 1.98026 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.37592 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Response_Data: 75361 5425992 [ 0 0 75361 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 282 20304 [ 0 0 282 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 1091 78552 [ 0 0 1091 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 366 2928 [ 0 0 366 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 76408 611264 [ 76408 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Forwarded_Control: 997 7976 [ 997 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 76735 613880 [ 76735 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 997 71784 [ 0 0 997 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 75837 5460264 [ 0 0 75837 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Control: 76408 611264 [ 76408 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 77246 617968 [ 0 0 77246 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 2.17149
+  links_utilized_percent_switch_6_link_0: 1.97336 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.36962 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Response_Data: 75141 5410152 [ 0 0 75141 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 277 19944 [ 0 0 277 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 393 3144 [ 0 0 393 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 76135 609080 [ 76135 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Forwarded_Control: 1037 8296 [ 1037 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 76462 611696 [ 76462 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 1037 74664 [ 0 0 1037 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 3 24 [ 0 0 3 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 75623 5444856 [ 0 0 75623 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Control: 76135 609080 [ 76135 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 76913 615304 [ 0 0 76913 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 2.17401
+  links_utilized_percent_switch_7_link_0: 1.97579 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.37222 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Response_Data: 75261 5418792 [ 0 0 75261 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 277 19944 [ 0 0 277 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 1020 73440 [ 0 0 1020 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 363 2904 [ 0 0 363 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 76198 609584 [ 76198 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Forwarded_Control: 1053 8424 [ 1053 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 76562 612496 [ 76562 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1053 75816 [ 0 0 1053 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 6 48 [ 0 0 6 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 75691 5449752 [ 0 0 75691 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 76198 609584 [ 76198 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 76999 615992 [ 0 0 76999 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 2.17389
+  links_utilized_percent_switch_8_link_0: 1.97667 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 2.37111 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Response_Data: 75218 5415696 [ 0 0 75218 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_ResponseL2hit_Data: 302 21744 [ 0 0 302 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_ResponseLocal_Data: 1073 77256 [ 0 0 1073 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Control: 362 2896 [ 0 0 362 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Control: 76226 609808 [ 76226 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Forwarded_Control: 1053 8424 [ 1053 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 76596 612768 [ 76596 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_ResponseLocal_Data: 1053 75816 [ 0 0 1053 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Control: 3 24 [ 0 0 3 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Data: 75621 5444712 [ 0 0 75621 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 76226 609808 [ 76226 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Unblock_Control: 77141 617128 [ 0 0 77141 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 13.0241
+  links_utilized_percent_switch_9_link_0: 10.5718 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 15.4763 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 600752 4806016 [ 0 600752 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Data: 212941 15331752 [ 0 0 212941 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 984104 7872832 [ 0 598523 385581 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Unblock_Control: 600727 4805816 [ 0 0 600727 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 600728 43252416 [ 0 0 600728 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 598522 4788176 [ 0 598522 0 0 0 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 6.05665
+  links_utilized_percent_switch_10_link_0: 34.22 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 1.97262 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 1.96119 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 1.9761 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 1.95871 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 1.98027 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 1.97336 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 1.97579 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 1.97667 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 10.5718 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Request_Control: 611261 4890088 [ 611261 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Response_Data: 600728 43252416 [ 0 0 600728 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Writeback_Data: 604218 43503696 [ 0 0 604218 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Writeback_Control: 1207058 9656464 [ 608536 598522 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Unblock_Control: 615104 4920832 [ 0 0 615104 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 75227 5416344 [ 0 0 75227 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 255 18360 [ 0 0 255 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 952 68544 [ 0 0 952 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Control: 354 2832 [ 0 0 354 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Writeback_Control: 76111 608888 [ 76111 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Forwarded_Control: 1038 8304 [ 1038 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Data: 74689 5377608 [ 0 0 74689 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 273 19656 [ 0 0 273 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 1033 74376 [ 0 0 1033 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Control: 342 2736 [ 0 0 342 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Writeback_Control: 75651 605208 [ 75651 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Forwarded_Control: 1024 8192 [ 1024 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Data: 75255 5418360 [ 0 0 75255 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 285 20520 [ 0 0 285 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 1029 74088 [ 0 0 1029 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Control: 359 2872 [ 0 0 359 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Writeback_Control: 76220 609760 [ 76220 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Forwarded_Control: 1058 8464 [ 1058 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Invalidate_Control: 4 32 [ 4 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Data: 74576 5369472 [ 0 0 74576 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 275 19800 [ 0 0 275 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 1044 75168 [ 0 0 1044 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Control: 347 2776 [ 0 0 347 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Writeback_Control: 75587 604696 [ 75587 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Forwarded_Control: 1023 8184 [ 1023 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Invalidate_Control: 1 8 [ 1 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Data: 75361 5425992 [ 0 0 75361 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 282 20304 [ 0 0 282 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 1091 78552 [ 0 0 1091 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Control: 366 2928 [ 0 0 366 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Writeback_Control: 76408 611264 [ 76408 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Forwarded_Control: 997 7976 [ 997 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Invalidate_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Data: 75141 5410152 [ 0 0 75141 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 277 19944 [ 0 0 277 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 1041 74952 [ 0 0 1041 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 393 3144 [ 0 0 393 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Writeback_Control: 76135 609080 [ 76135 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Forwarded_Control: 1037 8296 [ 1037 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Data: 75261 5418792 [ 0 0 75261 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 277 19944 [ 0 0 277 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 1020 73440 [ 0 0 1020 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Control: 363 2904 [ 0 0 363 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Writeback_Control: 76198 609584 [ 76198 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Forwarded_Control: 1053 8424 [ 1053 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Invalidate_Control: 6 48 [ 6 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Data: 75218 5415696 [ 0 0 75218 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_ResponseL2hit_Data: 302 21744 [ 0 0 302 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_ResponseLocal_Data: 1073 77256 [ 0 0 1073 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Control: 362 2896 [ 0 0 362 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Writeback_Control: 76226 609808 [ 76226 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Forwarded_Control: 1053 8424 [ 1053 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Invalidate_Control: 3 24 [ 3 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Request_Control: 600752 4806016 [ 0 600752 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Data: 212941 15331752 [ 0 0 212941 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Control: 984104 7872832 [ 0 598523 385581 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Unblock_Control: 600727 4805816 [ 0 0 600727 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+
+
+ --- L1Cache ---
+ - Event Counts -
+Load [49797 49666 49735 49595 49550 49631 49822 49360 ] 397156
+Ifetch [0 0 0 0 0 0 0 0 ] 0
+Store [26955 26819 26845 27019 26906 26394 26778 26567 ] 214283
+L1_Replacement [25735353 25750063 25730434 25732397 25751220 25755516 25726727 25772763 ] 205954473
+Own_GETX [0 0 0 0 0 0 0 0 ] 0
+Fwd_GETX [1201 1088 1161 1248 1126 1083 1138 1105 ] 9150
+Fwd_GETS [2081 2236 2314 2134 2386 2151 2251 2299 ] 17852
+Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+Inv [2 3 6 3 2 2 4 1 ] 23
+Ack [366 393 363 362 354 342 359 347 ] 2886
+Data [885 804 773 840 755 816 783 833 ] 6489
+Exclusive_Data [75849 75655 75785 75753 75679 75179 75786 75062 ] 604748
+Writeback_Ack [410 345 330 421 326 383 381 390 ] 2986
+Writeback_Ack_Data [75940 75732 75802 75748 75734 75210 75787 75147 ] 605100
+Writeback_Nack [58 58 66 57 51 58 52 50 ] 450
+All_acks [26949 26808 26837 27015 26900 26387 26768 26559 ] 214223
+Use_Timeout [75848 75655 75785 75753 75679 75179 75786 75062 ] 604747
+
+ - Transitions -
+I  Load [49785 49653 49722 49579 49537 49608 49805 49338 ] 397027
+I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I  Store [26950 26809 26840 27017 26900 26389 26768 26561 ] 214234
+I  L1_Replacement [380 380 421 419 372 399 397 356 ] 3124
+I  Inv [0 0 0 0 0 0 0 0 ] 0
+
+S  Load [0 0 1 1 0 0 0 0 ] 2
+S  Ifetch [0 0 0 0 0 0 0 0 ] 0
+S  Store [0 0 0 0 0 0 0 0 ] 0
+S  L1_Replacement [884 802 770 840 754 815 782 833 ] 6480
+S  Fwd_GETS [5 5 4 2 1 2 2 2 ] 23
+S  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+S  Inv [1 2 3 0 1 1 1 0 ] 9
+
+O  Load [0 0 0 0 0 0 0 0 ] 0
+O  Ifetch [0 0 0 0 0 0 0 0 ] 0
+O  Store [0 0 0 0 0 0 0 0 ] 0
+O  L1_Replacement [270 292 277 265 297 288 304 292 ] 2285
+O  Fwd_GETX [0 1 0 3 0 0 0 1 ] 5
+O  Fwd_GETS [2 3 2 3 3 0 1 2 ] 16
+O  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+
+M  Load [6 8 4 7 11 15 6 11 ] 68
+M  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M  Store [3 4 4 2 1 2 5 3 ] 24
+M  L1_Replacement [48440 48400 48483 48283 48315 48334 48541 48060 ] 386856
+M  Fwd_GETX [185 146 183 185 165 167 168 147 ] 1346
+M  Fwd_GETS [270 293 277 268 297 288 304 293 ] 2290
+M  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+
+M_W  Load [3 0 3 1 0 1 2 1 ] 11
+M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M_W  Store [0 3 1 0 0 0 0 0 ] 4
+M_W  L1_Replacement [862019 865045 861347 862435 865330 863842 861927 858142 ] 6900087
+M_W  Own_GETX [0 0 0 0 0 0 0 0 ] 0
+M_W  Fwd_GETX [553 488 543 526 522 437 519 441 ] 4029
+M_W  Fwd_GETS [1022 952 990 965 1095 988 964 1090 ] 8066
+M_W  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+M_W  Inv [0 0 0 0 0 0 0 0 ] 0
+M_W  Use_Timeout [48899 48844 48947 48738 48779 48792 49018 48503 ] 390520
+
+MM  Load [1 5 5 6 2 5 6 8 ] 38
+MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM  Store [2 3 0 0 5 2 4 2 ] 18
+MM  L1_Replacement [26757 26584 26606 26784 26695 26157 26545 26353 ] 212481
+MM  Fwd_GETX [83 81 70 82 66 79 77 90 ] 628
+MM  Fwd_GETS [111 150 166 150 140 152 151 119 ] 1139
+MM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+
+MM_W  Load [2 0 0 1 0 2 3 2 ] 10
+MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_W  Store [0 0 0 0 0 1 1 1 ] 3
+MM_W  L1_Replacement [474321 476437 474914 473259 476351 470916 474836 474286 ] 3795320
+MM_W  Own_GETX [0 0 0 0 0 0 0 0 ] 0
+MM_W  Fwd_GETX [277 263 253 325 258 298 260 324 ] 2258
+MM_W  Fwd_GETS [433 584 636 513 599 487 588 526 ] 4366
+MM_W  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+MM_W  Inv [0 0 0 0 0 0 0 0 ] 0
+MM_W  Use_Timeout [26949 26811 26838 27015 26900 26387 26768 26559 ] 214227
+
+IM  Load [0 0 0 0 0 0 0 0 ] 0
+IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM  Store [0 0 0 0 0 0 0 0 ] 0
+IM  L1_Replacement [8548786 8600158 8554391 8485164 8597672 8451758 8490064 8620969 ] 68348962
+IM  Inv [0 0 0 0 0 0 0 0 ] 0
+IM  Ack [364 390 361 361 352 342 355 342 ] 2867
+IM  Data [0 0 0 0 0 0 0 0 ] 0
+IM  Exclusive_Data [26949 26808 26837 27015 26900 26387 26768 26559 ] 214223
+
+SM  Load [0 0 0 0 0 0 0 0 ] 0
+SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM  Store [0 0 0 0 0 0 0 0 ] 0
+SM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+SM  Inv [0 0 0 0 0 0 0 0 ] 0
+SM  Ack [0 0 0 0 0 0 0 0 ] 0
+SM  Data [0 0 0 0 0 0 0 0 ] 0
+SM  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+
+OM  Load [0 0 0 0 0 0 0 0 ] 0
+OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OM  Store [0 0 0 0 0 0 0 0 ] 0
+OM  L1_Replacement [1257 1218 1142 1028 1412 1197 1328 1241 ] 9823
+OM  Own_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Fwd_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+OM  Ack [2 3 2 1 2 0 4 5 ] 19
+OM  All_acks [26949 26808 26837 27015 26900 26387 26768 26559 ] 214223
+
+IS  Load [0 0 0 0 0 0 0 0 ] 0
+IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS  Store [0 0 0 0 0 0 0 0 ] 0
+IS  L1_Replacement [15772239 15730747 15762083 15833920 15734022 15891810 15822003 15742231 ] 126289055
+IS  Inv [0 0 0 0 0 0 0 0 ] 0
+IS  Data [885 804 773 840 755 816 783 833 ] 6489
+IS  Exclusive_Data [48900 48847 48948 48738 48779 48792 49018 48503 ] 390525
+
+SI  Load [0 0 0 0 0 0 0 0 ] 0
+SI  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SI  Store [0 0 0 0 0 0 0 0 ] 0
+SI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SI  Fwd_GETS [0 2 0 2 0 2 2 1 ] 9
+SI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+SI  Inv [1 1 3 3 1 1 3 1 ] 14
+SI  Writeback_Ack [410 345 330 421 326 383 381 390 ] 2986
+SI  Writeback_Ack_Data [473 456 437 416 427 431 398 442 ] 3480
+SI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+
+OI  Load [0 0 0 0 0 0 0 0 ] 0
+OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OI  Store [0 0 0 0 0 0 0 0 ] 0
+OI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+OI  Fwd_GETX [1 0 2 0 1 1 1 0 ] 6
+OI  Fwd_GETS [0 0 1 0 4 1 0 3 ] 9
+OI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+OI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+OI  Writeback_Ack_Data [507 539 513 496 543 518 542 555 ] 4213
+OI  Writeback_Nack [57 57 62 54 50 57 48 49 ] 434
+
+MI  Load [0 0 0 0 0 0 0 0 ] 0
+MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MI  Store [0 0 0 0 0 0 0 0 ] 0
+MI  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+MI  Fwd_GETX [102 109 110 127 114 101 113 102 ] 878
+MI  Fwd_GETS [238 247 238 231 247 231 239 263 ] 1934
+MI  Fwd_DMA [0 0 0 0 0 0 0 0 ] 0
+MI  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+MI  Writeback_Ack_Data [74857 74628 74741 74709 74649 74159 74734 74048 ] 596525
+MI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+
+II  Load [0 0 0 0 0 0 0 0 ] 0
+II  Ifetch [0 0 0 0 0 0 0 0 ] 0
+II  Store [0 0 0 0 0 0 0 0 ] 0
+II  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+II  Inv [0 0 0 0 0 0 0 0 ] 0
+II  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+II  Writeback_Ack_Data [103 109 111 127 115 102 113 102 ] 882
+II  Writeback_Nack [1 1 4 3 1 1 4 1 ] 16
+
+Cache Stats: system.l1_cntrl1.L1IcacheMemory
+  system.l1_cntrl1.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl1.L1DcacheMemory
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl2.L1IcacheMemory
+  system.l1_cntrl2.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl2.L1DcacheMemory
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl3.L1IcacheMemory
+  system.l1_cntrl3.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl3.L1DcacheMemory
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl4.L1IcacheMemory
+  system.l1_cntrl4.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl4.L1DcacheMemory
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl5.L1IcacheMemory
+  system.l1_cntrl5.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl5.L1DcacheMemory
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl6.L1IcacheMemory
+  system.l1_cntrl6.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl6.L1DcacheMemory
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl7.L1IcacheMemory
+  system.l1_cntrl7.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl7.L1DcacheMemory
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 0
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+  system.l2_cntrl0.L2cacheMemory_total_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0
+  system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+
+ --- L2Cache ---
+ - Event Counts -
+L1_GETS [581619 ] 581619
+L1_GETX [313703 ] 313703
+L1_PUTO [3513 ] 3513
+L1_PUTX [605149 ] 605149
+L1_PUTS_only [8496 ] 8496
+L1_PUTS [95 ] 95
+Fwd_GETX [0 ] 0
+Fwd_GETS [0 ] 0
+Fwd_DMA [0 ] 0
+Own_GETX [0 ] 0
+Inv [0 ] 0
+IntAck [0 ] 0
+ExtAck [0 ] 0
+All_Acks [210583 ] 210583
+Data [212773 ] 212773
+Data_Exclusive [387955 ] 387955
+L1_WBCLEANDATA [390475 ] 390475
+L1_WBDIRTYDATA [213743 ] 213743
+Writeback_Ack [598522 ] 598522
+Writeback_Nack [0 ] 0
+Unblock [10357 ] 10357
+Exclusive_Unblock [604747 ] 604747
+DmaAck [0 ] 0
+L2_Replacement [602108 ] 602108
+
+ - Transitions -
+NP  L1_GETS [390158 ] 390158
+NP  L1_GETX [210572 ] 210572
+NP  L1_PUTO [0 ] 0
+NP  L1_PUTX [0 ] 0
+NP  L1_PUTS [0 ] 0
+NP  Inv [0 ] 0
+
+I  L1_GETS [0 ] 0
+I  L1_GETX [0 ] 0
+I  L1_PUTO [0 ] 0
+I  L1_PUTX [0 ] 0
+I  L1_PUTS [0 ] 0
+I  Inv [0 ] 0
+I  L2_Replacement [0 ] 0
+
+ILS  L1_GETS [32 ] 32
+ILS  L1_GETX [15 ] 15
+ILS  L1_PUTO [0 ] 0
+ILS  L1_PUTX [0 ] 0
+ILS  L1_PUTS_only [3444 ] 3444
+ILS  L1_PUTS [36 ] 36
+ILS  Inv [0 ] 0
+ILS  L2_Replacement [0 ] 0
+
+ILX  L1_GETS [5363 ] 5363
+ILX  L1_GETX [2852 ] 2852
+ILX  L1_PUTO [2 ] 2
+ILX  L1_PUTX [597406 ] 597406
+ILX  L1_PUTS_only [0 ] 0
+ILX  L1_PUTS [14 ] 14
+ILX  Fwd_GETX [0 ] 0
+ILX  Fwd_GETS [0 ] 0
+ILX  Fwd_DMA [0 ] 0
+ILX  Inv [0 ] 0
+ILX  Data [0 ] 0
+ILX  L2_Replacement [0 ] 0
+
+ILO  L1_GETS [0 ] 0
+ILO  L1_GETX [0 ] 0
+ILO  L1_PUTO [0 ] 0
+ILO  L1_PUTX [0 ] 0
+ILO  L1_PUTS [0 ] 0
+ILO  Fwd_GETX [0 ] 0
+ILO  Fwd_GETS [0 ] 0
+ILO  Fwd_DMA [0 ] 0
+ILO  Inv [0 ] 0
+ILO  Data [0 ] 0
+ILO  L2_Replacement [0 ] 0
+
+ILOX  L1_GETS [5 ] 5
+ILOX  L1_GETX [7 ] 7
+ILOX  L1_PUTO [1625 ] 1625
+ILOX  L1_PUTX [434 ] 434
+ILOX  L1_PUTS [0 ] 0
+ILOX  Fwd_GETX [0 ] 0
+ILOX  Fwd_GETS [0 ] 0
+ILOX  Fwd_DMA [0 ] 0
+ILOX  Data [0 ] 0
+
+ILOS  L1_GETS [0 ] 0
+ILOS  L1_GETX [0 ] 0
+ILOS  L1_PUTO [0 ] 0
+ILOS  L1_PUTX [0 ] 0
+ILOS  L1_PUTS_only [0 ] 0
+ILOS  L1_PUTS [0 ] 0
+ILOS  Fwd_GETX [0 ] 0
+ILOS  Fwd_GETS [0 ] 0
+ILOS  Fwd_DMA [0 ] 0
+ILOS  Data [0 ] 0
+ILOS  L2_Replacement [0 ] 0
+
+ILOSX  L1_GETS [20 ] 20
+ILOSX  L1_GETX [4 ] 4
+ILOSX  L1_PUTO [1092 ] 1092
+ILOSX  L1_PUTX [1497 ] 1497
+ILOSX  L1_PUTS_only [1637 ] 1637
+ILOSX  L1_PUTS [11 ] 11
+ILOSX  Fwd_GETX [0 ] 0
+ILOSX  Fwd_GETS [0 ] 0
+ILOSX  Fwd_DMA [0 ] 0
+ILOSX  Data [0 ] 0
+
+S  L1_GETS [13 ] 13
+S  L1_GETX [7 ] 7
+S  L1_PUTX [0 ] 0
+S  L1_PUTS [0 ] 0
+S  Inv [0 ] 0
+S  L2_Replacement [3444 ] 3444
+
+O  L1_GETS [0 ] 0
+O  L1_GETX [0 ] 0
+O  L1_PUTX [0 ] 0
+O  Fwd_GETX [0 ] 0
+O  Fwd_GETS [0 ] 0
+O  Fwd_DMA [0 ] 0
+O  L2_Replacement [0 ] 0
+
+OLS  L1_GETS [0 ] 0
+OLS  L1_GETX [0 ] 0
+OLS  L1_PUTX [0 ] 0
+OLS  L1_PUTS_only [0 ] 0
+OLS  L1_PUTS [0 ] 0
+OLS  Fwd_GETX [0 ] 0
+OLS  Fwd_GETS [0 ] 0
+OLS  Fwd_DMA [0 ] 0
+OLS  L2_Replacement [0 ] 0
+
+OLSX  L1_GETS [5 ] 5
+OLSX  L1_GETX [4 ] 4
+OLSX  L1_PUTO [0 ] 0
+OLSX  L1_PUTX [0 ] 0
+OLSX  L1_PUTS_only [1307 ] 1307
+OLSX  L1_PUTS [10 ] 10
+OLSX  Fwd_GETX [0 ] 0
+OLSX  Fwd_GETS [0 ] 0
+OLSX  Fwd_DMA [0 ] 0
+OLSX  L2_Replacement [1277 ] 1277
+
+SLS  L1_GETS [0 ] 0
+SLS  L1_GETX [0 ] 0
+SLS  L1_PUTX [0 ] 0
+SLS  L1_PUTS_only [21 ] 21
+SLS  L1_PUTS [0 ] 0
+SLS  Inv [0 ] 0
+SLS  L2_Replacement [28 ] 28
+
+M  L1_GETS [1431 ] 1431
+M  L1_GETX [773 ] 773
+M  L1_PUTO [0 ] 0
+M  L1_PUTX [0 ] 0
+M  L1_PUTS [0 ] 0
+M  Fwd_GETX [0 ] 0
+M  Fwd_GETS [0 ] 0
+M  Fwd_DMA [0 ] 0
+M  L2_Replacement [597246 ] 597246
+
+IFGX  L1_GETS [0 ] 0
+IFGX  L1_GETX [0 ] 0
+IFGX  L1_PUTO [0 ] 0
+IFGX  L1_PUTX [0 ] 0
+IFGX  L1_PUTS_only [0 ] 0
+IFGX  L1_PUTS [0 ] 0
+IFGX  Fwd_GETX [0 ] 0
+IFGX  Fwd_GETS [0 ] 0
+IFGX  Fwd_DMA [0 ] 0
+IFGX  Inv [0 ] 0
+IFGX  Data [0 ] 0
+IFGX  Data_Exclusive [0 ] 0
+IFGX  L2_Replacement [0 ] 0
+
+IFGS  L1_GETS [0 ] 0
+IFGS  L1_GETX [0 ] 0
+IFGS  L1_PUTO [0 ] 0
+IFGS  L1_PUTX [0 ] 0
+IFGS  L1_PUTS_only [0 ] 0
+IFGS  L1_PUTS [0 ] 0
+IFGS  Fwd_GETX [0 ] 0
+IFGS  Fwd_GETS [0 ] 0
+IFGS  Fwd_DMA [0 ] 0
+IFGS  Inv [0 ] 0
+IFGS  Data [0 ] 0
+IFGS  Data_Exclusive [0 ] 0
+IFGS  L2_Replacement [0 ] 0
+
+ISFGS  L1_GETS [0 ] 0
+ISFGS  L1_GETX [0 ] 0
+ISFGS  L1_PUTO [0 ] 0
+ISFGS  L1_PUTX [0 ] 0
+ISFGS  L1_PUTS_only [0 ] 0
+ISFGS  L1_PUTS [0 ] 0
+ISFGS  Fwd_GETX [0 ] 0
+ISFGS  Fwd_GETS [0 ] 0
+ISFGS  Fwd_DMA [0 ] 0
+ISFGS  Inv [0 ] 0
+ISFGS  Data [0 ] 0
+ISFGS  L2_Replacement [0 ] 0
+
+IFGXX  L1_GETS [0 ] 0
+IFGXX  L1_GETX [0 ] 0
+IFGXX  L1_PUTO [0 ] 0
+IFGXX  L1_PUTX [0 ] 0
+IFGXX  L1_PUTS_only [0 ] 0
+IFGXX  L1_PUTS [0 ] 0
+IFGXX  Fwd_GETX [0 ] 0
+IFGXX  Fwd_GETS [0 ] 0
+IFGXX  Fwd_DMA [0 ] 0
+IFGXX  Inv [0 ] 0
+IFGXX  IntAck [0 ] 0
+IFGXX  All_Acks [0 ] 0
+IFGXX  Data_Exclusive [0 ] 0
+IFGXX  L2_Replacement [0 ] 0
+
+OFGX  L1_GETS [0 ] 0
+OFGX  L1_GETX [0 ] 0
+OFGX  L1_PUTO [0 ] 0
+OFGX  L1_PUTX [0 ] 0
+OFGX  L1_PUTS_only [0 ] 0
+OFGX  L1_PUTS [0 ] 0
+OFGX  Fwd_GETX [0 ] 0
+OFGX  Fwd_GETS [0 ] 0
+OFGX  Fwd_DMA [0 ] 0
+OFGX  Inv [0 ] 0
+OFGX  L2_Replacement [0 ] 0
+
+OLSF  L1_GETS [0 ] 0
+OLSF  L1_GETX [0 ] 0
+OLSF  L1_PUTO [0 ] 0
+OLSF  L1_PUTX [0 ] 0
+OLSF  L1_PUTS_only [0 ] 0
+OLSF  L1_PUTS [0 ] 0
+OLSF  Fwd_GETX [0 ] 0
+OLSF  Fwd_GETS [0 ] 0
+OLSF  Fwd_DMA [0 ] 0
+OLSF  Inv [0 ] 0
+OLSF  IntAck [0 ] 0
+OLSF  All_Acks [0 ] 0
+OLSF  L2_Replacement [0 ] 0
+
+ILOW  L1_GETS [0 ] 0
+ILOW  L1_GETX [0 ] 0
+ILOW  L1_PUTO [0 ] 0
+ILOW  L1_PUTX [0 ] 0
+ILOW  L1_PUTS_only [0 ] 0
+ILOW  L1_PUTS [0 ] 0
+ILOW  Fwd_GETX [0 ] 0
+ILOW  Fwd_GETS [0 ] 0
+ILOW  Fwd_DMA [0 ] 0
+ILOW  Inv [0 ] 0
+ILOW  L1_WBCLEANDATA [0 ] 0
+ILOW  L1_WBDIRTYDATA [0 ] 0
+ILOW  Unblock [0 ] 0
+ILOW  L2_Replacement [0 ] 0
+
+ILOXW  L1_GETS [4 ] 4
+ILOXW  L1_GETX [13 ] 13
+ILOXW  L1_PUTO [306 ] 306
+ILOXW  L1_PUTX [953 ] 953
+ILOXW  L1_PUTS_only [0 ] 0
+ILOXW  L1_PUTS [0 ] 0
+ILOXW  Fwd_GETX [0 ] 0
+ILOXW  Fwd_GETS [0 ] 0
+ILOXW  Fwd_DMA [0 ] 0
+ILOXW  Inv [0 ] 0
+ILOXW  L1_WBCLEANDATA [1440 ] 1440
+ILOXW  L1_WBDIRTYDATA [185 ] 185
+ILOXW  Unblock [1637 ] 1637
+ILOXW  L2_Replacement [0 ] 0
+
+ILOSW  L1_GETS [0 ] 0
+ILOSW  L1_GETX [0 ] 0
+ILOSW  L1_PUTO [0 ] 0
+ILOSW  L1_PUTX [0 ] 0
+ILOSW  L1_PUTS_only [0 ] 0
+ILOSW  L1_PUTS [0 ] 0
+ILOSW  Fwd_GETX [0 ] 0
+ILOSW  Fwd_GETS [0 ] 0
+ILOSW  Fwd_DMA [0 ] 0
+ILOSW  Inv [0 ] 0
+ILOSW  L1_WBCLEANDATA [0 ] 0
+ILOSW  L1_WBDIRTYDATA [0 ] 0
+ILOSW  Unblock [0 ] 0
+ILOSW  L2_Replacement [0 ] 0
+
+ILOSXW  L1_GETS [4 ] 4
+ILOSXW  L1_GETX [9 ] 9
+ILOSXW  L1_PUTO [0 ] 0
+ILOSXW  L1_PUTX [6 ] 6
+ILOSXW  L1_PUTS_only [931 ] 931
+ILOSXW  L1_PUTS [7 ] 7
+ILOSXW  Fwd_GETX [0 ] 0
+ILOSXW  Fwd_GETS [0 ] 0
+ILOSXW  Fwd_DMA [0 ] 0
+ILOSXW  Inv [0 ] 0
+ILOSXW  L1_WBCLEANDATA [2033 ] 2033
+ILOSXW  L1_WBDIRTYDATA [555 ] 555
+ILOSXW  Unblock [12 ] 12
+ILOSXW  L2_Replacement [0 ] 0
+
+SLSW  L1_GETS [0 ] 0
+SLSW  L1_GETX [0 ] 0
+SLSW  L1_PUTO [0 ] 0
+SLSW  L1_PUTX [0 ] 0
+SLSW  L1_PUTS_only [0 ] 0
+SLSW  L1_PUTS [0 ] 0
+SLSW  Fwd_GETX [0 ] 0
+SLSW  Fwd_GETS [0 ] 0
+SLSW  Fwd_DMA [0 ] 0
+SLSW  Inv [0 ] 0
+SLSW  Unblock [0 ] 0
+SLSW  L2_Replacement [0 ] 0
+
+OLSW  L1_GETS [0 ] 0
+OLSW  L1_GETX [0 ] 0
+OLSW  L1_PUTO [0 ] 0
+OLSW  L1_PUTX [0 ] 0
+OLSW  L1_PUTS_only [0 ] 0
+OLSW  L1_PUTS [0 ] 0
+OLSW  Fwd_GETX [0 ] 0
+OLSW  Fwd_GETS [0 ] 0
+OLSW  Fwd_DMA [0 ] 0
+OLSW  Inv [0 ] 0
+OLSW  Unblock [0 ] 0
+OLSW  L2_Replacement [0 ] 0
+
+ILSW  L1_GETS [0 ] 0
+ILSW  L1_GETX [0 ] 0
+ILSW  L1_PUTO [0 ] 0
+ILSW  L1_PUTX [0 ] 0
+ILSW  L1_PUTS_only [0 ] 0
+ILSW  L1_PUTS [11 ] 11
+ILSW  Fwd_GETX [0 ] 0
+ILSW  Fwd_GETS [0 ] 0
+ILSW  Fwd_DMA [0 ] 0
+ILSW  Inv [0 ] 0
+ILSW  L1_WBCLEANDATA [36 ] 36
+ILSW  Unblock [0 ] 0
+ILSW  L2_Replacement [0 ] 0
+
+IW  L1_GETS [8 ] 8
+IW  L1_GETX [0 ] 0
+IW  L1_PUTO [0 ] 0
+IW  L1_PUTX [0 ] 0
+IW  L1_PUTS_only [0 ] 0
+IW  L1_PUTS [0 ] 0
+IW  Fwd_GETX [0 ] 0
+IW  Fwd_GETS [0 ] 0
+IW  Fwd_DMA [0 ] 0
+IW  Inv [0 ] 0
+IW  L1_WBCLEANDATA [3444 ] 3444
+IW  L2_Replacement [0 ] 0
+
+OW  L1_GETS [0 ] 0
+OW  L1_GETX [0 ] 0
+OW  L1_PUTO [0 ] 0
+OW  L1_PUTX [0 ] 0
+OW  L1_PUTS_only [0 ] 0
+OW  L1_PUTS [0 ] 0
+OW  Fwd_GETX [0 ] 0
+OW  Fwd_GETS [0 ] 0
+OW  Fwd_DMA [0 ] 0
+OW  Inv [0 ] 0
+OW  Unblock [0 ] 0
+OW  L2_Replacement [0 ] 0
+
+SW  L1_GETS [0 ] 0
+SW  L1_GETX [0 ] 0
+SW  L1_PUTO [0 ] 0
+SW  L1_PUTX [0 ] 0
+SW  L1_PUTS_only [0 ] 0
+SW  L1_PUTS [0 ] 0
+SW  Fwd_GETX [0 ] 0
+SW  Fwd_GETS [0 ] 0
+SW  Fwd_DMA [0 ] 0
+SW  Inv [0 ] 0
+SW  Unblock [21 ] 21
+SW  L2_Replacement [1 ] 1
+
+OXW  L1_GETS [2 ] 2
+OXW  L1_GETX [6 ] 6
+OXW  L1_PUTO [0 ] 0
+OXW  L1_PUTX [0 ] 0
+OXW  L1_PUTS_only [0 ] 0
+OXW  L1_PUTS [0 ] 0
+OXW  Fwd_GETX [0 ] 0
+OXW  Fwd_GETS [0 ] 0
+OXW  Fwd_DMA [0 ] 0
+OXW  Inv [0 ] 0
+OXW  Unblock [1307 ] 1307
+OXW  L2_Replacement [99 ] 99
+
+OLSXW  L1_GETS [0 ] 0
+OLSXW  L1_GETX [0 ] 0
+OLSXW  L1_PUTO [0 ] 0
+OLSXW  L1_PUTX [0 ] 0
+OLSXW  L1_PUTS_only [0 ] 0
+OLSXW  L1_PUTS [0 ] 0
+OLSXW  Fwd_GETX [0 ] 0
+OLSXW  Fwd_GETS [0 ] 0
+OLSXW  Fwd_DMA [0 ] 0
+OLSXW  Inv [0 ] 0
+OLSXW  Unblock [10 ] 10
+OLSXW  L2_Replacement [0 ] 0
+
+ILXW  L1_GETS [97 ] 97
+ILXW  L1_GETX [62 ] 62
+ILXW  L1_PUTO [0 ] 0
+ILXW  L1_PUTX [0 ] 0
+ILXW  L1_PUTS_only [0 ] 0
+ILXW  L1_PUTS [0 ] 0
+ILXW  Fwd_GETX [0 ] 0
+ILXW  Fwd_GETS [0 ] 0
+ILXW  Fwd_DMA [0 ] 0
+ILXW  Inv [0 ] 0
+ILXW  Data [0 ] 0
+ILXW  L1_WBCLEANDATA [383522 ] 383522
+ILXW  L1_WBDIRTYDATA [213003 ] 213003
+ILXW  Unblock [881 ] 881
+ILXW  L2_Replacement [0 ] 0
+
+IFLS  L1_GETS [0 ] 0
+IFLS  L1_GETX [0 ] 0
+IFLS  L1_PUTO [0 ] 0
+IFLS  L1_PUTX [0 ] 0
+IFLS  L1_PUTS_only [27 ] 27
+IFLS  L1_PUTS [0 ] 0
+IFLS  Fwd_GETX [0 ] 0
+IFLS  Fwd_GETS [0 ] 0
+IFLS  Fwd_DMA [0 ] 0
+IFLS  Inv [0 ] 0
+IFLS  Unblock [32 ] 32
+IFLS  L2_Replacement [0 ] 0
+
+IFLO  L1_GETS [0 ] 0
+IFLO  L1_GETX [0 ] 0
+IFLO  L1_PUTO [0 ] 0
+IFLO  L1_PUTX [0 ] 0
+IFLO  L1_PUTS_only [0 ] 0
+IFLO  L1_PUTS [0 ] 0
+IFLO  Fwd_GETX [0 ] 0
+IFLO  Fwd_GETS [0 ] 0
+IFLO  Fwd_DMA [0 ] 0
+IFLO  Inv [0 ] 0
+IFLO  Unblock [0 ] 0
+IFLO  L2_Replacement [0 ] 0
+
+IFLOX  L1_GETS [0 ] 0
+IFLOX  L1_GETX [0 ] 0
+IFLOX  L1_PUTO [2 ] 2
+IFLOX  L1_PUTX [3 ] 3
+IFLOX  L1_PUTS_only [7 ] 7
+IFLOX  L1_PUTS [0 ] 0
+IFLOX  Fwd_GETX [0 ] 0
+IFLOX  Fwd_GETS [0 ] 0
+IFLOX  Fwd_DMA [0 ] 0
+IFLOX  Inv [0 ] 0
+IFLOX  Unblock [5 ] 5
+IFLOX  Exclusive_Unblock [4 ] 4
+IFLOX  L2_Replacement [0 ] 0
+
+IFLOXX  L1_GETS [166 ] 166
+IFLOXX  L1_GETX [118 ] 118
+IFLOXX  L1_PUTO [481 ] 481
+IFLOXX  L1_PUTX [4826 ] 4826
+IFLOXX  L1_PUTS_only [0 ] 0
+IFLOXX  L1_PUTS [3 ] 3
+IFLOXX  Fwd_GETX [0 ] 0
+IFLOXX  Fwd_GETS [0 ] 0
+IFLOXX  Fwd_DMA [0 ] 0
+IFLOXX  Inv [0 ] 0
+IFLOXX  Unblock [4224 ] 4224
+IFLOXX  Exclusive_Unblock [3998 ] 3998
+IFLOXX  L2_Replacement [0 ] 0
+
+IFLOSX  L1_GETS [0 ] 0
+IFLOSX  L1_GETX [0 ] 0
+IFLOSX  L1_PUTO [5 ] 5
+IFLOSX  L1_PUTX [15 ] 15
+IFLOSX  L1_PUTS_only [6 ] 6
+IFLOSX  L1_PUTS [0 ] 0
+IFLOSX  Fwd_GETX [0 ] 0
+IFLOSX  Fwd_GETS [0 ] 0
+IFLOSX  Fwd_DMA [0 ] 0
+IFLOSX  Inv [0 ] 0
+IFLOSX  Unblock [20 ] 20
+IFLOSX  Exclusive_Unblock [0 ] 0
+IFLOSX  L2_Replacement [0 ] 0
+
+IFLXO  L1_GETS [0 ] 0
+IFLXO  L1_GETX [0 ] 0
+IFLXO  L1_PUTO [0 ] 0
+IFLXO  L1_PUTX [9 ] 9
+IFLXO  L1_PUTS_only [3 ] 3
+IFLXO  L1_PUTS [0 ] 0
+IFLXO  Fwd_GETX [0 ] 0
+IFLXO  Fwd_GETS [0 ] 0
+IFLXO  Fwd_DMA [0 ] 0
+IFLXO  Inv [0 ] 0
+IFLXO  Exclusive_Unblock [4 ] 4
+IFLXO  L2_Replacement [0 ] 0
+
+IGS  L1_GETS [119216 ] 119216
+IGS  L1_GETX [64381 ] 64381
+IGS  L1_PUTO [0 ] 0
+IGS  L1_PUTX [0 ] 0
+IGS  L1_PUTS_only [0 ] 0
+IGS  L1_PUTS [0 ] 0
+IGS  Fwd_GETX [0 ] 0
+IGS  Fwd_GETS [0 ] 0
+IGS  Fwd_DMA [0 ] 0
+IGS  Own_GETX [0 ] 0
+IGS  Inv [0 ] 0
+IGS  Data [2190 ] 2190
+IGS  Data_Exclusive [387955 ] 387955
+IGS  Unblock [2190 ] 2190
+IGS  Exclusive_Unblock [387954 ] 387954
+IGS  L2_Replacement [0 ] 0
+
+IGM  L1_GETS [62835 ] 62835
+IGM  L1_GETX [33663 ] 33663
+IGM  L1_PUTO [0 ] 0
+IGM  L1_PUTX [0 ] 0
+IGM  L1_PUTS_only [0 ] 0
+IGM  L1_PUTS [0 ] 0
+IGM  Fwd_GETX [0 ] 0
+IGM  Fwd_GETS [0 ] 0
+IGM  Fwd_DMA [0 ] 0
+IGM  Own_GETX [0 ] 0
+IGM  Inv [0 ] 0
+IGM  ExtAck [0 ] 0
+IGM  Data [210568 ] 210568
+IGM  Data_Exclusive [0 ] 0
+IGM  L2_Replacement [0 ] 0
+
+IGMLS  L1_GETS [0 ] 0
+IGMLS  L1_GETX [0 ] 0
+IGMLS  L1_PUTO [0 ] 0
+IGMLS  L1_PUTX [0 ] 0
+IGMLS  L1_PUTS_only [1022 ] 1022
+IGMLS  L1_PUTS [0 ] 0
+IGMLS  Inv [0 ] 0
+IGMLS  IntAck [0 ] 0
+IGMLS  ExtAck [0 ] 0
+IGMLS  All_Acks [0 ] 0
+IGMLS  Data [15 ] 15
+IGMLS  Data_Exclusive [0 ] 0
+IGMLS  L2_Replacement [0 ] 0
+
+IGMO  L1_GETS [2045 ] 2045
+IGMO  L1_GETX [1079 ] 1079
+IGMO  L1_PUTO [0 ] 0
+IGMO  L1_PUTX [0 ] 0
+IGMO  L1_PUTS_only [27 ] 27
+IGMO  L1_PUTS [0 ] 0
+IGMO  Fwd_GETX [0 ] 0
+IGMO  Fwd_GETS [0 ] 0
+IGMO  Fwd_DMA [0 ] 0
+IGMO  Own_GETX [0 ] 0
+IGMO  ExtAck [0 ] 0
+IGMO  All_Acks [210583 ] 210583
+IGMO  Exclusive_Unblock [210583 ] 210583
+IGMO  L2_Replacement [0 ] 0
+
+IGMIO  L1_GETS [0 ] 0
+IGMIO  L1_GETX [0 ] 0
+IGMIO  L1_PUTO [0 ] 0
+IGMIO  L1_PUTX [0 ] 0
+IGMIO  L1_PUTS_only [0 ] 0
+IGMIO  L1_PUTS [0 ] 0
+IGMIO  Fwd_GETX [0 ] 0
+IGMIO  Fwd_GETS [0 ] 0
+IGMIO  Fwd_DMA [0 ] 0
+IGMIO  Own_GETX [0 ] 0
+IGMIO  ExtAck [0 ] 0
+IGMIO  All_Acks [0 ] 0
+
+OGMIO  L1_GETS [0 ] 0
+OGMIO  L1_GETX [0 ] 0
+OGMIO  L1_PUTO [0 ] 0
+OGMIO  L1_PUTX [0 ] 0
+OGMIO  L1_PUTS_only [0 ] 0
+OGMIO  L1_PUTS [0 ] 0
+OGMIO  Fwd_GETX [0 ] 0
+OGMIO  Fwd_GETS [0 ] 0
+OGMIO  Fwd_DMA [0 ] 0
+OGMIO  Own_GETX [0 ] 0
+OGMIO  ExtAck [0 ] 0
+OGMIO  All_Acks [0 ] 0
+
+IGMIOF  L1_GETS [0 ] 0
+IGMIOF  L1_GETX [0 ] 0
+IGMIOF  L1_PUTO [0 ] 0
+IGMIOF  L1_PUTX [0 ] 0
+IGMIOF  L1_PUTS_only [0 ] 0
+IGMIOF  L1_PUTS [0 ] 0
+IGMIOF  IntAck [0 ] 0
+IGMIOF  All_Acks [0 ] 0
+IGMIOF  Data_Exclusive [0 ] 0
+
+IGMIOFS  L1_GETS [0 ] 0
+IGMIOFS  L1_GETX [0 ] 0
+IGMIOFS  L1_PUTO [0 ] 0
+IGMIOFS  L1_PUTX [0 ] 0
+IGMIOFS  L1_PUTS_only [0 ] 0
+IGMIOFS  L1_PUTS [0 ] 0
+IGMIOFS  Fwd_GETX [0 ] 0
+IGMIOFS  Fwd_GETS [0 ] 0
+IGMIOFS  Fwd_DMA [0 ] 0
+IGMIOFS  Inv [0 ] 0
+IGMIOFS  Data [0 ] 0
+IGMIOFS  L2_Replacement [0 ] 0
+
+OGMIOF  L1_GETS [0 ] 0
+OGMIOF  L1_GETX [0 ] 0
+OGMIOF  L1_PUTO [0 ] 0
+OGMIOF  L1_PUTX [0 ] 0
+OGMIOF  L1_PUTS_only [0 ] 0
+OGMIOF  L1_PUTS [0 ] 0
+OGMIOF  IntAck [0 ] 0
+OGMIOF  All_Acks [0 ] 0
+
+II  L1_GETS [0 ] 0
+II  L1_GETX [0 ] 0
+II  L1_PUTO [0 ] 0
+II  L1_PUTX [0 ] 0
+II  L1_PUTS_only [0 ] 0
+II  L1_PUTS [0 ] 0
+II  IntAck [0 ] 0
+II  All_Acks [0 ] 0
+
+MM  L1_GETS [2 ] 2
+MM  L1_GETX [0 ] 0
+MM  L1_PUTO [0 ] 0
+MM  L1_PUTX [0 ] 0
+MM  L1_PUTS_only [0 ] 0
+MM  L1_PUTS [0 ] 0
+MM  Fwd_GETX [0 ] 0
+MM  Fwd_GETS [0 ] 0
+MM  Fwd_DMA [0 ] 0
+MM  Inv [0 ] 0
+MM  Exclusive_Unblock [773 ] 773
+MM  L2_Replacement [0 ] 0
+
+SS  L1_GETS [0 ] 0
+SS  L1_GETX [0 ] 0
+SS  L1_PUTO [0 ] 0
+SS  L1_PUTX [0 ] 0
+SS  L1_PUTS_only [0 ] 0
+SS  L1_PUTS [0 ] 0
+SS  Fwd_GETX [0 ] 0
+SS  Fwd_GETS [0 ] 0
+SS  Fwd_DMA [0 ] 0
+SS  Inv [0 ] 0
+SS  Unblock [13 ] 13
+SS  L2_Replacement [0 ] 0
+
+OO  L1_GETS [1 ] 1
+OO  L1_GETX [1 ] 1
+OO  L1_PUTO [0 ] 0
+OO  L1_PUTX [0 ] 0
+OO  L1_PUTS_only [0 ] 0
+OO  L1_PUTS [0 ] 0
+OO  Fwd_GETX [0 ] 0
+OO  Fwd_GETS [0 ] 0
+OO  Fwd_DMA [0 ] 0
+OO  Inv [0 ] 0
+OO  Unblock [0 ] 0
+OO  Exclusive_Unblock [1431 ] 1431
+OO  L2_Replacement [13 ] 13
+
+OLSS  L1_GETS [0 ] 0
+OLSS  L1_GETX [0 ] 0
+OLSS  L1_PUTO [0 ] 0
+OLSS  L1_PUTX [0 ] 0
+OLSS  L1_PUTS_only [0 ] 0
+OLSS  L1_PUTS [0 ] 0
+OLSS  Fwd_GETX [0 ] 0
+OLSS  Fwd_GETS [0 ] 0
+OLSS  Fwd_DMA [0 ] 0
+OLSS  Inv [0 ] 0
+OLSS  Unblock [0 ] 0
+OLSS  L2_Replacement [0 ] 0
+
+OLSXS  L1_GETS [0 ] 0
+OLSXS  L1_GETX [0 ] 0
+OLSXS  L1_PUTO [0 ] 0
+OLSXS  L1_PUTX [0 ] 0
+OLSXS  L1_PUTS_only [0 ] 0
+OLSXS  L1_PUTS [0 ] 0
+OLSXS  Fwd_GETX [0 ] 0
+OLSXS  Fwd_GETS [0 ] 0
+OLSXS  Fwd_DMA [0 ] 0
+OLSXS  Inv [0 ] 0
+OLSXS  Unblock [5 ] 5
+OLSXS  L2_Replacement [0 ] 0
+
+SLSS  L1_GETS [0 ] 0
+SLSS  L1_GETX [0 ] 0
+SLSS  L1_PUTO [0 ] 0
+SLSS  L1_PUTX [0 ] 0
+SLSS  L1_PUTS_only [0 ] 0
+SLSS  L1_PUTS [0 ] 0
+SLSS  Fwd_GETX [0 ] 0
+SLSS  Fwd_GETS [0 ] 0
+SLSS  Fwd_DMA [0 ] 0
+SLSS  Inv [0 ] 0
+SLSS  Unblock [0 ] 0
+SLSS  L2_Replacement [0 ] 0
+
+OI  L1_GETS [0 ] 0
+OI  L1_GETX [0 ] 0
+OI  L1_PUTO [0 ] 0
+OI  L1_PUTX [0 ] 0
+OI  L1_PUTS_only [0 ] 0
+OI  L1_PUTS [0 ] 0
+OI  Fwd_GETX [0 ] 0
+OI  Fwd_GETS [0 ] 0
+OI  Fwd_DMA [0 ] 0
+OI  Writeback_Ack [0 ] 0
+OI  Writeback_Nack [0 ] 0
+OI  L2_Replacement [0 ] 0
+
+MI  L1_GETS [212 ] 212
+MI  L1_GETX [137 ] 137
+MI  L1_PUTO [0 ] 0
+MI  L1_PUTX [0 ] 0
+MI  L1_PUTS_only [0 ] 0
+MI  L1_PUTS [0 ] 0
+MI  Fwd_GETX [0 ] 0
+MI  Fwd_GETS [0 ] 0
+MI  Fwd_DMA [0 ] 0
+MI  Writeback_Ack [597245 ] 597245
+MI  L2_Replacement [0 ] 0
+
+MII  L1_GETS [0 ] 0
+MII  L1_GETX [0 ] 0
+MII  L1_PUTO [0 ] 0
+MII  L1_PUTX [0 ] 0
+MII  L1_PUTS_only [0 ] 0
+MII  L1_PUTS [0 ] 0
+MII  Writeback_Ack [0 ] 0
+MII  Writeback_Nack [0 ] 0
+MII  L2_Replacement [0 ] 0
+
+OLSI  L1_GETS [0 ] 0
+OLSI  L1_GETX [0 ] 0
+OLSI  L1_PUTO [0 ] 0
+OLSI  L1_PUTX [0 ] 0
+OLSI  L1_PUTS_only [64 ] 64
+OLSI  L1_PUTS [3 ] 3
+OLSI  Fwd_GETX [0 ] 0
+OLSI  Fwd_GETS [0 ] 0
+OLSI  Fwd_DMA [0 ] 0
+OLSI  Writeback_Ack [1277 ] 1277
+OLSI  L2_Replacement [0 ] 0
+
+ILSI  L1_GETS [0 ] 0
+ILSI  L1_GETX [0 ] 0
+ILSI  L1_PUTO [0 ] 0
+ILSI  L1_PUTX [0 ] 0
+ILSI  L1_PUTS_only [0 ] 0
+ILSI  L1_PUTS [0 ] 0
+ILSI  IntAck [0 ] 0
+ILSI  All_Acks [0 ] 0
+ILSI  Writeback_Ack [0 ] 0
+ILSI  L2_Replacement [0 ] 0
+
+ILOSD  L1_GETS [0 ] 0
+ILOSD  L1_GETX [0 ] 0
+ILOSD  L1_PUTO [0 ] 0
+ILOSD  L1_PUTX [0 ] 0
+ILOSD  L1_PUTS_only [0 ] 0
+ILOSD  L1_PUTS [0 ] 0
+ILOSD  Fwd_GETX [0 ] 0
+ILOSD  Fwd_GETS [0 ] 0
+ILOSD  Fwd_DMA [0 ] 0
+ILOSD  Own_GETX [0 ] 0
+ILOSD  Inv [0 ] 0
+ILOSD  DmaAck [0 ] 0
+ILOSD  L2_Replacement [0 ] 0
+
+ILOSXD  L1_GETS [0 ] 0
+ILOSXD  L1_GETX [0 ] 0
+ILOSXD  L1_PUTO [0 ] 0
+ILOSXD  L1_PUTX [0 ] 0
+ILOSXD  L1_PUTS_only [0 ] 0
+ILOSXD  L1_PUTS [0 ] 0
+ILOSXD  Fwd_GETX [0 ] 0
+ILOSXD  Fwd_GETS [0 ] 0
+ILOSXD  Fwd_DMA [0 ] 0
+ILOSXD  Own_GETX [0 ] 0
+ILOSXD  Inv [0 ] 0
+ILOSXD  DmaAck [0 ] 0
+ILOSXD  L2_Replacement [0 ] 0
+
+ILOD  L1_GETS [0 ] 0
+ILOD  L1_GETX [0 ] 0
+ILOD  L1_PUTO [0 ] 0
+ILOD  L1_PUTX [0 ] 0
+ILOD  L1_PUTS_only [0 ] 0
+ILOD  L1_PUTS [0 ] 0
+ILOD  Fwd_GETX [0 ] 0
+ILOD  Fwd_GETS [0 ] 0
+ILOD  Fwd_DMA [0 ] 0
+ILOD  Own_GETX [0 ] 0
+ILOD  Inv [0 ] 0
+ILOD  DmaAck [0 ] 0
+ILOD  L2_Replacement [0 ] 0
+
+ILXD  L1_GETS [0 ] 0
+ILXD  L1_GETX [0 ] 0
+ILXD  L1_PUTO [0 ] 0
+ILXD  L1_PUTX [0 ] 0
+ILXD  L1_PUTS_only [0 ] 0
+ILXD  L1_PUTS [0 ] 0
+ILXD  Fwd_GETX [0 ] 0
+ILXD  Fwd_GETS [0 ] 0
+ILXD  Fwd_DMA [0 ] 0
+ILXD  Own_GETX [0 ] 0
+ILXD  Inv [0 ] 0
+ILXD  DmaAck [0 ] 0
+ILXD  L2_Replacement [0 ] 0
+
+ILOXD  L1_GETS [0 ] 0
+ILOXD  L1_GETX [0 ] 0
+ILOXD  L1_PUTO [0 ] 0
+ILOXD  L1_PUTX [0 ] 0
+ILOXD  L1_PUTS_only [0 ] 0
+ILOXD  L1_PUTS [0 ] 0
+ILOXD  Fwd_GETX [0 ] 0
+ILOXD  Fwd_GETS [0 ] 0
+ILOXD  Fwd_DMA [0 ] 0
+ILOXD  Own_GETX [0 ] 0
+ILOXD  Inv [0 ] 0
+ILOXD  DmaAck [0 ] 0
+ILOXD  L2_Replacement [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 813693
+  memory_reads: 600734
+  memory_writes: 212933
+  memory_refreshes: 40419
+  memory_total_request_delays: 49780084
+  memory_delays_per_request: 61.178
+  memory_delays_in_input_queue: 345220
+  memory_delays_behind_head_of_bank_queue: 20547755
+  memory_delays_stalled_at_head_of_bank_queue: 28887109
+  memory_stalls_for_bank_busy: 4445044
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 6975038
+  memory_stalls_for_arbitration: 5947339
+  memory_stalls_for_bus: 8079080
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 2057549
+  memory_stalls_for_read_read_turnaround: 1383059
+  accesses_per_bank: 25590  25284  25425  25632  25643  25601  25766  25487  25702  25434  25459  25612  25246  25282  25451  25306  25312  25409  25456  25347  25503  25348  25473  25274  25313  24958  25440  24937  25294  25533  25671  25505  
+
+ --- Directory ---
+ - Event Counts -
+GETX [210594 ] 210594
+GETS [390158 ] 390158
+PUTX [597246 ] 597246
+PUTO [0 ] 0
+PUTO_SHARERS [1277 ] 1277
+Unblock [0 ] 0
+Last_Unblock [2190 ] 2190
+Exclusive_Unblock [598537 ] 598537
+Clean_Writeback [385581 ] 385581
+Dirty_Writeback [212941 ] 212941
+Memory_Data [600728 ] 600728
+Memory_Ack [212933 ] 212933
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+DMA_ACK [0 ] 0
+Data [0 ] 0
+
+ - Transitions -
+I  GETX [209329 ] 209329
+I  GETS [387968 ] 387968
+I  PUTX [0 ] 0
+I  PUTO [0 ] 0
+I  Memory_Data [0 ] 0
+I  Memory_Ack [209560 ] 209560
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+S  GETX [1265 ] 1265
+S  GETS [2190 ] 2190
+S  PUTX [0 ] 0
+S  PUTO [0 ] 0
+S  Memory_Data [0 ] 0
+S  Memory_Ack [234 ] 234
+S  DMA_READ [0 ] 0
+S  DMA_WRITE [0 ] 0
+
+O  GETX [0 ] 0
+O  GETS [0 ] 0
+O  PUTX [0 ] 0
+O  PUTO [0 ] 0
+O  PUTO_SHARERS [0 ] 0
+O  Memory_Data [0 ] 0
+O  Memory_Ack [0 ] 0
+O  DMA_READ [0 ] 0
+O  DMA_WRITE [0 ] 0
+
+M  GETX [0 ] 0
+M  GETS [0 ] 0
+M  PUTX [597246 ] 597246
+M  PUTO [0 ] 0
+M  PUTO_SHARERS [1277 ] 1277
+M  Memory_Data [0 ] 0
+M  Memory_Ack [0 ] 0
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+
+IS  GETX [0 ] 0
+IS  GETS [0 ] 0
+IS  PUTX [0 ] 0
+IS  PUTO [0 ] 0
+IS  PUTO_SHARERS [0 ] 0
+IS  Unblock [0 ] 0
+IS  Exclusive_Unblock [387954 ] 387954
+IS  Memory_Data [387955 ] 387955
+IS  Memory_Ack [2021 ] 2021
+IS  DMA_READ [0 ] 0
+IS  DMA_WRITE [0 ] 0
+
+SS  GETX [0 ] 0
+SS  GETS [0 ] 0
+SS  PUTX [0 ] 0
+SS  PUTO [0 ] 0
+SS  PUTO_SHARERS [0 ] 0
+SS  Unblock [0 ] 0
+SS  Last_Unblock [2190 ] 2190
+SS  Memory_Data [2190 ] 2190
+SS  Memory_Ack [2 ] 2
+SS  DMA_READ [0 ] 0
+SS  DMA_WRITE [0 ] 0
+
+OO  GETX [0 ] 0
+OO  GETS [0 ] 0
+OO  PUTX [0 ] 0
+OO  PUTO [0 ] 0
+OO  PUTO_SHARERS [0 ] 0
+OO  Unblock [0 ] 0
+OO  Last_Unblock [0 ] 0
+OO  Memory_Data [0 ] 0
+OO  Memory_Ack [0 ] 0
+OO  DMA_READ [0 ] 0
+OO  DMA_WRITE [0 ] 0
+
+MO  GETX [0 ] 0
+MO  GETS [0 ] 0
+MO  PUTX [0 ] 0
+MO  PUTO [0 ] 0
+MO  PUTO_SHARERS [0 ] 0
+MO  Unblock [0 ] 0
+MO  Exclusive_Unblock [0 ] 0
+MO  Memory_Data [0 ] 0
+MO  Memory_Ack [0 ] 0
+MO  DMA_READ [0 ] 0
+MO  DMA_WRITE [0 ] 0
+
+MM  GETX [0 ] 0
+MM  GETS [0 ] 0
+MM  PUTX [0 ] 0
+MM  PUTO [0 ] 0
+MM  PUTO_SHARERS [0 ] 0
+MM  Exclusive_Unblock [210583 ] 210583
+MM  Memory_Data [210583 ] 210583
+MM  Memory_Ack [1116 ] 1116
+MM  DMA_READ [0 ] 0
+MM  DMA_WRITE [0 ] 0
+
+
+MI  GETX [0 ] 0
+MI  GETS [0 ] 0
+MI  PUTX [0 ] 0
+MI  PUTO [0 ] 0
+MI  PUTO_SHARERS [0 ] 0
+MI  Unblock [0 ] 0
+MI  Clean_Writeback [384541 ] 384541
+MI  Dirty_Writeback [212704 ] 212704
+MI  Memory_Data [0 ] 0
+MI  Memory_Ack [0 ] 0
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+
+MIS  GETX [0 ] 0
+MIS  GETS [0 ] 0
+MIS  PUTX [0 ] 0
+MIS  PUTO [0 ] 0
+MIS  PUTO_SHARERS [0 ] 0
+MIS  Unblock [0 ] 0
+MIS  Clean_Writeback [1040 ] 1040
+MIS  Dirty_Writeback [237 ] 237
+MIS  Memory_Data [0 ] 0
+MIS  Memory_Ack [0 ] 0
+MIS  DMA_READ [0 ] 0
+MIS  DMA_WRITE [0 ] 0
+
+OS  GETX [0 ] 0
+OS  GETS [0 ] 0
+OS  PUTX [0 ] 0
+OS  PUTO [0 ] 0
+OS  PUTO_SHARERS [0 ] 0
+OS  Unblock [0 ] 0
+OS  Clean_Writeback [0 ] 0
+OS  Dirty_Writeback [0 ] 0
+OS  Memory_Data [0 ] 0
+OS  Memory_Ack [0 ] 0
+OS  DMA_READ [0 ] 0
+OS  DMA_WRITE [0 ] 0
+
+OSS  GETX [0 ] 0
+OSS  GETS [0 ] 0
+OSS  PUTX [0 ] 0
+OSS  PUTO [0 ] 0
+OSS  PUTO_SHARERS [0 ] 0
+OSS  Unblock [0 ] 0
+OSS  Clean_Writeback [0 ] 0
+OSS  Dirty_Writeback [0 ] 0
+OSS  Memory_Data [0 ] 0
+OSS  Memory_Ack [0 ] 0
+OSS  DMA_READ [0 ] 0
+OSS  DMA_WRITE [0 ] 0
+
+XI_M  GETX [0 ] 0
+XI_M  GETS [0 ] 0
+XI_M  PUTX [0 ] 0
+XI_M  PUTO [0 ] 0
+XI_M  PUTO_SHARERS [0 ] 0
+XI_M  Memory_Data [0 ] 0
+XI_M  Memory_Ack [0 ] 0
+XI_M  DMA_READ [0 ] 0
+XI_M  DMA_WRITE [0 ] 0
+
+XI_U  GETX [0 ] 0
+XI_U  GETS [0 ] 0
+XI_U  PUTX [0 ] 0
+XI_U  PUTO [0 ] 0
+XI_U  PUTO_SHARERS [0 ] 0
+XI_U  Exclusive_Unblock [0 ] 0
+XI_U  Memory_Ack [0 ] 0
+XI_U  DMA_READ [0 ] 0
+XI_U  DMA_WRITE [0 ] 0
+
+OI_D  GETX [0 ] 0
+OI_D  GETS [0 ] 0
+OI_D  PUTX [0 ] 0
+OI_D  PUTO [0 ] 0
+OI_D  PUTO_SHARERS [0 ] 0
+OI_D  DMA_READ [0 ] 0
+OI_D  DMA_WRITE [0 ] 0
+OI_D  Data [0 ] 0
+
+OD  GETX [0 ] 0
+OD  GETS [0 ] 0
+OD  PUTX [0 ] 0
+OD  PUTO [0 ] 0
+OD  PUTO_SHARERS [0 ] 0
+OD  DMA_READ [0 ] 0
+OD  DMA_WRITE [0 ] 0
+OD  DMA_ACK [0 ] 0
+
+MD  GETX [0 ] 0
+MD  GETS [0 ] 0
+MD  PUTX [0 ] 0
+MD  PUTO [0 ] 0
+MD  PUTO_SHARERS [0 ] 0
+MD  DMA_READ [0 ] 0
+MD  DMA_WRITE [0 ] 0
+MD  DMA_ACK [0 ] 0
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
new file mode 100755
index 000000000..5229c9187
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr
@@ -0,0 +1,74 @@
+system.cpu1: completed 10000 read, 5302 write accesses @1928146
+system.cpu4: completed 10000 read, 5365 write accesses @1942166
+system.cpu7: completed 10000 read, 5319 write accesses @1965207
+system.cpu3: completed 10000 read, 5359 write accesses @1968836
+system.cpu0: completed 10000 read, 5498 write accesses @1974677
+system.cpu2: completed 10000 read, 5513 write accesses @1977476
+system.cpu6: completed 10000 read, 5448 write accesses @1980956
+system.cpu5: completed 10000 read, 5483 write accesses @1995684
+system.cpu4: completed 20000 read, 10717 write accesses @3830467
+system.cpu1: completed 20000 read, 10577 write accesses @3871337
+system.cpu7: completed 20000 read, 10556 write accesses @3902287
+system.cpu5: completed 20000 read, 10901 write accesses @3923395
+system.cpu0: completed 20000 read, 10861 write accesses @3926315
+system.cpu2: completed 20000 read, 10674 write accesses @3934695
+system.cpu6: completed 20000 read, 10925 write accesses @3939046
+system.cpu3: completed 20000 read, 10752 write accesses @3981115
+system.cpu4: completed 30000 read, 16128 write accesses @5754566
+system.cpu7: completed 30000 read, 16027 write accesses @5841539
+system.cpu5: completed 30000 read, 16312 write accesses @5857206
+system.cpu2: completed 30000 read, 16104 write accesses @5869696
+system.cpu1: completed 30000 read, 16084 write accesses @5872577
+system.cpu0: completed 30000 read, 16133 write accesses @5895696
+system.cpu6: completed 30000 read, 16259 write accesses @5909016
+system.cpu3: completed 30000 read, 16253 write accesses @5970997
+system.cpu4: completed 40000 read, 21443 write accesses @7732298
+system.cpu7: completed 40000 read, 21518 write accesses @7817106
+system.cpu0: completed 40000 read, 21561 write accesses @7817675
+system.cpu2: completed 40000 read, 21432 write accesses @7822846
+system.cpu1: completed 40000 read, 21383 write accesses @7845525
+system.cpu5: completed 40000 read, 21816 write accesses @7858096
+system.cpu6: completed 40000 read, 21672 write accesses @7885486
+system.cpu3: completed 40000 read, 21581 write accesses @7941597
+system.cpu4: completed 50000 read, 26787 write accesses @9651285
+system.cpu7: completed 50000 read, 26989 write accesses @9793686
+system.cpu0: completed 50000 read, 26994 write accesses @9797807
+system.cpu2: completed 50000 read, 26921 write accesses @9830875
+system.cpu5: completed 50000 read, 27153 write accesses @9839316
+system.cpu6: completed 50000 read, 27189 write accesses @9858608
+system.cpu1: completed 50000 read, 26834 write accesses @9863587
+system.cpu3: completed 50000 read, 27039 write accesses @9921406
+system.cpu4: completed 60000 read, 32175 write accesses @11605575
+system.cpu2: completed 60000 read, 32358 write accesses @11729986
+system.cpu0: completed 60000 read, 32424 write accesses @11735436
+system.cpu7: completed 60000 read, 32432 write accesses @11778007
+system.cpu6: completed 60000 read, 32473 write accesses @11788255
+system.cpu5: completed 60000 read, 32623 write accesses @11789575
+system.cpu1: completed 60000 read, 32116 write accesses @11821356
+system.cpu3: completed 60000 read, 32229 write accesses @11884826
+system.cpu4: completed 70000 read, 37533 write accesses @13546365
+system.cpu0: completed 70000 read, 37907 write accesses @13701646
+system.cpu2: completed 70000 read, 37745 write accesses @13708257
+system.cpu6: completed 70000 read, 37768 write accesses @13710576
+system.cpu7: completed 70000 read, 37843 write accesses @13719776
+system.cpu5: completed 70000 read, 37934 write accesses @13770505
+system.cpu1: completed 70000 read, 37322 write accesses @13773596
+system.cpu3: completed 70000 read, 37575 write accesses @13859246
+system.cpu4: completed 80000 read, 42663 write accesses @15468226
+system.cpu6: completed 80000 read, 43059 write accesses @15617186
+system.cpu7: completed 80000 read, 43185 write accesses @15635279
+system.cpu0: completed 80000 read, 43129 write accesses @15668486
+system.cpu2: completed 80000 read, 43262 write accesses @15680656
+system.cpu1: completed 80000 read, 42658 write accesses @15703946
+system.cpu5: completed 80000 read, 43215 write accesses @15712586
+system.cpu3: completed 80000 read, 42991 write accesses @15858096
+system.cpu4: completed 90000 read, 48047 write accesses @17468576
+system.cpu2: completed 90000 read, 48557 write accesses @17581105
+system.cpu7: completed 90000 read, 48648 write accesses @17584296
+system.cpu6: completed 90000 read, 48515 write accesses @17584397
+system.cpu1: completed 90000 read, 48024 write accesses @17672186
+system.cpu0: completed 90000 read, 48750 write accesses @17683641
+system.cpu5: completed 90000 read, 48534 write accesses @17695277
+system.cpu3: completed 90000 read, 48496 write accesses @17843215
+system.cpu4: completed 100000 read, 53558 write accesses @19400856
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
new file mode 100755
index 000000000..b246a2d4a
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:47:36
+gem5 started Jan 23 2012 04:22:12
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 19400856 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
new file mode 100644
index 000000000..ec3afa4a7
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -0,0 +1,47 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.019401                       # Number of seconds simulated
+sim_ticks                                    19400856                       # Number of ticks simulated
+final_tick                                   19400856                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                  83409                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 348008                       # Number of bytes of host memory used
+host_seconds                                   232.60                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.cpu0.num_reads                           98844                       # number of read accesses completed
+system.cpu0.num_writes                          53478                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           98643                       # number of read accesses completed
+system.cpu1.num_writes                          52679                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           99369                       # number of read accesses completed
+system.cpu2.num_writes                          53574                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           97889                       # number of read accesses completed
+system.cpu3.num_writes                          52711                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                          100000                       # number of read accesses completed
+system.cpu4.num_writes                          53558                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                           98762                       # number of read accesses completed
+system.cpu5.num_writes                          53328                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           99308                       # number of read accesses completed
+system.cpu6.num_writes                          53445                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           99141                       # number of read accesses completed
+system.cpu7.num_writes                          53490                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
new file mode 100644
index 000000000..84c75eb68
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -0,0 +1,963 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby sys_port_proxy
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
+
+[system.cpu0]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.l1_cntrl0.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.l1_cntrl1.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.l1_cntrl2.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.l1_cntrl3.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.l1_cntrl4.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.l1_cntrl5.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.l1_cntrl6.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.l1_cntrl7.sequencer.port[0]
+
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+cntrl_id=9
+directory=system.dir_cntrl0.directory
+directory_latency=5
+distributed_persistent=true
+fixed_timeout_latency=100
+l2_select_num_bits=0
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=0
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.l1_cntrl1]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=1
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl1.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.l1_cntrl1.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl1.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl1.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=1
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.l1_cntrl2]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=2
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl2.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.l1_cntrl2.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl2.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl2.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=2
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.l1_cntrl3]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=3
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl3.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.l1_cntrl3.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl3.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl3.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=3
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.l1_cntrl4]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=4
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl4.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.l1_cntrl4.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl4.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl4.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=4
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.l1_cntrl5]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=5
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl5.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.l1_cntrl5.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl5.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl5.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=5
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.l1_cntrl6]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=6
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl6.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.l1_cntrl6.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl6.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl6.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=6
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.l1_cntrl7]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=7
+dynamic_timeout_enabled=true
+fixed_timeout_latency=300
+l1_request_latency=2
+l1_response_latency=2
+l2_select_num_bits=0
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+retry_threshold=1
+ruby_system=system.ruby
+sequencer=system.l1_cntrl7.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.l1_cntrl7.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl7.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl7.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=7
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.l2_cntrl0]
+type=L2Cache_Controller
+children=L2cacheMemory
+L2cacheMemory=system.l2_cntrl0.L2cacheMemory
+N_tokens=9
+buffer_size=0
+cntrl_id=8
+filtering_enabled=true
+l2_request_latency=5
+l2_response_latency=5
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.l2_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=network profiler
+block_size_bytes=64
+clock=1
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=false
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=1000
+number_of_virtual_networks=10
+ruby_system=system.ruby
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10
+description=Crossbar
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9
+print_config=false
+routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10
+
+[system.ruby.network.topology.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl0
+int_node=system.ruby.network.topology.routers00
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.topology.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl1
+int_node=system.ruby.network.topology.routers01
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.topology.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl2
+int_node=system.ruby.network.topology.routers02
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.topology.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl3
+int_node=system.ruby.network.topology.routers03
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.topology.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl4
+int_node=system.ruby.network.topology.routers04
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.topology.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl5
+int_node=system.ruby.network.topology.routers05
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.topology.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl6
+int_node=system.ruby.network.topology.routers06
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.topology.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl7
+int_node=system.ruby.network.topology.routers07
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.topology.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l2_cntrl0
+int_node=system.ruby.network.topology.routers08
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.topology.ext_links9]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.dir_cntrl0
+int_node=system.ruby.network.topology.routers09
+latency=1
+link_id=9
+weight=1
+
+[system.ruby.network.topology.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.topology.routers00
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.topology.routers01
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.topology.routers02
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.topology.routers03
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.topology.routers04
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.topology.routers05
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.topology.routers06
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.topology.routers07
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=18
+node_a=system.ruby.network.topology.routers08
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.int_links9]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=19
+node_a=system.ruby.network.topology.routers09
+node_b=system.ruby.network.topology.routers10
+weight=1
+
+[system.ruby.network.topology.routers00]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers01]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers02]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers03]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers04]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers05]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers06]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers07]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers08]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers09]
+type=BasicRouter
+router_id=9
+
+[system.ruby.network.topology.routers10]
+type=BasicRouter
+router_id=10
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
new file mode 100644
index 000000000..5b7a6fff2
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -0,0 +1,1403 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 1
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, ordered
+virtual_net_1: active, unordered
+virtual_net_2: active, unordered
+virtual_net_3: active, ordered
+virtual_net_4: active, unordered
+virtual_net_5: active, ordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/23/2012 04:24:27
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 120
+Elapsed_time_in_minutes: 2
+Elapsed_time_in_hours: 0.0333333
+Elapsed_time_in_days: 0.00138889
+
+Virtual_time_in_seconds: 119.35
+Virtual_time_in_minutes: 1.98917
+Virtual_time_in_hours:   0.0331528
+Virtual_time_in_days:    0.00138137
+
+Ruby_current_time: 19658320
+Ruby_start_time: 0
+Ruby_cycles: 19658320
+
+mbytes_resident: 41.6445
+mbytes_total: 339.402
+resident_ratio: 0.1227
+
+ruby_cycles_executed: [ 19658321 19658321 19658321 19658321 19658321 19658321 19658321 19658321 ]
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
+
+L2Cache-0:0  
+Directory-0:0  
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615732 average: 15.9984 | standard deviation: 0.126922 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615612 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 128 max: 18520 count: 615604 average: 4086.79 | standard deviation: 2944.53 | 596 6466 13264 14393 14238 17364 19534 19886 17213 15228 16326 15266 13085 12364 11235 10730 9475 9043 9065 7719 7748 7559 7862 7157 6552 7013 7074 6670 6771 6341 6912 6682 6584 6902 6301 6596 6654 7004 6743 6175 6952 7090 6725 6856 6582 7347 7091 7151 7379 6597 7114 7104 7285 7020 6346 6929 7026 6665 6372 5841 6151 5725 5614 5684 4803 4921 4577 4608 4096 3343 3553 3445 3118 2793 2470 2458 2157 1968 1839 1509 1491 1372 1275 1092 889 849 861 678 630 504 509 471 398 313 303 221 231 191 167 128 129 109 96 89 84 52 62 53 45 29 26 20 18 23 14 13 16 6 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 18520 count: 399925 average: 4085.78 | standard deviation: 2943.7 | 411 4241 8744 9371 9204 11299 12636 12913 11096 9899 10485 9918 8546 8048 7413 6933 6133 5806 5894 5034 5021 4872 5059 4679 4204 4555 4577 4358 4446 4076 4496 4395 4244 4508 4111 4303 4337 4576 4392 4020 4619 4630 4439 4337 4254 4804 4601 4590 4875 4227 4658 4573 4693 4557 4183 4441 4623 4325 4101 3776 4035 3686 3683 3683 3151 3218 2947 2959 2688 2200 2281 2233 2025 1848 1629 1589 1388 1243 1160 970 972 871 848 711 556 548 549 449 405 310 346 306 262 198 204 135 149 121 104 87 86 72 63 58 50 38 42 37 28 20 18 15 13 15 9 6 10 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 17820 count: 215679 average: 4088.66 | standard deviation: 2946.1 | 185 2225 4520 5022 5034 6065 6898 6973 6117 5329 5841 5348 4539 4316 3822 3797 3342 3237 3171 2685 2727 2687 2803 2478 2348 2458 2497 2312 2325 2265 2416 2287 2340 2394 2190 2293 2317 2428 2351 2155 2333 2460 2286 2519 2328 2543 2490 2561 2504 2370 2456 2531 2592 2463 2163 2488 2403 2340 2271 2065 2116 2039 1931 2001 1652 1703 1630 1649 1408 1143 1272 1212 1093 945 841 869 769 725 679 539 519 501 427 381 333 301 312 229 225 194 163 165 136 115 99 86 82 70 63 41 43 37 33 31 34 14 20 16 17 9 8 5 5 8 5 7 6 4 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 131 average:     2 | standard deviation: 0 | 0 0 131 ]
+miss_latency_L2Cache: [binsize: 128 max: 14875 count: 3746 average: 4024.34 | standard deviation: 3007.93 | 204 55 53 50 42 111 96 107 106 79 69 84 62 70 71 76 59 59 55 55 58 40 43 38 30 44 37 43 40 53 30 50 48 39 29 37 48 40 46 46 43 40 28 35 34 39 49 48 51 43 34 37 48 27 33 46 34 50 49 30 39 41 26 40 24 29 21 28 21 31 25 22 18 19 12 31 12 10 13 4 10 8 7 2 5 14 4 4 0 5 1 3 2 0 0 4 1 2 0 1 2 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 18520 count: 608513 average: 4090.49 | standard deviation: 2943.6 | 1 6328 13141 14257 14115 17140 19369 19675 17048 15093 16201 15110 12979 12234 11111 10605 9373 8948 8977 7617 7656 7477 7782 7092 6496 6928 6991 6601 6695 6251 6849 6600 6501 6828 6238 6511 6574 6914 6666 6091 6877 7011 6655 6787 6509 7277 7011 7063 7302 6516 7046 7036 7198 6971 6282 6863 6968 6580 6295 5779 6080 5663 5553 5625 4758 4866 4542 4559 4058 3292 3511 3409 3088 2765 2450 2423 2138 1954 1818 1495 1479 1357 1264 1084 879 829 853 671 630 497 506 467 396 312 301 217 229 189 166 127 126 108 95 89 83 52 59 53 44 28 26 20 18 23 14 13 15 5 7 4 4 2 4 5 2 9 0 1 1 1 1 3 0 0 1 2 1 1 1 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 128 max: 15052 count: 3214 average: 3625.44 | standard deviation: 2955.6 | 260 83 70 86 81 113 69 104 59 56 56 72 44 60 53 49 43 36 33 47 34 42 37 27 26 41 46 26 36 37 33 32 35 35 34 48 32 50 31 38 32 39 42 34 39 31 31 40 26 38 34 31 39 22 31 20 24 35 28 32 32 21 35 19 21 26 14 21 17 20 17 14 12 9 8 4 7 4 8 10 2 7 4 6 5 6 4 3 0 2 2 1 0 1 2 0 1 0 1 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 3214
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_first_response_to_completion: [binsize: 4 max: 559 count: 7 average:   349 | standard deviation: 173.877 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 608506
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 86 average:     2 | standard deviation: 0 | 0 0 86 ]
+miss_latency_LD_L2Cache: [binsize: 128 max: 14875 count: 2363 average: 3952.27 | standard deviation: 3021.97 | 138 36 38 38 21 71 69 68 68 51 47 56 34 47 47 50 35 39 35 34 38 21 26 23 18 22 23 28 23 30 17 34 30 26 12 16 26 34 31 31 28 25 23 30 23 23 29 25 31 27 17 21 34 13 22 28 18 31 27 21 21 20 18 26 15 20 11 15 13 22 18 12 14 13 6 13 7 7 8 4 7 7 7 1 3 8 2 2 0 2 1 2 2 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 128 max: 18520 count: 395348 average: 4090.03 | standard deviation: 2942.49 | 0 4146 8658 9278 9133 11157 12522 12773 10991 9808 10400 9813 8481 7963 7331 6853 6072 5743 5837 4969 4966 4821 5007 4640 4165 4510 4530 4311 4405 4020 4459 4342 4193 4458 4075 4256 4288 4508 4339 3960 4567 4580 4387 4287 4204 4758 4553 4542 4825 4173 4616 4533 4635 4531 4144 4401 4590 4272 4051 3734 3993 3654 3641 3648 3123 3177 2928 2929 2667 2166 2255 2210 2001 1827 1620 1572 1377 1232 1146 961 963 859 838 707 549 536 544 445 405 306 343 303 260 197 202 134 147 120 103 86 84 72 62 58 49 38 40 37 27 19 18 15 13 15 9 6 9 2 6 3 2 1 3 5 1 5 0 1 0 1 1 1 0 0 1 2 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 13969 count: 2128 average: 3610.63 | standard deviation: 2983.96 | 187 59 48 55 50 71 45 72 37 40 38 49 31 38 35 30 26 24 22 31 17 30 26 16 21 23 24 19 18 26 20 19 21 24 24 31 23 34 22 29 24 25 29 20 27 23 19 23 19 27 25 19 24 13 17 12 15 22 23 21 21 12 24 9 13 21 8 15 8 12 8 11 10 8 3 4 4 4 6 5 2 5 3 3 4 4 3 2 0 2 2 1 0 1 2 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 45 average:     2 | standard deviation: 0 | 0 0 45 ]
+miss_latency_ST_L2Cache: [binsize: 128 max: 13576 count: 1383 average: 4147.49 | standard deviation: 2980.85 | 66 19 15 12 21 40 27 39 38 28 22 28 28 23 24 26 24 20 20 21 20 19 17 15 12 22 14 15 17 23 13 16 18 13 17 21 22 6 15 15 15 15 5 5 11 16 20 23 20 16 17 16 14 14 11 18 16 19 22 9 18 21 8 14 9 9 10 13 8 9 7 10 4 6 6 18 5 3 5 0 3 1 0 1 2 6 2 2 0 3 0 1 0 0 0 3 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 17820 count: 213165 average: 4091.35 | standard deviation: 2945.66 | 1 2182 4483 4979 4982 5983 6847 6902 6057 5285 5801 5297 4498 4271 3780 3752 3301 3205 3140 2648 2690 2656 2775 2452 2331 2418 2461 2290 2290 2231 2390 2258 2308 2370 2163 2255 2286 2406 2327 2131 2310 2431 2268 2500 2305 2519 2458 2521 2477 2343 2430 2503 2563 2440 2138 2462 2378 2308 2244 2045 2087 2009 1912 1977 1635 1689 1614 1630 1391 1126 1256 1199 1087 938 830 851 761 722 672 534 516 498 426 377 330 293 309 226 225 191 163 164 136 115 99 83 82 69 63 41 42 36 33 31 34 14 19 16 17 9 8 5 5 8 5 7 6 3 1 1 2 1 1 0 1 4 0 0 1 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15052 count: 1086 average: 3654.46 | standard deviation: 2900.39 | 73 24 22 31 31 42 24 32 22 16 18 23 13 22 18 19 17 12 11 16 17 12 11 11 5 18 22 7 18 11 13 13 14 11 10 17 9 16 9 9 8 14 13 14 12 8 12 17 7 11 9 12 15 9 14 8 9 13 5 11 11 9 11 10 8 5 6 6 9 8 9 3 2 1 5 0 3 0 2 5 0 2 1 3 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 119
+system_time: 0
+page_reclaims: 10999
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 208
+
+Network Stats
+-------------
+
+total_msg_count_Request_Control: 3688391 29507128
+total_msg_count_Response_Data: 1832355 131929560
+total_msg_count_ResponseL2hit_Data: 4578 329616
+total_msg_count_ResponseLocal_Data: 6687 481464
+total_msg_count_Response_Control: 5517 44136
+total_msg_count_Writeback_Data: 2490666 179327952
+total_msg_count_Writeback_Control: 1184091 9472728
+total_msg_count_Broadcast_Control: 9232425 73859400
+total_msg_count_Persistent_Control: 8208600 65668800
+total_msgs: 26653310 total_bytes: 490620784
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 3.2394
+  links_utilized_percent_switch_0_link_0: 4.18174 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.29707 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 124 8928 [ 0 0 0 0 124 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_ResponseLocal_Data: 286 20592 [ 0 0 0 0 286 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 226 1808 [ 0 0 0 0 226 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 77037 5546664 [ 0 0 0 0 77037 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Broadcast_Control: 77189 617512 [ 0 77189 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Persistent_Control: 51505 412040 [ 0 0 0 51505 0 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 3.23446
+  links_utilized_percent_switch_1_link_0: 4.17797 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.29095 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 132 9504 [ 0 0 0 0 132 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_ResponseLocal_Data: 292 21024 [ 0 0 0 0 292 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 247 1976 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 76832 5531904 [ 0 0 0 0 76832 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Broadcast_Control: 77017 616136 [ 0 77017 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Persistent_Control: 51141 409128 [ 0 0 0 51141 0 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 3.2337
+  links_utilized_percent_switch_2_link_0: 4.17711 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.29029 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 118 8496 [ 0 0 0 0 118 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_ResponseLocal_Data: 273 19656 [ 0 0 0 0 273 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 240 1920 [ 0 0 0 0 240 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 76800 5529600 [ 0 0 0 0 76800 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Broadcast_Control: 76986 615888 [ 0 76986 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Persistent_Control: 51535 412280 [ 0 0 0 51535 0 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 3.24065
+  links_utilized_percent_switch_3_link_0: 4.18288 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.29842 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 116 8352 [ 0 0 0 0 116 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_ResponseLocal_Data: 296 21312 [ 0 0 0 0 296 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 77093 5550696 [ 0 0 0 0 77093 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Broadcast_Control: 77259 618072 [ 0 77259 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Persistent_Control: 51372 410976 [ 0 0 0 51372 0 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 3.22384
+  links_utilized_percent_switch_4_link_0: 4.1693 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.27838 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 129 9288 [ 0 0 0 0 129 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_ResponseLocal_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 211 1688 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 76442 5503824 [ 0 0 0 0 76442 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Broadcast_Control: 76585 612680 [ 0 76585 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Persistent_Control: 51095 408760 [ 0 0 0 51095 0 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 3.22911
+  links_utilized_percent_switch_5_link_0: 4.17325 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.28497 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 138 9936 [ 0 0 0 0 138 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_ResponseLocal_Data: 274 19728 [ 0 0 0 0 274 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 228 1824 [ 0 0 0 0 228 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 76617 5516424 [ 0 0 0 0 76617 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Broadcast_Control: 76775 614200 [ 0 76775 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Persistent_Control: 51335 410680 [ 0 0 0 51335 0 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 3.22368
+  links_utilized_percent_switch_6_link_0: 4.16935 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.278 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 120 8640 [ 0 0 0 0 120 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_ResponseLocal_Data: 269 19368 [ 0 0 0 0 269 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 239 1912 [ 0 0 0 0 239 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 76419 5502168 [ 0 0 0 0 76419 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Broadcast_Control: 76590 612720 [ 0 76590 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Persistent_Control: 50944 407552 [ 0 0 0 50944 0 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 3.23753
+  links_utilized_percent_switch_7_link_0: 4.18018 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.29487 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 108 7776 [ 0 0 0 0 108 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_ResponseLocal_Data: 298 21456 [ 0 0 0 0 298 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 217 1736 [ 0 0 0 0 217 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 76967 5541624 [ 0 0 0 0 76967 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Broadcast_Control: 77094 616752 [ 0 77094 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Persistent_Control: 51503 412024 [ 0 0 0 51503 0 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 12.1177
+  links_utilized_percent_switch_8_link_0: 16.6607 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 7.57472 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 1306 94032 [ 0 0 0 0 1306 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_ResponseL2hit_Data: 1526 109872 [ 0 0 0 0 1526 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Data: 215997 15551784 [ 0 0 0 0 215997 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 394694 3157552 [ 0 0 0 0 394694 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 2
+switch_9_outlinks: 2
+links_utilized_percent_switch_9: 11.2311
+  links_utilized_percent_switch_9_link_0: 8.53279 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 13.9295 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 613968 4911744 [ 0 0 613968 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 608494 43811568 [ 0 0 0 0 608494 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Data: 18 1296 [ 0 0 0 0 18 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1
+
+switch_10_inlinks: 10
+switch_10_outlinks: 10
+links_utilized_percent_switch_10: 5.75614
+  links_utilized_percent_switch_10_link_0: 4.05074 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_1: 4.0479 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_2: 4.04603 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_3: 4.05221 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_4: 4.03934 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_5: 4.04268 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_6: 4.03978 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_7: 4.04919 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_8: 16.6607 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_10_link_9: 8.53279 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_10_link_0_Response_Data: 76720 5523840 [ 0 0 0 0 76720 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseL2hit_Data: 204 14688 [ 0 0 0 0 204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_ResponseLocal_Data: 259 18648 [ 0 0 0 0 259 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Writeback_Data: 82 5904 [ 0 0 0 0 82 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Broadcast_Control: 538306 4306448 [ 0 538306 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_0_Persistent_Control: 358925 2871400 [ 0 0 0 358925 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Data: 76500 5508000 [ 0 0 0 0 76500 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseL2hit_Data: 196 14112 [ 0 0 0 0 196 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_ResponseLocal_Data: 276 19872 [ 0 0 0 0 276 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Writeback_Data: 109 7848 [ 0 0 0 0 109 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Broadcast_Control: 538478 4307824 [ 0 538478 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_1_Persistent_Control: 359289 2874312 [ 0 0 0 359289 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Response_Data: 76476 5506272 [ 0 0 0 0 76476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseL2hit_Data: 191 13752 [ 0 0 0 0 191 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_ResponseLocal_Data: 247 17784 [ 0 0 0 0 247 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Writeback_Data: 126 9072 [ 0 0 0 0 126 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Broadcast_Control: 538509 4308072 [ 0 538509 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_2_Persistent_Control: 358895 2871160 [ 0 0 0 358895 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Data: 76703 5522616 [ 0 0 0 0 76703 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseL2hit_Data: 171 12312 [ 0 0 0 0 171 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_ResponseLocal_Data: 265 19080 [ 0 0 0 0 265 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Writeback_Data: 183 13176 [ 0 0 0 0 183 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Broadcast_Control: 538236 4305888 [ 0 538236 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_3_Persistent_Control: 359058 2872464 [ 0 0 0 359058 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Data: 75931 5467032 [ 0 0 0 0 75931 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseL2hit_Data: 211 15192 [ 0 0 0 0 211 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_ResponseLocal_Data: 287 20664 [ 0 0 0 0 287 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Writeback_Data: 225 16200 [ 0 0 0 0 225 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Broadcast_Control: 538910 4311280 [ 0 538910 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_4_Persistent_Control: 359335 2874680 [ 0 0 0 359335 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Response_Data: 76128 5481216 [ 0 0 0 0 76128 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseL2hit_Data: 184 13248 [ 0 0 0 0 184 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_ResponseLocal_Data: 305 21960 [ 0 0 0 0 305 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Writeback_Data: 231 16632 [ 0 0 0 0 231 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Broadcast_Control: 538720 4309760 [ 0 538720 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_5_Persistent_Control: 359095 2872760 [ 0 0 0 359095 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Data: 75904 5465088 [ 0 0 0 0 75904 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseL2hit_Data: 201 14472 [ 0 0 0 0 201 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_ResponseLocal_Data: 289 20808 [ 0 0 0 0 289 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Writeback_Data: 263 18936 [ 0 0 0 0 263 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Broadcast_Control: 538905 4311240 [ 0 538905 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_6_Persistent_Control: 359486 2875888 [ 0 0 0 359486 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Data: 76423 5502456 [ 0 0 0 0 76423 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseL2hit_Data: 168 12096 [ 0 0 0 0 168 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_ResponseLocal_Data: 301 21672 [ 0 0 0 0 301 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Writeback_Data: 294 21168 [ 0 0 0 0 294 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Broadcast_Control: 538401 4307208 [ 0 538401 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_7_Persistent_Control: 358927 2871416 [ 0 0 0 358927 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Request_Control: 615495 4923960 [ 0 615495 0 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Response_Control: 1833 14664 [ 0 0 0 0 1833 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Writeback_Data: 613630 44181360 [ 0 0 0 0 613630 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_8_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Request_Control: 613969 4911752 [ 0 0 613969 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Data: 215079 15485688 [ 0 0 0 0 215079 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Writeback_Control: 394695 3157560 [ 0 0 0 0 394695 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_10_link_9_Persistent_Control: 410430 3283440 [ 0 0 0 410430 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 77189
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 77189
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.1557%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.8443%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   77189    100%
+
+ --- L1Cache ---
+ - Event Counts -
+Load [49690 49997 49629 50054 50303 50190 50006 50073 ] 399942
+Ifetch [0 0 0 0 0 0 0 0 ] 0
+Store [26905 26796 26976 27053 26903 26845 27007 27200 ] 215685
+Atomic [0 0 0 0 0 0 0 0 ] 0
+L1_Replacement [1281089 1281955 1281461 1287176 1288071 1285927 1285387 1289906 ] 10280972
+Data_Shared [262 248 238 231 241 229 241 222 ] 1912
+Data_Owner [57 66 67 68 67 47 58 64 ] 494
+Data_All_Tokens [76335 76534 76352 76887 76957 76805 76741 77036 ] 613647
+Ack [1 0 1 1 0 1 0 1 ] 5
+Ack_All_Tokens [0 0 0 1 0 0 0 1 ] 2
+Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+Transient_Local_GETX [188736 188850 188667 188589 188743 188802 188643 188443 ] 1509473
+Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+Transient_Local_GETS [350173 349869 350237 349812 349562 349676 349865 349793 ] 2798987
+Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
+Persistent_GETX [63290 63349 63338 63218 63414 63370 63215 63283 ] 506477
+Persistent_GETS [117375 117192 117390 117254 117011 117217 117177 117246 ] 937862
+Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
+Own_Lock_or_Unlock [229765 229889 229702 229958 230005 229843 230037 229901 ] 1839100
+Request_Timeout [490512 494638 490301 490311 493060 493644 493295 485817 ] 3931578
+Use_TimeoutStarverX [6 4 5 6 0 3 4 9 ] 37
+Use_TimeoutStarverS [12 18 9 7 5 3 13 9 ] 76
+Use_TimeoutNoStarvers [76249 76442 76272 76789 76882 76734 76675 76961 ] 613004
+Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
+
+ - Transitions -
+NP  Load [49577 49883 49528 49948 50192 50080 49879 49958 ] 399045
+NP  Ifetch [0 0 0 0 0 0 0 0 ] 0
+NP  Store [26838 26735 26909 27000 26843 26777 26936 27143 ] 215181
+NP  Atomic [0 0 0 0 0 0 0 0 ] 0
+NP  Data_Shared [0 0 0 1 0 0 0 0 ] 1
+NP  Data_Owner [4 4 5 8 9 1 8 8 ] 47
+NP  Data_All_Tokens [68 70 66 85 68 64 49 57 ] 527
+NP  Ack [0 0 0 1 0 0 0 1 ] 2
+NP  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+NP  Transient_Local_GETX [188060 188135 187942 187878 188024 188099 187945 187729 ] 1503812
+NP  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+NP  Transient_Local_GETS [348916 348636 348950 348528 348293 348374 348601 348501 ] 2788799
+NP  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+NP  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+NP  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+NP  Own_Lock_or_Unlock [199095 199187 199157 199216 199244 199357 199305 199312 ] 1593873
+
+I  Load [0 0 0 0 0 0 0 0 ] 0
+I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I  Store [0 0 1 0 0 0 0 1 ] 2
+I  Atomic [0 0 0 0 0 0 0 0 ] 0
+I  L1_Replacement [211 228 237 217 226 247 239 226 ] 1831
+I  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+I  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+I  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+I  Ack [0 0 0 0 0 0 0 0 ] 0
+I  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+I  Transient_Local_GETX [2 1 0 0 0 0 0 0 ] 3
+I  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+I  Transient_Local_GETS [2 0 0 2 0 1 1 1 ] 7
+I  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+I  Persistent_GETS [0 1 0 0 0 0 1 0 ] 2
+I  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+
+S  Load [0 0 0 0 0 0 0 0 ] 0
+S  Ifetch [0 0 0 0 0 0 0 0 ] 0
+S  Store [0 0 0 0 0 0 0 0 ] 0
+S  Atomic [0 0 0 0 0 0 0 0 ] 0
+S  L1_Replacement [319 311 290 284 299 283 290 272 ] 2348
+S  Data_Shared [0 0 0 0 0 1 0 1 ] 2
+S  Data_Owner [0 1 0 0 0 0 0 0 ] 1
+S  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+S  Ack [0 0 0 0 0 0 0 0 ] 0
+S  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+S  Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
+S  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+S  Transient_Local_GETS [1 0 0 0 0 0 0 0 ] 1
+S  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+S  Transient_Local_GETS_Last_Token [1 1 1 0 1 0 1 0 ] 5
+S  Persistent_GETX [0 0 1 0 0 0 0 0 ] 1
+S  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+S  Persistent_GETS_Last_Token [0 0 0 0 0 0 1 0 ] 1
+S  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+
+O  Load [0 0 0 0 0 0 0 0 ] 0
+O  Ifetch [0 0 0 0 0 0 0 0 ] 0
+O  Store [0 0 0 0 0 0 0 0 ] 0
+O  Atomic [0 0 0 0 0 0 0 0 ] 0
+O  L1_Replacement [153 182 161 192 182 167 153 188 ] 1378
+O  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+O  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+O  Ack [0 0 0 0 0 0 0 0 ] 0
+O  Ack_All_Tokens [0 0 0 0 0 0 0 1 ] 1
+O  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+O  Transient_Local_GETX [0 0 0 0 0 0 0 1 ] 1
+O  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+O  Transient_Local_GETS [1 0 0 2 0 0 0 0 ] 3
+O  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+O  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+O  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+O  Persistent_GETS [0 0 0 0 2 1 0 0 ] 3
+O  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+O  Own_Lock_or_Unlock [16 16 25 18 18 10 18 19 ] 140
+
+M  Load [4 7 7 7 6 6 8 8 ] 53
+M  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M  Store [2 2 1 1 4 3 7 2 ] 22
+M  Atomic [0 0 0 0 0 0 0 0 ] 0
+M  L1_Replacement [49126 49389 49077 49486 49717 49626 49450 49528 ] 395399
+M  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+M  Transient_Local_GETX [56 69 55 60 63 64 64 45 ] 476
+M  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+M  Transient_Local_GETS [100 120 99 133 126 122 103 134 ] 937
+M  Persistent_GETX [20 28 27 15 24 31 20 16 ] 181
+M  Persistent_GETS [47 54 45 47 52 51 41 43 ] 380
+M  Own_Lock_or_Unlock [2949 2916 2889 2948 2917 2850 2824 2858 ] 23151
+
+MM  Load [3 3 3 2 4 3 4 1 ] 23
+MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM  Store [0 3 2 1 2 5 4 1 ] 18
+MM  Atomic [0 0 0 0 0 0 0 0 ] 0
+MM  L1_Replacement [26772 26662 26820 26911 26761 26690 26850 27040 ] 214506
+MM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+MM  Transient_Local_GETX [30 28 41 35 44 40 37 28 ] 283
+MM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+MM  Transient_Local_GETS [53 57 74 68 53 66 69 88 ] 528
+MM  Persistent_GETX [15 14 9 10 15 14 16 16 ] 109
+MM  Persistent_GETS [29 20 25 23 26 29 24 23 ] 199
+MM  Own_Lock_or_Unlock [1614 1548 1613 1522 1530 1479 1526 1529 ] 12361
+
+M_W  Load [1 1 1 1 0 1 3 0 ] 8
+M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M_W  Store [0 0 0 1 1 0 0 0 ] 2
+M_W  Atomic [0 0 0 0 0 0 0 0 ] 0
+M_W  L1_Replacement [220700 219307 219095 219747 220275 220407 219276 220317 ] 1759124
+M_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+M_W  Transient_Local_GETX [9 9 11 11 9 9 17 9 ] 84
+M_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+M_W  Transient_Local_GETS [23 14 21 21 17 25 24 15 ] 160
+M_W  Persistent_GETX [3 2 2 3 0 3 2 7 ] 22
+M_W  Persistent_GETS [10 10 8 6 3 3 8 6 ] 54
+M_W  Own_Lock_or_Unlock [145 136 179 143 176 142 165 174 ] 1260
+M_W  Use_TimeoutStarverX [3 2 3 3 0 3 3 8 ] 25
+M_W  Use_TimeoutStarverS [10 10 8 7 4 3 9 8 ] 59
+M_W  Use_TimeoutNoStarvers [49352 49663 49304 49742 49987 49897 49685 49768 ] 397398
+M_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
+
+MM_W  Load [0 0 0 0 0 0 1 1 ] 2
+MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_W  Store [0 1 1 0 0 0 0 1 ] 3
+MM_W  Atomic [0 0 0 0 0 0 0 0 ] 0
+MM_W  L1_Replacement [120344 118153 120667 120138 118740 118451 120032 120021 ] 956546
+MM_W  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+MM_W  Transient_Local_GETX [7 5 5 3 4 9 3 5 ] 41
+MM_W  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_W  Transient_Local_GETS [10 9 14 10 6 13 8 11 ] 81
+MM_W  Persistent_GETX [3 1 2 3 0 0 1 1 ] 11
+MM_W  Persistent_GETS [2 7 1 0 0 0 4 1 ] 15
+MM_W  Own_Lock_or_Unlock [96 78 73 80 92 111 93 104 ] 727
+MM_W  Use_TimeoutStarverX [3 2 2 3 0 0 1 1 ] 12
+MM_W  Use_TimeoutStarverS [2 8 1 0 1 0 4 1 ] 17
+MM_W  Use_TimeoutNoStarvers [26897 26779 26968 27047 26895 26837 26990 27193 ] 215606
+MM_W  Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0
+
+IM  Load [0 0 0 0 0 0 0 0 ] 0
+IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM  Store [0 0 0 0 0 0 0 0 ] 0
+IM  Atomic [0 0 0 0 0 0 0 0 ] 0
+IM  L1_Replacement [301391 304654 304665 306965 304178 304263 304380 303335 ] 2433831
+IM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+IM  Data_Owner [0 0 0 1 0 0 0 0 ] 1
+IM  Data_All_Tokens [26902 26787 26971 27049 26894 26837 26995 27195 ] 215630
+IM  Ack [1 0 1 0 0 1 0 0 ] 3
+IM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+IM  Transient_Local_GETX [81 92 95 92 96 89 75 101 ] 721
+IM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+IM  Transient_Local_GETS [146 170 156 155 165 163 162 147 ] 1264
+IM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IM  Persistent_GETX [43 52 38 56 39 37 50 38 ] 353
+IM  Persistent_GETS [78 85 94 92 56 58 77 65 ] 605
+IM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IM  Own_Lock_or_Unlock [8886 8829 8871 8962 8795 8820 8972 8897 ] 71032
+IM  Request_Timeout [173243 171251 171891 171981 171016 170371 172749 170073 ] 1372575
+
+SM  Load [0 0 0 0 0 0 0 0 ] 0
+SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM  Store [0 0 0 0 0 0 0 0 ] 0
+SM  Atomic [0 0 0 0 0 0 0 0 ] 0
+SM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+SM  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+SM  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+SM  Ack [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+SM  Request_Timeout [0 0 0 0 0 0 0 0 ] 0
+
+OM  Load [0 0 0 0 0 0 0 0 ] 0
+OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OM  Store [0 0 0 0 0 0 0 0 ] 0
+OM  Atomic [0 0 0 0 0 0 0 0 ] 0
+OM  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+OM  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+OM  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+OM  Ack [0 0 0 0 0 0 0 0 ] 0
+OM  Ack_All_Tokens [0 0 0 1 0 0 0 0 ] 1
+OM  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+OM  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+OM  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+OM  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+OM  Request_Timeout [0 0 0 0 0 0 0 0 ] 0
+
+IS  Load [0 0 0 0 0 0 0 0 ] 0
+IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS  Store [0 0 0 0 0 0 0 0 ] 0
+IS  Atomic [0 0 0 0 0 0 0 0 ] 0
+IS  L1_Replacement [558391 559786 557026 559859 565174 562983 561754 565799 ] 4490772
+IS  Data_Shared [262 248 238 230 241 228 241 221 ] 1909
+IS  Data_Owner [53 61 62 59 58 46 50 56 ] 445
+IS  Data_All_Tokens [49365 49675 49314 49752 49992 49903 49695 49781 ] 397477
+IS  Ack [0 0 0 0 0 0 0 0 ] 0
+IS  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+IS  Transient_Local_GETX [152 165 194 154 155 145 162 176 ] 1303
+IS  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+IS  Transient_Local_GETS [307 263 305 268 293 329 302 280 ] 2347
+IS  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IS  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IS  Persistent_GETX [74 71 106 80 51 70 64 83 ] 599
+IS  Persistent_GETS [161 147 137 141 126 112 141 118 ] 1083
+IS  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IS  Own_Lock_or_Unlock [16309 16529 16248 16447 16685 16505 16513 16434 ] 131670
+IS  Request_Timeout [313059 320314 315804 315404 319222 320475 317516 312314 ] 2534108
+
+I_L  Load [105 103 90 96 101 100 111 105 ] 811
+I_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I_L  Store [65 55 62 50 53 60 60 52 ] 457
+I_L  Atomic [0 0 0 0 0 0 0 0 ] 0
+I_L  L1_Replacement [25 126 71 53 116 66 12 64 ] 533
+I_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+I_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+I_L  Data_All_Tokens [0 0 0 0 1 1 0 0 ] 2
+I_L  Ack [0 0 0 0 0 0 0 0 ] 0
+I_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+I_L  Transient_Local_GETX [339 346 324 355 348 347 338 348 ] 2745
+I_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+I_L  Transient_Local_GETS [612 599 617 623 607 583 593 613 ] 4847
+I_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I_L  Persistent_GETX [63107 63144 63106 63004 63284 63208 63045 63090 ] 504988
+I_L  Persistent_GETS [116967 116795 117007 116853 116744 116946 116855 116933 ] 935100
+I_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+I_L  Own_Lock_or_Unlock [72 75 68 54 66 77 69 65 ] 546
+
+S_L  Load [0 0 0 0 0 0 0 0 ] 0
+S_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
+S_L  Store [0 0 0 0 0 0 0 0 ] 0
+S_L  Atomic [0 0 0 0 0 0 0 0 ] 0
+S_L  L1_Replacement [0 32 14 9 5 4 36 16 ] 116
+S_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+S_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+S_L  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+S_L  Ack [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+S_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+S_L  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+S_L  Persistent_GETS [8 9 6 7 0 0 3 7 ] 40
+S_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+S_L  Own_Lock_or_Unlock [57 64 53 54 58 55 51 51 ] 443
+
+IM_L  Load [0 0 0 0 0 0 0 0 ] 0
+IM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM_L  Store [0 0 0 0 0 0 0 0 ] 0
+IM_L  Atomic [0 0 0 0 0 0 0 0 ] 0
+IM_L  L1_Replacement [1324 1203 1265 1139 949 800 1068 1198 ] 8946
+IM_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+IM_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+IM_L  Data_All_Tokens [0 2 0 0 1 0 0 0 ] 3
+IM_L  Ack [0 0 0 0 0 0 0 0 ] 0
+IM_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+IM_L  Transient_Local_GETX [0 0 0 0 0 0 1 0 ] 1
+IM_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+IM_L  Transient_Local_GETS [0 0 1 0 0 0 1 1 ] 3
+IM_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IM_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IM_L  Persistent_GETX [10 17 13 21 0 0 3 10 ] 74
+IM_L  Persistent_GETS [29 21 28 30 1 6 6 17 ] 138
+IM_L  Own_Lock_or_Unlock [186 190 194 198 147 155 187 155 ] 1412
+IM_L  Request_Timeout [1228 1042 1147 1157 934 789 1235 918 ] 8450
+
+SM_L  Load [0 0 0 0 0 0 0 0 ] 0
+SM_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM_L  Store [0 0 0 0 0 0 0 0 ] 0
+SM_L  Atomic [0 0 0 0 0 0 0 0 ] 0
+SM_L  L1_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+SM_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+SM_L  Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0
+SM_L  Ack [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM_L  Persistent_GETX [0 0 0 0 0 0 0 0 ] 0
+SM_L  Persistent_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_L  Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+SM_L  Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0
+SM_L  Request_Timeout [0 0 0 0 0 0 0 0 ] 0
+
+IS_L  Load [0 0 0 0 0 0 0 0 ] 0
+IS_L  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS_L  Store [0 0 0 0 0 0 0 0 ] 0
+IS_L  Atomic [0 0 0 0 0 0 0 0 ] 0
+IS_L  L1_Replacement [2333 1922 2073 2176 1449 1940 1847 1902 ] 15642
+IS_L  Data_Shared [0 0 0 0 0 0 0 0 ] 0
+IS_L  Data_Owner [0 0 0 0 0 0 0 0 ] 0
+IS_L  Data_All_Tokens [0 0 1 1 1 0 2 3 ] 8
+IS_L  Ack [0 0 0 0 0 0 0 0 ] 0
+IS_L  Transient_GETX [0 0 0 0 0 0 0 0 ] 0
+IS_L  Transient_Local_GETX [0 0 0 1 0 0 0 1 ] 2
+IS_L  Transient_GETS [0 0 0 0 0 0 0 0 ] 0
+IS_L  Transient_Local_GETS [2 1 0 2 2 0 1 2 ] 10
+IS_L  Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IS_L  Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0
+IS_L  Persistent_GETX [15 20 34 26 1 7 14 22 ] 139
+IS_L  Persistent_GETS [44 43 39 55 1 11 17 33 ] 243
+IS_L  Own_Lock_or_Unlock [340 321 332 316 277 282 314 303 ] 2485
+IS_L  Request_Timeout [2982 2031 1459 1769 1888 2009 1795 2512 ] 16445
+
+Cache Stats: system.l1_cntrl1.L1IcacheMemory
+  system.l1_cntrl1.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl1.L1DcacheMemory
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 77017
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 77017
+  system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.1544%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.8456%
+
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   77017    100%
+
+Cache Stats: system.l1_cntrl2.L1IcacheMemory
+  system.l1_cntrl2.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl2.L1DcacheMemory
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 76986
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76986
+  system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.9339%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.0661%
+
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76986    100%
+
+Cache Stats: system.l1_cntrl3.L1IcacheMemory
+  system.l1_cntrl3.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl3.L1DcacheMemory
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 77259
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 77259
+  system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.7989%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.2011%
+
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   77259    100%
+
+Cache Stats: system.l1_cntrl4.L1IcacheMemory
+  system.l1_cntrl4.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl4.L1DcacheMemory
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 76585
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 76585
+  system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.8717%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.1283%
+
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   76585    100%
+
+Cache Stats: system.l1_cntrl5.L1IcacheMemory
+  system.l1_cntrl5.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl5.L1DcacheMemory
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 76776
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 76776
+  system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   65.1063%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   34.8937%
+
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   76776    100%
+
+Cache Stats: system.l1_cntrl6.L1IcacheMemory
+  system.l1_cntrl6.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl6.L1DcacheMemory
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 76590
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76590
+  system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.7839%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.2161%
+
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76590    100%
+
+Cache Stats: system.l1_cntrl7.L1IcacheMemory
+  system.l1_cntrl7.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl7.L1DcacheMemory
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 77094
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 77094
+  system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.913%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.087%
+
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   77094    100%
+
+Cache Stats: system.l2_cntrl0.L2cacheMemory
+  system.l2_cntrl0.L2cacheMemory_total_misses: 613969
+  system.l2_cntrl0.L2cacheMemory_total_demand_misses: 613969
+  system.l2_cntrl0.L2cacheMemory_total_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+  system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l2_cntrl0.L2cacheMemory_request_type_GETS:   64.9684%
+  system.l2_cntrl0.L2cacheMemory_request_type_GETX:   35.0316%
+
+  system.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   613969    100%
+
+ --- L2Cache ---
+ - Event Counts -
+L1_GETS [399854 ] 399854
+L1_GETS_Last_Token [2 ] 2
+L1_GETX [215639 ] 215639
+L1_INV [1833 ] 1833
+Transient_GETX [0 ] 0
+Transient_GETS [0 ] 0
+Transient_GETS_Last_Token [0 ] 0
+L2_Replacement [610216 ] 610216
+Writeback_Tokens [0 ] 0
+Writeback_Shared_Data [1536 ] 1536
+Writeback_All_Tokens [610964 ] 610964
+Writeback_Owned [1130 ] 1130
+Data_Shared [0 ] 0
+Data_Owner [0 ] 0
+Data_All_Tokens [0 ] 0
+Ack [0 ] 0
+Ack_All_Tokens [0 ] 0
+Persistent_GETX [72354 ] 72354
+Persistent_GETS [133978 ] 133978
+Persistent_GETS_Last_Token [2 ] 2
+Own_Lock_or_Unlock [204096 ] 204096
+
+ - Transitions -
+NP  L1_GETS [398076 ] 398076
+NP  L1_GETX [214623 ] 214623
+NP  L1_INV [1288 ] 1288
+NP  Transient_GETX [0 ] 0
+NP  Transient_GETS [0 ] 0
+NP  Writeback_Tokens [0 ] 0
+NP  Writeback_Shared_Data [1529 ] 1529
+NP  Writeback_All_Tokens [607613 ] 607613
+NP  Writeback_Owned [1082 ] 1082
+NP  Data_Shared [0 ] 0
+NP  Data_Owner [0 ] 0
+NP  Data_All_Tokens [0 ] 0
+NP  Ack [0 ] 0
+NP  Persistent_GETX [0 ] 0
+NP  Persistent_GETS [0 ] 0
+NP  Persistent_GETS_Last_Token [0 ] 0
+NP  Own_Lock_or_Unlock [203275 ] 203275
+
+I  L1_GETS [1 ] 1
+I  L1_GETS_Last_Token [0 ] 0
+I  L1_GETX [0 ] 0
+I  L1_INV [1 ] 1
+I  Transient_GETX [0 ] 0
+I  Transient_GETS [0 ] 0
+I  Transient_GETS_Last_Token [0 ] 0
+I  L2_Replacement [533 ] 533
+I  Writeback_Tokens [0 ] 0
+I  Writeback_Shared_Data [1 ] 1
+I  Writeback_All_Tokens [846 ] 846
+I  Writeback_Owned [0 ] 0
+I  Data_Shared [0 ] 0
+I  Data_Owner [0 ] 0
+I  Data_All_Tokens [0 ] 0
+I  Ack [0 ] 0
+I  Persistent_GETX [0 ] 0
+I  Persistent_GETS [0 ] 0
+I  Persistent_GETS_Last_Token [0 ] 0
+I  Own_Lock_or_Unlock [0 ] 0
+
+S  L1_GETS [1 ] 1
+S  L1_GETS_Last_Token [2 ] 2
+S  L1_GETX [1 ] 1
+S  L1_INV [0 ] 0
+S  Transient_GETX [0 ] 0
+S  Transient_GETS [0 ] 0
+S  Transient_GETS_Last_Token [0 ] 0
+S  L2_Replacement [1276 ] 1276
+S  Writeback_Tokens [0 ] 0
+S  Writeback_Shared_Data [0 ] 0
+S  Writeback_All_Tokens [248 ] 248
+S  Writeback_Owned [1 ] 1
+S  Data_Shared [0 ] 0
+S  Data_Owner [0 ] 0
+S  Data_All_Tokens [0 ] 0
+S  Ack [0 ] 0
+S  Persistent_GETX [0 ] 0
+S  Persistent_GETS [0 ] 0
+S  Persistent_GETS_Last_Token [2 ] 2
+S  Own_Lock_or_Unlock [0 ] 0
+
+O  L1_GETS [4 ] 4
+O  L1_GETS_Last_Token [0 ] 0
+O  L1_GETX [0 ] 0
+O  L1_INV [0 ] 0
+O  Transient_GETX [0 ] 0
+O  Transient_GETS [0 ] 0
+O  Transient_GETS_Last_Token [0 ] 0
+O  L2_Replacement [1234 ] 1234
+O  Writeback_Tokens [0 ] 0
+O  Writeback_Shared_Data [5 ] 5
+O  Writeback_All_Tokens [812 ] 812
+O  Data_Shared [0 ] 0
+O  Data_All_Tokens [0 ] 0
+O  Ack [0 ] 0
+O  Ack_All_Tokens [0 ] 0
+O  Persistent_GETX [0 ] 0
+O  Persistent_GETS [0 ] 0
+O  Persistent_GETS_Last_Token [0 ] 0
+O  Own_Lock_or_Unlock [0 ] 0
+
+M  L1_GETS [963 ] 963
+M  L1_GETX [556 ] 556
+M  L1_INV [0 ] 0
+M  Transient_GETX [0 ] 0
+M  Transient_GETS [0 ] 0
+M  L2_Replacement [606686 ] 606686
+M  Persistent_GETX [487 ] 487
+M  Persistent_GETS [819 ] 819
+M  Own_Lock_or_Unlock [0 ] 0
+
+I_L  L1_GETS [809 ] 809
+I_L  L1_GETX [459 ] 459
+I_L  L1_INV [544 ] 544
+I_L  Transient_GETX [0 ] 0
+I_L  Transient_GETS [0 ] 0
+I_L  Transient_GETS_Last_Token [0 ] 0
+I_L  L2_Replacement [485 ] 485
+I_L  Writeback_Tokens [0 ] 0
+I_L  Writeback_Shared_Data [1 ] 1
+I_L  Writeback_All_Tokens [1445 ] 1445
+I_L  Writeback_Owned [47 ] 47
+I_L  Data_Shared [0 ] 0
+I_L  Data_Owner [0 ] 0
+I_L  Data_All_Tokens [0 ] 0
+I_L  Ack [0 ] 0
+I_L  Persistent_GETX [71867 ] 71867
+I_L  Persistent_GETS [133159 ] 133159
+I_L  Own_Lock_or_Unlock [821 ] 821
+
+S_L  L1_GETS [0 ] 0
+S_L  L1_GETS_Last_Token [0 ] 0
+S_L  L1_GETX [0 ] 0
+S_L  L1_INV [0 ] 0
+S_L  Transient_GETX [0 ] 0
+S_L  Transient_GETS [0 ] 0
+S_L  Transient_GETS_Last_Token [0 ] 0
+S_L  L2_Replacement [2 ] 2
+S_L  Writeback_Tokens [0 ] 0
+S_L  Writeback_Shared_Data [0 ] 0
+S_L  Writeback_All_Tokens [0 ] 0
+S_L  Writeback_Owned [0 ] 0
+S_L  Data_Shared [0 ] 0
+S_L  Data_Owner [0 ] 0
+S_L  Data_All_Tokens [0 ] 0
+S_L  Ack [0 ] 0
+S_L  Persistent_GETX [0 ] 0
+S_L  Persistent_GETS [0 ] 0
+S_L  Persistent_GETS_Last_Token [0 ] 0
+S_L  Own_Lock_or_Unlock [0 ] 0
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 823553
+  memory_reads: 608473
+  memory_writes: 215049
+  memory_refreshes: 40955
+  memory_total_request_delays: 49483061
+  memory_delays_per_request: 60.0849
+  memory_delays_in_input_queue: 412614
+  memory_delays_behind_head_of_bank_queue: 20169004
+  memory_delays_stalled_at_head_of_bank_queue: 28901443
+  memory_stalls_for_bank_busy: 4444487
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 6925202
+  memory_stalls_for_arbitration: 5968951
+  memory_stalls_for_bus: 8105541
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 2060025
+  memory_stalls_for_read_read_turnaround: 1397237
+  accesses_per_bank: 25898  25514  25666  25899  25982  25832  26034  25723  25946  25743  25754  25919  25502  25605  25766  25591  25671  25693  25738  25726  25790  25650  25833  25622  25617  25329  25704  25328  25634  25911  26070  25863  
+
+ --- Directory ---
+ - Event Counts -
+GETX [402036 ] 402036
+GETS [737914 ] 737914
+Lockdown [206334 ] 206334
+Unlockdown [204096 ] 204096
+Own_Lock_or_Unlock [0 ] 0
+Own_Lock_or_Unlock_Tokens [0 ] 0
+Data_Owner [210 ] 210
+Data_All_Tokens [214914 ] 214914
+Ack_Owner [665 ] 665
+Ack_Owner_All_Tokens [392751 ] 392751
+Tokens [512 ] 512
+Ack_All_Tokens [8723 ] 8723
+Request_Timeout [0 ] 0
+Memory_Data [608472 ] 608472
+Memory_Ack [215045 ] 215045
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+DMA_WRITE_All_Tokens [0 ] 0
+
+ - Transitions -
+O  GETX [211925 ] 211925
+O  GETS [393078 ] 393078
+O  Lockdown [1855 ] 1855
+O  Unlockdown [0 ] 0
+O  Own_Lock_or_Unlock [0 ] 0
+O  Own_Lock_or_Unlock_Tokens [0 ] 0
+O  Data_Owner [0 ] 0
+O  Data_All_Tokens [1 ] 1
+O  Tokens [1 ] 1
+O  Ack_All_Tokens [867 ] 867
+O  DMA_READ [0 ] 0
+O  DMA_WRITE [0 ] 0
+O  DMA_WRITE_All_Tokens [0 ] 0
+
+NO  GETX [1680 ] 1680
+NO  GETS [3187 ] 3187
+NO  Lockdown [8635 ] 8635
+NO  Unlockdown [0 ] 0
+NO  Own_Lock_or_Unlock [0 ] 0
+NO  Own_Lock_or_Unlock_Tokens [0 ] 0
+NO  Data_Owner [210 ] 210
+NO  Data_All_Tokens [214850 ] 214850
+NO  Ack_Owner [665 ] 665
+NO  Ack_Owner_All_Tokens [392729 ] 392729
+NO  Tokens [410 ] 410
+NO  DMA_READ [0 ] 0
+NO  DMA_WRITE [0 ] 0
+
+L  GETX [1478 ] 1478
+L  GETS [2620 ] 2620
+L  Lockdown [1289 ] 1289
+L  Unlockdown [204096 ] 204096
+L  Own_Lock_or_Unlock [0 ] 0
+L  Own_Lock_or_Unlock_Tokens [0 ] 0
+L  Data_Owner [0 ] 0
+L  Data_All_Tokens [18 ] 18
+L  Ack_Owner [0 ] 0
+L  Ack_Owner_All_Tokens [22 ] 22
+L  Tokens [2 ] 2
+L  DMA_READ [0 ] 0
+L  DMA_WRITE [0 ] 0
+L  DMA_WRITE_All_Tokens [0 ] 0
+
+O_W  GETX [47833 ] 47833
+O_W  GETS [90041 ] 90041
+O_W  Lockdown [1635 ] 1635
+O_W  Unlockdown [0 ] 0
+O_W  Own_Lock_or_Unlock [0 ] 0
+O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+O_W  Data_Owner [0 ] 0
+O_W  Data_All_Tokens [45 ] 45
+O_W  Ack_Owner [0 ] 0
+O_W  Tokens [99 ] 99
+O_W  Ack_All_Tokens [7756 ] 7756
+O_W  Memory_Data [0 ] 0
+O_W  Memory_Ack [213410 ] 213410
+O_W  DMA_READ [0 ] 0
+O_W  DMA_WRITE [0 ] 0
+O_W  DMA_WRITE_All_Tokens [0 ] 0
+
+L_O_W  GETX [46215 ] 46215
+L_O_W  GETS [84470 ] 84470
+L_O_W  Lockdown [45 ] 45
+L_O_W  Unlockdown [0 ] 0
+L_O_W  Own_Lock_or_Unlock [0 ] 0
+L_O_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+L_O_W  Data_Owner [0 ] 0
+L_O_W  Data_All_Tokens [0 ] 0
+L_O_W  Ack_Owner [0 ] 0
+L_O_W  Tokens [0 ] 0
+L_O_W  Ack_All_Tokens [88 ] 88
+L_O_W  Memory_Data [3490 ] 3490
+L_O_W  Memory_Ack [1635 ] 1635
+L_O_W  DMA_READ [0 ] 0
+L_O_W  DMA_WRITE [0 ] 0
+L_O_W  DMA_WRITE_All_Tokens [0 ] 0
+
+L_NO_W  GETX [42129 ] 42129
+L_NO_W  GETS [75055 ] 75055
+L_NO_W  Lockdown [898 ] 898
+L_NO_W  Unlockdown [0 ] 0
+L_NO_W  Own_Lock_or_Unlock [0 ] 0
+L_NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+L_NO_W  Data_Owner [0 ] 0
+L_NO_W  Data_All_Tokens [0 ] 0
+L_NO_W  Ack_Owner [0 ] 0
+L_NO_W  Tokens [0 ] 0
+L_NO_W  Ack_All_Tokens [12 ] 12
+L_NO_W  Memory_Data [191972 ] 191972
+L_NO_W  DMA_READ [0 ] 0
+L_NO_W  DMA_WRITE [0 ] 0
+L_NO_W  DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L_W  GETX [0 ] 0
+DR_L_W  GETS [0 ] 0
+DR_L_W  Lockdown [0 ] 0
+DR_L_W  Unlockdown [0 ] 0
+DR_L_W  Own_Lock_or_Unlock [0 ] 0
+DR_L_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L_W  Data_Owner [0 ] 0
+DR_L_W  Data_All_Tokens [0 ] 0
+DR_L_W  Ack_Owner [0 ] 0
+DR_L_W  Tokens [0 ] 0
+DR_L_W  Ack_All_Tokens [0 ] 0
+DR_L_W  Request_Timeout [0 ] 0
+DR_L_W  Memory_Data [0 ] 0
+DR_L_W  DMA_READ [0 ] 0
+DR_L_W  DMA_WRITE [0 ] 0
+DR_L_W  DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L_W  GETX [0 ] 0
+DW_L_W  GETS [0 ] 0
+DW_L_W  Lockdown [0 ] 0
+DW_L_W  Unlockdown [0 ] 0
+DW_L_W  Own_Lock_or_Unlock [0 ] 0
+DW_L_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L_W  Data_Owner [0 ] 0
+DW_L_W  Data_All_Tokens [0 ] 0
+DW_L_W  Ack_Owner [0 ] 0
+DW_L_W  Tokens [0 ] 0
+DW_L_W  Ack_All_Tokens [0 ] 0
+DW_L_W  Request_Timeout [0 ] 0
+DW_L_W  Memory_Ack [0 ] 0
+DW_L_W  DMA_READ [0 ] 0
+DW_L_W  DMA_WRITE [0 ] 0
+DW_L_W  DMA_WRITE_All_Tokens [0 ] 0
+
+NO_W  GETX [50776 ] 50776
+NO_W  GETS [89463 ] 89463
+NO_W  Lockdown [191977 ] 191977
+NO_W  Unlockdown [0 ] 0
+NO_W  Own_Lock_or_Unlock [0 ] 0
+NO_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_W  Data_Owner [0 ] 0
+NO_W  Data_All_Tokens [0 ] 0
+NO_W  Ack_Owner [0 ] 0
+NO_W  Tokens [0 ] 0
+NO_W  Ack_All_Tokens [0 ] 0
+NO_W  Memory_Data [413010 ] 413010
+NO_W  DMA_READ [0 ] 0
+NO_W  DMA_WRITE [0 ] 0
+NO_W  DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW_W  GETX [0 ] 0
+O_DW_W  GETS [0 ] 0
+O_DW_W  Lockdown [0 ] 0
+O_DW_W  Unlockdown [0 ] 0
+O_DW_W  Own_Lock_or_Unlock [0 ] 0
+O_DW_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW_W  Data_Owner [0 ] 0
+O_DW_W  Data_All_Tokens [0 ] 0
+O_DW_W  Ack_Owner [0 ] 0
+O_DW_W  Tokens [0 ] 0
+O_DW_W  Ack_All_Tokens [0 ] 0
+O_DW_W  Request_Timeout [0 ] 0
+O_DW_W  Memory_Ack [0 ] 0
+O_DW_W  DMA_READ [0 ] 0
+O_DW_W  DMA_WRITE [0 ] 0
+O_DW_W  DMA_WRITE_All_Tokens [0 ] 0
+
+O_DR_W  GETX [0 ] 0
+O_DR_W  GETS [0 ] 0
+O_DR_W  Lockdown [0 ] 0
+O_DR_W  Unlockdown [0 ] 0
+O_DR_W  Own_Lock_or_Unlock [0 ] 0
+O_DR_W  Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DR_W  Data_Owner [0 ] 0
+O_DR_W  Data_All_Tokens [0 ] 0
+O_DR_W  Ack_Owner [0 ] 0
+O_DR_W  Tokens [0 ] 0
+O_DR_W  Ack_All_Tokens [0 ] 0
+O_DR_W  Request_Timeout [0 ] 0
+O_DR_W  Memory_Data [0 ] 0
+O_DR_W  DMA_READ [0 ] 0
+O_DR_W  DMA_WRITE [0 ] 0
+O_DR_W  DMA_WRITE_All_Tokens [0 ] 0
+
+O_DW  GETX [0 ] 0
+O_DW  GETS [0 ] 0
+O_DW  Lockdown [0 ] 0
+O_DW  Unlockdown [0 ] 0
+O_DW  Own_Lock_or_Unlock [0 ] 0
+O_DW  Own_Lock_or_Unlock_Tokens [0 ] 0
+O_DW  Data_Owner [0 ] 0
+O_DW  Data_All_Tokens [0 ] 0
+O_DW  Ack_Owner [0 ] 0
+O_DW  Ack_Owner_All_Tokens [0 ] 0
+O_DW  Tokens [0 ] 0
+O_DW  Ack_All_Tokens [0 ] 0
+O_DW  Request_Timeout [0 ] 0
+O_DW  DMA_READ [0 ] 0
+O_DW  DMA_WRITE [0 ] 0
+O_DW  DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DW  GETX [0 ] 0
+NO_DW  GETS [0 ] 0
+NO_DW  Lockdown [0 ] 0
+NO_DW  Unlockdown [0 ] 0
+NO_DW  Own_Lock_or_Unlock [0 ] 0
+NO_DW  Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DW  Data_Owner [0 ] 0
+NO_DW  Data_All_Tokens [0 ] 0
+NO_DW  Tokens [0 ] 0
+NO_DW  Request_Timeout [0 ] 0
+NO_DW  DMA_READ [0 ] 0
+NO_DW  DMA_WRITE [0 ] 0
+NO_DW  DMA_WRITE_All_Tokens [0 ] 0
+
+NO_DR  GETX [0 ] 0
+NO_DR  GETS [0 ] 0
+NO_DR  Lockdown [0 ] 0
+NO_DR  Unlockdown [0 ] 0
+NO_DR  Own_Lock_or_Unlock [0 ] 0
+NO_DR  Own_Lock_or_Unlock_Tokens [0 ] 0
+NO_DR  Data_Owner [0 ] 0
+NO_DR  Data_All_Tokens [0 ] 0
+NO_DR  Tokens [0 ] 0
+NO_DR  Request_Timeout [0 ] 0
+NO_DR  DMA_READ [0 ] 0
+NO_DR  DMA_WRITE [0 ] 0
+NO_DR  DMA_WRITE_All_Tokens [0 ] 0
+
+DW_L  GETX [0 ] 0
+DW_L  GETS [0 ] 0
+DW_L  Lockdown [0 ] 0
+DW_L  Unlockdown [0 ] 0
+DW_L  Own_Lock_or_Unlock [0 ] 0
+DW_L  Own_Lock_or_Unlock_Tokens [0 ] 0
+DW_L  Data_Owner [0 ] 0
+DW_L  Data_All_Tokens [0 ] 0
+DW_L  Ack_Owner [0 ] 0
+DW_L  Ack_Owner_All_Tokens [0 ] 0
+DW_L  Tokens [0 ] 0
+DW_L  Request_Timeout [0 ] 0
+DW_L  DMA_READ [0 ] 0
+DW_L  DMA_WRITE [0 ] 0
+DW_L  DMA_WRITE_All_Tokens [0 ] 0
+
+DR_L  GETX [0 ] 0
+DR_L  GETS [0 ] 0
+DR_L  Lockdown [0 ] 0
+DR_L  Unlockdown [0 ] 0
+DR_L  Own_Lock_or_Unlock [0 ] 0
+DR_L  Own_Lock_or_Unlock_Tokens [0 ] 0
+DR_L  Data_Owner [0 ] 0
+DR_L  Data_All_Tokens [0 ] 0
+DR_L  Ack_Owner [0 ] 0
+DR_L  Ack_Owner_All_Tokens [0 ] 0
+DR_L  Tokens [0 ] 0
+DR_L  Request_Timeout [0 ] 0
+DR_L  DMA_READ [0 ] 0
+DR_L  DMA_WRITE [0 ] 0
+DR_L  DMA_WRITE_All_Tokens [0 ] 0
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
new file mode 100755
index 000000000..5a17811d1
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr
@@ -0,0 +1,74 @@
+system.cpu1: completed 10000 read, 5259 write accesses @1943940
+system.cpu2: completed 10000 read, 5332 write accesses @1962761
+system.cpu3: completed 10000 read, 5358 write accesses @1964980
+system.cpu7: completed 10000 read, 5453 write accesses @1976539
+system.cpu4: completed 10000 read, 5456 write accesses @1987569
+system.cpu5: completed 10000 read, 5433 write accesses @1990190
+system.cpu6: completed 10000 read, 5519 write accesses @1993800
+system.cpu0: completed 10000 read, 5421 write accesses @2013689
+system.cpu2: completed 20000 read, 10590 write accesses @3882080
+system.cpu5: completed 20000 read, 10671 write accesses @3928400
+system.cpu7: completed 20000 read, 10790 write accesses @3932180
+system.cpu1: completed 20000 read, 10547 write accesses @3932310
+system.cpu0: completed 20000 read, 10834 write accesses @3948113
+system.cpu6: completed 20000 read, 10955 write accesses @3962050
+system.cpu3: completed 20000 read, 10821 write accesses @3971009
+system.cpu4: completed 20000 read, 10681 write accesses @3977300
+system.cpu2: completed 30000 read, 16006 write accesses @5865020
+system.cpu1: completed 30000 read, 15879 write accesses @5876820
+system.cpu7: completed 30000 read, 16218 write accesses @5900140
+system.cpu5: completed 30000 read, 15930 write accesses @5906200
+system.cpu0: completed 30000 read, 16190 write accesses @5930280
+system.cpu4: completed 30000 read, 16199 write accesses @5936740
+system.cpu3: completed 30000 read, 16401 write accesses @5958400
+system.cpu6: completed 30000 read, 16369 write accesses @5969590
+system.cpu2: completed 40000 read, 21434 write accesses @7815170
+system.cpu7: completed 40000 read, 21668 write accesses @7856120
+system.cpu1: completed 40000 read, 21296 write accesses @7859890
+system.cpu5: completed 40000 read, 21183 write accesses @7885749
+system.cpu0: completed 40000 read, 21572 write accesses @7901159
+system.cpu6: completed 40000 read, 21926 write accesses @7959459
+system.cpu3: completed 40000 read, 21755 write accesses @7975160
+system.cpu4: completed 40000 read, 21520 write accesses @8005850
+system.cpu2: completed 50000 read, 26840 write accesses @9789230
+system.cpu1: completed 50000 read, 26675 write accesses @9813220
+system.cpu0: completed 50000 read, 26961 write accesses @9857191
+system.cpu7: completed 50000 read, 27124 write accesses @9870470
+system.cpu5: completed 50000 read, 26683 write accesses @9908920
+system.cpu3: completed 50000 read, 27202 write accesses @9939500
+system.cpu6: completed 50000 read, 27538 write accesses @10014701
+system.cpu4: completed 50000 read, 26958 write accesses @10027591
+system.cpu2: completed 60000 read, 32206 write accesses @11734940
+system.cpu1: completed 60000 read, 32043 write accesses @11782013
+system.cpu5: completed 60000 read, 31930 write accesses @11824240
+system.cpu7: completed 60000 read, 32526 write accesses @11842030
+system.cpu0: completed 60000 read, 32219 write accesses @11858030
+system.cpu3: completed 60000 read, 32666 write accesses @11893660
+system.cpu6: completed 60000 read, 32876 write accesses @11988610
+system.cpu4: completed 60000 read, 32390 write accesses @11997042
+system.cpu2: completed 70000 read, 37578 write accesses @13743359
+system.cpu5: completed 70000 read, 37050 write accesses @13756570
+system.cpu1: completed 70000 read, 37370 write accesses @13758070
+system.cpu0: completed 70000 read, 37494 write accesses @13761040
+system.cpu7: completed 70000 read, 37955 write accesses @13842700
+system.cpu3: completed 70000 read, 38057 write accesses @13861012
+system.cpu4: completed 70000 read, 37766 write accesses @13960260
+system.cpu6: completed 70000 read, 38323 write accesses @14032912
+system.cpu2: completed 80000 read, 42857 write accesses @15688757
+system.cpu0: completed 80000 read, 42870 write accesses @15694240
+system.cpu5: completed 80000 read, 42300 write accesses @15735600
+system.cpu1: completed 80000 read, 42715 write accesses @15772000
+system.cpu7: completed 80000 read, 43184 write accesses @15806450
+system.cpu3: completed 80000 read, 43353 write accesses @15812610
+system.cpu4: completed 80000 read, 43208 write accesses @15920280
+system.cpu6: completed 80000 read, 43672 write accesses @16021870
+system.cpu0: completed 90000 read, 48147 write accesses @17663030
+system.cpu2: completed 90000 read, 48318 write accesses @17663170
+system.cpu1: completed 90000 read, 47923 write accesses @17705777
+system.cpu5: completed 90000 read, 47730 write accesses @17748050
+system.cpu7: completed 90000 read, 48616 write accesses @17754820
+system.cpu3: completed 90000 read, 48969 write accesses @17819630
+system.cpu4: completed 90000 read, 48647 write accesses @17880960
+system.cpu6: completed 90000 read, 49180 write accesses @18069050
+system.cpu0: completed 100000 read, 53504 write accesses @19658320
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
new file mode 100755
index 000000000..0dc21efd5
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:50:16
+gem5 started Jan 23 2012 04:22:27
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 19658320 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
new file mode 100644
index 000000000..d79a41535
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -0,0 +1,47 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.019658                       # Number of seconds simulated
+sim_ticks                                    19658320                       # Number of ticks simulated
+final_tick                                   19658320                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                 164666                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347552                       # Number of bytes of host memory used
+host_seconds                                   119.38                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          53504                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           99869                       # number of read accesses completed
+system.cpu1.num_writes                          53121                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           99994                       # number of read accesses completed
+system.cpu2.num_writes                          53565                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           99591                       # number of read accesses completed
+system.cpu3.num_writes                          54122                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                           98976                       # number of read accesses completed
+system.cpu4.num_writes                          53568                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                           99562                       # number of read accesses completed
+system.cpu5.num_writes                          52869                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           98114                       # number of read accesses completed
+system.cpu6.num_writes                          53480                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           99618                       # number of read accesses completed
+system.cpu7.num_writes                          53886                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
new file mode 100644
index 000000000..74320f307
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini
@@ -0,0 +1,973 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
+
+[system.cpu0]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.l1_cntrl0.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.l1_cntrl1.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.l1_cntrl2.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.l1_cntrl3.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.l1_cntrl4.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.l1_cntrl5.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.l1_cntrl6.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.l1_cntrl7.sequencer.port[0]
+
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer probeFilter
+buffer_size=0
+cntrl_id=8
+directory=system.dir_cntrl0.directory
+full_bit_dir_enabled=false
+memBuffer=system.dir_cntrl0.memBuffer
+memory_controller_latency=2
+number_of_TBEs=256
+probeFilter=system.dir_cntrl0.probeFilter
+probe_filter_enabled=false
+recycle_latency=10
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.dir_cntrl0.probeFilter]
+type=RubyCache
+assoc=4
+is_icache=false
+latency=1
+replacement_policy=PSEUDO_LRU
+size=1024
+start_index_bit=6
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl0.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl0.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl0.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=0
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl0.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.l1_cntrl1]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl1.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl1.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl1.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=1
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl1.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.l1_cntrl1.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl1.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl1.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=1
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.l1_cntrl2]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl2.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl2.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl2.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=2
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl2.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.l1_cntrl2.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl2.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl2.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl2.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=2
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.l1_cntrl3]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl3.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl3.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl3.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=3
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl3.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.l1_cntrl3.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl3.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl3.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=3
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.l1_cntrl4]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl4.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl4.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl4.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=4
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl4.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.l1_cntrl4.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl4.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl4.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=4
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.l1_cntrl5]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl5.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl5.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl5.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=5
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl5.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.l1_cntrl5.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl5.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl5.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=5
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.l1_cntrl6]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl6.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl6.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl6.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=6
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl6.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.l1_cntrl6.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl6.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl6.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=6
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.l1_cntrl7]
+type=L1Cache_Controller
+children=L1DcacheMemory L1IcacheMemory L2cacheMemory sequencer
+L1DcacheMemory=system.l1_cntrl7.L1DcacheMemory
+L1IcacheMemory=system.l1_cntrl7.L1IcacheMemory
+L2cacheMemory=system.l1_cntrl7.L2cacheMemory
+buffer_size=0
+cache_response_latency=10
+cntrl_id=7
+issue_latency=2
+l2_cache_hit_latency=10
+no_mig_atomic=true
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl7.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.l1_cntrl7.L1DcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.L1IcacheMemory]
+type=RubyCache
+assoc=2
+is_icache=true
+latency=2
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.L2cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=10
+replacement_policy=PSEUDO_LRU
+size=512
+start_index_bit=6
+
+[system.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl7.L1DcacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl7.L1IcacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=7
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=network profiler
+block_size_bytes=64
+clock=1
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=false
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=1000
+number_of_virtual_networks=10
+ruby_system=system.ruby
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
+description=Crossbar
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
+print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9
+
+[system.ruby.network.topology.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl0
+int_node=system.ruby.network.topology.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.topology.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl1
+int_node=system.ruby.network.topology.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.topology.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl2
+int_node=system.ruby.network.topology.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.topology.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl3
+int_node=system.ruby.network.topology.routers3
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.topology.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl4
+int_node=system.ruby.network.topology.routers4
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.topology.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl5
+int_node=system.ruby.network.topology.routers5
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.topology.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl6
+int_node=system.ruby.network.topology.routers6
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.topology.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl7
+int_node=system.ruby.network.topology.routers7
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.topology.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.dir_cntrl0
+int_node=system.ruby.network.topology.routers8
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.topology.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=9
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.topology.routers3
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.topology.routers4
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.topology.routers5
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.topology.routers6
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.topology.routers7
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.topology.routers8
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers4]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers5]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers6]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers7]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers8]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers9]
+type=BasicRouter
+router_id=9
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
new file mode 100644
index 000000000..9f2e0a2cf
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -0,0 +1,1373 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 1
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
+virtual_net_2: active, unordered
+virtual_net_3: active, unordered
+virtual_net_4: active, unordered
+virtual_net_5: active, unordered
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/23/2012 04:23:36
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 107
+Elapsed_time_in_minutes: 1.78333
+Elapsed_time_in_hours: 0.0297222
+Elapsed_time_in_days: 0.00123843
+
+Virtual_time_in_seconds: 107.49
+Virtual_time_in_minutes: 1.7915
+Virtual_time_in_hours:   0.0298583
+Virtual_time_in_days:    0.0012441
+
+Ruby_current_time: 19076439
+Ruby_start_time: 0
+Ruby_cycles: 19076439
+
+mbytes_resident: 41.2852
+mbytes_total: 339.078
+resident_ratio: 0.121757
+
+ruby_cycles_executed: [ 19076440 19076440 19076440 19076440 19076440 19076440 19076440 19076440 ]
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
+
+Directory-0:0  
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 613136 average: 15.9984 | standard deviation: 0.127191 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 613016 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 128 max: 18400 count: 613008 average: 3982.62 | standard deviation: 2991.98 | 1907 7027 12453 16474 15845 18678 21073 22250 19210 16951 18183 17228 14390 12685 11884 11226 9753 9022 8545 7231 7216 6897 6866 6372 5663 6032 6139 5722 5632 5450 5777 5524 5508 5866 5290 5574 5878 6096 5990 5454 6175 6454 6237 6342 6339 6710 6642 6724 7271 6583 6832 6981 7466 7120 6561 7001 7133 6599 6513 6004 6322 6050 5882 5678 4966 4956 4706 4560 4034 3440 3593 3395 3030 2731 2397 2387 2033 1938 1786 1447 1457 1286 1233 1057 851 860 801 681 595 518 463 364 372 338 248 228 189 201 182 131 136 127 99 93 70 60 65 38 36 35 32 20 22 32 9 8 11 11 9 6 12 5 5 3 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 18400 count: 398225 average: 3984.55 | standard deviation: 2993.11 | 1287 4543 8056 10700 10250 12192 13683 14543 12441 11010 11748 11157 9395 8251 7689 7248 6295 5900 5500 4685 4642 4548 4399 4155 3756 3922 3916 3709 3663 3546 3691 3588 3583 3833 3439 3656 3870 3923 3953 3565 4037 4215 3989 4135 4211 4379 4361 4340 4671 4313 4374 4490 4818 4610 4195 4518 4637 4291 4226 3932 4150 3950 3804 3644 3279 3180 3044 3000 2663 2244 2358 2167 1961 1801 1561 1538 1287 1283 1178 965 932 823 847 675 567 561 527 421 387 352 301 246 248 226 159 150 121 119 121 77 94 90 59 60 45 45 47 23 25 18 19 12 10 23 5 4 6 7 6 4 8 4 3 3 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 18030 count: 214783 average: 3979.04 | standard deviation: 2989.88 | 620 2484 4397 5774 5595 6486 7390 7707 6769 5941 6435 6071 4995 4434 4195 3978 3458 3122 3045 2546 2574 2349 2467 2217 1907 2110 2223 2013 1969 1904 2086 1936 1925 2033 1851 1918 2008 2173 2037 1889 2138 2239 2248 2207 2128 2331 2281 2384 2600 2270 2458 2491 2648 2510 2366 2483 2496 2308 2287 2072 2172 2100 2078 2034 1687 1776 1662 1560 1371 1196 1235 1228 1069 930 836 849 746 655 608 482 525 463 386 382 284 299 274 260 208 166 162 118 124 112 89 78 68 82 61 54 42 37 40 33 25 15 18 15 11 17 13 8 12 9 4 4 5 4 3 2 4 1 2 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache: [binsize: 1 max: 2 count: 133 average:     2 | standard deviation: 0 | 0 0 133 ]
+miss_latency_L2Cache: [binsize: 64 max: 6752 count: 560 average: 508.952 | standard deviation: 604.29 | 140 23 35 31 29 33 25 30 22 37 18 13 12 14 11 19 4 8 4 7 4 5 2 1 4 1 1 3 2 5 3 3 1 2 1 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 18400 count: 592476 average: 4003.78 | standard deviation: 2989.72 | 0 6272 11730 15642 14987 18010 20490 21655 18688 16550 17820 16892 14128 12443 11607 10974 9537 8836 8342 7031 7021 6704 6659 6208 5479 5886 5943 5537 5438 5279 5557 5370 5349 5688 5094 5380 5656 5930 5773 5245 5961 6226 6024 6130 6115 6498 6422 6507 7027 6324 6593 6758 7260 6900 6355 6799 6932 6436 6315 5825 6120 5905 5713 5534 4838 4830 4600 4453 3942 3347 3503 3317 2967 2674 2340 2341 1986 1896 1758 1415 1423 1262 1209 1036 832 839 783 666 583 512 455 356 364 332 241 224 184 200 178 129 134 124 96 93 67 59 64 37 36 34 30 19 22 32 9 8 10 11 9 5 12 5 4 2 5 5 2 2 3 2 1 1 1 1 1 0 1 0 1 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 128 max: 15824 count: 19839 average: 3475.24 | standard deviation: 2990.25 | 1611 689 661 777 799 637 557 565 510 390 354 333 257 238 270 246 213 184 202 199 195 193 207 164 183 146 195 185 194 171 220 154 158 178 196 194 222 166 217 209 214 228 213 212 224 212 220 217 244 259 239 223 205 220 206 202 201 163 198 179 202 145 169 144 128 126 106 107 92 93 90 78 63 57 57 46 47 42 28 32 34 24 24 21 19 21 18 15 12 6 8 8 8 6 7 4 5 1 4 2 2 3 3 0 3 1 1 1 0 1 2 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 128 max: 15681 count: 19811 average: 3294.71 | standard deviation: 2973.49 | 2393 788 778 887 698 565 526 482 416 304 282 259 243 202 195 228 166 178 196 169 200 184 205 143 162 171 202 192 182 160 192 162 182 213 175 210 215 208 201 181 236 224 212 244 216 218 207 216 246 221 241 234 219 215 202 187 199 186 187 162 183 140 147 144 111 92 97 97 81 79 88 73 44 46 45 38 39 33 31 21 36 23 16 13 15 14 11 12 12 5 5 9 6 3 5 4 3 2 2 2 0 2 2 2 2 2 1 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 32 max: 3227 count: 19811 average: 155.584 | standard deviation: 322.971 | 14095 352 257 301 235 217 214 193 254 201 193 196 172 273 199 186 177 173 167 105 89 89 79 112 83 76 63 90 100 74 65 66 55 64 37 43 32 25 31 28 30 28 23 17 20 21 21 14 11 15 16 13 2 16 9 6 9 9 14 9 7 5 4 1 3 2 2 0 0 2 1 0 3 2 5 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 39 count: 19811 average: 24.6142 | standard deviation: 1.1529 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14531 121 4581 47 162 197 137 14 11 6 0 2 1 0 0 1 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 15 count: 19811 average: 1.76145 | standard deviation: 1.57115 | 4554 5044 5173 3088 639 541 631 34 49 30 20 5 1 1 0 1 ]
+imcomplete_wCC_Times: 28
+miss_latency_dir_issue_to_initial_request: [binsize: 128 max: 18051 count: 592476 average: 3281.72 | standard deviation: 2955.08 | 70738 24002 22428 26767 20802 17537 15706 15298 11350 8629 8834 8349 7073 6369 6165 6306 5814 5671 5976 5128 5478 5387 5706 5221 4890 5461 5662 5263 5277 5218 5675 5295 5531 5934 5491 5800 5887 6442 6263 5774 6483 6771 6588 6782 6489 7137 6981 6950 7319 6513 6851 6728 6955 6376 5730 6024 6115 5555 5189 4810 4902 4288 4077 3946 3271 3184 2971 2807 2494 2203 2085 1914 1703 1482 1343 1299 1108 980 926 758 674 638 624 469 397 443 342 270 271 222 182 157 129 127 119 91 112 77 74 63 52 40 17 28 22 12 18 12 19 14 9 9 10 4 6 3 4 9 3 1 2 2 2 4 0 3 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_dir_initial_forward_request: [binsize: 16 max: 3183 count: 592476 average: 11.5725 | standard deviation: 55.3766 | 588970 287 43 73 70 75 38 101 87 46 78 59 67 83 44 68 38 61 59 29 47 28 45 46 25 45 29 41 35 27 55 30 62 61 46 66 36 65 72 30 61 32 65 51 30 43 18 39 41 14 23 22 26 39 12 19 11 22 24 16 32 13 22 30 10 19 10 26 25 12 24 10 17 19 7 15 8 17 14 5 11 8 12 10 5 13 2 4 9 3 7 3 4 6 7 9 0 6 9 5 3 3 5 7 4 7 3 3 4 2 3 0 1 3 3 3 2 2 6 7 2 1 1 3 0 0 3 2 2 3 2 0 0 1 0 1 2 1 4 0 1 2 2 2 1 2 2 2 1 0 0 1 0 1 1 4 1 1 0 0 1 0 1 2 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 44 count: 592476 average: 24.8308 | standard deviation: 1.27632 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 380177 4933 182882 1518 7662 8302 5647 616 334 251 69 48 31 2 1 0 2 0 0 0 1 ]
+miss_latency_dir_first_response_to_completion: [binsize: 32 max: 4704 count: 592476 average: 685.659 | standard deviation: 462.491 | 0 0 0 14464 19382 17090 18564 21773 25259 21342 20460 19953 22247 24131 19251 17928 16594 16740 17436 13730 13612 13360 14457 15897 13132 13130 12935 14117 14423 10787 9485 8050 7825 7770 6022 5721 5406 5541 5804 4526 4531 4411 4773 4755 3548 3161 2840 2801 2682 2038 1914 1826 1855 1934 1543 1490 1384 1482 1482 1029 1018 859 937 852 670 579 559 605 593 449 492 416 403 476 305 323 254 257 252 203 193 173 174 161 112 123 126 106 110 94 80 75 54 61 54 42 40 40 44 38 24 28 24 18 16 12 10 20 7 7 4 5 8 7 6 6 4 8 8 4 3 1 2 2 4 2 2 0 1 1 0 1 2 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 0
+miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 95 average:     2 | standard deviation: 0 | 0 0 95 ]
+miss_latency_LD_L2Cache: [binsize: 32 max: 3352 count: 370 average: 491.168 | standard deviation: 559.428 | 88 17 6 9 14 10 12 9 9 11 6 12 6 5 10 6 6 6 14 13 3 6 4 6 3 6 2 5 5 5 0 12 2 0 2 2 1 1 2 1 1 2 0 3 0 1 0 1 2 1 0 1 1 0 0 3 1 0 2 1 0 2 0 2 0 1 0 2 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_Directory: [binsize: 128 max: 18400 count: 384794 average: 4005.68 | standard deviation: 2990.67 | 0 4044 7606 10161 9689 11763 13315 14152 12112 10749 11513 10944 9220 8095 7509 7070 6155 5776 5376 4556 4520 4412 4258 4050 3634 3824 3789 3586 3544 3426 3540 3485 3479 3711 3307 3538 3720 3817 3820 3436 3885 4068 3859 3995 4053 4235 4219 4194 4514 4156 4227 4343 4678 4471 4063 4388 4511 4181 4097 3810 4015 3854 3708 3548 3195 3091 2980 2922 2600 2180 2304 2121 1919 1760 1522 1506 1253 1255 1157 940 907 807 829 660 555 548 515 411 382 348 294 241 242 220 154 147 119 118 117 76 94 88 57 60 44 44 46 23 25 17 19 12 10 23 5 4 6 7 6 3 8 4 3 2 4 3 2 2 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 128 max: 15824 count: 12966 average: 3486.33 | standard deviation: 2996.66 | 1072 454 412 512 522 410 352 369 323 256 229 211 171 152 176 174 137 122 123 128 122 136 141 105 121 98 126 123 119 120 151 103 104 122 132 118 150 106 133 129 152 147 130 140 158 144 142 146 157 157 147 147 140 139 132 130 126 110 129 122 135 96 96 96 84 89 64 78 63 64 54 46 42 41 39 32 34 28 21 25 25 16 18 15 12 13 12 10 5 4 7 5 6 6 5 3 2 1 4 1 0 2 2 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 38 average:     2 | standard deviation: 0 | 0 0 38 ]
+miss_latency_ST_L2Cache: [binsize: 64 max: 6752 count: 190 average: 543.584 | standard deviation: 683.521 | 35 8 11 10 9 15 14 14 10 10 9 3 3 7 1 7 2 4 2 4 1 2 1 0 1 0 0 0 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_Directory: [binsize: 128 max: 18030 count: 207682 average: 4000.27 | standard deviation: 2987.96 | 0 2228 4124 5481 5298 6247 7175 7503 6576 5801 6307 5948 4908 4348 4098 3904 3382 3060 2966 2475 2501 2292 2401 2158 1845 2062 2154 1951 1894 1853 2017 1885 1870 1977 1787 1842 1936 2113 1953 1809 2076 2158 2165 2135 2062 2263 2203 2313 2513 2168 2366 2415 2582 2429 2292 2411 2421 2255 2218 2015 2105 2051 2005 1986 1643 1739 1620 1531 1342 1167 1199 1196 1048 914 818 835 733 641 601 475 516 455 380 376 277 291 268 255 201 164 161 115 122 112 87 77 65 82 61 53 40 36 39 33 23 15 18 14 11 17 11 7 12 9 4 4 4 4 3 2 4 1 1 0 1 2 0 0 2 1 1 1 1 1 1 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 128 max: 15717 count: 6873 average: 3454.33 | standard deviation: 2978.21 | 539 235 249 265 277 227 205 196 187 134 125 122 86 86 94 72 76 62 79 71 73 57 66 59 62 48 69 62 75 51 69 51 54 56 64 76 72 60 84 80 62 81 83 72 66 68 78 71 87 102 92 76 65 81 74 72 75 53 69 57 67 49 73 48 44 37 42 29 29 29 36 32 21 16 18 14 13 14 7 7 9 8 6 6 7 8 6 5 7 2 1 3 2 0 2 1 3 0 0 1 2 1 1 0 2 0 0 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 107
+system_time: 0
+page_reclaims: 10917
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 200
+
+Network Stats
+-------------
+
+total_msg_count_Request_Control: 1837086 14696688
+total_msg_count_Response_Data: 1836936 132259392
+total_msg_count_Response_Control: 12798939 102391512
+total_msg_count_Writeback_Data: 636630 45837360
+total_msg_count_Writeback_Control: 4561293 36490344
+total_msg_count_Broadcast_Control: 9184575 73476600
+total_msg_count_Unblock_Control: 1836972 14695776
+total_msgs: 32692431 total_bytes: 419847672
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 3.77725
+  links_utilized_percent_switch_0_link_0: 4.77637 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 2.77814 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Data: 76057 5476104 [ 0 0 0 0 76057 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Response_Control: 529924 4239392 [ 0 0 0 0 529924 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 71629 573032 [ 0 0 0 71629 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Broadcast_Control: 536252 4290016 [ 0 0 0 536252 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Request_Control: 76060 608480 [ 0 0 76060 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 2500 180000 [ 0 0 0 0 2500 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Control: 533753 4270024 [ 0 0 0 0 533753 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Data: 26039 1874808 [ 0 0 0 0 0 26039 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Writeback_Control: 117218 937744 [ 0 0 71629 0 0 45589 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Unblock_Control: 76058 608464 [ 0 0 0 0 0 76058 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 3.76513
+  links_utilized_percent_switch_1_link_0: 4.75543 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 2.77484 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Data: 75553 5439816 [ 0 0 0 0 75553 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Response_Control: 526391 4211128 [ 0 0 0 0 526391 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 71208 569664 [ 0 0 0 71208 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Broadcast_Control: 536756 4294048 [ 0 0 0 536756 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Request_Control: 75555 604440 [ 0 0 75555 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 2534 182448 [ 0 0 0 0 2534 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Control: 534222 4273776 [ 0 0 0 0 534222 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Data: 26016 1873152 [ 0 0 0 0 0 26016 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Writeback_Control: 116398 931184 [ 0 0 71208 0 0 45190 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Unblock_Control: 75555 604440 [ 0 0 0 0 0 75555 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 3.80471
+  links_utilized_percent_switch_2_link_0: 4.80919 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 2.80023 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Data: 76831 5531832 [ 0 0 0 0 76831 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Response_Control: 535348 4282784 [ 0 0 0 0 535348 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Broadcast_Control: 535476 4283808 [ 0 0 0 535476 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Request_Control: 76833 614664 [ 0 0 76833 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 2524 181728 [ 0 0 0 0 2524 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Control: 532955 4263640 [ 0 0 0 0 532955 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Data: 26745 1925640 [ 0 0 0 0 0 26745 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Writeback_Control: 118326 946608 [ 0 0 72536 0 0 45790 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Unblock_Control: 76832 614656 [ 0 0 0 0 0 76832 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 3.7982
+  links_utilized_percent_switch_3_link_0: 4.80209 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 2.79431 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Data: 76656 5519232 [ 0 0 0 0 76656 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Response_Control: 534204 4273632 [ 0 0 0 0 534204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 72377 579016 [ 0 0 0 72377 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Broadcast_Control: 535646 4285168 [ 0 0 0 535646 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Request_Control: 76659 613272 [ 0 0 76659 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 2425 174600 [ 0 0 0 0 2425 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Control: 533222 4265776 [ 0 0 0 0 533222 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Data: 26624 1916928 [ 0 0 0 0 0 26624 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Writeback_Control: 118125 945000 [ 0 0 72377 0 0 45748 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Unblock_Control: 76662 613296 [ 0 0 0 0 0 76662 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 3.80549
+  links_utilized_percent_switch_4_link_0: 4.81362 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 2.79737 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Data: 76939 5539608 [ 0 0 0 0 76939 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Response_Control: 536135 4289080 [ 0 0 0 0 536135 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 72578 580624 [ 0 0 0 72578 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Broadcast_Control: 535367 4282936 [ 0 0 0 535367 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Request_Control: 76942 615536 [ 0 0 76942 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 2449 176328 [ 0 0 0 0 2449 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Control: 532918 4263344 [ 0 0 0 0 532918 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Data: 26660 1919520 [ 0 0 0 0 0 26660 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Writeback_Control: 118496 947968 [ 0 0 72578 0 0 45918 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Unblock_Control: 76939 615512 [ 0 0 0 0 0 76939 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 3.81067
+  links_utilized_percent_switch_5_link_0: 4.81781 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 2.80353 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Data: 77040 5546880 [ 0 0 0 0 77040 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Response_Control: 536788 4294304 [ 0 0 0 0 536788 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 72718 581744 [ 0 0 0 72718 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Broadcast_Control: 535263 4282104 [ 0 0 0 535263 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Request_Control: 77043 616344 [ 0 0 77043 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 2536 182592 [ 0 0 0 0 2536 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Control: 532733 4261864 [ 0 0 0 0 532733 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Data: 26819 1930968 [ 0 0 0 0 0 26819 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Writeback_Control: 118616 948928 [ 0 0 72718 0 0 45898 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Unblock_Control: 77041 616328 [ 0 0 0 0 0 77041 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 3.79476
+  links_utilized_percent_switch_6_link_0: 4.79677 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 2.79275 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Data: 76540 5510880 [ 0 0 0 0 76540 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Response_Control: 533216 4265728 [ 0 0 0 0 533216 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 72261 578088 [ 0 0 0 72261 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Broadcast_Control: 535763 4286104 [ 0 0 0 535763 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Request_Control: 76544 612352 [ 0 0 76544 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 2407 173304 [ 0 0 0 0 2407 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Control: 533360 4266880 [ 0 0 0 0 533360 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Data: 26611 1915992 [ 0 0 0 0 0 26611 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Writeback_Control: 117909 943272 [ 0 0 72261 0 0 45648 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Unblock_Control: 76541 612328 [ 0 0 0 0 0 76541 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 3.79942
+  links_utilized_percent_switch_7_link_0: 4.80286 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 2.79599 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Data: 76696 5522112 [ 0 0 0 0 76696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Response_Control: 534307 4274456 [ 0 0 0 0 534307 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 72244 577952 [ 0 0 0 72244 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Broadcast_Control: 535612 4284896 [ 0 0 0 535612 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Request_Control: 76698 613584 [ 0 0 76698 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 2461 177192 [ 0 0 0 0 2461 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Control: 533150 4265200 [ 0 0 0 0 533150 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Data: 26696 1922112 [ 0 0 0 0 0 26696 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Writeback_Control: 117792 942336 [ 0 0 72244 0 0 45548 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Unblock_Control: 76696 613568 [ 0 0 0 0 0 76696 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 13.891
+  links_utilized_percent_switch_8_link_0: 10.6871 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 17.0948 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Request_Control: 612334 4898672 [ 0 0 612334 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Data: 212210 15279120 [ 0 0 0 0 0 212210 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Writeback_Control: 942880 7543040 [ 0 0 577551 0 0 365329 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Unblock_Control: 612324 4898592 [ 0 0 0 0 0 612324 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Request_Control: 28 224 [ 0 0 0 28 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 592476 42658272 [ 0 0 0 0 592476 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 577551 4620408 [ 0 0 0 577551 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Broadcast_Control: 612305 4898440 [ 0 0 0 612305 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 9
+switch_9_outlinks: 9
+links_utilized_percent_switch_9: 5.45125
+  links_utilized_percent_switch_9_link_0: 4.77637 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 4.75543 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 4.80919 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 4.80209 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 4.81362 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 4.81782 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 4.79677 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 4.80286 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 10.6871 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Data: 76057 5476104 [ 0 0 0 0 76057 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Response_Control: 529924 4239392 [ 0 0 0 0 529924 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 71629 573032 [ 0 0 0 71629 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Broadcast_Control: 536252 4290016 [ 0 0 0 536252 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 75553 5439816 [ 0 0 0 0 75553 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Control: 526391 4211128 [ 0 0 0 0 526391 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 71208 569664 [ 0 0 0 71208 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Broadcast_Control: 536756 4294048 [ 0 0 0 536756 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Request_Control: 5 40 [ 0 0 0 5 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 76831 5531832 [ 0 0 0 0 76831 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Control: 535348 4282784 [ 0 0 0 0 535348 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 72536 580288 [ 0 0 0 72536 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Broadcast_Control: 535476 4283808 [ 0 0 0 535476 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Request_Control: 3 24 [ 0 0 0 3 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 76656 5519232 [ 0 0 0 0 76656 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Control: 534204 4273632 [ 0 0 0 0 534204 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 72377 579016 [ 0 0 0 72377 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Broadcast_Control: 535646 4285168 [ 0 0 0 535646 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Request_Control: 2 16 [ 0 0 0 2 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 76939 5539608 [ 0 0 0 0 76939 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Control: 536135 4289080 [ 0 0 0 0 536135 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 72578 580624 [ 0 0 0 72578 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Broadcast_Control: 535367 4282936 [ 0 0 0 535367 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Request_Control: 8 64 [ 0 0 0 8 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 77040 5546880 [ 0 0 0 0 77040 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Control: 536788 4294304 [ 0 0 0 0 536788 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 72718 581744 [ 0 0 0 72718 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Broadcast_Control: 535263 4282104 [ 0 0 0 535263 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Request_Control: 4 32 [ 0 0 0 4 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 76540 5510880 [ 0 0 0 0 76540 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Control: 533216 4265728 [ 0 0 0 0 533216 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 72261 578088 [ 0 0 0 72261 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Broadcast_Control: 535763 4286104 [ 0 0 0 535763 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Request_Control: 1 8 [ 0 0 0 1 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 76696 5522112 [ 0 0 0 0 76696 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Control: 534307 4274456 [ 0 0 0 0 534307 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 72244 577952 [ 0 0 0 72244 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Broadcast_Control: 535612 4284896 [ 0 0 0 535612 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Request_Control: 612334 4898672 [ 0 0 612334 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Data: 212210 15279120 [ 0 0 0 0 0 212210 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Writeback_Control: 942880 7543040 [ 0 0 577551 0 0 365329 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Unblock_Control: 612324 4898592 [ 0 0 0 0 0 612324 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.L1IcacheMemory
+  system.l1_cntrl0.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl0.L1DcacheMemory
+  system.l1_cntrl0.L1DcacheMemory_total_misses: 76122
+  system.l1_cntrl0.L1DcacheMemory_total_demand_misses: 76122
+  system.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L1DcacheMemory_request_type_LD:   65.3648%
+  system.l1_cntrl0.L1DcacheMemory_request_type_ST:   34.6352%
+
+  system.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor:   76122    100%
+
+Cache Stats: system.l1_cntrl0.L2cacheMemory
+  system.l1_cntrl0.L2cacheMemory_total_misses: 76122
+  system.l1_cntrl0.L2cacheMemory_total_demand_misses: 76122
+  system.l1_cntrl0.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.L2cacheMemory_request_type_LD:   65.3648%
+  system.l1_cntrl0.L2cacheMemory_request_type_ST:   34.6352%
+
+  system.l1_cntrl0.L2cacheMemory_access_mode_type_Supervisor:   76122    100%
+
+ --- L1Cache ---
+ - Event Counts -
+Load [50083 50012 49809 49808 49791 49324 49816 49826 ] 398469
+Ifetch [0 0 0 0 0 0 0 0 ] 0
+Store [26984 27191 26853 27019 26384 26370 27145 26987 ] 214933
+L2_Replacement [76925 77030 76532 76686 76048 75543 76816 76643 ] 612223
+L1_to_L2 [839245 835114 838734 835659 830150 829067 840556 834819 ] 6683344
+Trigger_L2_to_L1D [75 86 65 64 62 86 67 85 ] 590
+Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+Complete_L2_to_L1 [75 86 65 64 62 86 67 85 ] 590
+Other_GETX [187618 187421 187747 187591 188220 188236 187485 187630 ] 1501948
+Other_GETS [347749 347842 348016 348021 348032 348520 347991 348016 ] 2784187
+Merged_GETS [2 8 4 1 3 2 5 3 ] 28
+Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+Invalidate [0 0 0 0 0 0 0 0 ] 0
+Ack [536086 536738 533148 534239 529862 526324 535299 534139 ] 4265835
+Shared_Ack [49 50 68 68 62 67 49 65 ] 478
+Data [2914 2924 2897 2923 2909 2833 2780 2891 ] 23071
+Shared_Data [1030 1060 1025 1106 1054 1053 1025 1032 ] 8385
+Exclusive_Data [72995 73056 72618 72667 72094 71667 73026 72733 ] 580856
+Writeback_Ack [72578 72718 72261 72244 71629 71208 72536 72377 ] 577551
+Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+All_acks [1071 1104 1085 1164 1106 1109 1064 1088 ] 8791
+All_acks_no_sharers [75868 75937 75456 75532 74951 74444 75767 75569 ] 603524
+Flush_line [0 0 0 0 0 0 0 0 ] 0
+Block_Ack [0 0 0 0 0 0 0 0 ] 0
+
+ - Transitions -
+I  Load [49994 49900 49727 49723 49716 49227 49752 49723 ] 397762
+I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I  Store [26941 27139 26815 26972 26343 26326 27075 26930 ] 214541
+I  L2_Replacement [1480 1453 1399 1468 1490 1446 1500 1426 ] 11662
+I  L1_to_L2 [324 304 306 328 332 308 317 321 ] 2540
+I  Trigger_L2_to_L1D [3 1 1 1 1 1 3 4 ] 15
+I  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+I  Other_GETX [186720 186513 186893 186678 187305 187379 186564 186756 ] 1494808
+I  Other_GETS [346096 346135 346378 346362 346346 346741 346289 346392 ] 2770739
+I  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+I  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+I  Invalidate [0 0 0 0 0 0 0 0 ] 0
+I  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+S  Load [0 2 0 0 0 1 0 1 ] 4
+S  Ifetch [0 0 0 0 0 0 0 0 ] 0
+S  Store [0 0 0 1 0 0 0 0 ] 1
+S  L2_Replacement [2867 2858 2872 2974 2929 2889 2780 2840 ] 23009
+S  L1_to_L2 [2906 2888 2894 3004 2954 2908 2809 2860 ] 23223
+S  Trigger_L2_to_L1D [6 7 1 2 1 2 5 4 ] 28
+S  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+S  Other_GETX [39 33 28 34 30 24 30 21 ] 239
+S  Other_GETS [57 52 56 62 61 71 65 54 ] 478
+S  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+S  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+S  Invalidate [0 0 0 0 0 0 0 0 ] 0
+S  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+O  Load [0 0 0 1 0 0 0 0 ] 1
+O  Ifetch [0 0 0 0 0 0 0 0 ] 0
+O  Store [0 0 0 0 0 0 0 0 ] 0
+O  L2_Replacement [983 1086 1008 1004 1012 1085 1016 989 ] 8183
+O  L1_to_L2 [216 230 238 228 211 237 236 218 ] 1814
+O  Trigger_L2_to_L1D [1 1 2 1 0 2 0 1 ] 8
+O  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+O  Other_GETX [9 7 8 5 5 7 6 4 ] 51
+O  Other_GETS [9 12 15 12 12 11 23 13 ] 107
+O  Merged_GETS [1 2 2 0 2 2 0 1 ] 10
+O  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+O  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+O  Invalidate [0 0 0 0 0 0 0 0 ] 0
+O  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+M  Load [5 8 8 10 6 5 8 9 ] 59
+M  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M  Store [1 2 5 2 2 1 5 4 ] 22
+M  L2_Replacement [45508 45383 45265 45118 45154 44656 45314 45309 ] 361707
+M  L1_to_L2 [46773 46703 46498 46388 46430 45989 46595 46538 ] 371914
+M  Trigger_L2_to_L1D [38 49 37 36 44 53 36 52 ] 345
+M  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+M  Other_GETX [567 512 528 570 562 538 578 536 ] 4391
+M  Other_GETS [991 1088 1015 1008 1016 1092 1017 992 ] 8219
+M  Merged_GETS [0 0 1 0 0 0 2 0 ] 3
+M  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+M  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+M  Invalidate [0 0 0 0 0 0 0 0 ] 0
+M  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM  Load [6 5 1 6 4 0 6 3 ] 31
+MM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM  Store [1 2 3 3 2 1 2 2 ] 16
+MM  L2_Replacement [26087 26250 25988 26122 25463 25467 26206 26079 ] 207662
+MM  L1_to_L2 [26787 26996 26667 26807 26189 26193 26932 26797 ] 213368
+MM  Trigger_L2_to_L1D [27 28 24 24 16 28 23 24 ] 194
+MM  Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0
+MM  Other_GETX [279 354 286 297 312 280 303 307 ] 2418
+MM  Other_GETS [589 548 550 563 583 598 587 563 ] 4581
+MM  Merged_GETS [1 6 1 1 1 0 3 2 ] 15
+MM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+MM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+MM  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MM  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+IR  Load [2 0 0 1 0 0 2 2 ] 7
+IR  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IR  Store [1 1 1 0 1 1 1 2 ] 8
+IR  L1_to_L2 [0 0 0 0 0 0 0 5 ] 5
+IR  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+SR  Load [2 5 1 1 1 1 2 3 ] 16
+SR  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SR  Store [4 2 0 1 0 1 3 1 ] 12
+SR  L1_to_L2 [13 20 14 16 2 0 7 0 ] 72
+SR  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+OR  Load [1 0 1 1 0 2 0 0 ] 5
+OR  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OR  Store [0 1 1 0 0 0 0 1 ] 3
+OR  L1_to_L2 [2 0 10 1 0 0 0 0 ] 13
+OR  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MR  Load [25 33 30 24 28 33 19 36 ] 228
+MR  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MR  Store [13 16 7 12 16 20 17 16 ] 117
+MR  L1_to_L2 [45 115 67 80 92 100 100 102 ] 701
+MR  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MMR  Load [18 19 13 12 12 23 10 14 ] 121
+MMR  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MMR  Store [9 9 11 12 4 5 13 10 ] 73
+MMR  L1_to_L2 [37 47 30 35 16 52 56 39 ] 312
+MMR  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+IM  Load [0 0 0 0 0 0 0 0 ] 0
+IM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM  Store [0 0 0 0 0 0 0 0 ] 0
+IM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+IM  L1_to_L2 [266453 264275 264595 266098 261822 263121 264961 265204 ] 2116529
+IM  Other_GETX [0 1 0 3 2 4 1 1 ] 12
+IM  Other_GETS [1 0 0 4 0 1 1 0 ] 7
+IM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+IM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+IM  Invalidate [0 0 0 0 0 0 0 0 ] 0
+IM  Ack [185233 186408 184012 185296 181158 181006 186013 185175 ] 1474301
+IM  Data [1029 1089 1021 1016 1004 971 989 1060 ] 8179
+IM  Exclusive_Data [25911 26049 25793 25954 25340 25355 26087 25871 ] 206360
+IM  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+SM  Load [0 0 0 0 0 0 0 0 ] 0
+SM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM  Store [0 0 0 0 0 0 0 0 ] 0
+SM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM  L1_to_L2 [3 1 0 2 0 4 5 0 ] 15
+SM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+SM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+SM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+SM  Invalidate [0 0 0 0 0 0 0 0 ] 0
+SM  Ack [28 13 0 14 0 7 21 7 ] 90
+SM  Data [4 2 0 2 0 1 3 1 ] 13
+SM  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+SM  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+OM  Load [0 0 0 0 0 0 0 0 ] 0
+OM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OM  Store [0 0 0 0 0 0 0 0 ] 0
+OM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+OM  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+OM  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+OM  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+OM  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+OM  Invalidate [0 0 0 0 0 0 0 0 ] 0
+OM  Ack [0 7 7 0 0 0 0 7 ] 21
+OM  All_acks [0 0 0 0 0 0 0 0 ] 0
+OM  All_acks_no_sharers [0 1 1 0 0 0 0 1 ] 3
+OM  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+ISM  Load [0 0 0 0 0 0 0 0 ] 0
+ISM  Ifetch [0 0 0 0 0 0 0 0 ] 0
+ISM  Store [0 0 0 0 0 0 0 0 ] 0
+ISM  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+ISM  L1_to_L2 [0 0 0 0 0 0 1 0 ] 1
+ISM  Ack [6 24 17 40 25 16 21 28 ] 177
+ISM  All_acks_no_sharers [1033 1091 1021 1018 1004 972 992 1061 ] 8192
+ISM  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+M_W  Load [0 0 0 0 0 0 0 0 ] 0
+M_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M_W  Store [0 0 0 0 0 0 0 0 ] 0
+M_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+M_W  L1_to_L2 [481 483 546 484 441 445 521 480 ] 3881
+M_W  Ack [1712 1778 1845 1689 1766 1619 1591 1607 ] 13607
+M_W  All_acks_no_sharers [47084 47007 46825 46713 46754 46312 46939 46862 ] 374496
+M_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM_W  Load [0 0 0 0 0 0 0 0 ] 0
+MM_W  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_W  Store [0 0 0 0 0 0 0 0 ] 0
+MM_W  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MM_W  L1_to_L2 [676 844 597 676 621 562 720 718 ] 5414
+MM_W  Ack [2530 2673 2765 2593 2405 2418 2604 2494 ] 20482
+MM_W  All_acks_no_sharers [25911 26049 25793 25954 25340 25355 26087 25871 ] 206360
+MM_W  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+IS  Load [0 0 0 0 0 0 0 0 ] 0
+IS  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IS  Store [0 0 0 0 0 0 0 0 ] 0
+IS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+IS  L1_to_L2 [493437 491159 495278 490401 489823 488117 496177 490336 ] 3934728
+IS  Other_GETX [4 0 4 4 3 2 2 0 ] 19
+IS  Other_GETS [3 1 1 5 8 2 5 0 ] 25
+IS  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+IS  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+IS  Invalidate [0 0 0 0 0 0 0 0 ] 0
+IS  Ack [343571 342587 341454 341364 341509 338211 342059 341851 ] 2732606
+IS  Shared_Ack [45 47 66 60 59 63 46 59 ] 445
+IS  Data [1881 1833 1876 1905 1905 1861 1788 1830 ] 14879
+IS  Shared_Data [1030 1060 1025 1106 1054 1053 1025 1032 ] 8385
+IS  Exclusive_Data [47084 47007 46825 46713 46754 46312 46939 46862 ] 374496
+IS  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+SS  Load [0 0 0 0 0 0 0 0 ] 0
+SS  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SS  Store [0 0 0 0 0 0 0 0 ] 0
+SS  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+SS  L1_to_L2 [745 782 789 848 1035 741 868 853 ] 6661
+SS  Ack [3006 3248 3048 3243 2999 3047 2990 2970 ] 24551
+SS  Shared_Ack [4 3 2 8 3 4 3 6 ] 33
+SS  All_acks [1071 1104 1085 1164 1106 1109 1064 1088 ] 8791
+SS  All_acks_no_sharers [1840 1789 1816 1847 1853 1805 1749 1774 ] 14473
+SS  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+OI  Load [0 0 0 0 0 0 0 0 ] 0
+OI  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OI  Store [0 0 0 0 0 0 0 0 ] 0
+OI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+OI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+OI  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+OI  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+OI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+OI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+OI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+OI  Invalidate [0 0 0 0 0 0 0 0 ] 0
+OI  Writeback_Ack [986 1092 1009 1009 1018 1089 1020 991 ] 8214
+OI  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MI  Load [10 11 12 9 7 10 6 12 ] 77
+MI  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MI  Store [4 7 4 4 6 5 8 6 ] 44
+MI  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MI  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MI  Other_GETX [0 1 0 0 1 2 1 5 ] 10
+MI  Other_GETS [3 6 1 5 6 4 4 2 ] 31
+MI  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+MI  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+MI  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+MI  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MI  Writeback_Ack [71592 71625 71252 71235 70610 70117 71515 71381 ] 569327
+MI  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+II  Load [0 0 0 0 0 0 0 0 ] 0
+II  Ifetch [0 0 0 0 0 0 0 0 ] 0
+II  Store [0 0 0 0 0 0 0 0 ] 0
+II  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+II  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+II  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+II  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+II  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+II  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+II  Invalidate [0 0 0 0 0 0 0 0 ] 0
+II  Writeback_Ack [0 1 0 0 1 2 1 5 ] 10
+II  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+II  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+IT  Load [0 0 0 0 0 0 1 1 ] 2
+IT  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IT  Store [0 0 0 0 0 0 0 0 ] 0
+IT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+IT  L1_to_L2 [4 0 1 4 0 12 0 5 ] 26
+IT  Complete_L2_to_L1 [3 1 1 1 1 1 3 4 ] 15
+
+ST  Load [0 2 1 1 1 0 0 0 ] 5
+ST  Ifetch [0 0 0 0 0 0 0 0 ] 0
+ST  Store [1 1 0 1 0 0 3 1 ] 7
+ST  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+ST  L1_to_L2 [16 28 14 16 2 10 15 7 ] 108
+ST  Complete_L2_to_L1 [6 7 1 2 1 2 5 4 ] 28
+
+OT  Load [1 0 0 1 0 0 0 0 ] 2
+OT  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OT  Store [0 1 1 0 0 0 0 0 ] 2
+OT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+OT  L1_to_L2 [2 0 22 1 0 5 0 0 ] 30
+OT  Complete_L2_to_L1 [1 1 2 1 0 2 0 1 ] 8
+
+MT  Load [10 17 12 12 13 12 8 17 ] 101
+MT  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MT  Store [5 7 2 7 8 8 10 11 ] 58
+MT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MT  L1_to_L2 [154 160 108 140 148 156 141 241 ] 1248
+MT  Complete_L2_to_L1 [38 49 37 36 44 53 36 52 ] 345
+
+MMT  Load [9 10 3 6 3 10 2 5 ] 48
+MMT  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MMT  Store [4 3 3 4 2 2 8 3 ] 29
+MMT  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MMT  L1_to_L2 [171 79 60 102 32 107 95 95 ] 741
+MMT  Complete_L2_to_L1 [27 28 24 24 16 28 23 24 ] 194
+
+MI_F  Load [0 0 0 0 0 0 0 0 ] 0
+MI_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MI_F  Store [0 0 0 0 0 0 0 0 ] 0
+MI_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MI_F  Writeback_Ack [0 0 0 0 0 0 0 0 ] 0
+MI_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM_F  Load [0 0 0 0 0 0 0 0 ] 0
+MM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_F  Store [0 0 0 0 0 0 0 0 ] 0
+MM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+MM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+MM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+MM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+MM_F  All_acks [0 0 0 0 0 0 0 0 ] 0
+MM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+MM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+MM_F  Block_Ack [0 0 0 0 0 0 0 0 ] 0
+
+IM_F  Load [0 0 0 0 0 0 0 0 ] 0
+IM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+IM_F  Store [0 0 0 0 0 0 0 0 ] 0
+IM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+IM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+IM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+IM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+IM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+IM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+IM_F  Data [0 0 0 0 0 0 0 0 ] 0
+IM_F  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+IM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+ISM_F  Load [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Store [0 0 0 0 0 0 0 0 ] 0
+ISM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+ISM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+ISM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+ISM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+SM_F  Load [0 0 0 0 0 0 0 0 ] 0
+SM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+SM_F  Store [0 0 0 0 0 0 0 0 ] 0
+SM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+SM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+SM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+SM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+SM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+SM_F  Data [0 0 0 0 0 0 0 0 ] 0
+SM_F  Exclusive_Data [0 0 0 0 0 0 0 0 ] 0
+SM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+OM_F  Load [0 0 0 0 0 0 0 0 ] 0
+OM_F  Ifetch [0 0 0 0 0 0 0 0 ] 0
+OM_F  Store [0 0 0 0 0 0 0 0 ] 0
+OM_F  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+OM_F  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETX [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Merged_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0
+OM_F  NC_DMA_GETS [0 0 0 0 0 0 0 0 ] 0
+OM_F  Invalidate [0 0 0 0 0 0 0 0 ] 0
+OM_F  Ack [0 0 0 0 0 0 0 0 ] 0
+OM_F  All_acks [0 0 0 0 0 0 0 0 ] 0
+OM_F  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+OM_F  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+MM_WF  Load [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Ifetch [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Store [0 0 0 0 0 0 0 0 ] 0
+MM_WF  L2_Replacement [0 0 0 0 0 0 0 0 ] 0
+MM_WF  L1_to_L2 [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Ack [0 0 0 0 0 0 0 0 ] 0
+MM_WF  All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0
+MM_WF  Flush_line [0 0 0 0 0 0 0 0 ] 0
+
+Cache Stats: system.l1_cntrl1.L1IcacheMemory
+  system.l1_cntrl1.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl1.L1DcacheMemory
+  system.l1_cntrl1.L1DcacheMemory_total_misses: 75641
+  system.l1_cntrl1.L1DcacheMemory_total_demand_misses: 75641
+  system.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L1DcacheMemory_request_type_LD:   65.1578%
+  system.l1_cntrl1.L1DcacheMemory_request_type_ST:   34.8422%
+
+  system.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor:   75641    100%
+
+Cache Stats: system.l1_cntrl1.L2cacheMemory
+  system.l1_cntrl1.L2cacheMemory_total_misses: 75641
+  system.l1_cntrl1.L2cacheMemory_total_demand_misses: 75641
+  system.l1_cntrl1.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.L2cacheMemory_request_type_LD:   65.1578%
+  system.l1_cntrl1.L2cacheMemory_request_type_ST:   34.8422%
+
+  system.l1_cntrl1.L2cacheMemory_access_mode_type_Supervisor:   75641    100%
+
+Cache Stats: system.l1_cntrl2.L1IcacheMemory
+  system.l1_cntrl2.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl2.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl2.L1DcacheMemory
+  system.l1_cntrl2.L1DcacheMemory_total_misses: 76900
+  system.l1_cntrl2.L1DcacheMemory_total_demand_misses: 76900
+  system.l1_cntrl2.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl2.L1DcacheMemory_request_type_LD:   64.7425%
+  system.l1_cntrl2.L1DcacheMemory_request_type_ST:   35.2575%
+
+  system.l1_cntrl2.L1DcacheMemory_access_mode_type_Supervisor:   76900    100%
+
+Cache Stats: system.l1_cntrl2.L2cacheMemory
+  system.l1_cntrl2.L2cacheMemory_total_misses: 76900
+  system.l1_cntrl2.L2cacheMemory_total_demand_misses: 76900
+  system.l1_cntrl2.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl2.L2cacheMemory_request_type_LD:   64.7425%
+  system.l1_cntrl2.L2cacheMemory_request_type_ST:   35.2575%
+
+  system.l1_cntrl2.L2cacheMemory_access_mode_type_Supervisor:   76900    100%
+
+Cache Stats: system.l1_cntrl3.L1IcacheMemory
+  system.l1_cntrl3.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl3.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl3.L1DcacheMemory
+  system.l1_cntrl3.L1DcacheMemory_total_misses: 76744
+  system.l1_cntrl3.L1DcacheMemory_total_demand_misses: 76744
+  system.l1_cntrl3.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl3.L1DcacheMemory_request_type_LD:   64.865%
+  system.l1_cntrl3.L1DcacheMemory_request_type_ST:   35.135%
+
+  system.l1_cntrl3.L1DcacheMemory_access_mode_type_Supervisor:   76744    100%
+
+Cache Stats: system.l1_cntrl3.L2cacheMemory
+  system.l1_cntrl3.L2cacheMemory_total_misses: 76744
+  system.l1_cntrl3.L2cacheMemory_total_demand_misses: 76744
+  system.l1_cntrl3.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl3.L2cacheMemory_request_type_LD:   64.865%
+  system.l1_cntrl3.L2cacheMemory_request_type_ST:   35.135%
+
+  system.l1_cntrl3.L2cacheMemory_access_mode_type_Supervisor:   76744    100%
+
+Cache Stats: system.l1_cntrl4.L1IcacheMemory
+  system.l1_cntrl4.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl4.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl4.L1DcacheMemory
+  system.l1_cntrl4.L1DcacheMemory_total_misses: 77017
+  system.l1_cntrl4.L1DcacheMemory_total_demand_misses: 77017
+  system.l1_cntrl4.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl4.L1DcacheMemory_request_type_LD:   64.9779%
+  system.l1_cntrl4.L1DcacheMemory_request_type_ST:   35.0221%
+
+  system.l1_cntrl4.L1DcacheMemory_access_mode_type_Supervisor:   77017    100%
+
+Cache Stats: system.l1_cntrl4.L2cacheMemory
+  system.l1_cntrl4.L2cacheMemory_total_misses: 77017
+  system.l1_cntrl4.L2cacheMemory_total_demand_misses: 77017
+  system.l1_cntrl4.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl4.L2cacheMemory_request_type_LD:   64.9779%
+  system.l1_cntrl4.L2cacheMemory_request_type_ST:   35.0221%
+
+  system.l1_cntrl4.L2cacheMemory_access_mode_type_Supervisor:   77017    100%
+
+Cache Stats: system.l1_cntrl5.L1IcacheMemory
+  system.l1_cntrl5.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl5.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl5.L1DcacheMemory
+  system.l1_cntrl5.L1DcacheMemory_total_misses: 77129
+  system.l1_cntrl5.L1DcacheMemory_total_demand_misses: 77129
+  system.l1_cntrl5.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl5.L1DcacheMemory_request_type_LD:   64.7707%
+  system.l1_cntrl5.L1DcacheMemory_request_type_ST:   35.2293%
+
+  system.l1_cntrl5.L1DcacheMemory_access_mode_type_Supervisor:   77129    100%
+
+Cache Stats: system.l1_cntrl5.L2cacheMemory
+  system.l1_cntrl5.L2cacheMemory_total_misses: 77129
+  system.l1_cntrl5.L2cacheMemory_total_demand_misses: 77129
+  system.l1_cntrl5.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl5.L2cacheMemory_request_type_LD:   64.7707%
+  system.l1_cntrl5.L2cacheMemory_request_type_ST:   35.2293%
+
+  system.l1_cntrl5.L2cacheMemory_access_mode_type_Supervisor:   77129    100%
+
+Cache Stats: system.l1_cntrl6.L1IcacheMemory
+  system.l1_cntrl6.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl6.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl6.L1DcacheMemory
+  system.l1_cntrl6.L1DcacheMemory_total_misses: 76609
+  system.l1_cntrl6.L1DcacheMemory_total_demand_misses: 76609
+  system.l1_cntrl6.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl6.L1DcacheMemory_request_type_LD:   64.9689%
+  system.l1_cntrl6.L1DcacheMemory_request_type_ST:   35.0311%
+
+  system.l1_cntrl6.L1DcacheMemory_access_mode_type_Supervisor:   76609    100%
+
+Cache Stats: system.l1_cntrl6.L2cacheMemory
+  system.l1_cntrl6.L2cacheMemory_total_misses: 76609
+  system.l1_cntrl6.L2cacheMemory_total_demand_misses: 76609
+  system.l1_cntrl6.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl6.L2cacheMemory_request_type_LD:   64.9689%
+  system.l1_cntrl6.L2cacheMemory_request_type_ST:   35.0311%
+
+  system.l1_cntrl6.L2cacheMemory_access_mode_type_Supervisor:   76609    100%
+
+Cache Stats: system.l1_cntrl7.L1IcacheMemory
+  system.l1_cntrl7.L1IcacheMemory_total_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_demand_misses: 0
+  system.l1_cntrl7.L1IcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1IcacheMemory_total_hw_prefetches: 0
+
+
+Cache Stats: system.l1_cntrl7.L1DcacheMemory
+  system.l1_cntrl7.L1DcacheMemory_total_misses: 76762
+  system.l1_cntrl7.L1DcacheMemory_total_demand_misses: 76762
+  system.l1_cntrl7.L1DcacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L1DcacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl7.L1DcacheMemory_request_type_LD:   64.8276%
+  system.l1_cntrl7.L1DcacheMemory_request_type_ST:   35.1724%
+
+  system.l1_cntrl7.L1DcacheMemory_access_mode_type_Supervisor:   76762    100%
+
+Cache Stats: system.l1_cntrl7.L2cacheMemory
+  system.l1_cntrl7.L2cacheMemory_total_misses: 76762
+  system.l1_cntrl7.L2cacheMemory_total_demand_misses: 76762
+  system.l1_cntrl7.L2cacheMemory_total_prefetches: 0
+  system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl7.L2cacheMemory_request_type_LD:   64.8276%
+  system.l1_cntrl7.L2cacheMemory_request_type_ST:   35.1724%
+
+  system.l1_cntrl7.L2cacheMemory_access_mode_type_Supervisor:   76762    100%
+
+Cache Stats: system.dir_cntrl0.probeFilter
+  system.dir_cntrl0.probeFilter_total_misses: 0
+  system.dir_cntrl0.probeFilter_total_demand_misses: 0
+  system.dir_cntrl0.probeFilter_total_prefetches: 0
+  system.dir_cntrl0.probeFilter_total_sw_prefetches: 0
+  system.dir_cntrl0.probeFilter_total_hw_prefetches: 0
+
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 804704
+  memory_reads: 592481
+  memory_writes: 212202
+  memory_refreshes: 39743
+  memory_total_request_delays: 51359262
+  memory_delays_per_request: 63.8238
+  memory_delays_in_input_queue: 641361
+  memory_delays_behind_head_of_bank_queue: 21004692
+  memory_delays_stalled_at_head_of_bank_queue: 29713209
+  memory_stalls_for_bank_busy: 4481481
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 7557465
+  memory_stalls_for_arbitration: 6067058
+  memory_stalls_for_bus: 8226319
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 2034883
+  memory_stalls_for_read_read_turnaround: 1346003
+  accesses_per_bank: 25333  25087  25174  25408  25390  25300  25486  25224  25408  25202  25227  25301  24969  24999  25175  24978  25048  25162  25177  25055  25180  25093  25154  25003  25003  24677  25093  24719  24960  25241  25333  25145  
+
+ --- Directory ---
+ - Event Counts -
+GETX [217788 ] 217788
+GETS [403728 ] 403728
+PUT [577768 ] 577768
+Unblock [10 ] 10
+UnblockS [23264 ] 23264
+UnblockM [589050 ] 589050
+Writeback_Clean [8115 ] 8115
+Writeback_Dirty [99 ] 99
+Writeback_Exclusive_Clean [357214 ] 357214
+Writeback_Exclusive_Dirty [212111 ] 212111
+Pf_Replacement [0 ] 0
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [592476 ] 592476
+Memory_Ack [212202 ] 212202
+Ack [0 ] 0
+Shared_Ack [0 ] 0
+Shared_Data [0 ] 0
+Data [0 ] 0
+Exclusive_Data [0 ] 0
+All_acks_and_shared_data [0 ] 0
+All_acks_and_owner_data [0 ] 0
+All_acks_and_data_no_sharers [0 ] 0
+All_Unblocks [28 ] 28
+GETF [0 ] 0
+PUTF [0 ] 0
+
+ - Transitions -
+NX  GETX [54 ] 54
+NX  GETS [107 ] 107
+NX  PUT [8224 ] 8224
+NX  Pf_Replacement [0 ] 0
+NX  DMA_READ [0 ] 0
+NX  DMA_WRITE [0 ] 0
+NX  GETF [0 ] 0
+
+NO  GETX [6819 ] 6819
+NO  GETS [12831 ] 12831
+NO  PUT [569327 ] 569327
+NO  Pf_Replacement [0 ] 0
+NO  DMA_READ [0 ] 0
+NO  DMA_WRITE [0 ] 0
+NO  GETF [0 ] 0
+
+S  GETX [0 ] 0
+S  GETS [0 ] 0
+S  PUT [0 ] 0
+S  Pf_Replacement [0 ] 0
+S  DMA_READ [0 ] 0
+S  DMA_WRITE [0 ] 0
+S  GETF [0 ] 0
+
+O  GETX [8131 ] 8131
+O  GETS [14879 ] 14879
+O  PUT [0 ] 0
+O  Pf_Replacement [0 ] 0
+O  DMA_READ [0 ] 0
+O  DMA_WRITE [0 ] 0
+O  GETF [0 ] 0
+
+E  GETX [199560 ] 199560
+E  GETS [369924 ] 369924
+E  PUT [0 ] 0
+E  DMA_READ [0 ] 0
+E  DMA_WRITE [0 ] 0
+E  GETF [0 ] 0
+
+O_R  GETX [0 ] 0
+O_R  GETS [0 ] 0
+O_R  PUT [0 ] 0
+O_R  Pf_Replacement [0 ] 0
+O_R  DMA_READ [0 ] 0
+O_R  DMA_WRITE [0 ] 0
+O_R  Ack [0 ] 0
+O_R  All_acks_and_data_no_sharers [0 ] 0
+O_R  GETF [0 ] 0
+
+S_R  GETX [0 ] 0
+S_R  GETS [0 ] 0
+S_R  PUT [0 ] 0
+S_R  Pf_Replacement [0 ] 0
+S_R  DMA_READ [0 ] 0
+S_R  DMA_WRITE [0 ] 0
+S_R  Ack [0 ] 0
+S_R  Data [0 ] 0
+S_R  All_acks_and_data_no_sharers [0 ] 0
+S_R  GETF [0 ] 0
+
+NO_R  GETX [0 ] 0
+NO_R  GETS [0 ] 0
+NO_R  PUT [0 ] 0
+NO_R  Pf_Replacement [0 ] 0
+NO_R  DMA_READ [0 ] 0
+NO_R  DMA_WRITE [0 ] 0
+NO_R  Ack [0 ] 0
+NO_R  Data [0 ] 0
+NO_R  Exclusive_Data [0 ] 0
+NO_R  All_acks_and_data_no_sharers [0 ] 0
+NO_R  GETF [0 ] 0
+
+NO_B  GETX [18 ] 18
+NO_B  GETS [28 ] 28
+NO_B  PUT [217 ] 217
+NO_B  UnblockS [8342 ] 8342
+NO_B  UnblockM [589019 ] 589019
+NO_B  Pf_Replacement [0 ] 0
+NO_B  DMA_READ [0 ] 0
+NO_B  DMA_WRITE [0 ] 0
+NO_B  GETF [0 ] 0
+
+NO_B_X  GETX [0 ] 0
+NO_B_X  GETS [0 ] 0
+NO_B_X  PUT [0 ] 0
+NO_B_X  UnblockS [5 ] 5
+NO_B_X  UnblockM [13 ] 13
+NO_B_X  Pf_Replacement [0 ] 0
+NO_B_X  DMA_READ [0 ] 0
+NO_B_X  DMA_WRITE [0 ] 0
+NO_B_X  GETF [0 ] 0
+
+NO_B_S  GETX [0 ] 0
+NO_B_S  GETS [0 ] 0
+NO_B_S  PUT [0 ] 0
+NO_B_S  UnblockS [10 ] 10
+NO_B_S  UnblockM [18 ] 18
+NO_B_S  Pf_Replacement [0 ] 0
+NO_B_S  DMA_READ [0 ] 0
+NO_B_S  DMA_WRITE [0 ] 0
+NO_B_S  GETF [0 ] 0
+
+NO_B_S_W  GETX [0 ] 0
+NO_B_S_W  GETS [0 ] 0
+NO_B_S_W  PUT [0 ] 0
+NO_B_S_W  UnblockS [28 ] 28
+NO_B_S_W  Pf_Replacement [0 ] 0
+NO_B_S_W  DMA_READ [0 ] 0
+NO_B_S_W  DMA_WRITE [0 ] 0
+NO_B_S_W  All_Unblocks [28 ] 28
+NO_B_S_W  GETF [0 ] 0
+
+O_B  GETX [0 ] 0
+O_B  GETS [0 ] 0
+O_B  PUT [0 ] 0
+O_B  UnblockS [14879 ] 14879
+O_B  UnblockM [0 ] 0
+O_B  Pf_Replacement [0 ] 0
+O_B  DMA_READ [0 ] 0
+O_B  DMA_WRITE [0 ] 0
+O_B  GETF [0 ] 0
+
+NO_B_W  GETX [2001 ] 2001
+NO_B_W  GETS [3732 ] 3732
+NO_B_W  PUT [0 ] 0
+NO_B_W  UnblockS [0 ] 0
+NO_B_W  UnblockM [0 ] 0
+NO_B_W  Pf_Replacement [0 ] 0
+NO_B_W  DMA_READ [0 ] 0
+NO_B_W  DMA_WRITE [0 ] 0
+NO_B_W  Memory_Data [577597 ] 577597
+NO_B_W  GETF [0 ] 0
+
+O_B_W  GETX [51 ] 51
+O_B_W  GETS [90 ] 90
+O_B_W  PUT [0 ] 0
+O_B_W  UnblockS [0 ] 0
+O_B_W  Pf_Replacement [0 ] 0
+O_B_W  DMA_READ [0 ] 0
+O_B_W  DMA_WRITE [0 ] 0
+O_B_W  Memory_Data [14879 ] 14879
+O_B_W  GETF [0 ] 0
+
+NO_W  GETX [0 ] 0
+NO_W  GETS [0 ] 0
+NO_W  PUT [0 ] 0
+NO_W  Pf_Replacement [0 ] 0
+NO_W  DMA_READ [0 ] 0
+NO_W  DMA_WRITE [0 ] 0
+NO_W  Memory_Data [0 ] 0
+NO_W  GETF [0 ] 0
+
+O_W  GETX [0 ] 0
+O_W  GETS [0 ] 0
+O_W  PUT [0 ] 0
+O_W  Pf_Replacement [0 ] 0
+O_W  DMA_READ [0 ] 0
+O_W  DMA_WRITE [0 ] 0
+O_W  Memory_Data [0 ] 0
+O_W  GETF [0 ] 0
+
+NO_DW_B_W  GETX [0 ] 0
+NO_DW_B_W  GETS [0 ] 0
+NO_DW_B_W  PUT [0 ] 0
+NO_DW_B_W  Pf_Replacement [0 ] 0
+NO_DW_B_W  DMA_READ [0 ] 0
+NO_DW_B_W  DMA_WRITE [0 ] 0
+NO_DW_B_W  Ack [0 ] 0
+NO_DW_B_W  Data [0 ] 0
+NO_DW_B_W  Exclusive_Data [0 ] 0
+NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
+NO_DW_B_W  GETF [0 ] 0
+
+NO_DR_B_W  GETX [0 ] 0
+NO_DR_B_W  GETS [0 ] 0
+NO_DR_B_W  PUT [0 ] 0
+NO_DR_B_W  Pf_Replacement [0 ] 0
+NO_DR_B_W  DMA_READ [0 ] 0
+NO_DR_B_W  DMA_WRITE [0 ] 0
+NO_DR_B_W  Memory_Data [0 ] 0
+NO_DR_B_W  Ack [0 ] 0
+NO_DR_B_W  Shared_Ack [0 ] 0
+NO_DR_B_W  Shared_Data [0 ] 0
+NO_DR_B_W  Data [0 ] 0
+NO_DR_B_W  Exclusive_Data [0 ] 0
+NO_DR_B_W  GETF [0 ] 0
+
+NO_DR_B_D  GETX [0 ] 0
+NO_DR_B_D  GETS [0 ] 0
+NO_DR_B_D  PUT [0 ] 0
+NO_DR_B_D  Pf_Replacement [0 ] 0
+NO_DR_B_D  DMA_READ [0 ] 0
+NO_DR_B_D  DMA_WRITE [0 ] 0
+NO_DR_B_D  Ack [0 ] 0
+NO_DR_B_D  Shared_Ack [0 ] 0
+NO_DR_B_D  Shared_Data [0 ] 0
+NO_DR_B_D  Data [0 ] 0
+NO_DR_B_D  Exclusive_Data [0 ] 0
+NO_DR_B_D  All_acks_and_shared_data [0 ] 0
+NO_DR_B_D  All_acks_and_owner_data [0 ] 0
+NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B_D  GETF [0 ] 0
+
+NO_DR_B  GETX [0 ] 0
+NO_DR_B  GETS [0 ] 0
+NO_DR_B  PUT [0 ] 0
+NO_DR_B  Pf_Replacement [0 ] 0
+NO_DR_B  DMA_READ [0 ] 0
+NO_DR_B  DMA_WRITE [0 ] 0
+NO_DR_B  Ack [0 ] 0
+NO_DR_B  Shared_Ack [0 ] 0
+NO_DR_B  Shared_Data [0 ] 0
+NO_DR_B  Data [0 ] 0
+NO_DR_B  Exclusive_Data [0 ] 0
+NO_DR_B  All_acks_and_shared_data [0 ] 0
+NO_DR_B  All_acks_and_owner_data [0 ] 0
+NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
+NO_DR_B  GETF [0 ] 0
+
+NO_DW_W  GETX [0 ] 0
+NO_DW_W  GETS [0 ] 0
+NO_DW_W  PUT [0 ] 0
+NO_DW_W  Pf_Replacement [0 ] 0
+NO_DW_W  DMA_READ [0 ] 0
+NO_DW_W  DMA_WRITE [0 ] 0
+NO_DW_W  Memory_Ack [0 ] 0
+NO_DW_W  GETF [0 ] 0
+
+O_DR_B_W  GETX [0 ] 0
+O_DR_B_W  GETS [0 ] 0
+O_DR_B_W  PUT [0 ] 0
+O_DR_B_W  Pf_Replacement [0 ] 0
+O_DR_B_W  DMA_READ [0 ] 0
+O_DR_B_W  DMA_WRITE [0 ] 0
+O_DR_B_W  Memory_Data [0 ] 0
+O_DR_B_W  Ack [0 ] 0
+O_DR_B_W  Shared_Ack [0 ] 0
+O_DR_B_W  GETF [0 ] 0
+
+O_DR_B  GETX [0 ] 0
+O_DR_B  GETS [0 ] 0
+O_DR_B  PUT [0 ] 0
+O_DR_B  Pf_Replacement [0 ] 0
+O_DR_B  DMA_READ [0 ] 0
+O_DR_B  DMA_WRITE [0 ] 0
+O_DR_B  Ack [0 ] 0
+O_DR_B  Shared_Ack [0 ] 0
+O_DR_B  All_acks_and_owner_data [0 ] 0
+O_DR_B  All_acks_and_data_no_sharers [0 ] 0
+O_DR_B  GETF [0 ] 0
+
+WB  GETX [94 ] 94
+WB  GETS [184 ] 184
+WB  PUT [0 ] 0
+WB  Unblock [10 ] 10
+WB  Writeback_Clean [8115 ] 8115
+WB  Writeback_Dirty [99 ] 99
+WB  Writeback_Exclusive_Clean [357214 ] 357214
+WB  Writeback_Exclusive_Dirty [212111 ] 212111
+WB  Pf_Replacement [0 ] 0
+WB  DMA_READ [0 ] 0
+WB  DMA_WRITE [0 ] 0
+WB  GETF [0 ] 0
+
+WB_O_W  GETX [0 ] 0
+WB_O_W  GETS [1 ] 1
+WB_O_W  PUT [0 ] 0
+WB_O_W  Pf_Replacement [0 ] 0
+WB_O_W  DMA_READ [0 ] 0
+WB_O_W  DMA_WRITE [0 ] 0
+WB_O_W  Memory_Ack [99 ] 99
+WB_O_W  GETF [0 ] 0
+
+WB_E_W  GETX [1060 ] 1060
+WB_E_W  GETS [1952 ] 1952
+WB_E_W  PUT [0 ] 0
+WB_E_W  Pf_Replacement [0 ] 0
+WB_E_W  DMA_READ [0 ] 0
+WB_E_W  DMA_WRITE [0 ] 0
+WB_E_W  Memory_Ack [212103 ] 212103
+WB_E_W  GETF [0 ] 0
+
+NO_F  GETX [0 ] 0
+NO_F  GETS [0 ] 0
+NO_F  PUT [0 ] 0
+NO_F  UnblockM [0 ] 0
+NO_F  Pf_Replacement [0 ] 0
+NO_F  GETF [0 ] 0
+NO_F  PUTF [0 ] 0
+
+NO_F_W  GETX [0 ] 0
+NO_F_W  GETS [0 ] 0
+NO_F_W  PUT [0 ] 0
+NO_F_W  Pf_Replacement [0 ] 0
+NO_F_W  DMA_READ [0 ] 0
+NO_F_W  DMA_WRITE [0 ] 0
+NO_F_W  Memory_Data [0 ] 0
+NO_F_W  GETF [0 ] 0
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
new file mode 100755
index 000000000..00cab8c91
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr
@@ -0,0 +1,74 @@
+system.cpu2: completed 10000 read, 5409 write accesses @1880159
+system.cpu1: completed 10000 read, 5299 write accesses @1882778
+system.cpu3: completed 10000 read, 5366 write accesses @1911159
+system.cpu7: completed 10000 read, 5649 write accesses @1917229
+system.cpu4: completed 10000 read, 5408 write accesses @1931479
+system.cpu0: completed 10000 read, 5286 write accesses @1950089
+system.cpu5: completed 10000 read, 5459 write accesses @1964580
+system.cpu6: completed 10000 read, 5463 write accesses @1972179
+system.cpu7: completed 20000 read, 10897 write accesses @3761849
+system.cpu2: completed 20000 read, 10831 write accesses @3800179
+system.cpu3: completed 20000 read, 10626 write accesses @3825708
+system.cpu4: completed 20000 read, 10811 write accesses @3842889
+system.cpu6: completed 20000 read, 10715 write accesses @3849899
+system.cpu1: completed 20000 read, 10702 write accesses @3854688
+system.cpu0: completed 20000 read, 10477 write accesses @3872776
+system.cpu5: completed 20000 read, 10977 write accesses @3877309
+system.cpu7: completed 30000 read, 16346 write accesses @5687720
+system.cpu2: completed 30000 read, 16162 write accesses @5688839
+system.cpu3: completed 30000 read, 16041 write accesses @5736199
+system.cpu4: completed 30000 read, 16234 write accesses @5749298
+system.cpu1: completed 30000 read, 15966 write accesses @5776163
+system.cpu5: completed 30000 read, 16541 write accesses @5808819
+system.cpu0: completed 30000 read, 15936 write accesses @5814209
+system.cpu6: completed 30000 read, 16131 write accesses @5822319
+system.cpu7: completed 40000 read, 21881 write accesses @7635659
+system.cpu2: completed 40000 read, 21509 write accesses @7644271
+system.cpu4: completed 40000 read, 21826 write accesses @7644629
+system.cpu3: completed 40000 read, 21340 write accesses @7664288
+system.cpu5: completed 40000 read, 21864 write accesses @7689069
+system.cpu1: completed 40000 read, 21331 write accesses @7720199
+system.cpu6: completed 40000 read, 21482 write accesses @7766439
+system.cpu0: completed 40000 read, 21218 write accesses @7770859
+system.cpu2: completed 50000 read, 26843 write accesses @9567509
+system.cpu4: completed 50000 read, 27341 write accesses @9587739
+system.cpu7: completed 50000 read, 27298 write accesses @9594538
+system.cpu5: completed 50000 read, 27297 write accesses @9615250
+system.cpu3: completed 50000 read, 26951 write accesses @9629869
+system.cpu1: completed 50000 read, 26588 write accesses @9668459
+system.cpu6: completed 50000 read, 26930 write accesses @9674989
+system.cpu0: completed 50000 read, 26761 write accesses @9717328
+system.cpu2: completed 60000 read, 32089 write accesses @11434469
+system.cpu4: completed 60000 read, 32753 write accesses @11460881
+system.cpu5: completed 60000 read, 32638 write accesses @11489388
+system.cpu7: completed 60000 read, 32763 write accesses @11509798
+system.cpu3: completed 60000 read, 32313 write accesses @11569698
+system.cpu0: completed 60000 read, 32096 write accesses @11591548
+system.cpu6: completed 60000 read, 32349 write accesses @11615831
+system.cpu1: completed 60000 read, 31983 write accesses @11646079
+system.cpu2: completed 70000 read, 37474 write accesses @13359218
+system.cpu4: completed 70000 read, 38151 write accesses @13362099
+system.cpu5: completed 70000 read, 38045 write accesses @13387329
+system.cpu7: completed 70000 read, 38043 write accesses @13412879
+system.cpu0: completed 70000 read, 37368 write accesses @13497038
+system.cpu3: completed 70000 read, 37733 write accesses @13497379
+system.cpu6: completed 70000 read, 37699 write accesses @13552039
+system.cpu1: completed 70000 read, 37272 write accesses @13629039
+system.cpu5: completed 80000 read, 43265 write accesses @15246808
+system.cpu4: completed 80000 read, 43470 write accesses @15247621
+system.cpu2: completed 80000 read, 42926 write accesses @15318609
+system.cpu7: completed 80000 read, 43420 write accesses @15337379
+system.cpu3: completed 80000 read, 42961 write accesses @15362279
+system.cpu0: completed 80000 read, 42538 write accesses @15399778
+system.cpu6: completed 80000 read, 42992 write accesses @15485249
+system.cpu1: completed 80000 read, 42648 write accesses @15573879
+system.cpu4: completed 90000 read, 48820 write accesses @17171059
+system.cpu5: completed 90000 read, 48731 write accesses @17183141
+system.cpu7: completed 90000 read, 48795 write accesses @17265336
+system.cpu2: completed 90000 read, 48519 write accesses @17267129
+system.cpu3: completed 90000 read, 48352 write accesses @17313919
+system.cpu0: completed 90000 read, 47888 write accesses @17331279
+system.cpu6: completed 90000 read, 48438 write accesses @17390512
+system.cpu1: completed 90000 read, 48044 write accesses @17499359
+system.cpu5: completed 100000 read, 53983 write accesses @19076439
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
new file mode 100755
index 000000000..8fe5f45d4
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 03:42:19
+gem5 started Jan 23 2012 04:21:49
+gem5 executing on zizzer
+command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 19076439 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
new file mode 100644
index 000000000..38761c37f
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -0,0 +1,47 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.019076                       # Number of seconds simulated
+sim_ticks                                    19076439                       # Number of ticks simulated
+final_tick                                   19076439                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                 177702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347220                       # Number of bytes of host memory used
+host_seconds                                   107.35                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.cpu0.num_reads                           99023                       # number of read accesses completed
+system.cpu0.num_writes                          52778                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           98234                       # number of read accesses completed
+system.cpu1.num_writes                          52491                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           99317                       # number of read accesses completed
+system.cpu2.num_writes                          53653                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           99210                       # number of read accesses completed
+system.cpu3.num_writes                          53360                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                           99715                       # number of read accesses completed
+system.cpu4.num_writes                          54038                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53983                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           98915                       # number of read accesses completed
+system.cpu6.num_writes                          53129                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           99404                       # number of read accesses completed
+system.cpu7.num_writes                          53890                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
new file mode 100644
index 000000000..bcc5fa575
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -0,0 +1,785 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000
+time_sync_spin_threshold=100000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby sys_port_proxy
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.sys_port_proxy.port[0]
+
+[system.cpu0]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.l1_cntrl0.sequencer.port[0]
+
+[system.cpu1]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.l1_cntrl1.sequencer.port[0]
+
+[system.cpu2]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.l1_cntrl2.sequencer.port[0]
+
+[system.cpu3]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.l1_cntrl3.sequencer.port[0]
+
+[system.cpu4]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.l1_cntrl4.sequencer.port[0]
+
+[system.cpu5]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.l1_cntrl5.sequencer.port[0]
+
+[system.cpu6]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.l1_cntrl6.sequencer.port[0]
+
+[system.cpu7]
+type=MemTest
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=0
+progress_interval=10000
+suppress_func_warnings=true
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.l1_cntrl7.sequencer.port[0]
+
+[system.dir_cntrl0]
+type=Directory_Controller
+children=directory memBuffer
+buffer_size=0
+cntrl_id=8
+directory=system.dir_cntrl0.directory
+directory_latency=12
+memBuffer=system.dir_cntrl0.memBuffer
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+transitions_per_cycle=32
+version=0
+
+[system.dir_cntrl0.directory]
+type=RubyDirectoryMemory
+map_levels=4
+numa_high_bit=6
+size=134217728
+use_map=false
+version=0
+
+[system.dir_cntrl0.memBuffer]
+type=RubyMemoryControl
+bank_bit_0=8
+bank_busy_time=11
+bank_queue_size=12
+banks_per_rank=8
+basic_bus_busy_time=2
+dimm_bit_0=12
+dimms_per_channel=2
+mem_bus_cycle_multiplier=10
+mem_ctl_latency=12
+mem_fixed_delay=0
+mem_random_arbitrate=0
+rank_bit_0=11
+rank_rank_delay=1
+ranks_per_dimm=2
+read_write_delay=2
+refresh_period=1560
+tFaw=0
+version=0
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l1_cntrl0]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl0.cacheMemory
+cache_response_latency=12
+cntrl_id=0
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl0.sequencer
+transitions_per_cycle=32
+version=0
+
+[system.l1_cntrl0.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl0.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl0.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl0.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[0]
+port=system.cpu0.test
+
+[system.l1_cntrl1]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl1.cacheMemory
+cache_response_latency=12
+cntrl_id=1
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl1.sequencer
+transitions_per_cycle=32
+version=1
+
+[system.l1_cntrl1.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl1.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl1.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl1.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=1
+physMemPort=system.physmem.port[1]
+port=system.cpu1.test
+
+[system.l1_cntrl2]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl2.cacheMemory
+cache_response_latency=12
+cntrl_id=2
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl2.sequencer
+transitions_per_cycle=32
+version=2
+
+[system.l1_cntrl2.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl2.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl2.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl2.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=2
+physMemPort=system.physmem.port[2]
+port=system.cpu2.test
+
+[system.l1_cntrl3]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl3.cacheMemory
+cache_response_latency=12
+cntrl_id=3
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl3.sequencer
+transitions_per_cycle=32
+version=3
+
+[system.l1_cntrl3.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl3.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl3.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl3.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=3
+physMemPort=system.physmem.port[3]
+port=system.cpu3.test
+
+[system.l1_cntrl4]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl4.cacheMemory
+cache_response_latency=12
+cntrl_id=4
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl4.sequencer
+transitions_per_cycle=32
+version=4
+
+[system.l1_cntrl4.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl4.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl4.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl4.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=4
+physMemPort=system.physmem.port[4]
+port=system.cpu4.test
+
+[system.l1_cntrl5]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl5.cacheMemory
+cache_response_latency=12
+cntrl_id=5
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl5.sequencer
+transitions_per_cycle=32
+version=5
+
+[system.l1_cntrl5.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl5.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl5.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl5.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=5
+physMemPort=system.physmem.port[5]
+port=system.cpu5.test
+
+[system.l1_cntrl6]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl6.cacheMemory
+cache_response_latency=12
+cntrl_id=6
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl6.sequencer
+transitions_per_cycle=32
+version=6
+
+[system.l1_cntrl6.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl6.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl6.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl6.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=6
+physMemPort=system.physmem.port[6]
+port=system.cpu6.test
+
+[system.l1_cntrl7]
+type=L1Cache_Controller
+children=cacheMemory sequencer
+buffer_size=0
+cacheMemory=system.l1_cntrl7.cacheMemory
+cache_response_latency=12
+cntrl_id=7
+issue_latency=2
+number_of_TBEs=256
+recycle_latency=10
+ruby_system=system.ruby
+sequencer=system.l1_cntrl7.sequencer
+transitions_per_cycle=32
+version=7
+
+[system.l1_cntrl7.cacheMemory]
+type=RubyCache
+assoc=2
+is_icache=false
+latency=3
+replacement_policy=PSEUDO_LRU
+size=256
+start_index_bit=6
+
+[system.l1_cntrl7.sequencer]
+type=RubySequencer
+access_phys_mem=false
+dcache=system.l1_cntrl7.cacheMemory
+deadlock_threshold=1000000
+icache=system.l1_cntrl7.cacheMemory
+max_outstanding_requests=16
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=7
+physMemPort=system.physmem.port[7]
+port=system.cpu7.test
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort system.sys_port_proxy.physMemPort
+
+[system.ruby]
+type=RubySystem
+children=network profiler
+block_size_bytes=64
+clock=1
+mem_size=134217728
+no_mem_vec=false
+random_seed=1234
+randomization=false
+stats_filename=ruby.stats
+
+[system.ruby.network]
+type=SimpleNetwork
+children=topology
+adaptive_routing=false
+buffer_size=0
+control_msg_size=8
+endpoint_bandwidth=1000
+number_of_virtual_networks=10
+ruby_system=system.ruby
+topology=system.ruby.network.topology
+
+[system.ruby.network.topology]
+type=Topology
+children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9
+description=Crossbar
+ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8
+int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8
+print_config=false
+routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9
+
+[system.ruby.network.topology.ext_links0]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl0
+int_node=system.ruby.network.topology.routers0
+latency=1
+link_id=0
+weight=1
+
+[system.ruby.network.topology.ext_links1]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl1
+int_node=system.ruby.network.topology.routers1
+latency=1
+link_id=1
+weight=1
+
+[system.ruby.network.topology.ext_links2]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl2
+int_node=system.ruby.network.topology.routers2
+latency=1
+link_id=2
+weight=1
+
+[system.ruby.network.topology.ext_links3]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl3
+int_node=system.ruby.network.topology.routers3
+latency=1
+link_id=3
+weight=1
+
+[system.ruby.network.topology.ext_links4]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl4
+int_node=system.ruby.network.topology.routers4
+latency=1
+link_id=4
+weight=1
+
+[system.ruby.network.topology.ext_links5]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl5
+int_node=system.ruby.network.topology.routers5
+latency=1
+link_id=5
+weight=1
+
+[system.ruby.network.topology.ext_links6]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl6
+int_node=system.ruby.network.topology.routers6
+latency=1
+link_id=6
+weight=1
+
+[system.ruby.network.topology.ext_links7]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.l1_cntrl7
+int_node=system.ruby.network.topology.routers7
+latency=1
+link_id=7
+weight=1
+
+[system.ruby.network.topology.ext_links8]
+type=SimpleExtLink
+bandwidth_factor=16
+ext_node=system.dir_cntrl0
+int_node=system.ruby.network.topology.routers8
+latency=1
+link_id=8
+weight=1
+
+[system.ruby.network.topology.int_links0]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=9
+node_a=system.ruby.network.topology.routers0
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links1]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=10
+node_a=system.ruby.network.topology.routers1
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links2]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=11
+node_a=system.ruby.network.topology.routers2
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links3]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=12
+node_a=system.ruby.network.topology.routers3
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links4]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=13
+node_a=system.ruby.network.topology.routers4
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links5]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=14
+node_a=system.ruby.network.topology.routers5
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links6]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=15
+node_a=system.ruby.network.topology.routers6
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links7]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=16
+node_a=system.ruby.network.topology.routers7
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.int_links8]
+type=SimpleIntLink
+bandwidth_factor=16
+latency=1
+link_id=17
+node_a=system.ruby.network.topology.routers8
+node_b=system.ruby.network.topology.routers9
+weight=1
+
+[system.ruby.network.topology.routers0]
+type=BasicRouter
+router_id=0
+
+[system.ruby.network.topology.routers1]
+type=BasicRouter
+router_id=1
+
+[system.ruby.network.topology.routers2]
+type=BasicRouter
+router_id=2
+
+[system.ruby.network.topology.routers3]
+type=BasicRouter
+router_id=3
+
+[system.ruby.network.topology.routers4]
+type=BasicRouter
+router_id=4
+
+[system.ruby.network.topology.routers5]
+type=BasicRouter
+router_id=5
+
+[system.ruby.network.topology.routers6]
+type=BasicRouter
+router_id=6
+
+[system.ruby.network.topology.routers7]
+type=BasicRouter
+router_id=7
+
+[system.ruby.network.topology.routers8]
+type=BasicRouter
+router_id=8
+
+[system.ruby.network.topology.routers9]
+type=BasicRouter
+router_id=9
+
+[system.ruby.profiler]
+type=RubyProfiler
+all_instructions=false
+hot_lines=false
+num_of_sequencers=8
+ruby_system=system.ruby
+
+[system.sys_port_proxy]
+type=RubyPortProxy
+access_phys_mem=true
+physmem=system.physmem
+ruby_system=system.ruby
+using_network_tester=false
+using_ruby_tester=false
+version=0
+physMemPort=system.physmem.port[8]
+port=system.system_port
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
new file mode 100644
index 000000000..d3193509d
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -0,0 +1,498 @@
+
+================ Begin RubySystem Configuration Print ================
+
+RubySystem config:
+  random_seed: 1234
+  randomization: 0
+  cycle_period: 1
+  block_size_bytes: 64
+  block_size_bits: 6
+  memory_size_bytes: 134217728
+  memory_size_bits: 27
+
+Network Configuration
+---------------------
+network: SIMPLE_NETWORK
+topology: 
+
+virtual_net_0: active, ordered
+virtual_net_1: active, ordered
+virtual_net_2: active, ordered
+virtual_net_3: active, ordered
+virtual_net_4: active, ordered
+virtual_net_5: inactive
+virtual_net_6: inactive
+virtual_net_7: inactive
+virtual_net_8: inactive
+virtual_net_9: inactive
+
+
+Profiler Configuration
+----------------------
+periodic_stats_period: 1000000
+
+================ End RubySystem Configuration Print ================
+
+
+Real time: Jan/23/2012 05:00:08
+
+Profiler Stats
+--------------
+Elapsed_time_in_seconds: 40
+Elapsed_time_in_minutes: 0.666667
+Elapsed_time_in_hours: 0.0111111
+Elapsed_time_in_days: 0.000462963
+
+Virtual_time_in_seconds: 40.57
+Virtual_time_in_minutes: 0.676167
+Virtual_time_in_hours:   0.0112694
+Virtual_time_in_days:    0.00046956
+
+Ruby_current_time: 28725020
+Ruby_start_time: 0
+Ruby_cycles: 28725020
+
+mbytes_resident: 41.0898
+mbytes_total: 338.922
+resident_ratio: 0.121237
+
+ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ]
+
+Busy Controller Counts:
+L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
+
+Directory-0:0  
+
+
+Busy Bank Count:0
+
+sequencer_requests_outstanding: [binsize: 1 max: 16 count: 615998 average: 15.9984 | standard deviation: 0.126895 | 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 615878 ]
+
+All Non-Zero Cycle Demand Cache Accesses
+----------------------------------------
+miss_latency: [binsize: 128 max: 17550 count: 615870 average: 5969.46 | standard deviation: 7116.59 | 0 4 6 6 5 4 5 1 5 4 3 6 4 5 21 31 46 90 169 235 418 648 1027 1394 1760 2694 3780 4717 5558 6535 8753 9589 11125 13750 13954 15292 17133 20395 19978 18654 22068 23938 22152 22290 22426 24096 21689 21471 22547 19077 18860 18264 18773 15923 13248 14135 13631 11388 10257 9512 9377 7381 6802 6677 5240 4722 4293 4074 3235 2564 2639 2296 1833 1614 1375 1233 1052 854 776 591 544 492 453 330 284 288 215 200 140 122 116 82 91 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 128 max: 17550 count: 400035 average: 5968.22 | standard deviation: 1417.97 | 0 4 3 5 3 2 4 1 2 2 1 2 2 4 14 21 27 59 108 148 275 433 688 907 1155 1771 2429 3013 3676 4199 5764 6270 7293 8986 9054 9918 11064 13179 12948 12115 14336 15590 14383 14461 14549 15708 14037 13915 14593 12436 12325 11870 12195 10304 8534 9247 8896 7405 6689 6174 6004 4768 4401 4309 3422 3106 2791 2621 2096 1647 1749 1478 1176 1060 878 801 692 570 497 397 361 314 289 233 190 190 131 126 85 78 64 59 58 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 128 max: 16420 count: 215835 average: 5971.76 | standard deviation: 1418.95 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 7 10 19 31 61 87 143 215 339 487 605 923 1351 1704 1882 2336 2989 3319 3832 4764 4900 5374 6069 7216 7030 6539 7732 8348 7769 7829 7877 8388 7652 7556 7954 6641 6535 6394 6578 5619 4714 4888 4735 3983 3568 3338 3373 2613 2401 2368 1818 1616 1502 1453 1139 917 890 818 657 554 497 432 360 284 279 194 183 178 164 97 94 98 84 74 55 44 52 23 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Directory: [binsize: 128 max: 17550 count: 607509 average: 5975.88 | standard deviation: 7210.5 | 0 4 6 6 5 4 5 1 5 4 2 6 4 5 17 27 42 88 158 222 402 618 977 1328 1698 2630 3655 4589 5430 6369 8536 9419 10886 13519 13647 15042 16854 20026 19684 18343 21765 23626 21819 22017 22137 23782 21417 21230 22311 18836 18644 18063 18598 15763 13119 14010 13517 11272 10178 9410 9289 7324 6756 6627 5186 4688 4257 4046 3210 2538 2620 2281 1809 1600 1365 1221 1045 850 772 587 539 484 451 326 282 287 213 200 140 121 112 80 90 55 52 34 38 32 20 19 15 17 10 8 11 3 5 4 3 1 0 0 1 2 2 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_L1Cache_wCC: [binsize: 64 max: 11892 count: 8361 average: 5503.07 | standard deviation: 1405.32 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 2 2 2 2 1 3 0 2 5 6 7 6 10 6 16 14 19 31 39 27 26 36 23 41 67 58 59 69 63 65 72 94 106 111 94 76 113 126 110 121 152 155 134 116 137 142 173 196 157 137 171 140 153 150 150 162 167 166 135 138 142 147 168 146 131 141 113 128 99 137 136 105 110 106 88 113 83 92 85 75 72 57 65 60 51 63 66 50 39 40 51 51 44 44 31 26 20 26 28 22 29 25 18 16 22 14 12 16 13 12 15 11 12 7 7 8 15 9 5 9 4 6 7 5 4 3 3 1 2 2 3 1 3 2 4 4 1 1 2 2 2 0 1 0 0 2 0 0 0 0 1 0 3 1 1 1 0 1 ]
+miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+imcomplete_wCC_Times: 8361
+miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 7 average:     0 | standard deviation: 0 | 7 ]
+miss_latency_dir_first_response_to_completion: [binsize: 4 max: 539 count: 7 average: 334.714 | standard deviation: 168.608 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+imcomplete_dir_Times: 607502
+miss_latency_LD_Directory: [binsize: 128 max: 17550 count: 394629 average: 5974.59 | standard deviation: 1417.29 | 0 4 3 5 3 2 4 1 2 2 0 2 2 4 12 19 26 58 101 141 268 411 656 862 1113 1732 2355 2930 3601 4101 5626 6152 7140 8833 8863 9755 10888 12929 12755 11909 14133 15388 14160 14288 14352 15497 13858 13765 14436 12280 12181 11739 12073 10206 8456 9180 8819 7329 6645 6110 5948 4735 4371 4278 3389 3086 2766 2599 2081 1630 1735 1469 1159 1055 871 794 686 566 493 394 358 310 288 231 189 189 130 126 85 78 62 58 57 30 29 16 25 20 14 11 10 13 6 4 6 2 3 1 1 0 0 0 1 2 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD_L1Cache_wCC: [binsize: 64 max: 11892 count: 5406 average: 5502.87 | standard deviation: 1389.98 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 0 1 0 1 3 4 6 1 3 4 11 11 12 20 23 22 18 24 18 21 41 33 36 47 39 36 42 56 71 67 63 55 69 84 71 82 98 93 85 78 90 86 118 132 103 90 116 90 106 97 93 109 110 113 88 85 95 102 115 96 79 100 69 81 57 100 89 67 62 82 57 74 55 67 55 43 46 32 35 32 35 42 42 34 22 22 37 27 26 30 18 15 12 18 20 11 14 19 9 11 15 10 10 12 10 5 9 8 10 4 5 4 10 7 2 3 2 5 4 3 4 2 3 1 2 2 2 1 2 1 0 4 0 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 ]
+miss_latency_ST_Directory: [binsize: 128 max: 16420 count: 212880 average: 5978.26 | standard deviation: 1417.67 | 0 0 3 1 2 2 1 0 3 2 2 4 2 1 5 8 16 30 57 81 134 207 321 466 585 898 1300 1659 1829 2268 2910 3267 3746 4686 4784 5287 5966 7097 6929 6434 7632 8238 7659 7729 7785 8285 7559 7465 7875 6556 6463 6324 6525 5557 4663 4830 4698 3943 3533 3300 3341 2589 2385 2349 1797 1602 1491 1447 1129 908 885 812 650 545 494 427 359 284 279 193 181 174 163 95 93 98 83 74 55 43 50 22 33 25 23 18 13 12 6 8 5 4 4 4 5 1 2 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_L1Cache_wCC: [binsize: 64 max: 11673 count: 2955 average: 5503.42 | standard deviation: 1433.2 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 2 0 1 2 2 1 5 7 2 5 3 7 11 16 5 8 12 5 20 26 25 23 22 24 29 30 38 35 44 31 21 44 42 39 39 54 62 49 38 47 56 55 64 54 47 55 50 47 53 57 53 57 53 47 53 47 45 53 50 52 41 44 47 42 37 47 38 48 24 31 39 28 25 30 32 26 25 30 28 16 21 24 16 17 18 14 24 18 14 13 11 8 8 8 11 15 6 9 5 7 4 2 4 3 7 6 3 2 3 2 4 5 2 3 6 2 1 3 2 0 1 0 0 0 0 1 0 1 1 4 0 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 0 2 0 1 ]
+
+All Non-Zero Cycle SW Prefetch Requests
+------------------------------------
+prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+Request vs. RubySystem State Profile
+--------------------------------
+
+
+filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Message Delayed Cycles
+----------------------
+Total_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 | standard deviation: 0.17583 | 1231378 88 178 447 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_1_delay_cycles: [binsize: 1 max: 3 count: 615870 average: 0.000342605 | standard deviation: 0.0243446 | 615732 69 65 4 ]
+  virtual_network_2_delay_cycles: [binsize: 1 max: 22 count: 618018 average: 0.01454 | standard deviation: 0.24705 | 615646 19 113 443 1777 0 0 1 0 0 0 0 1 11 0 0 0 0 3 0 0 0 4 ]
+  virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+  virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
+
+Resource Usage
+--------------
+page_size: 4096
+user_time: 40
+system_time: 0
+page_reclaims: 10928
+page_faults: 0
+swaps: 0
+block_inputs: 0
+block_outputs: 168
+
+Network Stats
+-------------
+
+total_msg_count_Control: 1847643 14781144
+total_msg_count_Data: 1829024 131689728
+total_msg_count_Response_Data: 1847610 133027920
+total_msg_count_Writeback_Control: 1854054 14832432
+total_msgs: 7378331 total_bytes: 294331224
+
+switch_0_inlinks: 2
+switch_0_outlinks: 2
+links_utilized_percent_switch_0: 1.34528
+  links_utilized_percent_switch_0_link_0: 1.34317 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_0_link_1: 1.34738 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_0_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Control: 77138 617104 [ 0 0 77138 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Data: 76420 5502240 [ 0 0 76420 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_0_link_1_Response_Data: 1017 73224 [ 0 0 0 0 1017 0 0 0 0 0 ] base_latency: 1
+
+switch_1_inlinks: 2
+switch_1_outlinks: 2
+links_utilized_percent_switch_1: 1.34599
+  links_utilized_percent_switch_1_link_0: 1.34421 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_1_link_1: 1.34776 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_1_link_0_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_0_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Control: 77201 617608 [ 0 0 77201 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Data: 76436 5503392 [ 0 0 76436 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_1_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
+
+switch_2_inlinks: 2
+switch_2_outlinks: 2
+links_utilized_percent_switch_2: 1.34111
+  links_utilized_percent_switch_2_link_0: 1.33905 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_2_link_1: 1.34318 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_2_link_0_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_0_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Control: 76900 615200 [ 0 0 76900 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Data: 76098 5479056 [ 0 0 76098 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_2_link_1_Response_Data: 1097 78984 [ 0 0 0 0 1097 0 0 0 0 0 ] base_latency: 1
+
+switch_3_inlinks: 2
+switch_3_outlinks: 2
+links_utilized_percent_switch_3: 1.34039
+  links_utilized_percent_switch_3_link_0: 1.33852 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_3_link_1: 1.34225 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_3_link_0_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_0_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Control: 76875 615000 [ 0 0 76875 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Data: 76106 5479632 [ 0 0 76106 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_3_link_1_Response_Data: 1033 74376 [ 0 0 0 0 1033 0 0 0 0 0 ] base_latency: 1
+
+switch_4_inlinks: 2
+switch_4_outlinks: 2
+links_utilized_percent_switch_4: 1.34098
+  links_utilized_percent_switch_4_link_0: 1.33927 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_4_link_1: 1.34269 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_4_link_0_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_0_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Control: 76918 615344 [ 0 0 76918 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Data: 76104 5479488 [ 0 0 76104 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_4_link_1_Response_Data: 1058 76176 [ 0 0 0 0 1058 0 0 0 0 0 ] base_latency: 1
+
+switch_5_inlinks: 2
+switch_5_outlinks: 2
+links_utilized_percent_switch_5: 1.34326
+  links_utilized_percent_switch_5_link_0: 1.34149 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_5_link_1: 1.34504 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_5_link_0_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_0_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Control: 77044 616352 [ 0 0 77044 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Data: 76280 5492160 [ 0 0 76280 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_5_link_1_Response_Data: 1018 73296 [ 0 0 0 0 1018 0 0 0 0 0 ] base_latency: 1
+
+switch_6_inlinks: 2
+switch_6_outlinks: 2
+links_utilized_percent_switch_6: 1.33528
+  links_utilized_percent_switch_6_link_0: 1.33337 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_6_link_1: 1.33719 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_6_link_0_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_0_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Control: 76576 612608 [ 0 0 76576 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Data: 75797 5457384 [ 0 0 75797 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_6_link_1_Response_Data: 1052 75744 [ 0 0 0 0 1052 0 0 0 0 0 ] base_latency: 1
+
+switch_7_inlinks: 2
+switch_7_outlinks: 2
+links_utilized_percent_switch_7: 1.34665
+  links_utilized_percent_switch_7_link_0: 1.34474 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_7_link_1: 1.34856 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_7_link_0_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_0_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Control: 77229 617832 [ 0 0 77229 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Data: 76434 5503248 [ 0 0 76434 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_7_link_1_Response_Data: 1068 76896 [ 0 0 0 0 1068 0 0 0 0 0 ] base_latency: 1
+
+switch_8_inlinks: 2
+switch_8_outlinks: 2
+links_utilized_percent_switch_8: 10.608
+  links_utilized_percent_switch_8_link_0: 10.6231 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_8_link_1: 10.5929 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_8_link_0_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_0_Data: 609674 43896528 [ 0 0 609674 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Response_Data: 607509 43740648 [ 0 0 0 0 607509 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_8_link_1_Writeback_Control: 618018 4944144 [ 0 0 0 618018 0 0 0 0 0 0 ] base_latency: 1
+
+switch_9_inlinks: 9
+switch_9_outlinks: 9
+links_utilized_percent_switch_9: 2.37188
+  links_utilized_percent_switch_9_link_0: 1.34318 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_1: 1.34421 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_2: 1.33905 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_3: 1.33852 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_4: 1.33927 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_5: 1.34149 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_6: 1.33337 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_7: 1.34474 bw: 16000 base_latency: 1
+  links_utilized_percent_switch_9_link_8: 10.6231 bw: 16000 base_latency: 1
+
+  outgoing_messages_switch_9_link_0_Response_Data: 77136 5553792 [ 0 0 0 0 77136 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_0_Writeback_Control: 77433 619464 [ 0 0 0 77433 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Response_Data: 77200 5558400 [ 0 0 0 0 77200 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_1_Writeback_Control: 77452 619616 [ 0 0 0 77452 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Response_Data: 76899 5536728 [ 0 0 0 0 76899 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_2_Writeback_Control: 77195 617560 [ 0 0 0 77195 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Response_Data: 76872 5534784 [ 0 0 0 0 76872 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_3_Writeback_Control: 77134 617072 [ 0 0 0 77134 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Response_Data: 76917 5538024 [ 0 0 0 0 76917 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_4_Writeback_Control: 77161 617288 [ 0 0 0 77161 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Response_Data: 77043 5547096 [ 0 0 0 0 77043 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_5_Writeback_Control: 77297 618376 [ 0 0 0 77297 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Response_Data: 76575 5513400 [ 0 0 0 0 76575 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_6_Writeback_Control: 76846 614768 [ 0 0 0 76846 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Response_Data: 77228 5560416 [ 0 0 0 0 77228 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_7_Writeback_Control: 77500 620000 [ 0 0 0 77500 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Control: 615881 4927048 [ 0 0 615881 0 0 0 0 0 0 0 ] base_latency: 1
+  outgoing_messages_switch_9_link_8_Data: 609675 43896600 [ 0 0 609675 0 0 0 0 0 0 0 ] base_latency: 1
+
+Cache Stats: system.l1_cntrl0.cacheMemory
+  system.l1_cntrl0.cacheMemory_total_misses: 77138
+  system.l1_cntrl0.cacheMemory_total_demand_misses: 77138
+  system.l1_cntrl0.cacheMemory_total_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl0.cacheMemory_request_type_LD:   65.2065%
+  system.l1_cntrl0.cacheMemory_request_type_ST:   34.7935%
+
+  system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor:   77138    100%
+
+ --- L1Cache ---
+ - Event Counts -
+Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
+Ifetch [0 0 0 0 0 0 0 0 ] 0
+Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
+Data [76917 77043 76575 77228 77136 77200 76899 76872 ] 615870
+Fwd_GETX [1058 1018 1052 1068 1017 1018 1097 1033 ] 8361
+Inv [0 0 0 0 0 0 0 0 ] 0
+Replacement [76914 77040 76572 77225 77134 77197 76896 76872 ] 615850
+Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
+Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
+
+ - Transitions -
+I  Load [50062 49936 49885 50169 50299 50006 49692 49994 ] 400043
+I  Ifetch [0 0 0 0 0 0 0 0 ] 0
+I  Store [26856 27108 26691 27060 26839 27195 27208 26882 ] 215839
+I  Inv [0 0 0 0 0 0 0 0 ] 0
+I  Replacement [810 760 775 791 714 761 798 766 ] 6175
+
+II  Writeback_Nack [248 258 277 277 303 257 299 267 ] 2186
+
+M  Load [0 0 0 0 0 0 0 0 ] 0
+M  Ifetch [0 0 0 0 0 0 0 0 ] 0
+M  Store [0 0 0 0 0 0 0 0 ] 0
+M  Fwd_GETX [810 760 775 791 714 761 798 766 ] 6175
+M  Inv [0 0 0 0 0 0 0 0 ] 0
+M  Replacement [76104 76280 75797 76434 76420 76436 76098 76106 ] 609675
+
+MI  Fwd_GETX [248 258 277 277 303 257 299 267 ] 2186
+MI  Inv [0 0 0 0 0 0 0 0 ] 0
+MI  Writeback_Ack [75855 76021 75517 76155 76113 76177 75799 75834 ] 607471
+MI  Writeback_Nack [0 0 0 0 0 0 0 0 ] 0
+
+MII  Fwd_GETX [0 0 0 0 0 0 0 0 ] 0
+
+IS  Data [50061 49936 49885 50168 50297 50005 49691 49992 ] 400035
+
+IM  Data [26856 27107 26690 27060 26839 27195 27208 26880 ] 215835
+
+Cache Stats: system.l1_cntrl1.cacheMemory
+  system.l1_cntrl1.cacheMemory_total_misses: 77201
+  system.l1_cntrl1.cacheMemory_total_demand_misses: 77201
+  system.l1_cntrl1.cacheMemory_total_prefetches: 0
+  system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl1.cacheMemory_request_type_LD:   64.7738%
+  system.l1_cntrl1.cacheMemory_request_type_ST:   35.2262%
+
+  system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor:   77201    100%
+
+Cache Stats: system.l1_cntrl2.cacheMemory
+  system.l1_cntrl2.cacheMemory_total_misses: 76900
+  system.l1_cntrl2.cacheMemory_total_demand_misses: 76900
+  system.l1_cntrl2.cacheMemory_total_prefetches: 0
+  system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl2.cacheMemory_request_type_LD:   64.619%
+  system.l1_cntrl2.cacheMemory_request_type_ST:   35.381%
+
+  system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor:   76900    100%
+
+Cache Stats: system.l1_cntrl3.cacheMemory
+  system.l1_cntrl3.cacheMemory_total_misses: 76876
+  system.l1_cntrl3.cacheMemory_total_demand_misses: 76876
+  system.l1_cntrl3.cacheMemory_total_prefetches: 0
+  system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl3.cacheMemory_request_type_LD:   65.032%
+  system.l1_cntrl3.cacheMemory_request_type_ST:   34.968%
+
+  system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor:   76876    100%
+
+Cache Stats: system.l1_cntrl4.cacheMemory
+  system.l1_cntrl4.cacheMemory_total_misses: 76918
+  system.l1_cntrl4.cacheMemory_total_demand_misses: 76918
+  system.l1_cntrl4.cacheMemory_total_prefetches: 0
+  system.l1_cntrl4.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl4.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl4.cacheMemory_request_type_LD:   65.0849%
+  system.l1_cntrl4.cacheMemory_request_type_ST:   34.9151%
+
+  system.l1_cntrl4.cacheMemory_access_mode_type_Supervisor:   76918    100%
+
+Cache Stats: system.l1_cntrl5.cacheMemory
+  system.l1_cntrl5.cacheMemory_total_misses: 77044
+  system.l1_cntrl5.cacheMemory_total_demand_misses: 77044
+  system.l1_cntrl5.cacheMemory_total_prefetches: 0
+  system.l1_cntrl5.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl5.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl5.cacheMemory_request_type_LD:   64.8149%
+  system.l1_cntrl5.cacheMemory_request_type_ST:   35.1851%
+
+  system.l1_cntrl5.cacheMemory_access_mode_type_Supervisor:   77044    100%
+
+Cache Stats: system.l1_cntrl6.cacheMemory
+  system.l1_cntrl6.cacheMemory_total_misses: 76576
+  system.l1_cntrl6.cacheMemory_total_demand_misses: 76576
+  system.l1_cntrl6.cacheMemory_total_prefetches: 0
+  system.l1_cntrl6.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl6.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl6.cacheMemory_request_type_LD:   65.1444%
+  system.l1_cntrl6.cacheMemory_request_type_ST:   34.8556%
+
+  system.l1_cntrl6.cacheMemory_access_mode_type_Supervisor:   76576    100%
+
+Cache Stats: system.l1_cntrl7.cacheMemory
+  system.l1_cntrl7.cacheMemory_total_misses: 77229
+  system.l1_cntrl7.cacheMemory_total_demand_misses: 77229
+  system.l1_cntrl7.cacheMemory_total_prefetches: 0
+  system.l1_cntrl7.cacheMemory_total_sw_prefetches: 0
+  system.l1_cntrl7.cacheMemory_total_hw_prefetches: 0
+
+  system.l1_cntrl7.cacheMemory_request_type_LD:   64.9613%
+  system.l1_cntrl7.cacheMemory_request_type_ST:   35.0387%
+
+  system.l1_cntrl7.cacheMemory_access_mode_type_Supervisor:   77229    100%
+
+Memory controller: system.dir_cntrl0.memBuffer:
+  memory_total_requests: 1215007
+  memory_reads: 607514
+  memory_writes: 607471
+  memory_refreshes: 59844
+  memory_total_request_delays: 94490839
+  memory_delays_per_request: 77.7698
+  memory_delays_in_input_queue: 4956280
+  memory_delays_behind_head_of_bank_queue: 42721539
+  memory_delays_stalled_at_head_of_bank_queue: 46813020
+  memory_stalls_for_bank_busy: 7203781
+  memory_stalls_for_random_busy: 0
+  memory_stalls_for_anti_starvation: 12030630
+  memory_stalls_for_arbitration: 9262268
+  memory_stalls_for_bus: 12663868
+  memory_stalls_for_tfaw: 0
+  memory_stalls_for_read_write_turnaround: 4593756
+  memory_stalls_for_read_read_turnaround: 1058717
+  accesses_per_bank: 38064  37906  37810  38185  38131  38139  38459  38015  38286  38038  38075  38326  37705  37695  37985  37984  37848  37764  37931  38109  38114  37875  38032  37917  37934  37358  38024  37068  37768  38020  38377  38065  
+
+ --- Directory ---
+ - Event Counts -
+GETX [1243024 ] 1243024
+GETS [0 ] 0
+PUTX [607488 ] 607488
+PUTX_NotOwner [2186 ] 2186
+DMA_READ [0 ] 0
+DMA_WRITE [0 ] 0
+Memory_Data [607509 ] 607509
+Memory_Ack [607471 ] 607471
+
+ - Transitions -
+I  GETX [607519 ] 607519
+I  PUTX_NotOwner [0 ] 0
+I  DMA_READ [0 ] 0
+I  DMA_WRITE [0 ] 0
+
+M  GETX [8361 ] 8361
+M  PUTX [607488 ] 607488
+M  PUTX_NotOwner [2186 ] 2186
+M  DMA_READ [0 ] 0
+M  DMA_WRITE [0 ] 0
+
+M_DRD  GETX [0 ] 0
+M_DRD  PUTX [0 ] 0
+
+M_DWR  GETX [0 ] 0
+M_DWR  PUTX [0 ] 0
+
+M_DWRI  GETX [0 ] 0
+M_DWRI  Memory_Ack [0 ] 0
+
+M_DRDI  GETX [0 ] 0
+M_DRDI  Memory_Ack [0 ] 0
+
+IM  GETX [250002 ] 250002
+IM  GETS [0 ] 0
+IM  PUTX [0 ] 0
+IM  PUTX_NotOwner [0 ] 0
+IM  DMA_READ [0 ] 0
+IM  DMA_WRITE [0 ] 0
+IM  Memory_Data [607509 ] 607509
+
+MI  GETX [377142 ] 377142
+MI  GETS [0 ] 0
+MI  PUTX [0 ] 0
+MI  PUTX_NotOwner [0 ] 0
+MI  DMA_READ [0 ] 0
+MI  DMA_WRITE [0 ] 0
+MI  Memory_Ack [607471 ] 607471
+
+ID  GETX [0 ] 0
+ID  GETS [0 ] 0
+ID  PUTX [0 ] 0
+ID  PUTX_NotOwner [0 ] 0
+ID  DMA_READ [0 ] 0
+ID  DMA_WRITE [0 ] 0
+ID  Memory_Data [0 ] 0
+
+ID_W  GETX [0 ] 0
+ID_W  GETS [0 ] 0
+ID_W  PUTX [0 ] 0
+ID_W  PUTX_NotOwner [0 ] 0
+ID_W  DMA_READ [0 ] 0
+ID_W  DMA_WRITE [0 ] 0
+ID_W  Memory_Ack [0 ] 0
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
new file mode 100755
index 000000000..8802752c7
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simerr
@@ -0,0 +1,74 @@
+system.cpu5: completed 10000 read, 5419 write accesses @2858002
+system.cpu7: completed 10000 read, 5473 write accesses @2858520
+system.cpu0: completed 10000 read, 5305 write accesses @2868940
+system.cpu1: completed 10000 read, 5416 write accesses @2893421
+system.cpu4: completed 10000 read, 5371 write accesses @2900102
+system.cpu2: completed 10000 read, 5337 write accesses @2905419
+system.cpu3: completed 10000 read, 5513 write accesses @2916882
+system.cpu6: completed 10000 read, 5458 write accesses @2971509
+system.cpu1: completed 20000 read, 10866 write accesses @5727829
+system.cpu0: completed 20000 read, 10592 write accesses @5734440
+system.cpu4: completed 20000 read, 10679 write accesses @5748810
+system.cpu7: completed 20000 read, 10819 write accesses @5759030
+system.cpu3: completed 20000 read, 10666 write accesses @5769940
+system.cpu5: completed 20000 read, 10771 write accesses @5778709
+system.cpu6: completed 20000 read, 10832 write accesses @5805350
+system.cpu2: completed 20000 read, 10785 write accesses @5828740
+system.cpu1: completed 30000 read, 16207 write accesses @8557570
+system.cpu0: completed 30000 read, 15949 write accesses @8566069
+system.cpu7: completed 30000 read, 16214 write accesses @8624139
+system.cpu4: completed 30000 read, 16127 write accesses @8660230
+system.cpu3: completed 30000 read, 16038 write accesses @8676099
+system.cpu5: completed 30000 read, 16217 write accesses @8736099
+system.cpu6: completed 30000 read, 16240 write accesses @8737471
+system.cpu2: completed 30000 read, 16356 write accesses @8775610
+system.cpu4: completed 40000 read, 21442 write accesses @11430710
+system.cpu1: completed 40000 read, 21431 write accesses @11446880
+system.cpu0: completed 40000 read, 21249 write accesses @11450119
+system.cpu7: completed 40000 read, 21591 write accesses @11495090
+system.cpu3: completed 40000 read, 21525 write accesses @11637130
+system.cpu6: completed 40000 read, 21625 write accesses @11655440
+system.cpu5: completed 40000 read, 21557 write accesses @11655900
+system.cpu2: completed 40000 read, 22064 write accesses @11762920
+system.cpu0: completed 50000 read, 26643 write accesses @14301920
+system.cpu7: completed 50000 read, 26956 write accesses @14350920
+system.cpu1: completed 50000 read, 26912 write accesses @14419140
+system.cpu4: completed 50000 read, 27035 write accesses @14428630
+system.cpu3: completed 50000 read, 26875 write accesses @14456189
+system.cpu6: completed 50000 read, 26968 write accesses @14552960
+system.cpu5: completed 50000 read, 27033 write accesses @14560100
+system.cpu2: completed 50000 read, 27494 write accesses @14706770
+system.cpu0: completed 60000 read, 32018 write accesses @17124880
+system.cpu7: completed 60000 read, 32300 write accesses @17213372
+system.cpu3: completed 60000 read, 32247 write accesses @17322589
+system.cpu4: completed 60000 read, 32351 write accesses @17326542
+system.cpu1: completed 60000 read, 32302 write accesses @17368660
+system.cpu6: completed 60000 read, 32274 write accesses @17446980
+system.cpu5: completed 60000 read, 32418 write accesses @17468540
+system.cpu2: completed 60000 read, 32981 write accesses @17554781
+system.cpu0: completed 70000 read, 37316 write accesses @19965899
+system.cpu7: completed 70000 read, 37727 write accesses @20108089
+system.cpu4: completed 70000 read, 37633 write accesses @20233790
+system.cpu1: completed 70000 read, 37821 write accesses @20289790
+system.cpu3: completed 70000 read, 37645 write accesses @20291829
+system.cpu6: completed 70000 read, 37499 write accesses @20304889
+system.cpu5: completed 70000 read, 37769 write accesses @20345680
+system.cpu2: completed 70000 read, 38246 write accesses @20384949
+system.cpu0: completed 80000 read, 42438 write accesses @22835499
+system.cpu7: completed 80000 read, 43085 write accesses @23031949
+system.cpu4: completed 80000 read, 42968 write accesses @23134444
+system.cpu3: completed 80000 read, 42908 write accesses @23138450
+system.cpu1: completed 80000 read, 43002 write accesses @23183439
+system.cpu6: completed 80000 read, 42955 write accesses @23224650
+system.cpu2: completed 80000 read, 43596 write accesses @23229730
+system.cpu5: completed 80000 read, 43242 write accesses @23231600
+system.cpu0: completed 90000 read, 47763 write accesses @25792220
+system.cpu7: completed 90000 read, 48675 write accesses @25948310
+system.cpu3: completed 90000 read, 48223 write accesses @26022110
+system.cpu4: completed 90000 read, 48406 write accesses @26054041
+system.cpu6: completed 90000 read, 48309 write accesses @26074843
+system.cpu2: completed 90000 read, 49141 write accesses @26106590
+system.cpu5: completed 90000 read, 48681 write accesses @26106730
+system.cpu1: completed 90000 read, 48449 write accesses @26117229
+system.cpu0: completed 100000 read, 53147 write accesses @28725020
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
new file mode 100755
index 000000000..0a1ec6a6d
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:28
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest-ruby
+Global frequency set at 1000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 28725020 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
new file mode 100644
index 000000000..95c30ab1c
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -0,0 +1,47 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.028725                       # Number of seconds simulated
+sim_ticks                                    28725020                       # Number of ticks simulated
+final_tick                                   28725020                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                   1000000000                       # Frequency of simulated ticks
+host_tick_rate                                 711274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 347060                       # Number of bytes of host memory used
+host_seconds                                    40.39                       # Real time elapsed on the host
+system.physmem.bytes_read                           0                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                        0                       # Number of bytes written to this memory
+system.physmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.physmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.cpu0.num_reads                          100000                       # number of read accesses completed
+system.cpu0.num_writes                          53147                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu1.num_reads                           99027                       # number of read accesses completed
+system.cpu1.num_writes                          53354                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu2.num_reads                           98992                       # number of read accesses completed
+system.cpu2.num_writes                          53956                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu3.num_reads                           99374                       # number of read accesses completed
+system.cpu3.num_writes                          53181                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu4.num_reads                           99392                       # number of read accesses completed
+system.cpu4.num_writes                          53489                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu5.num_reads                           99177                       # number of read accesses completed
+system.cpu5.num_writes                          53605                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu6.num_reads                           99055                       # number of read accesses completed
+system.cpu6.num_writes                          53188                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu7.num_reads                           99520                       # number of read accesses completed
+system.cpu7.num_writes                          53821                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
new file mode 100644
index 000000000..ac8d82ede
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
@@ -0,0 +1,495 @@
+[root]
+type=Root
+children=system
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
+mem_mode=timing
+memories=system.physmem system.funcmem
+num_work_ids=16
+physmem=system.physmem
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.port[1]
+
+[system.cpu0]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[0]
+test=system.cpu0.l1c.cpu_side
+
+[system.cpu0.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.test
+mem_side=system.toL2Bus.port[1]
+
+[system.cpu1]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[1]
+test=system.cpu1.l1c.cpu_side
+
+[system.cpu1.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.test
+mem_side=system.toL2Bus.port[2]
+
+[system.cpu2]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[2]
+test=system.cpu2.l1c.cpu_side
+
+[system.cpu2.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.test
+mem_side=system.toL2Bus.port[3]
+
+[system.cpu3]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[3]
+test=system.cpu3.l1c.cpu_side
+
+[system.cpu3.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.test
+mem_side=system.toL2Bus.port[4]
+
+[system.cpu4]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[4]
+test=system.cpu4.l1c.cpu_side
+
+[system.cpu4.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu4.test
+mem_side=system.toL2Bus.port[5]
+
+[system.cpu5]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[5]
+test=system.cpu5.l1c.cpu_side
+
+[system.cpu5.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu5.test
+mem_side=system.toL2Bus.port[6]
+
+[system.cpu6]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[6]
+test=system.cpu6.l1c.cpu_side
+
+[system.cpu6.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu6.test
+mem_side=system.toL2Bus.port[7]
+
+[system.cpu7]
+type=MemTest
+children=l1c
+atomic=false
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+trace_addr=0
+functional=system.funcmem.port[7]
+test=system.cpu7.l1c.cpu_side
+
+[system.cpu7.l1c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=4
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=true
+latency=1000
+max_miss_count=0
+mshrs=12
+num_cpus=1
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=32768
+subblock_size=0
+tgts_per_mshr=8
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu7.test
+mem_side=system.toL2Bus.port[8]
+
+[system.funcmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.l2c]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+forward_snoops=true
+hash_delay=1
+is_top_level=false
+latency=10000
+max_miss_count=0
+mshrs=92
+num_cpus=8
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=100000
+prefetch_on_access=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=65536
+subblock_size=0
+tgts_per_mshr=16
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.port[0]
+mem_side=system.membus.port[0]
+
+[system.membus]
+type=Bus
+block_size=64
+bus_id=0
+clock=2
+header_cycles=1
+use_default_range=false
+width=16
+port=system.l2c.mem_side system.system_port system.physmem.port[0]
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+zero=false
+port=system.membus.port[2]
+
+[system.toL2Bus]
+type=Bus
+block_size=64
+bus_id=0
+clock=2
+header_cycles=1
+use_default_range=false
+width=16
+port=system.l2c.cpu_side system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
new file mode 100755
index 000000000..afb940009
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
@@ -0,0 +1,74 @@
+system.cpu5: completed 10000 read, 5261 write accesses @25602084
+system.cpu0: completed 10000 read, 5478 write accesses @26185688
+system.cpu4: completed 10000 read, 5410 write accesses @26212882
+system.cpu3: completed 10000 read, 5338 write accesses @26366308
+system.cpu1: completed 10000 read, 5460 write accesses @26447108
+system.cpu7: completed 10000 read, 5362 write accesses @26537664
+system.cpu2: completed 10000 read, 5282 write accesses @26676832
+system.cpu6: completed 10000 read, 5370 write accesses @26707781
+system.cpu3: completed 20000 read, 10741 write accesses @51951998
+system.cpu5: completed 20000 read, 10677 write accesses @52231737
+system.cpu0: completed 20000 read, 11006 write accesses @52523512
+system.cpu4: completed 20000 read, 10704 write accesses @52614186
+system.cpu7: completed 20000 read, 10588 write accesses @52674871
+system.cpu1: completed 20000 read, 10959 write accesses @52986792
+system.cpu2: completed 20000 read, 10676 write accesses @53365626
+system.cpu6: completed 20000 read, 10788 write accesses @53537042
+system.cpu5: completed 30000 read, 16233 write accesses @78528098
+system.cpu3: completed 30000 read, 16192 write accesses @78636475
+system.cpu7: completed 30000 read, 15958 write accesses @79069859
+system.cpu0: completed 30000 read, 16488 write accesses @79082669
+system.cpu4: completed 30000 read, 16215 write accesses @79163244
+system.cpu6: completed 30000 read, 16191 write accesses @79592442
+system.cpu2: completed 30000 read, 16073 write accesses @79845712
+system.cpu1: completed 30000 read, 16466 write accesses @80286691
+system.cpu5: completed 40000 read, 21620 write accesses @103783596
+system.cpu0: completed 40000 read, 21781 write accesses @103983848
+system.cpu7: completed 40000 read, 21333 write accesses @104306510
+system.cpu3: completed 40000 read, 21577 write accesses @104792070
+system.cpu6: completed 40000 read, 21636 write accesses @104882247
+system.cpu4: completed 40000 read, 21525 write accesses @104921736
+system.cpu1: completed 40000 read, 21768 write accesses @105789168
+system.cpu2: completed 40000 read, 21470 write accesses @106255146
+system.cpu5: completed 50000 read, 26996 write accesses @130119835
+system.cpu0: completed 50000 read, 27148 write accesses @130621851
+system.cpu4: completed 50000 read, 26714 write accesses @131102250
+system.cpu7: completed 50000 read, 26744 write accesses @131131435
+system.cpu3: completed 50000 read, 26919 write accesses @131315326
+system.cpu6: completed 50000 read, 27071 write accesses @131463045
+system.cpu2: completed 50000 read, 26691 write accesses @132748289
+system.cpu1: completed 50000 read, 27351 write accesses @133533726
+system.cpu0: completed 60000 read, 32524 write accesses @157291050
+system.cpu5: completed 60000 read, 32351 write accesses @157331674
+system.cpu3: completed 60000 read, 32133 write accesses @157609229
+system.cpu4: completed 60000 read, 32278 write accesses @158092666
+system.cpu7: completed 60000 read, 32237 write accesses @158094050
+system.cpu6: completed 60000 read, 32492 write accesses @158284016
+system.cpu2: completed 60000 read, 32099 write accesses @159310066
+system.cpu1: completed 60000 read, 32786 write accesses @160315811
+system.cpu5: completed 70000 read, 37785 write accesses @184174146
+system.cpu0: completed 70000 read, 37907 write accesses @184194427
+system.cpu3: completed 70000 read, 37695 write accesses @184756116
+system.cpu7: completed 70000 read, 37537 write accesses @185107500
+system.cpu6: completed 70000 read, 37865 write accesses @185115722
+system.cpu4: completed 70000 read, 37642 write accesses @185437602
+system.cpu2: completed 70000 read, 37459 write accesses @186101472
+system.cpu1: completed 70000 read, 38271 write accesses @187053767
+system.cpu0: completed 80000 read, 43182 write accesses @210453706
+system.cpu7: completed 80000 read, 43001 write accesses @210994557
+system.cpu5: completed 80000 read, 43199 write accesses @211075215
+system.cpu3: completed 80000 read, 43061 write accesses @211165517
+system.cpu4: completed 80000 read, 43118 write accesses @211798954
+system.cpu6: completed 80000 read, 43219 write accesses @211876903
+system.cpu2: completed 80000 read, 43025 write accesses @212410812
+system.cpu1: completed 80000 read, 43805 write accesses @214554639
+system.cpu0: completed 90000 read, 48653 write accesses @236986702
+system.cpu5: completed 90000 read, 48401 write accesses @237258796
+system.cpu7: completed 90000 read, 48251 write accesses @237456793
+system.cpu4: completed 90000 read, 48341 write accesses @237741580
+system.cpu3: completed 90000 read, 48504 write accesses @237892702
+system.cpu6: completed 90000 read, 48675 write accesses @238620248
+system.cpu2: completed 90000 read, 48457 write accesses @239205755
+system.cpu1: completed 90000 read, 49067 write accesses @239913307
+system.cpu5: completed 100000 read, 53710 write accesses @263488655
+hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
new file mode 100755
index 000000000..c76c33576
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System.  http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Jan 23 2012 04:48:33
+gem5 started Jan 23 2012 04:59:28
+gem5 executing on zizzer
+command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0.  Starting simulation...
+Exiting @ tick 263488655 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
new file mode 100644
index 000000000..82bd7a1b0
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -0,0 +1,960 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds                                  0.000263                       # Number of seconds simulated
+sim_ticks                                   263488655                       # Number of ticks simulated
+final_tick                                  263488655                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+host_tick_rate                                1768401                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335780                       # Number of bytes of host memory used
+host_seconds                                   149.00                       # Real time elapsed on the host
+system.physmem.bytes_read                     4057580                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.physmem.bytes_written                  2644316                       # Number of bytes written to this memory
+system.physmem.num_reads                       141878                       # Number of read requests responded to by this memory
+system.physmem.num_writes                       83744                       # Number of write requests responded to by this memory
+system.physmem.num_other                            0                       # Number of other requests responded to by this memory
+system.physmem.bw_read                    15399448602                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write                   10035786930                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total                   25435235532                       # Total bandwidth to/from this memory (bytes/s)
+system.funcmem.bytes_read                           0                       # Number of bytes read from this memory
+system.funcmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
+system.funcmem.bytes_written                        0                       # Number of bytes written to this memory
+system.funcmem.num_reads                            0                       # Number of read requests responded to by this memory
+system.funcmem.num_writes                           0                       # Number of write requests responded to by this memory
+system.funcmem.num_other                            0                       # Number of other requests responded to by this memory
+system.l2c.replacements                         76856                       # number of replacements
+system.l2c.tagsinuse                       657.714518                       # Cycle average of tags in use
+system.l2c.total_refs                          139150                       # Total number of references to valid blocks.
+system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
+system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
+system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
+system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
+system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
+system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
+system.l2c.occ_blocks::3                    24.461210                       # Average occupied blocks per context
+system.l2c.occ_blocks::4                    24.025606                       # Average occupied blocks per context
+system.l2c.occ_blocks::5                    23.167376                       # Average occupied blocks per context
+system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
+system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
+system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
+system.l2c.occ_percent::0                    0.023513                       # Average percentage of cache occupancy
+system.l2c.occ_percent::1                    0.023339                       # Average percentage of cache occupancy
+system.l2c.occ_percent::2                    0.023014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::3                    0.023888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::4                    0.023463                       # Average percentage of cache occupancy
+system.l2c.occ_percent::5                    0.022624                       # Average percentage of cache occupancy
+system.l2c.occ_percent::6                    0.022944                       # Average percentage of cache occupancy
+system.l2c.occ_percent::7                    0.022464                       # Average percentage of cache occupancy
+system.l2c.occ_percent::8                    0.457051                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::0                      10466                       # number of ReadReq hits
+system.l2c.ReadReq_hits::1                      10370                       # number of ReadReq hits
+system.l2c.ReadReq_hits::2                      10579                       # number of ReadReq hits
+system.l2c.ReadReq_hits::3                      10469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::4                      10390                       # number of ReadReq hits
+system.l2c.ReadReq_hits::5                      10384                       # number of ReadReq hits
+system.l2c.ReadReq_hits::6                      10590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::7                      10463                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
+system.l2c.Writeback_hits::0                    94038                       # number of Writeback hits
+system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::0                     457                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::1                     419                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::2                     446                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::3                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::4                     430                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::5                     463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::6                     415                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::7                     411                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::0                     2829                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::1                     2819                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::2                     2901                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::3                     2765                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::4                     2827                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::5                     2929                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::6                     2882                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::7                     2913                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total                22865                       # number of ReadExReq hits
+system.l2c.demand_hits::0                       13295                       # number of demand (read+write) hits
+system.l2c.demand_hits::1                       13189                       # number of demand (read+write) hits
+system.l2c.demand_hits::2                       13480                       # number of demand (read+write) hits
+system.l2c.demand_hits::3                       13234                       # number of demand (read+write) hits
+system.l2c.demand_hits::4                       13217                       # number of demand (read+write) hits
+system.l2c.demand_hits::5                       13313                       # number of demand (read+write) hits
+system.l2c.demand_hits::6                       13472                       # number of demand (read+write) hits
+system.l2c.demand_hits::7                       13376                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
+system.l2c.overall_hits::0                      13295                       # number of overall hits
+system.l2c.overall_hits::1                      13189                       # number of overall hits
+system.l2c.overall_hits::2                      13480                       # number of overall hits
+system.l2c.overall_hits::3                      13234                       # number of overall hits
+system.l2c.overall_hits::4                      13217                       # number of overall hits
+system.l2c.overall_hits::5                      13313                       # number of overall hits
+system.l2c.overall_hits::6                      13472                       # number of overall hits
+system.l2c.overall_hits::7                      13376                       # number of overall hits
+system.l2c.overall_hits::total                 106576                       # number of overall hits
+system.l2c.ReadReq_misses::0                     5163                       # number of ReadReq misses
+system.l2c.ReadReq_misses::1                     5186                       # number of ReadReq misses
+system.l2c.ReadReq_misses::2                     5173                       # number of ReadReq misses
+system.l2c.ReadReq_misses::3                     5223                       # number of ReadReq misses
+system.l2c.ReadReq_misses::4                     5193                       # number of ReadReq misses
+system.l2c.ReadReq_misses::5                     5114                       # number of ReadReq misses
+system.l2c.ReadReq_misses::6                     5145                       # number of ReadReq misses
+system.l2c.ReadReq_misses::7                     4996                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::0                  1644                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::1                  1598                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::2                  1617                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::3                  1610                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::4                  1586                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::5                  1626                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::6                  1624                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::7                  1582                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::0                   5539                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::1                   5808                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::2                   5466                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::3                   5538                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::4                   5599                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::5                   5507                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::6                   5800                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::7                   5643                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total              44900                       # number of ReadExReq misses
+system.l2c.demand_misses::0                     10702                       # number of demand (read+write) misses
+system.l2c.demand_misses::1                     10994                       # number of demand (read+write) misses
+system.l2c.demand_misses::2                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::3                     10761                       # number of demand (read+write) misses
+system.l2c.demand_misses::4                     10792                       # number of demand (read+write) misses
+system.l2c.demand_misses::5                     10621                       # number of demand (read+write) misses
+system.l2c.demand_misses::6                     10945                       # number of demand (read+write) misses
+system.l2c.demand_misses::7                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
+system.l2c.overall_misses::0                    10702                       # number of overall misses
+system.l2c.overall_misses::1                    10994                       # number of overall misses
+system.l2c.overall_misses::2                    10639                       # number of overall misses
+system.l2c.overall_misses::3                    10761                       # number of overall misses
+system.l2c.overall_misses::4                    10792                       # number of overall misses
+system.l2c.overall_misses::5                    10621                       # number of overall misses
+system.l2c.overall_misses::6                    10945                       # number of overall misses
+system.l2c.overall_misses::7                    10639                       # number of overall misses
+system.l2c.overall_misses::total                86093                       # number of overall misses
+system.l2c.ReadReq_miss_latency            2043791615                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency          261408598                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency          2236788368                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency             4280579983                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency            4280579983                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::0                  15629                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::1                  15556                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::2                  15752                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::3                  15692                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::4                  15583                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::5                  15498                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::6                  15735                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::7                  15459                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total             124904                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::0                94038                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::0                2101                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::1                2017                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::2                2063                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::3                2073                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::4                2016                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::5                2089                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::6                2039                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::7                1993                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total           16391                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::0                 8368                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::1                 8627                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::2                 8367                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::3                 8303                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::4                 8426                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::5                 8436                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::6                 8682                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::7                 8556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total            67765                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::0                   23997                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::1                   24183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::2                   24119                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::3                   23995                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::4                   24009                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::5                   23934                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::6                   24417                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::7                   24015                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::3                  23995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::4                  24009                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::5                  23934                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::6                  24417                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::7                  24015                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::0              0.330347                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::1              0.333376                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::2              0.328403                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::3              0.332845                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::4              0.333248                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::5              0.329978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::6              0.326978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::7              0.323177                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          2.638352                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::0           0.782485                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::1           0.792266                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::2           0.783810                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::3           0.776652                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::4           0.786706                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::5           0.778363                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::6           0.796469                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::7           0.793778                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       6.290529                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::0            0.661926                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::1            0.673235                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::2            0.653281                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::3            0.666988                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::4            0.664491                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::5            0.652798                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::6            0.668049                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::7            0.659537                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total        5.300305                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::0               0.445972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::1               0.454617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::2               0.441105                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::3               0.448468                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::4               0.449498                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::5               0.443762                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::6               0.448253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::7               0.443015                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           3.574690                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::0              0.445972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::1              0.454617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::2              0.441105                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::3              0.448468                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::4              0.449498                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::5              0.443762                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::6              0.448253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::7              0.443015                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          3.574690                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::0   395853.498935                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::1   394097.881797                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::2   395088.268896                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::3   391306.072181                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::4   393566.650298                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::5   399646.385413                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::6   397238.409135                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::7   409085.591473                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 3175882.758128                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::0 403825.305651                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::1 385121.964187                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::2 409218.508599                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::3 403898.224630                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::4 399497.833184                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::5 406171.848193                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::6 385653.166897                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::7 396382.840333                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::0    399979.441506                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::1    389356.010824                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::2    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::3    397786.449494                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::4    396643.808655                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::5    403029.844930                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::6    391099.130471                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::7    402347.963436                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::0   399979.441506                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::1   389356.010824                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::2   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::3   397786.449494                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::4   396643.808655                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::5   403029.844930                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::6   391099.130471                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::7   402347.963436                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.writebacks                           40644                       # number of writebacks
+system.l2c.ReadReq_mshr_hits                      961                       # number of ReadReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits                    49                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits                    507                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits                      1468                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits                     1468                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses                  40232                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses               12838                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses                44393                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses                   84625                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses                  84625                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency       1609227416                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency     513507057                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency     1775748338                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency        3384975754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency       3384975754                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency   3189139994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency   1723903484                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency   4913043478                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::0         2.574189                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::1         2.586269                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::2         2.554088                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::3         2.563854                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::4         2.581788                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::5         2.595948                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::6         2.556848                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::7         2.602497                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total    20.615481                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::0      6.110424                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::1      6.364898                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::2      6.222976                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::3      6.192957                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::4      6.368056                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::5      6.145524                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::6      6.296224                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::7      6.441545                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total    50.142604                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::0       5.305091                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::1       5.145821                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::2       5.305725                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::3       5.346622                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::4       5.268573                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::5       5.262328                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::6       5.113223                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::7       5.188523                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total    41.935906                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::0          3.526482                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::1          3.499359                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::2          3.508645                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::3          3.526776                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::4          3.524720                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::5          3.535765                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::6          3.465823                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::7          3.523839                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total     28.111410                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::0         3.526482                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::1         3.499359                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::2         3.508645                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::3         3.526776                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::4         3.524720                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::5         3.535765                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::6         3.465823                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::7         3.523839                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total    28.111410                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency  39999.713489                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency 39999.713489                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
+system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
+system.cpu0.num_reads                           99815                       # number of read accesses completed
+system.cpu0.num_writes                          53929                       # number of write accesses completed
+system.cpu0.num_copies                              0                       # number of copy accesses completed
+system.cpu0.l1c.replacements                    27826                       # number of replacements
+system.cpu0.l1c.tagsinuse                  102.742005                       # Cycle average of tags in use
+system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
+system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
+system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
+system.cpu0.l1c.occ_percent::0               0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::1              -0.477715                       # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits                     7530                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits                    1059                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits                      8589                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits                     8589                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses                  37279                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses                 23202                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses                   60481                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses                  60481                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency       1299667421                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency      1001508092                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency        2301175513                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency       2301175513                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses                44809                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses                 69070                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate            0.831953                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate           0.956350                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate             0.875648                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate            0.875648                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency  38047.907822                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398                       # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu0.l1c.writebacks                      11972                       # number of writebacks
+system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu0.l1c.ReadReq_mshr_misses             37279                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses            23202                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses              60481                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses             60481                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency   1262244251                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency    978215253                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency   2240459504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency   2240459504                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    894578632                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    569723237                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency   1464301869                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831953                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956350                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate        0.875648                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate       0.875648                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu1.num_reads                           98493                       # number of read accesses completed
+system.cpu1.num_writes                          53671                       # number of write accesses completed
+system.cpu1.num_copies                              0                       # number of copy accesses completed
+system.cpu1.l1c.replacements                    27684                       # number of replacements
+system.cpu1.l1c.tagsinuse                   93.018974                       # Cycle average of tags in use
+system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
+system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
+system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
+system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
+system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
+system.cpu1.l1c.occ_percent::0               0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::1              -0.493432                       # Average percentage of cache occupancy
+system.cpu1.l1c.ReadReq_hits                     7429                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits                    1066                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits                      8495                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits                     8495                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses                  37110                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses                 23275                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses                   60385                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses                  60385                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency       1301760811                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency      1014297005                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency        2316057816                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency       2316057816                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses                44539                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses               24341                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses                 68880                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate            0.833202                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate           0.956206                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate             0.876670                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate            0.876670                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency  38354.853291                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237                       # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu1.l1c.writebacks                      11809                       # number of writebacks
+system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu1.l1c.ReadReq_mshr_misses             37110                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses            23275                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses              60385                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses             60385                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency   1264508347                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency    990933889                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency   2255442236                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency   2255442236                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    877119159                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    578327433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency   1455446592                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833202                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956206                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate        0.876670                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate       0.876670                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu2.num_reads                           99149                       # number of read accesses completed
+system.cpu2.num_writes                          53185                       # number of write accesses completed
+system.cpu2.num_copies                              0                       # number of copy accesses completed
+system.cpu2.l1c.replacements                    27627                       # number of replacements
+system.cpu2.l1c.tagsinuse                   84.373112                       # Cycle average of tags in use
+system.cpu2.l1c.total_refs                      11519                       # Total number of references to valid blocks.
+system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
+system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
+system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
+system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
+system.cpu2.l1c.occ_percent::0               0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::1              -0.509877                       # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits                     7576                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits                    1069                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits                      8645                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits                     8645                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses                  37144                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses                 22885                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses                   60029                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses                  60029                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency       1302790562                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency       991654869                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency        2294445431                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency       2294445431                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses                44720                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses               23954                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses                 68674                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate            0.830590                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate           0.955373                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate             0.874115                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate            0.874115                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency  38222.283080                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
+system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
+system.cpu2.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105                       # average number of cycles each access was blocked
+system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu2.l1c.writebacks                      11784                       # number of writebacks
+system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu2.l1c.ReadReq_mshr_misses             37144                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses            22885                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses              60029                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses             60029                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency   1265501937                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency    968684322                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency   2234186259                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency   2234186259                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    900513056                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    566349170                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency   1466862226                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830590                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate      0.955373                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate        0.874115                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate       0.874115                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu3.num_reads                           99588                       # number of read accesses completed
+system.cpu3.num_writes                          53645                       # number of write accesses completed
+system.cpu3.num_copies                              0                       # number of copy accesses completed
+system.cpu3.l1c.replacements                    27837                       # number of replacements
+system.cpu3.l1c.tagsinuse                  104.177298                       # Cycle average of tags in use
+system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
+system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
+system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
+system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
+system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
+system.cpu3.l1c.occ_percent::0               0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::1              -0.475386                       # Average percentage of cache occupancy
+system.cpu3.l1c.ReadReq_hits                     7552                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits                    1078                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits                      8630                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits                     8630                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses                  37191                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses                 23219                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses                   60410                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses                  60410                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency       1312024933                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency       995527685                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency        2307552618                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency       2307552618                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses                44743                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses               24297                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses                 69040                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate            0.831214                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate           0.955632                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate             0.875000                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate            0.875000                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency  38198.189340                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
+system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
+system.cpu3.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910                       # average number of cycles each access was blocked
+system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu3.l1c.writebacks                      11956                       # number of writebacks
+system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu3.l1c.ReadReq_mshr_misses             37191                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses            23219                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses              60410                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses             60410                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency   1274692143                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency    972218785                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency   2246910928                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency   2246910928                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    889431937                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    569772276                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency   1459204213                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate       0.831214                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate      0.955632                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate        0.875000                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate       0.875000                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu4.num_reads                           99725                       # number of read accesses completed
+system.cpu4.num_writes                          53533                       # number of write accesses completed
+system.cpu4.num_copies                              0                       # number of copy accesses completed
+system.cpu4.l1c.replacements                    27683                       # number of replacements
+system.cpu4.l1c.tagsinuse                   94.681644                       # Cycle average of tags in use
+system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
+system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
+system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
+system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
+system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
+system.cpu4.l1c.occ_percent::0               0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_percent::1              -0.494043                       # Average percentage of cache occupancy
+system.cpu4.l1c.ReadReq_hits                     7686                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits                    1123                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits                      8809                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits                     8809                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses                  37251                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses                 22937                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses                   60188                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses                  60188                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency       1303112178                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency       994450363                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency        2297562541                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency       2297562541                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses                44937                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses               24060                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate            0.828961                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate           0.953325                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate             0.872328                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate            0.872328                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency  38173.099970                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
+system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
+system.cpu4.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653                       # average number of cycles each access was blocked
+system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu4.l1c.writebacks                      11763                       # number of writebacks
+system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu4.l1c.ReadReq_mshr_misses             37251                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses            22937                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency   1265717116                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency    971425596                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency   2237142712                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency   2237142712                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    898461911                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    576408625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency   1474870536                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate       0.828961                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate      0.953325                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate        0.872328                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate       0.872328                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53710                       # number of write accesses completed
+system.cpu5.num_copies                              0                       # number of copy accesses completed
+system.cpu5.l1c.replacements                    27832                       # number of replacements
+system.cpu5.l1c.tagsinuse                   93.507234                       # Cycle average of tags in use
+system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
+system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
+system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
+system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
+system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
+system.cpu5.l1c.occ_percent::0               0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::1              -0.494726                       # Average percentage of cache occupancy
+system.cpu5.l1c.ReadReq_hits                     7592                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits                    1126                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits                      8718                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits                     8718                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses                  37349                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses                 23013                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses                   60362                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses                  60362                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency       1291933371                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency       998304045                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency        2290237416                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency       2290237416                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses                44941                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses               24139                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses                 69080                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate            0.831067                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate           0.953353                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate             0.873798                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate            0.873798                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency  37941.708625                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
+system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
+system.cpu5.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624                       # average number of cycles each access was blocked
+system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu5.l1c.writebacks                      11908                       # number of writebacks
+system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu5.l1c.ReadReq_mshr_misses             37349                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses            23013                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses              60362                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses             60362                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency   1254436910                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency    975203983                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency   2229640893                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency   2229640893                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    902856034                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    567587171                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency   1470443205                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831067                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate      0.953353                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate        0.873798                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate       0.873798                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu6.num_reads                           99389                       # number of read accesses completed
+system.cpu6.num_writes                          53686                       # number of write accesses completed
+system.cpu6.num_copies                              0                       # number of copy accesses completed
+system.cpu6.l1c.replacements                    27861                       # number of replacements
+system.cpu6.l1c.tagsinuse                   89.788098                       # Cycle average of tags in use
+system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
+system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
+system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
+system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
+system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
+system.cpu6.l1c.occ_percent::0               0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::1              -0.502932                       # Average percentage of cache occupancy
+system.cpu6.l1c.ReadReq_hits                     7543                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits                    1119                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits                      8662                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits                     8662                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses                  37109                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses                 23142                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses                   60251                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses                  60251                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency       1299799162                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency      1015775810                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency        2315574972                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency       2315574972                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses                44652                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses                 68913                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate            0.831071                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate           0.953877                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate             0.874305                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate            0.874305                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency  38432.141740                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
+system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
+system.cpu6.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332                       # average number of cycles each access was blocked
+system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu6.l1c.writebacks                      11849                       # number of writebacks
+system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu6.l1c.ReadReq_mshr_misses             37109                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses            23142                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses              60251                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses             60251                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency   1262548698                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency    992541214                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency   2255089912                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency   2255089912                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    877981455                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    574689009                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency   1452670464                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate       0.831071                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate      0.953877                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate        0.874305                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate       0.874305                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+system.cpu7.num_reads                           99694                       # number of read accesses completed
+system.cpu7.num_writes                          53501                       # number of write accesses completed
+system.cpu7.num_copies                              0                       # number of copy accesses completed
+system.cpu7.l1c.replacements                    27727                       # number of replacements
+system.cpu7.l1c.tagsinuse                   84.250612                       # Cycle average of tags in use
+system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
+system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
+system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
+system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
+system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
+system.cpu7.l1c.occ_percent::0               0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::1              -0.511413                       # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits                     7593                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits                    1111                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits                      8704                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits                     8704                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses                  37155                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses                 23121                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses                   60276                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses                  60276                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency       1287127315                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency      1006139538                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency        2293266853                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency       2293266853                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses                44748                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses               24232                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses                 68980                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate            0.830316                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate           0.954152                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate             0.873818                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate            0.873818                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency  38046.102147                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_targets                 0                       # number of cycles access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981                       # average number of cycles each access was blocked
+system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
+system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
+system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
+system.cpu7.l1c.writebacks                      11797                       # number of writebacks
+system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
+system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
+system.cpu7.l1c.ReadReq_mshr_misses             37155                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses            23121                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses              60276                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses             60276                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency   1249829653                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency    982928032                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency   2232757685                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency   2232757685                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    901961636                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    558194703                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency   1460156339                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate       0.830316                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate      0.954152                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate        0.873818                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate       0.873818                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
+system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
+system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
+
+---------- End Simulation Statistics   ----------