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authorAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
committerAndreas Hansson <andreas.hansson@arm.com>2015-03-02 05:04:20 -0500
commit8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch)
tree446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick/se/50.memtest/ref
parentfc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff)
downloadgem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing, interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick/se/50.memtest/ref')
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt3128
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt3087
2 files changed, 3106 insertions, 3109 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
index a27123aa4..4a7304d33 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -1,195 +1,195 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.001493 # Number of seconds simulated
-sim_ticks 1493307500 # Number of ticks simulated
-final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000729 # Number of seconds simulated
+sim_ticks 728722500 # Number of ticks simulated
+final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 295462472 # Simulator tick rate (ticks/s)
-host_mem_usage 222068 # Number of bytes of host memory used
-host_seconds 5.05 # Real time elapsed on the host
+host_tick_rate 162031375 # Simulator tick rate (ticks/s)
+host_mem_usage 277108 # Number of bytes of host memory used
+host_seconds 4.50 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory
-system.physmem.bytes_read::total 619989 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory
-system.physmem.bytes_written::total 427483 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 3617473 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 3616134 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 3692475 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 3703189 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 3575955 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 3617473 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 3600732 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 286265890 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 257147306 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 53781288 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 56343385 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 56389592 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 56051416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 55433995 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 53449809 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 56796072 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 56051416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 701444277 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory
+system.physmem.bytes_read::total 634443 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory
+system.physmem.bytes_written::total 443379 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu0.num_reads 99767 # number of read accesses completed
-system.cpu0.num_writes 55259 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22696 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks.
+system.cpu0.num_reads 100000 # number of read accesses completed
+system.cpu0.num_writes 54791 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22240 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9858 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9858 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36982 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36982 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23775 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23775 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60757 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60757 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60757 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60757 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 2501825237 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 2501825237 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 1853114266 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 1853114266 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 4354939503 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 4354939503 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 4354939503 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 4354939503 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45690 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45690 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24925 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24925 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70615 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70615 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70615 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953862 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.953862 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.860398 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.860398 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.860398 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.860398 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 2197094 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9793 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses
+system.cpu0.l1c.overall_misses::total 60366 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses
+system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency
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+system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.312002 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9747 # number of writebacks
-system.cpu0.l1c.writebacks::total 9747 # number of writebacks
-system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36982 # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_misses::total 36982 # number of ReadReq MSHR misses
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-system.cpu0.l1c.WriteReq_mshr_misses::total 23775 # number of WriteReq MSHR misses
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-system.cpu0.l1c.overall_mshr_misses::total 60757 # number of overall MSHR misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2423727133 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2423727133 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1803343082 # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1803343082 # number of WriteReq MSHR miss cycles
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-system.cpu0.l1c.demand_mshr_miss_latency::total 4227070215 # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4227070215 # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency::total 4227070215 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1077807594 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1077807594 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4091615147 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4091615147 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5169422741 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5169422741 # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809411 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809411 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953862 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953862 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_miss_rate::total 0.860398 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.860398 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513 # average WriteReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency
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+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles
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+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
@@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.num_writes 54988 # number of write accesses completed
-system.cpu1.l1c.tags.replacements 22397 # number of replacements
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-system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks.
-system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks.
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+system.cpu1.num_writes 55132 # number of write accesses completed
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+system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
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+system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency
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system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks
-system.cpu1.l1c.writebacks::total 9809 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36639 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23767 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23767 # number of WriteReq MSHR misses
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-system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60406 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60406 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2408616840 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2408616840 # number of ReadReq MSHR miss cycles
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-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1812196150 # number of WriteReq MSHR miss cycles
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-system.cpu1.l1c.demand_mshr_miss_latency::total 4220812990 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4220812990 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 4220812990 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1084723149 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4036922188 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5121645337 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804881 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804881 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954191 # mshr miss rate for WriteReq accesses
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-system.cpu1.l1c.demand_mshr_miss_rate::total 0.857686 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency
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-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles
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+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807369 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953287 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
@@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 55347 # number of write accesses completed
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-system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks.
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+system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles
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-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles
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-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles
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-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses
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-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency
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-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency
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-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency
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+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency
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+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
@@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 55235 # number of write accesses completed
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.demand_mshr_miss_rate::total 0.862048 # mshr miss rate for demand accesses
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-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency
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+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
@@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
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system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
@@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
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system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
@@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
@@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
@@ -1037,566 +1037,565 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.l2c.tags.sampled_refs 13527 # Sample count of references to valid blocks.
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+system.l2c.tags.replacements 13121 # number of replacements
+system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use
+system.l2c.tags.total_refs 150276 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.813557 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0 5.728717 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 6.680211 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.211499 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 5.648633 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.142733 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 5.860524 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.858945 # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::total 75478 # number of Writeback hits
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system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.l2c.blocked::no_targets 0 # number of cycles access was blocked
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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+system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060425 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5 0.060470 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059067 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062259 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.060888 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846421 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856953 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.852076 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.845799 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846816 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855517 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844664 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.847241 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.849435 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.707806 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.695827 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.690230 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.701732 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695496 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700452 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700143 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.700770 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.699049 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.287810 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.287810 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
@@ -1625,109 +1624,108 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 83923 # Transaction distribution
-system.membus.trans_dist::ReadResp 83923 # Transaction distribution
-system.membus.trans_dist::WriteReq 43483 # Transaction distribution
-system.membus.trans_dist::WriteResp 43481 # Transaction distribution
-system.membus.trans_dist::Writeback 6000 # Transaction distribution
+system.membus.trans_dist::ReadReq 84424 # Transaction distribution
+system.membus.trans_dist::ReadResp 84420 # Transaction distribution
+system.membus.trans_dist::WriteReq 43379 # Transaction distribution
+system.membus.trans_dist::WriteResp 43377 # Transaction distribution
+system.membus.trans_dist::Writeback 6250 # Transaction distribution
system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50527 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3086 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 58495 # Total snoops (count)
-system.membus.snoop_fanout::samples 122833 # Request fanout histogram
+system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50299 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3116 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58193 # Total snoops (count)
+system.membus.snoop_fanout::samples 123722 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 122833 # Request fanout histogram
-system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 31.7 # Layer utilization (%)
-system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total 123722 # Request fanout histogram
+system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 48.1 # Layer utilization (%)
+system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 42.9 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 323561 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 322707 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
index f348549bd..b29e580fa 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
@@ -1,195 +1,195 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000667 # Number of seconds simulated
-sim_ticks 667077000 # Number of ticks simulated
-final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000476 # Number of seconds simulated
+sim_ticks 475552000 # Number of ticks simulated
+final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 152389795 # Simulator tick rate (ticks/s)
-host_mem_usage 222064 # Number of bytes of host memory used
-host_seconds 4.38 # Real time elapsed on the host
+host_tick_rate 102852654 # Simulator tick rate (ticks/s)
+host_mem_usage 276856 # Number of bytes of host memory used
+host_seconds 4.62 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory
-system.physmem.bytes_read::total 640052 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory
-system.physmem.bytes_written::total 442654 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory
+system.physmem.bytes_read::total 649301 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory
+system.physmem.bytes_written::total 454846 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.num_reads 100000 # number of read accesses completed
-system.cpu0.num_writes 55151 # number of write accesses completed
-system.cpu0.l1c.tags.replacements 22523 # number of replacements
-system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use
-system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks.
-system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks.
-system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks.
+system.cpu0.num_writes 55373 # number of write accesses completed
+system.cpu0.l1c.tags.replacements 22370 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks.
system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor
-system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy
-system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id
-system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id
-system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses
-system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses
-system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits
-system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits
-system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits
-system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits
-system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits
-system.cpu0.l1c.overall_hits::total 9993 # number of overall hits
-system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses
-system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses
-system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses
-system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses
-system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses
-system.cpu0.l1c.overall_misses::total 60443 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles
-system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses
-system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses
-system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses
-system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses
-system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency
-system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency
-system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked
+system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits
+system.cpu0.l1c.overall_hits::total 9779 # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses
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+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
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+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks
-system.cpu0.l1c.writebacks::total 9806 # number of writebacks
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-system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles
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-system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles
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-system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses
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-system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency
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+system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency
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+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
@@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks.
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+system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks.
system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses
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+system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses
+system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency
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system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
-system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks
-system.cpu1.l1c.writebacks::total 9956 # number of writebacks
-system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses
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-system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles
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-system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
@@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 55132 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22573 # number of replacements
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-system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks.
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+system.cpu2.num_writes 55482 # number of write accesses completed
+system.cpu2.l1c.tags.replacements 22450 # number of replacements
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+system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks.
system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency
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system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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+system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked
system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
-system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks
-system.cpu2.l1c.writebacks::total 9915 # number of writebacks
-system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses
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-system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses
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-system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses
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-system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles
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-system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles
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-system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses
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-system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency
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-system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency
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+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles
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+system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency
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+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
@@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 54955 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22662 # number of replacements
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-system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks.
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+system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks.
+system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks.
system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses
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-system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles
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-system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles
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-system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles
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-system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses
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-system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses
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-system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses
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-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency
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-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency
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-system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency
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+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
@@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 54781 # number of write accesses completed
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-system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles
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-system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses
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-system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses
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-system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses
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-system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses
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-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency
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+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
@@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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@@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
@@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
@@ -1037,567 +1037,566 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
@@ -1626,64 +1625,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 84242 # Transaction distribution
-system.membus.trans_dist::ReadResp 84239 # Transaction distribution
-system.membus.trans_dist::WriteReq 43998 # Transaction distribution
-system.membus.trans_dist::WriteResp 43998 # Transaction distribution
-system.membus.trans_dist::Writeback 6229 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50044 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3111 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 57731 # Total snoops (count)
-system.membus.snoop_fanout::samples 123701 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84922 # Transaction distribution
+system.membus.trans_dist::ReadResp 84916 # Transaction distribution
+system.membus.trans_dist::WriteReq 43774 # Transaction distribution
+system.membus.trans_dist::WriteResp 43771 # Transaction distribution
+system.membus.trans_dist::Writeback 6423 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50059 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3238 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57586 # Total snoops (count)
+system.membus.snoop_fanout::samples 124108 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123701 # Request fanout histogram
-system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 43.5 # Layer utilization (%)
-system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 46.8 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 321748 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram
+system.membus.snoop_fanout::total 124108 # Request fanout histogram
+system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 60.1 # Layer utilization (%)
+system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 64.5 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 322486 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
@@ -1694,29 +1693,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
---------- End Simulation Statistics ----------