diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/quick/se/50.memtest | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/quick/se/50.memtest')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3416 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt | 3412 |
2 files changed, 3423 insertions, 3405 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a994433c5..4b7a057ad 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,1771 +1,1777 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000502 # Number of seconds simulated -sim_ticks 501584000 # Number of ticks simulated -final_tick 501584000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000520 # Number of seconds simulated +sim_ticks 519755500 # Number of ticks simulated +final_tick 519755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 67567713 # Simulator tick rate (ticks/s) -host_mem_usage 232512 # Number of bytes of host memory used -host_seconds 7.42 # Real time elapsed on the host +host_tick_rate 97602781 # Simulator tick rate (ticks/s) +host_mem_usage 236356 # Number of bytes of host memory used +host_seconds 5.33 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 77173 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 79943 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80467 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 80557 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77449 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 81573 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79541 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 76446 # Number of bytes read from this memory -system.physmem.bytes_read::total 633149 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 399616 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5376 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5525 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5482 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5537 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5409 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5437 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5416 # Number of bytes written to this memory -system.physmem.bytes_written::total 443294 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10960 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10958 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11104 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10879 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10858 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10887 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10871 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6244 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5376 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5525 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5482 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5537 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5409 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5437 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5416 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49922 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 153858576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 159381081 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 160425771 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 160605203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 154408833 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 162630786 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 158579620 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 152409168 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1262299037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 796708029 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10718045 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 11015104 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10929376 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11039028 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 10957287 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10783837 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 10839660 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10797793 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 883788159 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 796708029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 164576621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 170396185 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 171355147 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171644231 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 165366120 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 173414622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 169419280 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 163206960 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2146087196 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0 252685 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 258147 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 248443 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 257431 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 256206 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 249786 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 257817 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 255503 # Number of bytes read from this memory +system.physmem.bytes_read::total 2036018 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 1421696 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5545 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5403 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5468 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5504 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5430 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5562 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5554 # Number of bytes written to this memory +system.physmem.bytes_written::total 1465524 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 13663 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 13833 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 13579 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 13621 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 13782 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 13599 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 13692 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 13646 # Number of read requests responded to by this memory +system.physmem.num_reads::total 109415 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 22214 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5545 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5403 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5504 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5430 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5562 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5554 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66042 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 486161282 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 496670069 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 477999752 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 495292498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 492935621 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 480583659 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 496035155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 491583062 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3917261097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2735316894 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10668478 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10395272 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10520331 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10589595 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10447220 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10316389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10701185 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10685794 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2819641158 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2735316894 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 496829759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 507065341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 488520083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 505882093 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 503382841 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 490900048 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 506736340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 502268855 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6736902255 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99682 # number of read accesses completed -system.cpu0.num_writes 55240 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22392 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.390751 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13565 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.595348 # Average number of references to valid blocks. +system.cpu0.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.num_reads 99523 # number of read accesses completed +system.cpu0.num_writes 55175 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.tags.replacements 22190 # number of replacements +system.cpu0.l1c.tags.tagsinuse 391.732266 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13637 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22577 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.604022 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.390751 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.768341 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.768341 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_blocks::cpu0 391.732266 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.765102 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.765102 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 377 # Occupied blocks per task id system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339133 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339133 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8847 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8847 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1120 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1120 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9967 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9967 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9967 # number of overall hits -system.cpu0.l1c.overall_hits::total 9967 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36618 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36618 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23969 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60587 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60587 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60587 # number of overall misses -system.cpu0.l1c.overall_misses::total 60587 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 672506192 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 672506192 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 563028530 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 563028530 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1235534722 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1235534722 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1235534722 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1235534722 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45465 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45465 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25089 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25089 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70554 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70554 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70554 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70554 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955359 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.955359 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858732 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858732 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858732 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858732 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18365.453930 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 18365.453930 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23489.863157 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 23489.863157 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20392.736429 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20392.736429 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20392.736429 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20392.736429 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 823442 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338094 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338094 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.ReadReq_hits::cpu0 8745 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8745 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1203 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1203 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9948 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9948 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9948 # number of overall hits +system.cpu0.l1c.overall_hits::total 9948 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36338 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36338 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24073 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24073 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60411 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60411 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60411 # number of overall misses +system.cpu0.l1c.overall_misses::total 60411 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 720327390 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 720327390 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 585363499 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 585363499 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1305690889 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1305690889 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1305690889 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1305690889 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45083 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45083 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25276 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25276 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70359 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70359 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70359 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70359 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806024 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806024 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952405 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.952405 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858611 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858611 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858611 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858611 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19822.978425 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 19822.978425 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24316.184065 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 24316.184065 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21613.462598 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21613.462598 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21613.462598 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21613.462598 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 881814 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 66357 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67116 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.409271 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.138655 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 9844 # number of writebacks -system.cpu0.l1c.writebacks::total 9844 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36618 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36618 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60587 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60587 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60587 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60587 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9910 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5376 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15286 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15286 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 635888192 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 635888192 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 539061530 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 539061530 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1174949722 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1174949722 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1174949722 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1174949722 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 753971133 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 753971133 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 753971133 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 753971133 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955359 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955359 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858732 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858732 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858732 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17365.453930 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17365.453930 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22489.946598 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22489.946598 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19392.769439 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 76081.849950 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76081.849950 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 49324.292359 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 49324.292359 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99541 # number of read accesses completed -system.cpu1.num_writes 55028 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22314 # number of replacements -system.cpu1.l1c.tags.tagsinuse 393.210618 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13573 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22722 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597351 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 9797 # number of writebacks +system.cpu0.l1c.writebacks::total 9797 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36338 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36338 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24073 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24073 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60411 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60411 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60411 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60411 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9869 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9869 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5547 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5547 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15416 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15416 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 683989390 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 683989390 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 561290499 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 561290499 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245279889 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1245279889 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245279889 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1245279889 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 771084187 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 771084187 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 771084187 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 771084187 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806024 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806024 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952405 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952405 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858611 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858611 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858611 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18822.978425 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18822.978425 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23316.184065 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23316.184065 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20613.462598 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78131.947208 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78131.947208 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50018.434549 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50018.434549 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.num_reads 99560 # number of read accesses completed +system.cpu1.num_writes 54738 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.tags.replacements 22160 # number of replacements +system.cpu1.l1c.tags.tagsinuse 392.166928 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13521 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22561 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.599309 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 393.210618 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.767989 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.767989 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 408 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.796875 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338638 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338638 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8704 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8704 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9853 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9853 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9853 # number of overall hits -system.cpu1.l1c.overall_hits::total 9853 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36652 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36652 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23946 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23946 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60598 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60598 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60598 # number of overall misses -system.cpu1.l1c.overall_misses::total 60598 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 672762640 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 672762640 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 564762705 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 564762705 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1237525345 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1237525345 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1237525345 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1237525345 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45356 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45356 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25095 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25095 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70451 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70451 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70451 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70451 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.808096 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.808096 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954214 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954214 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.860144 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.860144 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.860144 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.860144 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18355.414166 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 18355.414166 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23584.845277 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 23584.845277 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20421.884303 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20421.884303 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20421.884303 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20421.884303 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 822356 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 392.166928 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.765951 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.765951 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 337076 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 337076 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.ReadReq_hits::cpu1 8807 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8807 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1218 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1218 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 10025 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 10025 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 10025 # number of overall hits +system.cpu1.l1c.overall_hits::total 10025 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36399 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36399 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23708 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23708 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60107 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60107 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60107 # number of overall misses +system.cpu1.l1c.overall_misses::total 60107 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 728138208 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 728138208 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 572668423 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 572668423 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1300806631 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1300806631 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1300806631 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1300806631 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45206 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45206 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24926 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24926 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70132 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70132 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70132 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70132 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805181 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805181 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.951135 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.951135 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857055 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857055 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857055 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857055 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 20004.346493 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 20004.346493 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24155.070989 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 24155.070989 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21641.516479 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21641.516479 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21641.516479 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21641.516479 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 883013 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66159 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66936 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.429994 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 13.191900 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9894 # number of writebacks -system.cpu1.l1c.writebacks::total 9894 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36652 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36652 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23946 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23946 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60598 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60598 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60598 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60598 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9864 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9864 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5527 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5527 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15391 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15391 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 636111640 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 636111640 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 540817705 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 540817705 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1176929345 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1176929345 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1176929345 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1176929345 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 750538193 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 750538193 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 750538193 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 750538193 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.808096 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.808096 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954214 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954214 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.860144 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860144 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.860144 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17355.441449 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17355.441449 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22584.887038 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22584.887038 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19421.917308 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 76088.624594 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76088.624594 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48764.745176 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48764.745176 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 99993 # number of read accesses completed -system.cpu2.num_writes 55211 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22333 # number of replacements -system.cpu2.l1c.tags.tagsinuse 392.533782 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13552 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595509 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9595 # number of writebacks +system.cpu1.l1c.writebacks::total 9595 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36399 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36399 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23708 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23708 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60107 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60107 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60107 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60107 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9955 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9955 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5404 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5404 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15359 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15359 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 691742208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 691742208 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 548961423 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 548961423 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1240703631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1240703631 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1240703631 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1240703631 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 776683501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 776683501 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 776683501 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 776683501 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805181 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.951135 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.951135 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857055 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857055 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857055 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 19004.428913 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 19004.428913 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23155.113169 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23155.113169 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20641.583027 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78019.437569 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78019.437569 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50568.624325 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50568.624325 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.num_reads 98983 # number of read accesses completed +system.cpu2.num_writes 55204 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.tags.replacements 22113 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.892697 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13532 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22515 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.601022 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 392.533782 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.766668 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.766668 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 424 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 419 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.828125 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338842 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338842 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8700 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8700 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1131 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1131 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9831 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9831 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9831 # number of overall hits -system.cpu2.l1c.overall_hits::total 9831 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36743 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36743 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23917 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23917 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60660 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60660 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60660 # number of overall misses -system.cpu2.l1c.overall_misses::total 60660 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 667892138 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 667892138 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 561829218 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 561829218 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1229721356 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1229721356 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1229721356 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1229721356 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45443 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45443 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25048 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25048 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70491 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70491 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70491 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70491 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.808551 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.808551 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954847 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954847 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.860535 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.860535 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.860535 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.860535 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18177.398089 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 18177.398089 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23490.789731 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 23490.789731 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20272.359974 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20272.359974 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20272.359974 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20272.359974 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 824101 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.892697 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.765415 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.765415 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337818 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337818 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.ReadReq_hits::cpu2 8790 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8790 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1144 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1144 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9934 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9934 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9934 # number of overall hits +system.cpu2.l1c.overall_hits::total 9934 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36176 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36176 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24169 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24169 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60345 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60345 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60345 # number of overall misses +system.cpu2.l1c.overall_misses::total 60345 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 716181593 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 716181593 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 589266088 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 589266088 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1305447681 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1305447681 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1305447681 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1305447681 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44966 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44966 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25313 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25313 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70279 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70279 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70279 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70279 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804519 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.804519 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954806 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954806 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858649 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858649 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858649 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858649 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19797.147086 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 19797.147086 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24381.070297 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 24381.070297 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21633.071191 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21633.071191 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21633.071191 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21633.071191 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 879879 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66507 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66865 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.391192 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.159037 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9742 # number of writebacks -system.cpu2.l1c.writebacks::total 9742 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36743 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36743 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23917 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23917 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60660 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60660 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60660 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60660 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 10005 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5482 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15487 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 631149138 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 631149138 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537912218 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537912218 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1169061356 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1169061356 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1169061356 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1169061356 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 759988155 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 759988155 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 759988155 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 759988155 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.808551 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.808551 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954847 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954847 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.860535 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.860535 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.860535 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17177.398089 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17177.398089 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22490.789731 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22490.789731 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19272.359974 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 75960.835082 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75960.835082 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 49072.651579 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 49072.651579 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 99085 # number of read accesses completed -system.cpu3.num_writes 55606 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22528 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.624901 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13493 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22909 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.588982 # Average number of references to valid blocks. +system.cpu2.l1c.writebacks::writebacks 9745 # number of writebacks +system.cpu2.l1c.writebacks::total 9745 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36176 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36176 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24169 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24169 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60345 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60345 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60345 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9851 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9851 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5469 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15320 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15320 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 680005593 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 680005593 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 565098088 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 565098088 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245103681 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1245103681 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245103681 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1245103681 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769729433 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769729433 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769729433 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769729433 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804519 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804519 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954806 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954806 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858649 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858649 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858649 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18797.147086 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18797.147086 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23381.111672 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23381.111672 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20633.087762 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78137.187392 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78137.187392 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50243.435574 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50243.435574 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 55136 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.tags.replacements 22201 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.334218 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13633 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22606 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.603070 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.624901 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.764892 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.764892 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 381 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.744141 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 339302 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 339302 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8770 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8770 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1134 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1134 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9904 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9904 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9904 # number of overall hits -system.cpu3.l1c.overall_hits::total 9904 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36439 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36439 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 24225 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 24225 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60664 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60664 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60664 # number of overall misses -system.cpu3.l1c.overall_misses::total 60664 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 671429109 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 671429109 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 572133441 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 572133441 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1243562550 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1243562550 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1243562550 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1243562550 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45209 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25359 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70568 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70568 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70568 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70568 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806012 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.806012 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955282 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955282 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859653 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859653 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859653 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859653 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18426.112380 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 18426.112380 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23617.479505 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 23617.479505 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20499.184854 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20499.184854 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20499.184854 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20499.184854 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 821290 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.334218 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766278 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766278 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 339332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 339332 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.ReadReq_hits::cpu3 8805 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8805 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1190 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1190 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9995 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9995 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9995 # number of overall hits +system.cpu3.l1c.overall_hits::total 9995 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36852 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36852 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23757 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23757 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60609 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60609 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60609 # number of overall misses +system.cpu3.l1c.overall_misses::total 60609 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 737200497 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 737200497 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 577684792 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 577684792 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1314885289 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1314885289 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1314885289 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1314885289 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45657 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45657 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24947 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24947 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70604 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70604 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70604 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70604 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807149 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807149 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.952299 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.952299 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858436 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858436 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858436 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858436 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 20004.355177 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 20004.355177 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24316.403250 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 24316.403250 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21694.555083 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21694.555083 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21694.555083 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21694.555083 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 880663 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66174 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67164 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.411068 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.112129 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 10017 # number of writebacks -system.cpu3.l1c.writebacks::total 10017 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36439 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36439 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24225 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 24225 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60664 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60664 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60664 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60664 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9773 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5538 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5538 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15311 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15311 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 634992109 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 634992109 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 547908441 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 547908441 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1182900550 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1182900550 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1182900550 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1182900550 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 743773245 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 743773245 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 743773245 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 743773245 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806012 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806012 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955282 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955282 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859653 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859653 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859653 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17426.167266 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17426.167266 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22617.479505 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22617.479505 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19499.217823 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 76104.905863 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76104.905863 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 48577.705245 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 48577.705245 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 99978 # number of read accesses completed -system.cpu4.num_writes 55474 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22223 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.899958 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13858 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22628 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.612427 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 9556 # number of writebacks +system.cpu3.l1c.writebacks::total 9556 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36852 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36852 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23757 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23757 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60609 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60609 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60609 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60609 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9752 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9752 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5506 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15258 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15258 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 700349497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 700349497 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 553928792 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 553928792 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1254278289 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1254278289 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1254278289 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1254278289 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 761853080 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 761853080 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 761853080 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 761853080 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807149 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807149 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.952299 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.952299 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858436 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858436 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858436 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 19004.382313 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 19004.382313 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23316.445342 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23316.445342 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20694.588081 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78122.752256 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78122.752256 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 49931.385503 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 49931.385503 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.num_reads 99808 # number of read accesses completed +system.cpu4.num_writes 55157 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.tags.replacements 22030 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.026241 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13726 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22418 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.612276 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.899958 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765430 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765430 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 396 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 340964 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 340964 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8890 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8890 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1171 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1171 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10061 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10061 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10061 # number of overall hits -system.cpu4.l1c.overall_hits::total 10061 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36725 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36725 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24186 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24186 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60911 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60911 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60911 # number of overall misses -system.cpu4.l1c.overall_misses::total 60911 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 668441602 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 668441602 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 573535032 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 573535032 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1241976634 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1241976634 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1241976634 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1241976634 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45615 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45615 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25357 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25357 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70972 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70972 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70972 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70972 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805108 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.805108 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953819 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953819 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.858240 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.858240 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.858240 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.858240 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18201.268945 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 18201.268945 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23713.513272 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 23713.513272 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20390.022065 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20390.022065 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20390.022065 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20390.022065 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 823668 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.026241 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.765676 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.765676 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 388 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338084 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338084 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.ReadReq_hits::cpu4 8869 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8869 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1181 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1181 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 10050 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 10050 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 10050 # number of overall hits +system.cpu4.l1c.overall_hits::total 10050 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36458 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23868 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23868 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60326 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60326 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60326 # number of overall misses +system.cpu4.l1c.overall_misses::total 60326 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 723342269 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 723342269 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 578669341 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 578669341 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1302011610 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1302011610 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1302011610 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1302011610 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45327 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45327 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25049 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25049 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70376 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70376 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70376 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70376 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804333 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804333 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952852 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952852 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.857196 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.857196 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.857196 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.857196 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19840.426491 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 19840.426491 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24244.567664 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 24244.567664 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21582.926267 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21582.926267 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21582.926267 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21582.926267 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 883463 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 66629 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67109 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.362005 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.164598 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9699 # number of writebacks -system.cpu4.l1c.writebacks::total 9699 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36725 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36725 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24186 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24186 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60911 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60911 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60911 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60911 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9801 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5498 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15299 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 631717602 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 631717602 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 549351032 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 549351032 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1181068634 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1181068634 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1181068634 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1181068634 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 748050214 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 748050214 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 748050214 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 748050214 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805108 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805108 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953819 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953819 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.858240 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858240 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.858240 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17201.296174 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17201.296174 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22713.595965 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22713.595965 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19390.071317 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 76323.866340 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76323.866340 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48895.366625 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48895.366625 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 55110 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22358 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.816568 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22751 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.599095 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9613 # number of writebacks +system.cpu4.l1c.writebacks::total 9613 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36458 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23868 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23868 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60326 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60326 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60326 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60326 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9934 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9934 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5430 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5430 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15364 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15364 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 686885269 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 686885269 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 554802341 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 554802341 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1241687610 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1241687610 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1241687610 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1241687610 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 775754665 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 775754665 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 775754665 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 775754665 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804333 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804333 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952852 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952852 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.857196 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857196 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.857196 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18840.453920 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18840.453920 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23244.609561 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23244.609561 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20582.959420 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78090.866217 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78090.866217 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50491.712119 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50491.712119 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.num_reads 99404 # number of read accesses completed +system.cpu5.num_writes 55162 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.tags.replacements 22439 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.788419 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13514 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22846 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.591526 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.816568 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765267 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765267 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 388 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 340100 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 340100 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8821 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8821 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1107 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1107 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9928 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9928 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9928 # number of overall hits -system.cpu5.l1c.overall_hits::total 9928 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36801 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36801 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24029 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24029 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60830 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60830 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60830 # number of overall misses -system.cpu5.l1c.overall_misses::total 60830 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 677475643 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 677475643 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 566244558 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 566244558 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1243720201 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1243720201 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1243720201 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1243720201 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45622 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45622 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25136 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70758 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70758 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70758 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70758 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806650 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.806650 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955960 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955960 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859691 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859691 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859691 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859691 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18409.163963 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 18409.163963 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23565.048816 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 23565.048816 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20445.835953 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20445.835953 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20445.835953 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20445.835953 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 821580 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.788419 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.765212 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.765212 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338295 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338295 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.ReadReq_hits::cpu5 8686 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8686 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1223 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1223 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9909 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9909 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9909 # number of overall hits +system.cpu5.l1c.overall_hits::total 9909 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36676 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36676 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23788 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60464 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60464 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60464 # number of overall misses +system.cpu5.l1c.overall_misses::total 60464 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 728782621 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 728782621 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 575848202 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 575848202 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1304630823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1304630823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1304630823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1304630823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45362 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45362 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25011 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25011 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70373 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70373 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70373 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70373 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808518 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808518 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951102 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.951102 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859193 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859193 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859193 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859193 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19870.831634 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 19870.831634 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24207.508071 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 24207.508071 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21576.985032 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21576.985032 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21576.985032 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21576.985032 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 880240 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66406 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 67028 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.372075 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.132422 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 10004 # number of writebacks -system.cpu5.l1c.writebacks::total 10004 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36801 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36801 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24029 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24029 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60830 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60830 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60830 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60830 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9765 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5412 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5412 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15177 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15177 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 640675643 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 640675643 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 542215558 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 542215558 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1182891201 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1182891201 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1182891201 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1182891201 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 744215663 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 744215663 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 744215663 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 744215663 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806650 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806650 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955960 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955960 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859691 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859691 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859691 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17409.191136 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17409.191136 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22565.048816 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22565.048816 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19445.852392 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 76212.561495 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76212.561495 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 49035.755617 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 49035.755617 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 99774 # number of read accesses completed -system.cpu6.num_writes 55185 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22542 # number of replacements -system.cpu6.l1c.tags.tagsinuse 391.726459 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13419 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22929 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.585241 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 9753 # number of writebacks +system.cpu5.l1c.writebacks::total 9753 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36676 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36676 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23788 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60464 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60464 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60464 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60464 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9850 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9850 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5362 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5362 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15212 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15212 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 692108621 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 692108621 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 552061202 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 552061202 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1244169823 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1244169823 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1244169823 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1244169823 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 771042075 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 771042075 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 771042075 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 771042075 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808518 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808518 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951102 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951102 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859193 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859193 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859193 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18870.886165 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18870.886165 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23207.550109 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23207.550109 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20577.034649 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78278.383249 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78278.383249 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50686.436695 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50686.436695 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.num_reads 99584 # number of read accesses completed +system.cpu6.num_writes 55158 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.tags.replacements 22137 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.593819 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13609 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22548 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.603557 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 391.726459 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765091 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765091 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 375 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_blocks::cpu6 391.593819 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.764832 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.764832 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id system.cpu6.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 339673 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 339673 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8710 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8710 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1147 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1147 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9857 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9857 # number of overall hits -system.cpu6.l1c.overall_hits::total 9857 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36696 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36696 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 24079 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 24079 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60775 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60775 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60775 # number of overall misses -system.cpu6.l1c.overall_misses::total 60775 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 672502171 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 672502171 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 571063447 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 571063447 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1243565618 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1243565618 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1243565618 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1243565618 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45406 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45406 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25226 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25226 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70632 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70632 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70632 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70632 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808175 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.808175 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954531 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954531 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860446 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860446 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860446 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860446 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18326.307254 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 18326.307254 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23716.244321 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 23716.244321 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20461.795442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20461.795442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20461.795442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20461.795442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 822508 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 338403 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 338403 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.ReadReq_hits::cpu6 8781 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8781 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1188 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9969 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9969 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9969 # number of overall hits +system.cpu6.l1c.overall_hits::total 9969 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36497 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36497 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23948 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23948 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60445 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60445 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60445 # number of overall misses +system.cpu6.l1c.overall_misses::total 60445 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 730258004 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 730258004 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 580007386 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 580007386 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1310265390 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1310265390 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1310265390 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1310265390 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45278 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45278 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25136 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25136 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70414 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70414 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70414 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70414 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806065 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806065 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.952737 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.952737 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858423 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858423 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858423 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858423 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 20008.713155 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 20008.713155 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24219.449891 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 24219.449891 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21676.985524 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21676.985524 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21676.985524 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21676.985524 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 882368 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66430 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 67127 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.381575 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.144755 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9969 # number of writebacks -system.cpu6.l1c.writebacks::total 9969 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36696 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36696 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 24079 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 24079 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60775 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60775 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60775 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60775 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9782 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5438 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15220 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 635806171 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 635806171 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 546984447 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 546984447 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1182790618 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1182790618 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1182790618 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1182790618 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 745377162 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 745377162 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 745377162 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 745377162 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808175 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808175 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954531 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954531 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860446 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860446 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860446 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17326.307254 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17326.307254 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22716.244321 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22716.244321 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19461.795442 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 76198.851155 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76198.851155 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 48973.532326 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 48973.532326 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 99703 # number of read accesses completed -system.cpu7.num_writes 55656 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 22447 # number of replacements -system.cpu7.l1c.tags.tagsinuse 392.675740 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13542 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22845 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.592777 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9587 # number of writebacks +system.cpu6.l1c.writebacks::total 9587 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36497 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36497 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23948 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23948 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60445 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60445 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60445 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60445 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9817 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9817 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5564 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5564 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15381 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15381 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 693763004 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 693763004 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 556061386 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 556061386 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1249824390 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1249824390 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1249824390 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1249824390 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 767059984 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 767059984 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 767059984 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 767059984 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806065 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806065 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.952737 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.952737 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858423 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858423 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858423 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 19008.767954 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 19008.767954 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23219.533406 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23219.533406 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20677.051700 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78135.885097 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78135.885097 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 49870.618555 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 49870.618555 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.num_reads 98890 # number of read accesses completed +system.cpu7.num_writes 55602 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.tags.replacements 22121 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.886114 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13491 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22504 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.599493 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 392.675740 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.766945 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.766945 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 391 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 338950 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 338950 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8682 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8682 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1173 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1173 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9855 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9855 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9855 # number of overall hits -system.cpu7.l1c.overall_hits::total 9855 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36511 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36511 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24145 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24145 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60656 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60656 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60656 # number of overall misses -system.cpu7.l1c.overall_misses::total 60656 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 668215285 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 668215285 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 564137498 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 564137498 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1232352783 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1232352783 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1232352783 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1232352783 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45193 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45193 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25318 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25318 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70511 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70511 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70511 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70511 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807891 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807891 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953669 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953669 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.860235 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.860235 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.860235 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.860235 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18301.752486 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 18301.752486 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23364.568151 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 23364.568151 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20317.079646 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20317.079646 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20317.079646 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20317.079646 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 824059 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 391.886114 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.765403 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.765403 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 383 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 374 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.748047 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 336547 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 336547 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.ReadReq_hits::cpu7 8615 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1223 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1223 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9838 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9838 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9838 # number of overall hits +system.cpu7.l1c.overall_hits::total 9838 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36077 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36077 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24110 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24110 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60187 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60187 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60187 # number of overall misses +system.cpu7.l1c.overall_misses::total 60187 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 719876948 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 719876948 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 591584960 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 591584960 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1311461908 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1311461908 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1311461908 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1311461908 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44692 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25333 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25333 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70025 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70025 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70025 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70025 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807236 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807236 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.951723 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.951723 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859507 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859507 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859507 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859507 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19953.902708 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 19953.902708 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24536.912484 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 24536.912484 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21789.786964 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21789.786964 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21789.786964 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21789.786964 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 881767 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 66592 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66704 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.374745 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.219102 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9889 # number of writebacks -system.cpu7.l1c.writebacks::total 9889 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36511 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36511 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24145 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24145 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60656 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60656 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60656 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60656 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9951 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5417 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5417 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15368 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15368 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 631704285 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 631704285 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 539994498 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 539994498 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1171698783 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1171698783 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1171698783 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1171698783 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 757938041 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 757938041 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 757938041 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 757938041 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807891 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807891 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953669 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953669 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.860235 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.860235 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.860235 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17301.752486 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17301.752486 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22364.650984 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22364.650984 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19317.112619 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 76167.022510 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 76167.022510 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49319.237441 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49319.237441 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 13600 # number of replacements -system.l2c.tags.tagsinuse 785.994901 # Cycle average of tags in use -system.l2c.tags.total_refs 164496 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14391 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.430477 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.947637 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.698781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.684981 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.056959 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 6.865777 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.833706 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 7.577663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.826515 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.502881 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713816 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006528 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006892 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006705 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006674 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.007400 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006667 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006350 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.767573 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 651 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 140 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.772461 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2102241 # Number of tag accesses -system.l2c.tags.data_accesses 2102241 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 77703 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77703 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 290 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 294 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 264 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 279 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 289 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 268 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2299 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1816 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1719 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1709 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1788 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1754 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1794 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1762 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14182 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10810 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10840 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 11008 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 10829 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10875 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10716 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 10827 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10910 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 86815 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12626 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12559 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12717 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12669 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12663 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12470 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12621 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12672 # number of demand (read+write) hits -system.l2c.demand_hits::total 100997 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12626 # number of overall hits -system.l2c.overall_hits::cpu1 12559 # number of overall hits -system.l2c.overall_hits::cpu2 12717 # number of overall hits -system.l2c.overall_hits::cpu3 12669 # number of overall hits -system.l2c.overall_hits::cpu4 12663 # number of overall hits -system.l2c.overall_hits::cpu5 12470 # number of overall hits -system.l2c.overall_hits::cpu6 12621 # number of overall hits -system.l2c.overall_hits::cpu7 12672 # number of overall hits -system.l2c.overall_hits::total 100997 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 1987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2133 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2089 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2051 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 2132 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2090 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2082 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16603 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4589 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4573 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4653 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4696 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4757 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4526 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4651 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4580 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37025 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 704 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 708 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 710 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 726 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 671 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 758 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 689 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 675 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5641 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5293 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5363 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5422 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5428 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5284 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5340 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5255 # 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number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 35922999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 36683500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 35141499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 35012999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 282539995 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 156097931 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 156545440 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 159419095 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 159741454 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 162402934 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 154349443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 159730395 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 156156442 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1264443134 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 50090895 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 50336063 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 50437231 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 51704240 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 47729417 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 53673691 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 48908906 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 47302737 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 400183180 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 206188826 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 206881503 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 209856326 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 211445694 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 210132351 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 208023134 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 208639301 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 203459179 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1664626314 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 206188826 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 206881503 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 209856326 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 211445694 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 210132351 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 208023134 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 208639301 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 203459179 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1664626314 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77703 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77703 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2277 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2423 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2383 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2315 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2411 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2379 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2350 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2364 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18902 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6405 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6292 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6362 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6536 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6545 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6445 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6342 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51207 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11514 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11548 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11718 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11555 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11546 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11474 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11516 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11585 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92456 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17919 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17840 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18080 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18091 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17754 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17961 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17927 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 143663 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17919 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17840 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18080 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18091 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17754 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17961 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17927 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 143663 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.872639 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.880314 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.876626 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.885961 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.884280 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.878520 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.885957 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.862521 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.878373 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.716472 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.726796 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.731374 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.718482 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.726814 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.720701 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.721645 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.722170 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.723046 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.061143 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061309 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.060591 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062830 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.058115 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.066062 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.059830 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.058265 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.061013 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.295385 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.296020 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.296626 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.299707 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.300039 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.297623 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.297311 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.293133 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.296987 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.295385 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.296020 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.296626 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.299707 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.300039 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.297623 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.297311 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.293133 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.296987 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16624.810770 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 17381.152836 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16995.691719 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16658.946855 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 16849.436679 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 17551.913876 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16878.721902 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 17171.652281 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 17017.406192 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 34015.674657 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 34232.547562 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 34261.572104 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 34016.493612 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 34139.780114 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 34102.837605 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 34343.236938 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 34095.293013 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 34151.063714 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 71151.839489 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 71096.134181 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 71038.353521 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 71217.961433 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 71131.769001 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70809.618734 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 70985.349782 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70078.128889 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 70941.886190 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 38955.002078 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 39174.683393 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 39130.398285 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 38997.730358 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 38712.665991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 39368.496215 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 39071.030150 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 38717.255756 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 39015.288848 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 38955.002078 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 39174.683393 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 39130.398285 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 38997.730358 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 38712.665991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 39368.496215 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 39071.030150 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 38717.255756 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 39015.288848 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 20827 # number of cycles access was blocked +system.cpu7.l1c.writebacks::writebacks 9764 # number of writebacks +system.cpu7.l1c.writebacks::total 9764 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36077 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36077 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24110 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24110 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60187 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60187 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60187 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60187 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9808 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5554 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5554 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15362 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15362 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 683799948 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 683799948 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 567476960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 567476960 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1251276908 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1251276908 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1251276908 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1251276908 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 764550984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 764550984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 764550984 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 764550984 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807236 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807236 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.951723 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.951723 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859507 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859507 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859507 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18953.902708 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18953.902708 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23536.995438 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23536.995438 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20789.820194 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 77951.772431 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 77951.772431 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49768.974352 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49768.974352 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 90719 # number of replacements +system.l2c.tags.tagsinuse 1018.150991 # Cycle average of tags in use +system.l2c.tags.total_refs 149983 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 91743 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.634817 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 9046000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 702.470265 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 39.119320 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 40.193520 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 38.067708 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 40.504400 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 39.836129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 39.104490 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 39.067369 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 39.787790 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.686006 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.038202 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.039251 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.037175 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.039555 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.038902 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.038188 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.038152 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.038855 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994288 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 929 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 95 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2127679 # Number of tag accesses +system.l2c.tags.data_accesses 2127679 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 76258 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 76258 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 455 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 421 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 452 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 407 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 451 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 439 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 454 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 475 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3554 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1826 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1861 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1960 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1829 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1871 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1808 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1856 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1881 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 14892 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 9343 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 9296 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 9301 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 9456 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 9362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 9172 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 9284 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 9134 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 74348 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 11169 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 11157 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 11261 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 11285 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 11233 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 10980 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 11140 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 11015 # number of demand (read+write) hits +system.l2c.demand_hits::total 89240 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 11169 # number of overall hits +system.l2c.overall_hits::cpu1 11157 # number of overall hits +system.l2c.overall_hits::cpu2 11261 # number of overall hits +system.l2c.overall_hits::cpu3 11285 # number of overall hits +system.l2c.overall_hits::cpu4 11233 # number of overall hits +system.l2c.overall_hits::cpu5 10980 # number of overall hits +system.l2c.overall_hits::cpu6 11140 # number of overall hits +system.l2c.overall_hits::cpu7 11015 # number of overall hits +system.l2c.overall_hits::total 89240 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1925 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1914 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1906 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1942 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1877 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1898 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1911 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15209 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4693 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4629 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4644 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4614 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4607 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4628 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4562 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4784 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37161 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 2455 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 2583 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 2376 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 2554 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 2482 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 2499 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 2567 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 2497 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 20013 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 7148 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 7212 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 7020 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 7168 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 7089 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 7127 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 7129 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 7281 # number of demand (read+write) misses +system.l2c.demand_misses::total 57174 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 7148 # number of overall misses +system.l2c.overall_misses::cpu1 7212 # number of overall misses +system.l2c.overall_misses::cpu2 7020 # number of overall misses +system.l2c.overall_misses::cpu3 7168 # number of overall misses +system.l2c.overall_misses::cpu4 7089 # number of overall misses +system.l2c.overall_misses::cpu5 7127 # number of overall misses +system.l2c.overall_misses::cpu6 7129 # number of overall misses +system.l2c.overall_misses::cpu7 7281 # number of overall misses +system.l2c.overall_misses::total 57174 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 32240808 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 31334307 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 31443971 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 32481798 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 31939294 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 32487949 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 32438947 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 31458982 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 255826056 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 205522581 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 201589053 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 204096506 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 201630443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 202953396 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 200092863 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 200475342 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 208573158 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1624933342 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 170016591 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 178762923 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 164403073 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 176363992 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 171439292 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 173166429 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 177285527 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 173293048 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1384730875 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 375539172 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 380351976 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 368499579 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 377994435 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 374392688 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 373259292 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 377760869 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 381866206 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 3009664217 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 375539172 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 380351976 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 368499579 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 377994435 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 374392688 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 373259292 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 377760869 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 381866206 # number of overall miss cycles +system.l2c.overall_miss_latency::total 3009664217 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 76258 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 76258 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2380 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2366 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2313 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2393 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2386 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18763 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6519 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6490 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6604 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6443 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6478 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6436 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6418 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6665 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 52053 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11798 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11879 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11677 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 12010 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11844 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11671 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11851 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11631 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 94361 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18317 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18369 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18281 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18453 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18322 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18107 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18269 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18296 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 146414 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18317 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18369 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18281 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18453 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18322 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18107 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18269 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18296 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 146414 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.808824 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.813469 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.808960 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.824038 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.811534 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.810449 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.806973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.800922 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.810585 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.719896 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.713251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.703210 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.716126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.711176 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.719080 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.710813 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.717779 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.713907 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.208086 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.217443 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.203477 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.212656 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.209558 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.214120 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.216606 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.214685 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.212090 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.390239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.392618 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.384005 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.388446 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.386912 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.393605 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.390224 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.397956 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.390495 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.390239 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.392618 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.384005 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.388446 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.386912 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.393605 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.390224 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.397956 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.390495 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16748.471688 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17066.616013 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16428.407001 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 17041.866737 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16446.598352 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 17308.443793 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 17091.120653 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 16462.052329 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16820.701953 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 43793.432985 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 43549.158134 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 43948.429371 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 43699.705895 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 44053.265900 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 43235.277226 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 43944.616835 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 43598.068144 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43726.846479 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 69253.193890 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69207.480836 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 69193.212542 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69054.029757 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69073.042707 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 69294.289316 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69063.313985 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 69400.499800 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 69191.569230 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 52537.656967 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 52738.765391 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 52492.817521 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 52733.598633 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 52813.187756 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 52372.567981 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 52989.320943 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 52446.944925 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52640.434761 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 52537.656967 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 52738.765391 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 52492.817521 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 52733.598633 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 52813.187756 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 52372.567981 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 52989.320943 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 52446.944925 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52640.434761 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 47178 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 3189 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7722 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.530887 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.109557 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 6244 # number of writebacks -system.l2c.writebacks::total 6244 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 22214 # number of writebacks +system.l2c.writebacks::total 22214 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 3 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 3 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 6 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 35 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 4 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 15 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 77 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 20 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 18 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 21 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 112 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 20 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 18 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 21 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 112 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1208 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1208 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2132 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2088 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2051 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 2132 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2088 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2082 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2039 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16599 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4587 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4571 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4648 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4690 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4753 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4524 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4643 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4574 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 36990 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 694 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 699 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 695 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 722 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 667 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 748 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 679 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 660 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5564 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5270 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5343 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5412 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5420 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5272 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5322 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5234 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42554 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5270 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5343 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5412 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5420 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5272 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5322 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5234 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42554 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9909 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9863 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 10005 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9773 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9801 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9765 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9782 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9951 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78849 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5376 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5525 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5482 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5537 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5496 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5409 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5438 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5416 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43679 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15285 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15388 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15487 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15310 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15297 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15174 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15220 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15367 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122528 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 41114731 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 44135575 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 43262560 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 42495420 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 44129731 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 43370592 # 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number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 302054261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 306322137 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 296297099 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 304395905 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 301535545 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 299654753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 304396658 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 306944563 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2421600921 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 302054261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 306322137 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 296297099 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 304395905 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 301535545 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 299654753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 304396658 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 306944563 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2421600921 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 562092060 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 566771491 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 561276835 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 555967979 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 566543445 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 562440249 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 559671781 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 557696401 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4492460241 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 562092060 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 566771491 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 561276835 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 555967979 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 566543445 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 562440249 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 559671781 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 557696401 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4492460241 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.872639 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.879901 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.876206 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885961 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.884280 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877680 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.885957 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.862521 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.878161 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.716159 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.726478 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.730588 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.717564 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.726203 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.720382 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.720403 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.721224 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.722362 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.060274 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060530 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.059310 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.062484 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.057769 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.065191 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.058961 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.056970 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060180 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.296207 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.294715 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.295404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.295520 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.299154 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.299596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.296947 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.296309 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.291962 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.296207 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 20691.862607 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 20701.489212 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 20719.616858 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 20719.366163 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 20698.748124 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 20771.356322 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 20749.953410 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 20709.958803 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20720.381830 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 24001.767822 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 24221.536863 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 24262.455034 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 23997.184435 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 24131.203240 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 24085.288904 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 24326.427956 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 24073.189550 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 24137.530954 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61507.478386 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 61362.762518 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 61487.571223 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 61213.202216 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 61137.245877 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 61185.187166 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 61326.808542 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60535.683333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 61223.593098 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 28930.562204 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 29147.858824 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 29104.576642 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 28962.070769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 28685.267897 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 29349.083270 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 29047.070274 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 28671.058464 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 28986.589792 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 53681.966192 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 53649.439217 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 53634.408396 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 53694.368464 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 53733.009183 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 53665.975422 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 53639.533020 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 53741.686363 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 53680.037122 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 34801.086228 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 34386.822134 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 34649.206173 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 34275.314370 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 34427.484016 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 34535.933175 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 34474.501445 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 34800.775753 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 34544.081736 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 125015 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 119335 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.808403 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.812140 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.808538 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.822741 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810280 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.809585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.806548 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.799246 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.809625 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.717441 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.710478 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.700333 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.712711 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.707471 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.716128 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708165 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.715079 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.710968 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.204780 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.214496 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.200051 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.209908 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.207109 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.210779 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.213484 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.211934 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209080 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.387511 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.387236 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.389733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.380778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.385466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.384019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.390402 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.387268 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.395223 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.387511 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 23061.571206 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22859.004910 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22975.897020 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22883.091435 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 23164.956163 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 23028.385067 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 23177.657354 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22932.680650 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 23011.397736 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 33776.545221 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33575.478421 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33974.752432 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33713.470819 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 34070.032730 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33189.968757 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33914.038504 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33567.862568 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33721.740840 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 59636.324089 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59460.598901 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59573.574058 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59335.044427 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59271.335100 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59626.905285 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59390.258103 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59618.713996 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59487.390947 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42584.838714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42788.397402 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42565.306565 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42794.306903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42856.103610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42389.977790 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43024.262615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42448.425252 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42681.159050 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56955.320701 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56933.349171 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56976.635367 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 57016.508973 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 57030.747433 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 57100.532893 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 57010.469695 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56861.378569 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56985.605898 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36463.967564 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36903.990819 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36639.260722 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36444.967486 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36874.736071 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36973.458388 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36389.582640 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36303.632405 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 36623.814788 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 164288 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 148961 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78845 # Transaction distribution -system.membus.trans_dist::ReadResp 84388 # Transaction distribution -system.membus.trans_dist::WriteReq 43678 # Transaction distribution -system.membus.trans_dist::WriteResp 43672 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6244 # Transaction distribution -system.membus.trans_dist::CleanEvict 1238 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61417 # Transaction distribution -system.membus.trans_dist::ReadExReq 49074 # Transaction distribution -system.membus.trans_dist::ReadExResp 3109 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5552 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377217 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 377217 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1076434 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1076434 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56879 # Total snoops (count) +system.membus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 78834 # Transaction distribution +system.membus.trans_dist::ReadResp 98509 # Transaction distribution +system.membus.trans_dist::WriteReq 43828 # Transaction distribution +system.membus.trans_dist::WriteResp 43821 # Transaction distribution +system.membus.trans_dist::WritebackDirty 22214 # Transaction distribution +system.membus.trans_dist::CleanEvict 4965 # Transaction distribution +system.membus.trans_dist::UpgradeReq 52120 # Transaction distribution +system.membus.trans_dist::ReadExReq 56238 # Transaction distribution +system.membus.trans_dist::ReadExResp 10901 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 19680 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 431110 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 431110 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3501537 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 3501537 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 56051 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 245548 # Request fanout histogram +system.membus.snoop_fanout::samples 276559 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 245548 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 276559 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 245548 # Request fanout histogram -system.membus.reqLayer0.occupancy 288762573 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 57.6 # Layer utilization (%) -system.membus.respLayer0.occupancy 244649000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 48.8 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 663848 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 283900 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 334405 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12239 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5805 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6434 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 501584000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78849 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 372013 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43679 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43671 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83947 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105636 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29816 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29815 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162678 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162674 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 293185 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133340 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 134024 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133820 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133294 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1069251 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1781172 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1779932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1786043 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1802764 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1783744 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1780612 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1792304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1782917 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14289488 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 336712 # Total snoops (count) -system.toL2Bus.snoopTraffic 20380288 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 624467 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.150434 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.985907 # Request fanout histogram +system.membus.snoop_fanout::total 276559 # Request fanout histogram +system.membus.reqLayer0.occupancy 402118445 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 77.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 354384000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 68.2 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 665414 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 284013 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335409 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 85048 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 42676 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 42372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 519755500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 78835 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370283 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43830 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43821 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 98472 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 166953 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29477 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161940 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161937 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291468 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133274 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133373 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133750 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133468 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133407 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133623 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133404 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1068068 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1804723 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795646 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1797908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1798742 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1795138 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1788203 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1789204 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1803712 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14373276 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 408427 # Total snoops (count) +system.toL2Bus.snoopTraffic 21069312 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 705291 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.195765 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.989501 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 172892 27.69% 27.69% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 258676 41.42% 69.11% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133601 21.39% 90.50% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 46619 7.47% 97.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 10890 1.74% 99.71% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1624 0.26% 99.97% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 162 0.03% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 180431 25.58% 25.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 295517 41.90% 67.48% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 157808 22.37% 89.86% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 56265 7.98% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 13098 1.86% 99.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1998 0.28% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 166 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 8 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 624467 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 494463871 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.6 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102665881 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102599371 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102945420 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102767709 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102912196 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102768177 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102966672 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 102752542 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 705291 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 498497896 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102236927 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101928534 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102159135 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102401165 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102112987 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102230994 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102247991 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101908995 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index bfbf99e79..797f06fbf 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,1765 +1,1777 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000500 # Number of seconds simulated -sim_ticks 500337000 # Number of ticks simulated -final_tick 500337000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000522 # Number of seconds simulated +sim_ticks 521659000 # Number of ticks simulated +final_tick 521659000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 71022114 # Simulator tick rate (ticks/s) -host_mem_usage 232508 # Number of bytes of host memory used -host_seconds 7.04 # Real time elapsed on the host +host_tick_rate 99821577 # Simulator tick rate (ticks/s) +host_mem_usage 236108 # Number of bytes of host memory used +host_seconds 5.23 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0 75919 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81043 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 80577 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 79993 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82197 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 76405 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 83460 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78091 # Number of bytes read from this memory -system.physmem.bytes_read::total 637685 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 400320 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5398 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5467 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5426 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5579 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5520 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5589 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5357 # Number of bytes written to this memory -system.physmem.bytes_written::total 444107 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10777 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10924 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11007 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10807 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87506 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6255 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5398 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5467 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5579 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5520 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5589 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5357 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50042 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 151735730 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 161976828 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 161045455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 159878242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 164283273 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 152707075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 166807572 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 156076804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1274510980 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 800100732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 10788728 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 10926635 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 10844691 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 11150485 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 11032564 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 10894657 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 11170471 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 10706784 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 887615747 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 800100732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 162524459 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 172903463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 171890146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 171028727 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 175315837 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 163601732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 177978043 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 166783588 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2162126727 # Total bandwidth to/from this memory (bytes/s) -system.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states +system.physmem.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0 261574 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 259726 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 254844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 256223 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 261709 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 259188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 257071 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 253171 # Number of bytes read from this memory +system.physmem.bytes_read::total 2063506 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 1454400 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5412 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5468 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5497 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5437 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5503 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5505 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5688 # Number of bytes written to this memory +system.physmem.bytes_written::total 1498291 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 13795 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 13774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 13680 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 13673 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 13678 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 13740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 13765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 13771 # Number of read requests responded to by this memory +system.physmem.num_reads::total 109876 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 22725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5412 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5468 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5497 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5437 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5503 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5505 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5688 # Number of write requests responded to by this memory +system.physmem.num_writes::total 66616 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 501427178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 497884633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 488526029 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 491169519 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 501685967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 496853308 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 492795102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 485318954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3955660690 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2788028195 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 10374593 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 10481943 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 10537535 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 10315168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 10422517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 10549037 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 10552871 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 10903675 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2872165533 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2788028195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 511801771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 508366577 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 499063565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 501484686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 512108485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 507402345 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 503347973 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 496222628 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6827826224 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.num_reads 99905 # number of read accesses completed -system.cpu0.num_writes 55400 # number of write accesses completed -system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.tags.replacements 22463 # number of replacements -system.cpu0.l1c.tags.tagsinuse 391.153981 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13877 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22862 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.606990 # Average number of references to valid blocks. +system.cpu0.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.num_reads 99316 # number of read accesses completed +system.cpu0.num_writes 55523 # number of write accesses completed +system.cpu0.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.tags.replacements 22284 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.956341 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13404 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.590667 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 391.153981 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.763973 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.763973 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 340651 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 340651 # Number of data accesses -system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu0.l1c.ReadReq_hits::cpu0 8894 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8894 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1261 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1261 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 10155 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 10155 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 10155 # number of overall hits -system.cpu0.l1c.overall_hits::total 10155 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36720 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36720 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 24041 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 24041 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60761 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60761 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60761 # number of overall misses -system.cpu0.l1c.overall_misses::total 60761 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 677337671 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 677337671 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 564207136 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 564207136 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1241544807 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1241544807 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1241544807 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1241544807 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45614 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45614 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 25302 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 25302 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70916 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70916 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70916 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70916 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805016 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.805016 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.950162 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.950162 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.856802 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.856802 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.856802 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.856802 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 18446.015005 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 18446.015005 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 23468.538580 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 23468.538580 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 20433.251708 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 20433.251708 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 20433.251708 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 20433.251708 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 800862 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.956341 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763587 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763587 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337730 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337730 # Number of data accesses +system.cpu0.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu0.l1c.ReadReq_hits::cpu0 8729 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8729 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1158 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1158 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9887 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9887 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9887 # number of overall hits +system.cpu0.l1c.overall_hits::total 9887 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36226 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36226 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 24124 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 24124 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60350 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60350 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60350 # number of overall misses +system.cpu0.l1c.overall_misses::total 60350 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 712731918 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 712731918 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 593276823 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 593276823 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1306008741 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1306008741 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1306008741 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1306008741 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44955 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44955 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25282 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25282 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70237 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70237 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70237 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70237 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805828 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805828 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954197 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954197 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859234 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859234 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859234 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859234 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 19674.596091 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 19674.596091 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 24592.804800 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 24592.804800 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 21640.575659 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 21640.575659 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 21640.575659 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 21640.575659 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 872655 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 65942 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66710 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 12.144946 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 13.081322 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.l1c.writebacks::writebacks 10055 # number of writebacks -system.cpu0.l1c.writebacks::total 10055 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36720 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36720 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24041 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 24041 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60761 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60761 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60761 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60761 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9743 # number of ReadReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5400 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5400 # number of WriteReq MSHR uncacheable -system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15143 # number of overall MSHR uncacheable misses -system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15143 # number of overall MSHR uncacheable misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 640619671 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 640619671 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 540167136 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 540167136 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1180786807 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1180786807 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1180786807 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1180786807 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 730760811 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 730760811 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 730760811 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 730760811 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805016 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805016 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.950162 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.950162 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.856802 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.856802 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.856802 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 17446.069472 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 17446.069472 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 22468.580176 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 22468.580176 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19433.301081 # average overall mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 75003.675562 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.675562 # average ReadReq mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 48257.334148 # average overall mshr uncacheable latency -system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 48257.334148 # average overall mshr uncacheable latency -system.cpu1.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.num_reads 99552 # number of read accesses completed -system.cpu1.num_writes 55243 # number of write accesses completed -system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.tags.replacements 22440 # number of replacements -system.cpu1.l1c.tags.tagsinuse 392.475962 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13641 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22851 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.596954 # Average number of references to valid blocks. +system.cpu0.l1c.writebacks::writebacks 9923 # number of writebacks +system.cpu0.l1c.writebacks::total 9923 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36226 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36226 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 24124 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 24124 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60350 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60350 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60350 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60350 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable::cpu0 9863 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.ReadReq_mshr_uncacheable::total 9863 # number of ReadReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::cpu0 5414 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.WriteReq_mshr_uncacheable::total 5414 # number of WriteReq MSHR uncacheable +system.cpu0.l1c.overall_mshr_uncacheable_misses::cpu0 15277 # number of overall MSHR uncacheable misses +system.cpu0.l1c.overall_mshr_uncacheable_misses::total 15277 # number of overall MSHR uncacheable misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 676507918 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 676507918 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 569152823 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 569152823 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1245660741 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1245660741 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1245660741 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1245660741 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 770027425 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 770027425 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 770027425 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 770027425 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805828 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805828 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954197 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954197 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859234 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859234 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859234 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 18674.651300 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 18674.651300 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 23592.804800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 23592.804800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 20640.608799 # average overall mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 78072.333469 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78072.333469 # average ReadReq mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 50404.361131 # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 50404.361131 # average overall mshr uncacheable latency +system.cpu1.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.num_reads 99894 # number of read accesses completed +system.cpu1.num_writes 55231 # number of write accesses completed +system.cpu1.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.tags.replacements 22436 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.315294 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13542 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22813 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.593609 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 392.475962 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.766555 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.766555 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 399 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339640 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339640 # Number of data accesses -system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu1.l1c.ReadReq_hits::cpu1 8906 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8906 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1136 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1136 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10042 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10042 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10042 # number of overall hits -system.cpu1.l1c.overall_hits::total 10042 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36595 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36595 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 24033 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 24033 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60628 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60628 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60628 # number of overall misses -system.cpu1.l1c.overall_misses::total 60628 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 675076804 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 675076804 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 561344066 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 561344066 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1236420870 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1236420870 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1236420870 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1236420870 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45501 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45501 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 25169 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 25169 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70670 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70670 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70670 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70670 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804268 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804268 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954865 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954865 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857903 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857903 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857903 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857903 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 18447.241536 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 18447.241536 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 23357.219906 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 23357.219906 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 20393.561886 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 20393.561886 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 20393.561886 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 20393.561886 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 800224 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.315294 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764288 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764288 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 377 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 366 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.736328 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338824 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338824 # Number of data accesses +system.cpu1.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu1.l1c.ReadReq_hits::cpu1 8855 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8855 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1149 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1149 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 10004 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 10004 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 10004 # number of overall hits +system.cpu1.l1c.overall_hits::total 10004 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36651 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36651 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23831 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23831 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60482 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60482 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60482 # number of overall misses +system.cpu1.l1c.overall_misses::total 60482 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 724296905 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 724296905 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 578481683 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 578481683 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1302778588 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1302778588 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1302778588 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1302778588 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45506 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45506 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24980 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24980 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70486 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70486 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70486 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70486 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805410 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805410 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954003 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954003 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858071 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858071 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858071 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858071 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 19761.995716 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 19761.995716 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 24274.335236 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 24274.335236 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 21539.938957 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 21539.938957 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 21539.938957 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 21539.938957 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 869423 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 65844 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66885 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.153332 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 12.998774 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.l1c.writebacks::writebacks 9864 # number of writebacks -system.cpu1.l1c.writebacks::total 9864 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36595 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36595 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24033 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 24033 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60628 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60628 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60628 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60628 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9811 # number of ReadReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5468 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5468 # number of WriteReq MSHR uncacheable -system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15279 # number of overall MSHR uncacheable misses -system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15279 # number of overall MSHR uncacheable misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 638481804 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 638481804 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 537312066 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 537312066 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1175793870 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1175793870 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1175793870 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1175793870 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 734637731 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 734637731 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 734637731 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 734637731 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804268 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804268 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954865 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954865 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857903 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857903 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857903 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 17447.241536 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 17447.241536 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 22357.261515 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 22357.261515 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19393.578380 # average overall mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 74878.985934 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74878.985934 # average ReadReq mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 48081.532234 # average overall mshr uncacheable latency -system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 48081.532234 # average overall mshr uncacheable latency -system.cpu2.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.num_reads 100001 # number of read accesses completed -system.cpu2.num_writes 55556 # number of write accesses completed -system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.tags.replacements 22129 # number of replacements -system.cpu2.l1c.tags.tagsinuse 390.469202 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13617 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22527 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.604475 # Average number of references to valid blocks. +system.cpu1.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu1.l1c.writebacks::total 9819 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36651 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36651 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23831 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23831 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60482 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60482 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60482 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60482 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable::cpu1 9872 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.ReadReq_mshr_uncacheable::total 9872 # number of ReadReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::cpu1 5469 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.WriteReq_mshr_uncacheable::total 5469 # number of WriteReq MSHR uncacheable +system.cpu1.l1c.overall_mshr_uncacheable_misses::cpu1 15341 # number of overall MSHR uncacheable misses +system.cpu1.l1c.overall_mshr_uncacheable_misses::total 15341 # number of overall MSHR uncacheable misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 687646905 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 687646905 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 554650683 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 554650683 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1242297588 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1242297588 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1242297588 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1242297588 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 771585814 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 771585814 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 771585814 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 771585814 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805410 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805410 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954003 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954003 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858071 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858071 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858071 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 18762.023001 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 18762.023001 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 23274.335236 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 23274.335236 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 20539.955491 # average overall mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 78159.016815 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78159.016815 # average ReadReq mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 50295.666123 # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 50295.666123 # average overall mshr uncacheable latency +system.cpu2.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.num_reads 99314 # number of read accesses completed +system.cpu2.num_writes 55477 # number of write accesses completed +system.cpu2.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.tags.replacements 22237 # number of replacements +system.cpu2.l1c.tags.tagsinuse 390.931192 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13493 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.596086 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 390.469202 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.762635 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.762635 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 390 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339163 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339163 # Number of data accesses -system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu2.l1c.ReadReq_hits::cpu2 8741 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8741 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1177 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1177 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9918 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9918 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9918 # number of overall hits -system.cpu2.l1c.overall_hits::total 9918 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36520 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36520 # number of ReadReq misses +system.cpu2.l1c.tags.occ_blocks::cpu2 390.931192 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.763537 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.763537 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337492 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337492 # Number of data accesses +system.cpu2.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu2.l1c.ReadReq_hits::cpu2 8705 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8705 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1188 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9893 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9893 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9893 # number of overall hits +system.cpu2.l1c.overall_hits::total 9893 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36190 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36190 # number of ReadReq misses system.cpu2.l1c.WriteReq_misses::cpu2 24129 # number of WriteReq misses system.cpu2.l1c.WriteReq_misses::total 24129 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60649 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60649 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60649 # number of overall misses -system.cpu2.l1c.overall_misses::total 60649 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 666978729 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 666978729 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 561823462 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 561823462 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1228802191 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1228802191 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1228802191 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1228802191 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45261 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45261 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25306 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25306 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70567 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70567 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70567 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70567 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806876 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806876 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953489 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.953489 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.859453 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.859453 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.859453 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.859453 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 18263.382503 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 18263.382503 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 23284.158564 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 23284.158564 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 20260.881317 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 20260.881317 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 20260.881317 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 20260.881317 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 804972 # number of cycles access was blocked +system.cpu2.l1c.demand_misses::cpu2 60319 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60319 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60319 # number of overall misses +system.cpu2.l1c.overall_misses::total 60319 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 713868287 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 713868287 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 591883556 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 591883556 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1305751843 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1305751843 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1305751843 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1305751843 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44895 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44895 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25317 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25317 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70212 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70212 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70212 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70212 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806103 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806103 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953075 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953075 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.859098 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.859098 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.859098 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.859098 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 19725.567477 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 19725.567477 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 24529.966265 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 24529.966265 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 21647.438502 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 21647.438502 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 21647.438502 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 21647.438502 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 871392 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66283 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66762 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 12.144471 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 13.052215 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.l1c.writebacks::writebacks 9821 # number of writebacks -system.cpu2.l1c.writebacks::total 9821 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36520 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36520 # number of ReadReq MSHR misses +system.cpu2.l1c.writebacks::writebacks 9753 # number of writebacks +system.cpu2.l1c.writebacks::total 9753 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36190 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24129 # number of WriteReq MSHR misses system.cpu2.l1c.WriteReq_mshr_misses::total 24129 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60649 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60649 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60649 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60649 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9985 # number of ReadReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5427 # number of WriteReq MSHR uncacheable -system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses -system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15412 # number of overall MSHR uncacheable misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 630459729 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 630459729 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 537696462 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 537696462 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1168156191 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1168156191 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1168156191 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1168156191 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 746431095 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 746431095 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 746431095 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 746431095 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806876 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806876 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953489 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953489 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.859453 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859453 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.859453 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 17263.409885 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 17263.409885 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 22284.241452 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 22284.241452 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19260.930782 # average overall mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 74755.242364 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74755.242364 # average ReadReq mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 48431.812549 # average overall mshr uncacheable latency -system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 48431.812549 # average overall mshr uncacheable latency -system.cpu3.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.num_reads 99831 # number of read accesses completed -system.cpu3.num_writes 55461 # number of write accesses completed -system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.tags.replacements 22291 # number of replacements -system.cpu3.l1c.tags.tagsinuse 391.006782 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13350 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22681 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.588598 # Average number of references to valid blocks. +system.cpu2.l1c.demand_mshr_misses::cpu2 60319 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60319 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60319 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60319 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable::cpu2 9852 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.ReadReq_mshr_uncacheable::total 9852 # number of ReadReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::cpu2 5498 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.WriteReq_mshr_uncacheable::total 5498 # number of WriteReq MSHR uncacheable +system.cpu2.l1c.overall_mshr_uncacheable_misses::cpu2 15350 # number of overall MSHR uncacheable misses +system.cpu2.l1c.overall_mshr_uncacheable_misses::total 15350 # number of overall MSHR uncacheable misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 677680287 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 677680287 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 567754556 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 567754556 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1245434843 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1245434843 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1245434843 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1245434843 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 769926007 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 769926007 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 769926007 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 769926007 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806103 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806103 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953075 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953075 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.859098 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.859098 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.859098 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 18725.622741 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 18725.622741 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 23529.966265 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 23529.966265 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 20647.471659 # average overall mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 78149.208993 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78149.208993 # average ReadReq mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 50158.046059 # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 50158.046059 # average overall mshr uncacheable latency +system.cpu3.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.num_reads 99963 # number of read accesses completed +system.cpu3.num_writes 54829 # number of write accesses completed +system.cpu3.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.tags.replacements 22502 # number of replacements +system.cpu3.l1c.tags.tagsinuse 392.266593 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13442 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22904 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.586884 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 391.006782 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.763685 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.763685 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 390 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.761719 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 338050 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 338050 # Number of data accesses -system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu3.l1c.ReadReq_hits::cpu3 8529 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8529 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1176 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1176 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9705 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9705 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9705 # number of overall hits -system.cpu3.l1c.overall_hits::total 9705 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36689 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36689 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23899 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23899 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60588 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60588 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60588 # number of overall misses -system.cpu3.l1c.overall_misses::total 60588 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 675943664 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 675943664 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 557387689 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 557387689 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1233331353 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1233331353 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1233331353 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1233331353 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45218 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45218 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25075 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25075 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70293 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70293 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.811380 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.811380 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953101 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953101 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861935 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861935 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861935 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861935 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 18423.605549 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 18423.605549 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 23322.636470 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 23322.636470 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 20356.033422 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 20356.033422 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 20356.033422 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 20356.033422 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 801051 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 392.266593 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.766146 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.766146 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 394 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338127 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338127 # Number of data accesses +system.cpu3.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu3.l1c.ReadReq_hits::cpu3 8758 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8758 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1160 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1160 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9918 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9918 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9918 # number of overall hits +system.cpu3.l1c.overall_hits::total 9918 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36654 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36654 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23751 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23751 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60405 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60405 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60405 # number of overall misses +system.cpu3.l1c.overall_misses::total 60405 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 726630781 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 726630781 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 580088175 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 580088175 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1306718956 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1306718956 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1306718956 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1306718956 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45412 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45412 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24911 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24911 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70323 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70323 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70323 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70323 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807143 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807143 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953434 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953434 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.858965 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.858965 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.858965 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.858965 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 19824.051427 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 19824.051427 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 24423.736895 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 24423.736895 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 21632.629021 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 21632.629021 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 21632.629021 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 21632.629021 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 870625 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 65873 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66788 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 12.160536 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 13.035650 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.l1c.writebacks::writebacks 9857 # number of writebacks -system.cpu3.l1c.writebacks::total 9857 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36689 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36689 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23899 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23899 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60588 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60588 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60588 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60588 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9849 # number of ReadReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5582 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5582 # number of WriteReq MSHR uncacheable -system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15431 # number of overall MSHR uncacheable misses -system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15431 # number of overall MSHR uncacheable misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 639257664 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 639257664 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 533488689 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 533488689 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1172746353 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1172746353 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1172746353 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1172746353 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 738856089 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 738856089 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 738856089 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 738856089 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.811380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.811380 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953101 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953101 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861935 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861935 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861935 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 17423.687318 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 17423.687318 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 22322.636470 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 22322.636470 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19356.082937 # average overall mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 75018.386537 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75018.386537 # average ReadReq mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 47881.283715 # average overall mshr uncacheable latency -system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 47881.283715 # average overall mshr uncacheable latency -system.cpu4.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.num_reads 99911 # number of read accesses completed -system.cpu4.num_writes 55300 # number of write accesses completed -system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.tags.replacements 22364 # number of replacements -system.cpu4.l1c.tags.tagsinuse 391.705900 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13535 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22773 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.594344 # Average number of references to valid blocks. +system.cpu3.l1c.writebacks::writebacks 9808 # number of writebacks +system.cpu3.l1c.writebacks::total 9808 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36654 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36654 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23751 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23751 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60405 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60405 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60405 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60405 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable::cpu3 9824 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.ReadReq_mshr_uncacheable::total 9824 # number of ReadReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::cpu3 5382 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.WriteReq_mshr_uncacheable::total 5382 # number of WriteReq MSHR uncacheable +system.cpu3.l1c.overall_mshr_uncacheable_misses::cpu3 15206 # number of overall MSHR uncacheable misses +system.cpu3.l1c.overall_mshr_uncacheable_misses::total 15206 # number of overall MSHR uncacheable misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 689977781 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 689977781 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 556338175 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 556338175 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1246315956 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1246315956 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1246315956 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1246315956 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 768661965 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 768661965 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 768661965 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 768661965 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807143 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807143 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953434 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953434 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.858965 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.858965 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.858965 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 18824.078709 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 18824.078709 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 23423.778999 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 23423.778999 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 20632.662131 # average overall mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 78243.278196 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78243.278196 # average ReadReq mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 50549.912206 # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 50549.912206 # average overall mshr uncacheable latency +system.cpu4.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.num_reads 98794 # number of read accesses completed +system.cpu4.num_writes 54937 # number of write accesses completed +system.cpu4.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.tags.replacements 22508 # number of replacements +system.cpu4.l1c.tags.tagsinuse 392.668091 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13409 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22922 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.584984 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 391.705900 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.765051 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.765051 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 409 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 401 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.798828 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 339861 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 339861 # Number of data accesses -system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu4.l1c.ReadReq_hits::cpu4 8886 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8886 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1168 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1168 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 10054 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 10054 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 10054 # number of overall hits -system.cpu4.l1c.overall_hits::total 10054 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36446 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36446 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 24191 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 24191 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60637 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60637 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60637 # number of overall misses -system.cpu4.l1c.overall_misses::total 60637 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 672672441 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 672672441 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 560233927 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 560233927 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1232906368 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1232906368 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1232906368 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1232906368 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45332 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45332 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 25359 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 25359 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70691 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70691 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70691 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70691 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.803980 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.803980 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953941 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953941 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857775 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857775 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857775 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857775 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 18456.687730 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 18456.687730 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 23158.775040 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 23158.775040 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 20332.575292 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 20332.575292 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 20332.575292 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 20332.575292 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 801696 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 392.668091 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.766930 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.766930 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 414 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 402 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.808594 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337369 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337369 # Number of data accesses +system.cpu4.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu4.l1c.ReadReq_hits::cpu4 8739 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8739 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1134 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9873 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9873 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9873 # number of overall hits +system.cpu4.l1c.overall_hits::total 9873 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36311 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36311 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23983 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23983 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60294 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60294 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60294 # number of overall misses +system.cpu4.l1c.overall_misses::total 60294 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 724331862 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 724331862 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 586488864 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 586488864 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1310820726 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1310820726 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1310820726 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1310820726 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45050 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45050 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25117 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25117 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70167 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70167 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70167 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70167 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.806016 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.806016 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954851 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.954851 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859293 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859293 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859293 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859293 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 19948.000936 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 19948.000936 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 24454.357837 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 24454.357837 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 21740.483730 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 21740.483730 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 21740.483730 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 21740.483730 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 869421 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 65950 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66532 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 12.156118 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 13.067712 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu4.l1c.writebacks::writebacks 9921 # number of writebacks -system.cpu4.l1c.writebacks::total 9921 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36446 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36446 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24191 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 24191 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60637 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60637 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60637 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60637 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9877 # number of ReadReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5522 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5522 # number of WriteReq MSHR uncacheable -system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15399 # number of overall MSHR uncacheable misses -system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15399 # number of overall MSHR uncacheable misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 636227441 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 636227441 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 536043927 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 536043927 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1172271368 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1172271368 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1172271368 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1172271368 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 739458183 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 739458183 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 739458183 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 739458183 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.803980 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.803980 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953941 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953941 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857775 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857775 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857775 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 17456.715168 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 17456.715168 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 22158.816378 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 22158.816378 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19332.608275 # average overall mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 74866.678445 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74866.678445 # average ReadReq mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 48019.883304 # average overall mshr uncacheable latency -system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 48019.883304 # average overall mshr uncacheable latency -system.cpu5.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.num_reads 99665 # number of read accesses completed -system.cpu5.num_writes 55439 # number of write accesses completed -system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.tags.replacements 22286 # number of replacements -system.cpu5.l1c.tags.tagsinuse 391.859990 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13458 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22703 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592785 # Average number of references to valid blocks. +system.cpu4.l1c.writebacks::writebacks 9883 # number of writebacks +system.cpu4.l1c.writebacks::total 9883 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36311 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36311 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23983 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23983 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60294 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60294 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60294 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60294 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable::cpu4 9741 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.ReadReq_mshr_uncacheable::total 9741 # number of ReadReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::cpu4 5439 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.WriteReq_mshr_uncacheable::total 5439 # number of WriteReq MSHR uncacheable +system.cpu4.l1c.overall_mshr_uncacheable_misses::cpu4 15180 # number of overall MSHR uncacheable misses +system.cpu4.l1c.overall_mshr_uncacheable_misses::total 15180 # number of overall MSHR uncacheable misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 688022862 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 688022862 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 562507864 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 562507864 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1250530726 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1250530726 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1250530726 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1250530726 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 763019844 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 763019844 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 763019844 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 763019844 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.806016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.806016 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954851 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954851 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859293 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859293 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859293 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 18948.056016 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 18948.056016 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 23454.441229 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 23454.441229 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 20740.550071 # average overall mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 78330.750847 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78330.750847 # average ReadReq mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 50264.811858 # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 50264.811858 # average overall mshr uncacheable latency +system.cpu5.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.num_reads 99762 # number of read accesses completed +system.cpu5.num_writes 55488 # number of write accesses completed +system.cpu5.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.tags.replacements 22372 # number of replacements +system.cpu5.l1c.tags.tagsinuse 391.676077 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13488 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22774 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592254 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 391.859990 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.765352 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.765352 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 417 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 407 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.814453 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 338594 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 338594 # Number of data accesses -system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu5.l1c.ReadReq_hits::cpu5 8649 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8649 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1196 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1196 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9845 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9845 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9845 # number of overall hits -system.cpu5.l1c.overall_hits::total 9845 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36574 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36574 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 24003 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 24003 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60577 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60577 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60577 # number of overall misses -system.cpu5.l1c.overall_misses::total 60577 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 671451246 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 671451246 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 559158053 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 559158053 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1230609299 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1230609299 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1230609299 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1230609299 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45223 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45223 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 25199 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 25199 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70422 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70422 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70422 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70422 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808748 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808748 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952538 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952538 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.860200 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.860200 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.860200 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.860200 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 18358.704161 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 18358.704161 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 23295.340291 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 23295.340291 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 20314.794377 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 20314.794377 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 20314.794377 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 20314.794377 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 802483 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 391.676077 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.764992 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.764992 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 387 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 338416 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 338416 # Number of data accesses +system.cpu5.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu5.l1c.ReadReq_hits::cpu5 8728 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8728 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1164 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1164 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9892 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9892 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9892 # number of overall hits +system.cpu5.l1c.overall_hits::total 9892 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36506 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36506 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23995 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23995 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60501 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60501 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60501 # number of overall misses +system.cpu5.l1c.overall_misses::total 60501 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 721706442 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 721706442 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 584665158 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 584665158 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1306371600 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1306371600 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1306371600 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1306371600 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45234 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45234 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25159 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25159 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70393 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70393 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70393 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70393 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807048 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807048 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953734 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953734 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859475 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859475 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859475 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859475 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 19769.529447 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 19769.529447 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 24366.124526 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 24366.124526 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 21592.562106 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 21592.562106 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 21592.562106 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 21592.562106 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 870792 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66128 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66903 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 12.135298 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 13.015739 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu5.l1c.writebacks::writebacks 9886 # number of writebacks -system.cpu5.l1c.writebacks::total 9886 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36574 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36574 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 24003 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 24003 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60577 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60577 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60577 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60577 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9910 # number of ReadReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5451 # number of WriteReq MSHR uncacheable -system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses -system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15361 # number of overall MSHR uncacheable misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 634877246 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 634877246 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 535156053 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 535156053 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1170033299 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1170033299 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1170033299 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1170033299 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 742019082 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 742019082 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 742019082 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 742019082 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808748 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808748 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952538 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952538 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.860200 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860200 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.860200 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 17358.704161 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 17358.704161 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 22295.381952 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 22295.381952 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19314.810885 # average overall mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 74875.790313 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74875.790313 # average ReadReq mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 48305.389102 # average overall mshr uncacheable latency -system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 48305.389102 # average overall mshr uncacheable latency -system.cpu6.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.num_reads 99712 # number of read accesses completed -system.cpu6.num_writes 55282 # number of write accesses completed -system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.tags.replacements 22239 # number of replacements -system.cpu6.l1c.tags.tagsinuse 392.046110 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13503 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22637 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.596501 # Average number of references to valid blocks. +system.cpu5.l1c.writebacks::writebacks 9839 # number of writebacks +system.cpu5.l1c.writebacks::total 9839 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36506 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36506 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23995 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60501 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60501 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60501 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60501 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable::cpu5 9845 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.ReadReq_mshr_uncacheable::total 9845 # number of ReadReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::cpu5 5507 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.WriteReq_mshr_uncacheable::total 5507 # number of WriteReq MSHR uncacheable +system.cpu5.l1c.overall_mshr_uncacheable_misses::cpu5 15352 # number of overall MSHR uncacheable misses +system.cpu5.l1c.overall_mshr_uncacheable_misses::total 15352 # number of overall MSHR uncacheable misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 685200442 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 685200442 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 560672158 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 560672158 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1245872600 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1245872600 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1245872600 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1245872600 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 769357074 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 769357074 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 769357074 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 769357074 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807048 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807048 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953734 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953734 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859475 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859475 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859475 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 18769.529447 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 18769.529447 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 23366.207877 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 23366.207877 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 20592.595164 # average overall mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 78146.985678 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78146.985678 # average ReadReq mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 50114.452449 # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 50114.452449 # average overall mshr uncacheable latency +system.cpu6.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 55102 # number of write accesses completed +system.cpu6.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.tags.replacements 22254 # number of replacements +system.cpu6.l1c.tags.tagsinuse 391.922561 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13477 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22655 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.594880 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 392.046110 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.765715 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.765715 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338073 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338073 # Number of data accesses -system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu6.l1c.ReadReq_hits::cpu6 8758 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8758 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1067 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1067 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9825 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9825 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9825 # number of overall hits -system.cpu6.l1c.overall_hits::total 9825 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36548 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36548 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23952 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23952 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60500 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60500 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60500 # number of overall misses -system.cpu6.l1c.overall_misses::total 60500 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 674135322 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 674135322 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 560982121 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 560982121 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1235117443 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1235117443 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1235117443 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1235117443 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45306 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45306 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25019 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25019 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70325 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70325 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70325 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70325 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806692 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.957352 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.957352 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.860292 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.860292 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.860292 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.860292 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 18445.204170 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 18445.204170 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 23421.097236 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 23421.097236 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 20415.164347 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 20415.164347 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 20415.164347 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 20415.164347 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 802988 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 391.922561 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.765474 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.765474 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337953 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337953 # Number of data accesses +system.cpu6.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu6.l1c.ReadReq_hits::cpu6 8677 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8677 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1226 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1226 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9903 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9903 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9903 # number of overall hits +system.cpu6.l1c.overall_hits::total 9903 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36565 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36565 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23825 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23825 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60390 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60390 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60390 # number of overall misses +system.cpu6.l1c.overall_misses::total 60390 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 723690383 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 723690383 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 577264297 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 577264297 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1300954680 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1300954680 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1300954680 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1300954680 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45242 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45242 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25051 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25051 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70293 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70293 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70293 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70293 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.808209 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.808209 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951060 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.951060 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859118 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859118 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859118 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859118 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 19791.887953 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 19791.887953 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 24229.351396 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 24229.351396 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 21542.551416 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 21542.551416 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 21542.551416 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 21542.551416 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 870051 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 65839 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66789 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 12.196236 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 13.026861 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu6.l1c.writebacks::writebacks 9826 # number of writebacks -system.cpu6.l1c.writebacks::total 9826 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36548 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36548 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23952 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23952 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60500 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60500 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60500 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60500 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9861 # number of ReadReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5592 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5592 # number of WriteReq MSHR uncacheable -system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15453 # number of overall MSHR uncacheable misses -system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15453 # number of overall MSHR uncacheable misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 637587322 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 637587322 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 537030121 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 537030121 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1174617443 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1174617443 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1174617443 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1174617443 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 737828201 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 737828201 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 737828201 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 737828201 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806692 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806692 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.957352 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.957352 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.860292 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.860292 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.860292 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 17445.204170 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 17445.204170 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 22421.097236 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 22421.097236 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19415.164347 # average overall mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 74822.857824 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 74822.857824 # average ReadReq mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 47746.599431 # average overall mshr uncacheable latency -system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 47746.599431 # average overall mshr uncacheable latency -system.cpu7.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.num_reads 99031 # number of read accesses completed -system.cpu7.num_writes 54931 # number of write accesses completed -system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.tags.replacements 22638 # number of replacements -system.cpu7.l1c.tags.tagsinuse 391.993848 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13556 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 23038 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.588419 # Average number of references to valid blocks. +system.cpu6.l1c.writebacks::writebacks 9787 # number of writebacks +system.cpu6.l1c.writebacks::total 9787 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36565 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36565 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23825 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23825 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60390 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60390 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60390 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60390 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable::cpu6 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.ReadReq_mshr_uncacheable::total 9904 # number of ReadReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::cpu6 5506 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.WriteReq_mshr_uncacheable::total 5506 # number of WriteReq MSHR uncacheable +system.cpu6.l1c.overall_mshr_uncacheable_misses::cpu6 15410 # number of overall MSHR uncacheable misses +system.cpu6.l1c.overall_mshr_uncacheable_misses::total 15410 # number of overall MSHR uncacheable misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 687127383 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 687127383 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 553439297 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 553439297 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1240566680 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1240566680 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1240566680 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1240566680 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 773835448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 773835448 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 773835448 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 773835448 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.808209 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.808209 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951060 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951060 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859118 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859118 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859118 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 18791.942650 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 18791.942650 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 23229.351396 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 23229.351396 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 20542.584534 # average overall mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 78133.627625 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78133.627625 # average ReadReq mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 50216.446982 # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 50216.446982 # average overall mshr uncacheable latency +system.cpu7.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.num_reads 99606 # number of read accesses completed +system.cpu7.num_writes 54773 # number of write accesses completed +system.cpu7.l1c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.tags.replacements 21949 # number of replacements +system.cpu7.l1c.tags.tagsinuse 391.189669 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13361 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22347 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.597888 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 391.993848 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.765613 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.765613 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 386 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.781250 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 339734 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 339734 # Number of data accesses -system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.cpu7.l1c.ReadReq_hits::cpu7 8818 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8818 # number of ReadReq hits +system.cpu7.l1c.tags.occ_blocks::cpu7 391.189669 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.764042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.764042 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 335877 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 335877 # Number of data accesses +system.cpu7.l1c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.cpu7.l1c.ReadReq_hits::cpu7 8692 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8692 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1148 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1148 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9966 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9966 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9966 # number of overall hits -system.cpu7.l1c.overall_hits::total 9966 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36554 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36554 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 24149 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 24149 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60703 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60703 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60703 # number of overall misses -system.cpu7.l1c.overall_misses::total 60703 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 675691654 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 675691654 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 565139421 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 565139421 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1240831075 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1240831075 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1240831075 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1240831075 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45372 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45372 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25297 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25297 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 70669 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 70669 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 70669 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 70669 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805651 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805651 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954619 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954619 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.858976 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.858976 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.858976 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.858976 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 18484.752804 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 18484.752804 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 23402.187296 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 23402.187296 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 20441.017330 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 20441.017330 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 20441.017330 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 20441.017330 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 799894 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 9840 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9840 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9840 # number of overall hits +system.cpu7.l1c.overall_hits::total 9840 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36424 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36424 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23598 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23598 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60022 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60022 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60022 # number of overall misses +system.cpu7.l1c.overall_misses::total 60022 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 721113865 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 721113865 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 575330708 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 575330708 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1296444573 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1296444573 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1296444573 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1296444573 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45116 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45116 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24746 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24746 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69862 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69862 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69862 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69862 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807341 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953609 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953609 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859151 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859151 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859151 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859151 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 19797.766994 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 19797.766994 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 24380.485973 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 24380.485973 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 21599.489737 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 21599.489737 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 21599.489737 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 21599.489737 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 871786 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 65859 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66469 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 12.145553 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 13.115678 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu7.l1c.writebacks::writebacks 9912 # number of writebacks -system.cpu7.l1c.writebacks::total 9912 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36554 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36554 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24149 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 24149 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60703 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60703 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60703 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60703 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9740 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9740 # number of ReadReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5359 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5359 # number of WriteReq MSHR uncacheable -system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15099 # number of overall MSHR uncacheable misses -system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15099 # number of overall MSHR uncacheable misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 639138654 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 639138654 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 540990421 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 540990421 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1180129075 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1180129075 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1180129075 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1180129075 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 730529776 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 730529776 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 730529776 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 730529776 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805651 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954619 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954619 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.858976 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858976 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.858976 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 17484.780161 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 17484.780161 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 22402.187296 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 22402.187296 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19441.033804 # average overall mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 75003.057084 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 75003.057084 # average ReadReq mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 48382.659514 # average overall mshr uncacheable latency -system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 48382.659514 # average overall mshr uncacheable latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 13688 # number of replacements -system.l2c.tags.tagsinuse 782.559938 # Cycle average of tags in use -system.l2c.tags.total_refs 164623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14478 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.370562 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 726.348525 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 6.677170 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.765222 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.924842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.010620 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 7.585654 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.814501 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 7.441816 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.991588 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.709325 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006521 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006763 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006846 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.007408 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.006655 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.007267 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006828 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764219 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 664 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 126 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 2107372 # Number of tag accesses -system.l2c.tags.data_accesses 2107372 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 77671 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 77671 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0 272 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 284 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 276 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 280 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 255 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 283 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 239 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 262 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2151 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1876 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1780 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1805 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1782 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1816 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1727 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1803 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1809 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 14398 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0 10873 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1 10958 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu2 10812 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu3 11007 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu4 10755 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu5 10989 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu6 11012 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu7 10808 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 87214 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0 12749 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12738 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12789 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12571 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12716 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12815 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12617 # number of demand (read+write) hits -system.l2c.demand_hits::total 101612 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12749 # number of overall hits -system.l2c.overall_hits::cpu1 12738 # number of overall hits -system.l2c.overall_hits::cpu2 12617 # number of overall hits -system.l2c.overall_hits::cpu3 12789 # number of overall hits -system.l2c.overall_hits::cpu4 12571 # number of overall hits -system.l2c.overall_hits::cpu5 12716 # number of overall hits -system.l2c.overall_hits::cpu6 12815 # number of overall hits -system.l2c.overall_hits::cpu7 12617 # number of overall hits -system.l2c.overall_hits::total 101612 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0 2119 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 2003 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 2061 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2101 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1934 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2026 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2139 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 2027 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 16410 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4596 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4672 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4641 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4561 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4696 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4677 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4637 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4651 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 37131 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0 698 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1 712 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu2 734 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu3 737 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu4 740 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu5 681 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu6 738 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu7 697 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 5737 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0 5294 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5384 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5298 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5436 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5358 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5375 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5348 # number of demand (read+write) misses -system.l2c.demand_misses::total 42868 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5294 # number of overall misses -system.l2c.overall_misses::cpu1 5384 # number of overall misses -system.l2c.overall_misses::cpu2 5375 # number of overall misses -system.l2c.overall_misses::cpu3 5298 # number of overall misses -system.l2c.overall_misses::cpu4 5436 # number of overall misses -system.l2c.overall_misses::cpu5 5358 # number of overall misses -system.l2c.overall_misses::cpu6 5375 # number of overall misses -system.l2c.overall_misses::cpu7 5348 # number of overall misses -system.l2c.overall_misses::total 42868 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0 34306000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 32515999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 33970000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 33665000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 30524499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 33417998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 35180998 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 31945000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 265525494 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 148628443 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 153234943 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 151708946 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 148204781 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 153854439 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 151693945 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 152734439 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 151392920 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1211452856 # number of ReadExReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu0 49327224 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu1 49579908 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu2 50488876 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu3 50929398 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu4 51564743 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu5 47695729 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu6 51087902 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::cpu7 48881401 # number of ReadSharedReq miss cycles -system.l2c.ReadSharedReq_miss_latency::total 399555181 # number of ReadSharedReq miss cycles -system.l2c.demand_miss_latency::cpu0 197955667 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 202814851 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 202197822 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 199134179 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 205419182 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 199389674 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 203822341 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 200274321 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1611008037 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 197955667 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 202814851 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 202197822 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 199134179 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 205419182 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 199389674 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 203822341 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 200274321 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1611008037 # number of overall miss cycles -system.l2c.WritebackDirty_accesses::writebacks 77671 # number of WritebackDirty accesses(hits+misses) -system.l2c.WritebackDirty_accesses::total 77671 # number of WritebackDirty accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2391 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2287 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2337 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2381 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2189 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2309 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2378 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18561 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6472 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6452 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6446 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6343 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6512 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6404 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6440 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6460 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 51529 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu0 11571 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu1 11670 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu2 11546 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu3 11744 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu4 11495 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu5 11670 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu6 11750 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::cpu7 11505 # number of ReadSharedReq accesses(hits+misses) -system.l2c.ReadSharedReq_accesses::total 92951 # number of ReadSharedReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18043 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18122 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17992 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18087 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18007 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 18074 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17965 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 144480 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18043 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18122 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17992 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18087 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18007 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 18074 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17965 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 144480 # number of overall (read+write) accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.886240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.875820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.881900 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.882402 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.883508 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.877436 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.899495 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.885540 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.884112 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.710136 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.724117 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.719981 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.719060 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.721130 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.730325 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.720031 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.719969 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.720585 # miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu0 0.060323 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu1 0.061011 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu2 0.063572 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu3 0.062755 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu4 0.064376 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu5 0.058355 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu6 0.062809 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::cpu7 0.060582 # miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_miss_rate::total 0.061721 # miss rate for ReadSharedReq accesses -system.l2c.demand_miss_rate::cpu0 0.293410 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.297097 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.298744 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.292918 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.301883 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.296448 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.295492 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.297690 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.296705 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.293410 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.297097 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.298744 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.292918 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.301883 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.296448 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.295492 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.297690 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.296705 # miss rate for overall accesses -system.l2c.UpgradeReq_avg_miss_latency::cpu0 16189.712128 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 16233.649026 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 16482.290150 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 16023.322228 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 15783.091520 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 16494.569595 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 16447.404395 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 15759.743463 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 16180.712614 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 32338.651654 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 32798.575128 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 32688.848524 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 32493.922605 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 32762.870315 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 32434.027154 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 32938.201208 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 32550.617072 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 32626.453799 # average ReadExReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu0 70669.375358 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu1 69634.702247 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68785.934605 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu3 69103.660787 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu4 69682.085135 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu5 70037.781204 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu6 69224.799458 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::cpu7 70131.134864 # average ReadSharedReq miss latency -system.l2c.ReadSharedReq_avg_miss_latency::total 69645.316542 # average ReadSharedReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 37392.456932 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 37669.920319 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 37618.199442 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 37586.670253 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 37788.664827 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 37213.451661 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 37920.435535 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 37448.451945 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 37580.667094 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 37392.456932 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 37669.920319 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 37618.199442 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 37586.670253 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 37788.664827 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 37213.451661 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 37920.435535 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 37448.451945 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 37580.667094 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 19223 # number of cycles access was blocked +system.cpu7.l1c.writebacks::writebacks 9508 # number of writebacks +system.cpu7.l1c.writebacks::total 9508 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36424 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36424 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23598 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23598 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60022 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60022 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60022 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60022 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable::cpu7 9972 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.ReadReq_mshr_uncacheable::total 9972 # number of ReadReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::cpu7 5689 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.WriteReq_mshr_uncacheable::total 5689 # number of WriteReq MSHR uncacheable +system.cpu7.l1c.overall_mshr_uncacheable_misses::cpu7 15661 # number of overall MSHR uncacheable misses +system.cpu7.l1c.overall_mshr_uncacheable_misses::total 15661 # number of overall MSHR uncacheable misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 684690865 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 684690865 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 551733708 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 551733708 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1236424573 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1236424573 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1236424573 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1236424573 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 778989868 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 778989868 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 778989868 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 778989868 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807341 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953609 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953609 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859151 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859151 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859151 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 18797.794449 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 18797.794449 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 23380.528350 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 23380.528350 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 20599.523058 # average overall mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 78117.716406 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78117.716406 # average ReadReq mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 49740.748867 # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 49740.748867 # average overall mshr uncacheable latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 91944 # number of replacements +system.l2c.tags.tagsinuse 1018.135199 # Cycle average of tags in use +system.l2c.tags.total_refs 150035 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 92968 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.613835 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 8704000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 700.601873 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 40.249147 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 40.174988 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 39.327766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 40.057426 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 39.781379 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 39.374996 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 39.797467 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 38.770159 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.684182 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.039306 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.039233 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.038406 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.039119 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.038849 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.038452 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.038865 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.037861 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994273 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 947 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 2139200 # Number of tag accesses +system.l2c.tags.data_accesses 2139200 # Number of data accesses +system.l2c.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.l2c.WritebackDirty_hits::writebacks 77024 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 77024 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0 414 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 433 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 398 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 417 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 426 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 450 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 421 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 435 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3394 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1934 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1949 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1865 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1828 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1873 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1869 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1854 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15034 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0 9356 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1 9333 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu2 9371 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu3 9291 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu4 9201 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu5 9292 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu6 9177 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu7 9226 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 74247 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0 11218 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 11267 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 11320 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 11156 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 11029 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 11165 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 11046 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 11080 # number of demand (read+write) hits +system.l2c.demand_hits::total 89281 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 11218 # number of overall hits +system.l2c.overall_hits::cpu1 11267 # number of overall hits +system.l2c.overall_hits::cpu2 11320 # number of overall hits +system.l2c.overall_hits::cpu3 11156 # number of overall hits +system.l2c.overall_hits::cpu4 11029 # number of overall hits +system.l2c.overall_hits::cpu5 11165 # number of overall hits +system.l2c.overall_hits::cpu6 11046 # number of overall hits +system.l2c.overall_hits::cpu7 11080 # number of overall hits +system.l2c.overall_hits::total 89281 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0 1872 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1844 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1947 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1836 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1852 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1900 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1862 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1851 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14964 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4900 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4669 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4784 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4718 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4791 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4701 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4630 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4626 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 37819 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0 2463 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1 2553 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu2 2469 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu3 2512 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu4 2543 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu5 2510 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu6 2544 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu7 2476 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 20070 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0 7363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 7222 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 7253 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 7230 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 7334 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 7211 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 7174 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 7102 # number of demand (read+write) misses +system.l2c.demand_misses::total 57889 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 7363 # number of overall misses +system.l2c.overall_misses::cpu1 7222 # number of overall misses +system.l2c.overall_misses::cpu2 7253 # number of overall misses +system.l2c.overall_misses::cpu3 7230 # number of overall misses +system.l2c.overall_misses::cpu4 7334 # number of overall misses +system.l2c.overall_misses::cpu5 7211 # number of overall misses +system.l2c.overall_misses::cpu6 7174 # number of overall misses +system.l2c.overall_misses::cpu7 7102 # number of overall misses +system.l2c.overall_misses::total 57889 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0 31234104 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 31358138 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 32572788 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 30120451 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 30799263 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 31792446 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 30352791 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 30383968 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 248613949 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 215803873 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 203805632 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 208081416 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 204329473 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 209030536 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 205216215 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 201405883 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 201887028 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1649560056 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0 169116609 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1 174843463 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu2 170153096 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu3 173149203 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu4 175448063 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu5 172961782 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu6 175284714 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu7 170387602 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 1381344532 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0 384920482 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 378649095 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 378234512 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 377478676 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 384478599 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 378177997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 376690597 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 372274630 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 3030904588 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 384920482 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 378649095 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 378234512 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 377478676 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 384478599 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 378177997 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 376690597 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 372274630 # number of overall miss cycles +system.l2c.overall_miss_latency::total 3030904588 # number of overall miss cycles +system.l2c.WritebackDirty_accesses::writebacks 77024 # number of WritebackDirty accesses(hits+misses) +system.l2c.WritebackDirty_accesses::total 77024 # number of WritebackDirty accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2277 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2253 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2278 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2350 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2283 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18358 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6762 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6603 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6733 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6583 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6619 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6574 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6499 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6480 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 52853 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0 11819 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1 11886 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu2 11840 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu3 11803 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu4 11744 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu5 11802 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu6 11721 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu7 11702 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 94317 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 18581 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18489 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18573 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18386 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18363 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18376 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18220 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18182 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 147170 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 18581 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18489 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18573 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18386 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18363 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18376 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18220 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18182 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 147170 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.818898 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.809838 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.830277 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.814913 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.812994 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.808511 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.815594 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.809711 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.815121 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.724638 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.707103 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.710530 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.716695 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.723825 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.715090 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.712417 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.713889 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.715551 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0 0.208393 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1 0.214791 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu2 0.208530 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu3 0.212827 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu4 0.216536 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu5 0.212676 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu6 0.217046 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu7 0.211588 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.212793 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0 0.396265 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.390611 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.390513 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.393234 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.399390 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.392414 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.393743 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.390606 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.393348 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.396265 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.390611 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.390513 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.393234 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.399390 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.392414 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.393743 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.390606 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.393348 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0 16684.884615 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 17005.497831 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 16729.731895 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 16405.474401 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 16630.271598 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 16732.866316 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 16301.176692 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 16414.893571 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 16614.137196 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 44041.606735 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 43650.810024 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 43495.279264 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 43308.493641 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 43629.834273 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 43653.736439 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 43500.190713 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 43641.813230 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 43617.230916 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0 68662.853837 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1 68485.492754 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu2 68915.794249 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu3 68928.822850 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu4 68992.553284 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu5 68909.076494 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu6 68901.224057 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu7 68815.671244 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 68826.334429 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 52277.669700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 52429.949460 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 52148.698745 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 52210.052006 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 52424.134033 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 52444.598114 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 52507.749791 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 52418.280766 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52357.176458 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 52277.669700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 52429.949460 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 52148.698745 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 52210.052006 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 52424.134033 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 52444.598114 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 52507.749791 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 52418.280766 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52357.176458 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 46726 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2973 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 7668 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.465859 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 6.093636 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.writebacks::writebacks 6255 # number of writebacks -system.l2c.writebacks::total 6255 # number of writebacks -system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 22726 # number of writebacks +system.l2c.writebacks::total 22726 # number of writebacks +system.l2c.UpgradeReq_mshr_hits::cpu0 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 3 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 5 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 5 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 40 # number of ReadExReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu0 11 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu1 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu2 14 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu3 13 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu4 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu5 9 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu6 8 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::cpu7 10 # number of ReadSharedReq MSHR hits -system.l2c.ReadSharedReq_mshr_hits::total 83 # number of ReadSharedReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 23 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 123 # number of overall MSHR hits -system.l2c.CleanEvict_mshr_misses::writebacks 1242 # number of CleanEvict MSHR misses -system.l2c.CleanEvict_mshr_misses::total 1242 # number of CleanEvict MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 2119 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 2003 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 2060 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2101 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1934 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2026 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2138 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 2027 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 16408 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4594 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4668 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4632 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4558 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4689 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4672 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4632 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4646 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 37091 # number of ReadExReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu0 687 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu1 702 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu2 720 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu3 724 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu4 732 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu5 672 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu6 730 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::cpu7 687 # number of ReadSharedReq MSHR misses -system.l2c.ReadSharedReq_mshr_misses::total 5654 # number of ReadSharedReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5281 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5370 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5352 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5282 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5421 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5344 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5362 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5333 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 42745 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5281 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5370 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5352 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5282 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5421 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5344 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5362 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5333 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 42745 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0 9743 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1 9811 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu2 9985 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu3 9849 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu4 9877 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu5 9910 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu6 9861 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu7 9739 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 78775 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0 5399 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1 5467 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu2 5427 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu3 5579 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu4 5520 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu5 5451 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu6 5590 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu7 5357 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 43790 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0 15142 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1 15278 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu2 15412 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu3 15428 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu4 15397 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu5 15361 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu6 15451 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu7 15096 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 122565 # number of overall MSHR uncacheable misses -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 40841935 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 38564215 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 39647592 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 40417370 # 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number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 309516427 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 304572317 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 303948293 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 303334260 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 308814583 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 303747957 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 302674437 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 298948081 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 2435556355 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 309516427 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 304572317 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 303948293 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 303334260 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 308814583 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 303747957 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 302674437 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 298948081 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 2435556355 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 558924481 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 559228006 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 558782791 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 556927201 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 552042138 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 557542912 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 561245949 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 564245669 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 4468939147 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 558924481 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 559228006 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 558782791 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 556927201 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 552042138 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 557542912 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 561245949 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 564245669 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4468939147 # number of overall MSHR uncacheable cycles system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.875820 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.881472 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.882402 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.883508 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.877436 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.899075 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.885540 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.884004 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.709827 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.723497 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.718585 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.718587 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.720055 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.729544 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.719255 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.719195 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.719808 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.059373 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.060154 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.062359 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.061649 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.063680 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.057584 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.062128 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.059713 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.060828 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.295854 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.292690 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.296325 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.297466 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.292033 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.301050 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.295673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.294777 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.296855 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.295854 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 19274.155262 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 19253.227659 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 19246.403883 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 19237.206092 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 19206.719235 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 19200.354393 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 19283.960243 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 19244.956586 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 19243.994332 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 22334.515237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 22783.451371 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 22680.037781 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 22477.211496 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 22744.141395 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 22433.699058 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 22933.635363 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 22549.261946 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 22617.696207 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 61112.551674 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 59870.158120 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59292.448611 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59588.425414 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59871.435792 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 60236.848214 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59459.368493 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 60442.264920 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59971.698797 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 27379.111153 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 27631.657728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 27605.474215 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 27564.019311 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 27757.456189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 27187.388473 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 27906.366654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 27430.659479 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 27558.613990 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 51975.587807 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 51914.458465 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 51919.662694 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 51952.415169 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 51935.072593 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 51933.073461 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 51940.917554 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 51928.287298 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 51937.372529 # average ReadReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 33443.280412 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 33337.658856 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 33637.284713 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 33165.629829 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 33315.757096 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 33504.118091 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 33149.271115 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 33500.900238 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 33381.197903 # average overall mshr uncacheable latency -system.membus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 78773 # Transaction distribution -system.membus.trans_dist::ReadResp 84410 # Transaction distribution -system.membus.trans_dist::WriteReq 43787 # Transaction distribution -system.membus.trans_dist::WriteResp 43783 # Transaction distribution -system.membus.trans_dist::WritebackDirty 6255 # Transaction distribution -system.membus.trans_dist::CleanEvict 1278 # Transaction distribution -system.membus.trans_dist::UpgradeReq 61348 # Transaction distribution -system.membus.trans_dist::ReadExReq 49073 # Transaction distribution -system.membus.trans_dist::ReadExResp 3087 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 5646 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 377440 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 377440 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1081783 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1081783 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 56900 # Total snoops (count) +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.817585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.808081 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.829424 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.813582 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.810799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.807660 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.815155 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.807524 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.813760 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.721680 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.704528 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.707857 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.713504 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.721106 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.711287 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.708417 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.710648 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.712410 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0 0.205601 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1 0.212267 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2 0.205997 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3 0.210540 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu4 0.213641 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu5 0.209541 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu6 0.214060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu7 0.208084 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.209962 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.390406 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.393413 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.388069 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.387929 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.390623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.396558 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.389040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.390395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.387196 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.390406 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 22899.217228 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 22771.945109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 22900.155784 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 22541.062193 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 22900.107201 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 22754.594837 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 22859.188071 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 22453.338570 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22761.370708 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 34053.276230 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 33649.557825 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 33507.751783 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 33343.235469 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 33599.888121 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 33677.057528 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 33509.805604 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 33616.542454 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 33621.713091 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0 58986.188889 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1 58674.028537 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2 59143.234112 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3 59042.689336 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu4 59163.936628 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu5 59148.417307 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu6 59145.194101 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu7 59196.674743 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 59061.656921 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42341.508482 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42449.103415 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42185.745038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42235.346700 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42407.935045 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42488.174150 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42552.289751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42464.216051 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42389.939345 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 56668.810808 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 56647.893639 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 56717.701076 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 56696.243612 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 56672.019095 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 56637.841528 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 56668.613590 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 56588.674055 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 56662.091378 # average ReadReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 36588.405407 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 36453.165113 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 36402.787687 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 36630.307880 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 36368.808090 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 36326.746938 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 36423.255825 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 36031.013346 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 36401.794839 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 165129 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 149421 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 78866 # Transaction distribution +system.membus.trans_dist::ReadResp 98603 # Transaction distribution +system.membus.trans_dist::WriteReq 43891 # Transaction distribution +system.membus.trans_dist::WriteResp 43890 # Transaction distribution +system.membus.trans_dist::WritebackDirty 22725 # Transaction distribution +system.membus.trans_dist::CleanEvict 5096 # Transaction distribution +system.membus.trans_dist::UpgradeReq 51962 # Transaction distribution +system.membus.trans_dist::ReadExReq 56321 # Transaction distribution +system.membus.trans_dist::ReadExResp 11265 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 19745 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 432364 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 432364 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 3561537 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 3561537 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 55548 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 253448 # Request fanout histogram +system.membus.snoop_fanout::samples 277065 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 253448 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 277065 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 253448 # Request fanout histogram -system.membus.reqLayer0.occupancy 289313112 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 57.8 # Layer utilization (%) -system.membus.respLayer0.occupancy 244976000 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 49.0 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 662658 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 284136 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 332740 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 12293 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 5765 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 6528 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 500337000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 78775 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371396 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43790 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43780 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 83926 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105295 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29475 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29475 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 162920 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 162916 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 292639 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133502 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 133647 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133520 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133779 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133528 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133790 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133396 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1068709 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1800550 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1795691 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1783667 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1792707 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1790564 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791999 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1796631 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788086 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14339895 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 335681 # Total snoops (count) -system.toL2Bus.snoopTraffic 20309376 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 623777 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.148975 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.984758 # Request fanout histogram +system.membus.snoop_fanout::total 277065 # Request fanout histogram +system.membus.reqLayer0.occupancy 406206026 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 77.9 # Layer utilization (%) +system.membus.respLayer0.occupancy 356644000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 68.4 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 666785 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 283960 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 335937 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 86136 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 43107 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 43029 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 521659000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 78870 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 370375 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43897 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43890 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 99750 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 167866 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 28850 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 28850 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162383 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162380 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 291522 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 133688 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 134001 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 133796 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 133576 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 133426 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 133904 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 133634 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 133439 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1069464 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1829226 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1815722 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1817716 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1809443 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1812235 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1808884 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1798064 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1779371 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14470661 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 409171 # Total snoops (count) +system.toL2Bus.snoopTraffic 21085504 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 706797 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.196447 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.990756 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 172972 27.73% 27.73% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 258444 41.43% 69.16% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 133198 21.35% 90.52% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 46670 7.48% 98.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 10752 1.72% 99.72% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 1603 0.26% 99.98% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 135 0.02% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 3 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 181481 25.68% 25.68% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 294628 41.68% 67.36% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 158602 22.44% 89.80% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 56776 8.03% 97.83% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 13243 1.87% 99.71% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 1898 0.27% 99.98% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 160 0.02% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 9 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 623777 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 493769156 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 102470874 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 102502346 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 102645272 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 102492443 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 102725884 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 102549521 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 102424000 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 20.5 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 102560017 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 20.5 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 706797 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 500161714 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 95.9 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102256739 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 102545160 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 19.7 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 102125332 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 102285646 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 102013056 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 102427641 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 102433420 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 19.6 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101994041 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 19.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- |