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authorAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:41 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-07-09 12:35:41 -0400
commitfda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch)
tree20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/se/50.memtest
parentb265d9925c123f0df50db98cf56dab6a3596b54b (diff)
downloadgem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the introduction of the state variable, the division into a request and response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/se/50.memtest')
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr146
-rwxr-xr-xtests/quick/se/50.memtest/ref/alpha/linux/memtest/simout6
-rw-r--r--tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt2859
3 files changed, 1507 insertions, 1504 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
index a874a3f37..b8bd8a115 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu4: completed 10000 read, 5380 write accesses @22344646
-system.cpu6: completed 10000 read, 5214 write accesses @22747629
-system.cpu7: completed 10000 read, 5415 write accesses @22929508
-system.cpu2: completed 10000 read, 5407 write accesses @23019836
-system.cpu5: completed 10000 read, 5331 write accesses @23061044
-system.cpu0: completed 10000 read, 5432 write accesses @23140146
-system.cpu3: completed 10000 read, 5376 write accesses @23188049
-system.cpu1: completed 10000 read, 5387 write accesses @23350185
-system.cpu4: completed 20000 read, 10814 write accesses @44761691
-system.cpu7: completed 20000 read, 10827 write accesses @45213444
-system.cpu1: completed 20000 read, 10711 write accesses @45275122
-system.cpu6: completed 20000 read, 10548 write accesses @45324102
-system.cpu3: completed 20000 read, 10701 write accesses @45506880
-system.cpu2: completed 20000 read, 10922 write accesses @45734056
-system.cpu5: completed 20000 read, 10686 write accesses @45942373
-system.cpu0: completed 20000 read, 10937 write accesses @46044746
-system.cpu7: completed 30000 read, 16167 write accesses @66979485
-system.cpu4: completed 30000 read, 16361 write accesses @67223162
-system.cpu6: completed 30000 read, 15931 write accesses @67873351
-system.cpu3: completed 30000 read, 16353 write accesses @68348826
-system.cpu5: completed 30000 read, 16080 write accesses @68377482
-system.cpu1: completed 30000 read, 16196 write accesses @68419268
-system.cpu0: completed 30000 read, 16219 write accesses @68619325
-system.cpu2: completed 30000 read, 16526 write accesses @68648506
-system.cpu4: completed 40000 read, 21581 write accesses @88592659
-system.cpu7: completed 40000 read, 21651 write accesses @88863809
-system.cpu6: completed 40000 read, 21187 write accesses @89230569
-system.cpu1: completed 40000 read, 21556 write accesses @89813083
-system.cpu2: completed 40000 read, 21771 write accesses @90046604
-system.cpu3: completed 40000 read, 21725 write accesses @90210729
-system.cpu5: completed 40000 read, 21435 write accesses @90283858
-system.cpu0: completed 40000 read, 21836 write accesses @90947960
-system.cpu4: completed 50000 read, 27034 write accesses @111338978
-system.cpu6: completed 50000 read, 26346 write accesses @111492478
-system.cpu1: completed 50000 read, 26820 write accesses @112199634
-system.cpu7: completed 50000 read, 27390 write accesses @112358430
-system.cpu5: completed 50000 read, 26711 write accesses @112747804
-system.cpu3: completed 50000 read, 27030 write accesses @113062631
-system.cpu2: completed 50000 read, 27246 write accesses @113387493
-system.cpu0: completed 50000 read, 27088 write accesses @113621350
-system.cpu4: completed 60000 read, 32322 write accesses @134108306
-system.cpu6: completed 60000 read, 31811 write accesses @134700049
-system.cpu2: completed 60000 read, 32452 write accesses @135470855
-system.cpu1: completed 60000 read, 32239 write accesses @135474213
-system.cpu7: completed 60000 read, 32783 write accesses @135487924
-system.cpu5: completed 60000 read, 32297 write accesses @135551091
-system.cpu3: completed 60000 read, 32475 write accesses @135953364
-system.cpu0: completed 60000 read, 32594 write accesses @136506452
-system.cpu4: completed 70000 read, 37624 write accesses @156509147
-system.cpu6: completed 70000 read, 37191 write accesses @157507230
-system.cpu2: completed 70000 read, 37791 write accesses @158024045
-system.cpu7: completed 70000 read, 38252 write accesses @158415918
-system.cpu1: completed 70000 read, 37644 write accesses @158423190
-system.cpu5: completed 70000 read, 37691 write accesses @158678523
-system.cpu3: completed 70000 read, 38021 write accesses @158813067
-system.cpu0: completed 70000 read, 37965 write accesses @159679646
-system.cpu4: completed 80000 read, 42948 write accesses @178855235
-system.cpu6: completed 80000 read, 42510 write accesses @180069540
-system.cpu2: completed 80000 read, 43201 write accesses @180702038
-system.cpu1: completed 80000 read, 43267 write accesses @181114200
-system.cpu7: completed 80000 read, 43705 write accesses @181378010
-system.cpu3: completed 80000 read, 43552 write accesses @181443642
-system.cpu5: completed 80000 read, 43080 write accesses @181574154
-system.cpu0: completed 80000 read, 43418 write accesses @182451715
-system.cpu4: completed 90000 read, 48279 write accesses @201435873
-system.cpu6: completed 90000 read, 47918 write accesses @202390012
-system.cpu2: completed 90000 read, 48513 write accesses @203087400
-system.cpu1: completed 90000 read, 48611 write accesses @203141768
-system.cpu7: completed 90000 read, 48973 write accesses @204050544
-system.cpu5: completed 90000 read, 48423 write accesses @204299514
-system.cpu0: completed 90000 read, 48663 write accesses @204396348
-system.cpu3: completed 90000 read, 48999 write accesses @204475748
-system.cpu4: completed 100000 read, 53697 write accesses @224044586
+system.cpu3: completed 10000 read, 5269 write accesses @22241329
+system.cpu6: completed 10000 read, 5339 write accesses @22510874
+system.cpu4: completed 10000 read, 5452 write accesses @22618520
+system.cpu2: completed 10000 read, 5274 write accesses @22652245
+system.cpu5: completed 10000 read, 5225 write accesses @22698654
+system.cpu0: completed 10000 read, 5313 write accesses @22972460
+system.cpu1: completed 10000 read, 5425 write accesses @23112052
+system.cpu7: completed 10000 read, 5664 write accesses @23303588
+system.cpu3: completed 20000 read, 10591 write accesses @44494817
+system.cpu6: completed 20000 read, 10810 write accesses @44620430
+system.cpu2: completed 20000 read, 10802 write accesses @45009184
+system.cpu0: completed 20000 read, 10643 write accesses @45009224
+system.cpu5: completed 20000 read, 10647 write accesses @45039314
+system.cpu1: completed 20000 read, 10757 write accesses @45068735
+system.cpu4: completed 20000 read, 10808 write accesses @45199458
+system.cpu7: completed 20000 read, 11080 write accesses @45757070
+system.cpu2: completed 30000 read, 16115 write accesses @67069204
+system.cpu3: completed 30000 read, 16110 write accesses @67286000
+system.cpu5: completed 30000 read, 16163 write accesses @67388496
+system.cpu4: completed 30000 read, 16262 write accesses @67495238
+system.cpu6: completed 30000 read, 16234 write accesses @67566368
+system.cpu0: completed 30000 read, 16102 write accesses @67625583
+system.cpu1: completed 30000 read, 16288 write accesses @67665372
+system.cpu7: completed 30000 read, 16608 write accesses @68406261
+system.cpu4: completed 40000 read, 21521 write accesses @88522458
+system.cpu2: completed 40000 read, 21461 write accesses @88760475
+system.cpu5: completed 40000 read, 21540 write accesses @88851958
+system.cpu3: completed 40000 read, 21536 write accesses @88901742
+system.cpu6: completed 40000 read, 21498 write accesses @88910943
+system.cpu1: completed 40000 read, 21730 write accesses @89071047
+system.cpu0: completed 40000 read, 21414 write accesses @89232143
+system.cpu7: completed 40000 read, 22063 write accesses @90453997
+system.cpu4: completed 50000 read, 26910 write accesses @111349230
+system.cpu1: completed 50000 read, 26996 write accesses @111399385
+system.cpu2: completed 50000 read, 26807 write accesses @111571994
+system.cpu6: completed 50000 read, 26876 write accesses @111619105
+system.cpu3: completed 50000 read, 27009 write accesses @111789131
+system.cpu0: completed 50000 read, 26777 write accesses @111829265
+system.cpu5: completed 50000 read, 26952 write accesses @111861140
+system.cpu7: completed 50000 read, 27397 write accesses @112901639
+system.cpu1: completed 60000 read, 32331 write accesses @134016224
+system.cpu2: completed 60000 read, 32246 write accesses @134236668
+system.cpu4: completed 60000 read, 32290 write accesses @134236929
+system.cpu5: completed 60000 read, 32370 write accesses @134256674
+system.cpu6: completed 60000 read, 32444 write accesses @134707450
+system.cpu0: completed 60000 read, 32183 write accesses @134767456
+system.cpu3: completed 60000 read, 32423 write accesses @134996472
+system.cpu7: completed 60000 read, 32735 write accesses @135678114
+system.cpu2: completed 70000 read, 37600 write accesses @156516476
+system.cpu1: completed 70000 read, 37730 write accesses @156721328
+system.cpu5: completed 70000 read, 37748 write accesses @156805205
+system.cpu6: completed 70000 read, 37760 write accesses @156910635
+system.cpu4: completed 70000 read, 37725 write accesses @156961462
+system.cpu0: completed 70000 read, 37635 write accesses @158012668
+system.cpu3: completed 70000 read, 37942 write accesses @158279756
+system.cpu7: completed 70000 read, 38031 write accesses @158283192
+system.cpu5: completed 80000 read, 43255 write accesses @179067469
+system.cpu2: completed 80000 read, 43125 write accesses @179091672
+system.cpu1: completed 80000 read, 43134 write accesses @179182044
+system.cpu6: completed 80000 read, 43119 write accesses @179350821
+system.cpu4: completed 80000 read, 43054 write accesses @179621308
+system.cpu7: completed 80000 read, 43393 write accesses @180749386
+system.cpu0: completed 80000 read, 43229 write accesses @180793374
+system.cpu3: completed 80000 read, 43339 write accesses @180920432
+system.cpu6: completed 90000 read, 48363 write accesses @201441693
+system.cpu2: completed 90000 read, 48516 write accesses @201463344
+system.cpu5: completed 90000 read, 48731 write accesses @201471872
+system.cpu1: completed 90000 read, 48576 write accesses @201752753
+system.cpu4: completed 90000 read, 48432 write accesses @201853284
+system.cpu7: completed 90000 read, 48666 write accesses @202980078
+system.cpu3: completed 90000 read, 48647 write accesses @203163876
+system.cpu0: completed 90000 read, 48482 write accesses @203365064
+system.cpu6: completed 100000 read, 53510 write accesses @223713460
hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
index 2045d5848..ed860ddcf 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
@@ -1,10 +1,10 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jun 28 2012 22:05:18
-gem5 started Jun 28 2012 22:09:54
+gem5 compiled Jul 2 2012 08:30:56
+gem5 started Jul 2 2012 09:08:41
gem5 executing on zizzer
command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 224044586 because maximum number of loads reached
+Exiting @ tick 223713460 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
index 9c1b7f7cc..1fe48d0c8 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
@@ -1,637 +1,640 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000224 # Number of seconds simulated
-sim_ticks 224044586 # Number of ticks simulated
-final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 223713460 # Number of ticks simulated
+final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 1786168 # Simulator tick rate (ticks/s)
-host_mem_usage 347548 # Number of bytes of host memory used
-host_seconds 125.43 # Real time elapsed on the host
-system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory
-system.physmem.bytes_read::total 700372 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory
-system.physmem.bytes_written::total 498192 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 14607 # number of replacements
-system.l2c.tagsinuse 798.832185 # Cycle average of tags in use
-system.l2c.total_refs 150557 # Total number of references to valid blocks.
-system.l2c.sampled_refs 15432 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.756156 # Average number of references to valid blocks.
+host_tick_rate 1721618 # Simulator tick rate (ticks/s)
+host_mem_usage 347508 # Number of bytes of host memory used
+host_seconds 129.94 # Real time elapsed on the host
+system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory
+system.physmem.bytes_read::total 663539 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory
+system.physmem.bytes_written::total 466370 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s)
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
@@ -660,114 +663,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf
system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.num_reads 98637 # number of read accesses completed
-system.cpu0.num_writes 53345 # number of write accesses completed
+system.cpu0.num_reads 99016 # number of read accesses completed
+system.cpu0.num_writes 53340 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
-system.cpu0.l1c.replacements 22018 # number of replacements
-system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use
-system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks.
-system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks.
-system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks.
+system.cpu0.l1c.replacements 21906 # number of replacements
+system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use
+system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks.
+system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks.
+system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy
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-system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits
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-system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency
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-system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency
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system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked
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system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks
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-system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
@@ -775,114 +778,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.num_copies 0 # number of copy accesses completed
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system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
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system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
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system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
@@ -890,114 +893,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency
system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
@@ -1005,114 +1008,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 53451 # number of write accesses completed
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system.cpu3.num_copies 0 # number of copy accesses completed
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system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency
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+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency
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system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
@@ -1120,114 +1123,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 53697 # number of write accesses completed
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system.cpu4.num_copies 0 # number of copy accesses completed
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-system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks.
-system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks.
+system.cpu4.l1c.replacements 22293 # number of replacements
+system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
@@ -1235,114 +1238,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses
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-system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses
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-system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses
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system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
@@ -1350,114 +1353,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu6.num_reads 100000 # number of read accesses completed
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system.cpu6.num_copies 0 # number of copy accesses completed
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-system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks.
+system.cpu6.l1c.replacements 22177 # number of replacements
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system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.writebacks::total 9438 # number of writebacks
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-system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses
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system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
@@ -1465,114 +1468,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 53688 # number of write accesses completed
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system.cpu7.num_copies 0 # number of copy accesses completed
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-system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks.
-system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks.
+system.cpu7.l1c.replacements 22218 # number of replacements
+system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use
+system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks.
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+system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency
+system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked
+system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu7.l1c.writebacks::total 9457 # number of writebacks
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-system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses
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-system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses
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-system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses
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-system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses
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-system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles
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-system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles
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-system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency
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+system.cpu7.l1c.writebacks::total 9581 # number of writebacks
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+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles
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+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles
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+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses
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+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses
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+system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency
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+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency
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system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency