diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
| commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
| tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/quick/se/50.memtest | |
| parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
| download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz | |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/quick/se/50.memtest')
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt | 3128 | ||||
| -rw-r--r-- | tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt | 3087 |
2 files changed, 3106 insertions, 3109 deletions
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt index a27123aa4..4a7304d33 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.001493 # Number of seconds simulated -sim_ticks 1493307500 # Number of ticks simulated -final_tick 1493307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000729 # Number of seconds simulated +sim_ticks 728722500 # Number of ticks simulated +final_tick 728722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 295462472 # Simulator tick rate (ticks/s) -host_mem_usage 222068 # Number of bytes of host memory used -host_seconds 5.05 # Real time elapsed on the host +host_tick_rate 162031375 # Simulator tick rate (ticks/s) +host_mem_usage 277108 # Number of bytes of host memory used +host_seconds 4.50 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 74794 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 78736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 78807 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 78188 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 77250 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 74477 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 79412 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78325 # Number of bytes read from this memory -system.physmem.bytes_read::total 619989 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 384000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5518 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5400 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5514 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5530 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5340 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5402 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5377 # Number of bytes written to this memory -system.physmem.bytes_written::total 427483 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 10849 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10948 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10767 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10841 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10974 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10721 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10994 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10915 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87009 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6000 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5518 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5400 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5514 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5530 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5340 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5402 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49483 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 50086134 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 52725912 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 52773458 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 52358941 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 51730806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 49873854 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 53178599 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 52450684 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 415178388 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 257147306 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 3695153 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 3616134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 3692475 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 3703189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 3575955 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 3617473 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 3600732 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 286265890 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 257147306 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 53781288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 56343385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 56389592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 55433995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 53449809 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 56796072 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 56051416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 701444277 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 79470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 78418 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 80729 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80022 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 80096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 78976 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 78470 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 78262 # Number of bytes read from this memory +system.physmem.bytes_read::total 634443 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 400000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5381 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5473 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5390 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5494 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5433 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5395 # Number of bytes written to this memory +system.physmem.bytes_written::total 443379 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10882 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10862 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11100 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 10733 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 10873 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 10934 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::total 87540 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6250 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5381 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5473 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5390 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5494 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5433 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5395 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49629 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 109053858 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 107610236 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 110781539 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 109811348 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 109912896 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 108375959 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 107681593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 107396162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 870623591 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 548905791 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7384155 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 7470608 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7510403 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7396506 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 7367688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7539221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7455513 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7403367 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 608433251 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 548905791 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 116438013 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 115080844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 118291942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 117207853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 117280583 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 115915180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 115137106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 114799529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1479056843 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.num_reads 99767 # number of read accesses completed -system.cpu0.num_writes 55259 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22696 # number of replacements -system.cpu0.l1c.tags.tagsinuse 395.365301 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13357 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 23083 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.578651 # Average number of references to valid blocks. +system.cpu0.num_reads 100000 # number of read accesses completed +system.cpu0.num_writes 54791 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22240 # number of replacements +system.cpu0.l1c.tags.tagsinuse 394.087405 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13441 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22636 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.593789 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 395.365301 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.772198 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 272 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 339665 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 339665 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8708 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8708 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1150 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1150 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9858 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9858 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9858 # number of overall hits -system.cpu0.l1c.overall_hits::total 9858 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36982 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36982 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23775 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23775 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60757 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60757 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60757 # number of overall misses -system.cpu0.l1c.overall_misses::total 60757 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 2501825237 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1853114266 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 4354939503 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 4354939503 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 4354939503 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45690 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24925 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70615 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70615 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70615 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70615 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809411 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.953862 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860398 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860398 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860398 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860398 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 67649.809015 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 77943.817708 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 71677.987771 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 71677.987771 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 2197094 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 394.087405 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.769702 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 337290 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 337290 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8682 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8682 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1111 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1111 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9793 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9793 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9793 # number of overall hits +system.cpu0.l1c.overall_hits::total 9793 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36727 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36727 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23639 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23639 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60366 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60366 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60366 # number of overall misses +system.cpu0.l1c.overall_misses::total 60366 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1016702315 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 918792240 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1935494555 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1935494555 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1935494555 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45409 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24750 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70159 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70159 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70159 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70159 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.808804 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.955111 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860417 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860417 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860417 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860417 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 27682.694339 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38867.644147 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 32062.660355 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 32062.660355 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1074391 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 60506 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 61970 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.312002 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 17.337276 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9747 # number of writebacks -system.cpu0.l1c.writebacks::total 9747 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36982 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23775 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60757 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60757 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60757 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 2423727133 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1803343082 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 4227070215 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 4227070215 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1077807594 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 4091615147 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5169422741 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809411 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953862 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860398 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860398 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65538.022092 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 75850.392513 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69573.386030 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69573.386030 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu0.l1c.writebacks::total 9656 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36727 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23639 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60366 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60366 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60366 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 960514497 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 882874166 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1843388663 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1843388663 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 755586835 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1939842714 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2695429549 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808804 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.955111 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860417 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860417 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 26152.816647 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37348.202800 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 30536.869480 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 30536.869480 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 54988 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22397 # number of replacements -system.cpu1.l1c.tags.tagsinuse 395.796271 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13630 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 22804 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.597702 # Average number of references to valid blocks. +system.cpu1.num_reads 99410 # number of read accesses completed +system.cpu1.num_writes 55132 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22295 # number of replacements +system.cpu1.l1c.tags.tagsinuse 393.820804 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13496 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22679 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.595088 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 395.796271 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.773040 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 269 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 138 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 338465 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 338465 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8882 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8882 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1141 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1141 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 10023 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 10023 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 10023 # number of overall hits -system.cpu1.l1c.overall_hits::total 10023 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36639 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36639 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23767 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23767 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60406 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60406 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60406 # number of overall misses -system.cpu1.l1c.overall_misses::total 60406 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 2485954076 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1862028208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 4347982284 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 4347982284 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 4347982284 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24908 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70429 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70429 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70429 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70429 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.804881 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954191 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.857686 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.857686 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.857686 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.857686 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 67849.943394 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 78345.109101 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 71979.311393 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 71979.311393 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 2202198 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 393.820804 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.769181 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 384 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 343 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 41 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.750000 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338268 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338268 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8726 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8726 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1171 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1171 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9897 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9897 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9897 # number of overall hits +system.cpu1.l1c.overall_hits::total 9897 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36573 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36573 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23897 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23897 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60470 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60470 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60470 # number of overall misses +system.cpu1.l1c.overall_misses::total 60470 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1020722242 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 921634198 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1942356440 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1942356440 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1942356440 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25068 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70367 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70367 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70367 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70367 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807369 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953287 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.859352 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.859352 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.859352 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.859352 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 27909.174582 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38566.941373 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 32120.992889 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 32120.992889 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1066797 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 60277 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 61607 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.534632 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 17.316165 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9809 # number of writebacks -system.cpu1.l1c.writebacks::total 9809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36639 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23767 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60406 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60406 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60406 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 2408616840 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1812196150 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 4220812990 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 4220812990 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1084723149 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 4036922188 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 5121645337 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.804881 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954191 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.857686 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.857686 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 65739.153361 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 76248.417975 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 69874.068636 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 69874.068636 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9694 # number of writebacks +system.cpu1.l1c.writebacks::total 9694 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36573 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23897 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60470 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60470 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60470 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 964784026 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 885327122 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1850111148 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1850111148 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 740106955 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1954561172 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2694668127 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807369 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953287 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.859352 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.859352 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 26379.679709 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37047.626146 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 30595.520886 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 30595.520886 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99645 # number of read accesses completed -system.cpu2.num_writes 55347 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22638 # number of replacements -system.cpu2.l1c.tags.tagsinuse 395.541236 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.593323 # Average number of references to valid blocks. +system.cpu2.num_reads 99274 # number of read accesses completed +system.cpu2.num_writes 54884 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22456 # number of replacements +system.cpu2.l1c.tags.tagsinuse 393.843880 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13581 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22857 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.594172 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 395.541236 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.772541 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 271 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 339287 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 339287 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8844 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8844 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1130 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9974 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9974 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9974 # number of overall hits -system.cpu2.l1c.overall_hits::total 9974 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36761 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36761 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23865 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23865 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60626 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60626 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60626 # number of overall misses -system.cpu2.l1c.overall_misses::total 60626 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 2497854261 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1869962350 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 4367816611 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 4367816611 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 4367816611 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45605 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24995 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70600 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70600 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70600 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70600 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.806074 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.954791 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.858725 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.858725 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.858725 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.858725 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 67948.485106 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 78355.849571 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 72045.271187 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 72045.271187 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 2198319 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 393.843880 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.769226 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 373 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 337451 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 337451 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8813 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8813 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1134 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1134 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9947 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9947 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9947 # number of overall hits +system.cpu2.l1c.overall_hits::total 9947 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36457 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36457 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23816 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23816 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60273 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60273 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60273 # number of overall misses +system.cpu2.l1c.overall_misses::total 60273 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1014308258 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 924910230 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1939218488 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1939218488 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1939218488 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45270 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24950 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70220 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70220 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70220 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70220 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805324 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.954549 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858345 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858345 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858345 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858345 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 27822.043997 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38835.666359 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 32173.916812 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 32173.916812 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1061117 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 60200 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 61178 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 36.516927 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 17.344748 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9871 # number of writebacks -system.cpu2.l1c.writebacks::total 9871 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36761 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23865 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60626 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60626 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60626 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 2420242117 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1819999216 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 4240241333 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 4240241333 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1065167222 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 3984850744 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 5050017966 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806074 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954791 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.858725 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.858725 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 65837.221974 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 76262.275969 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 69940.971415 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 69940.971415 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9940 # number of writebacks +system.cpu2.l1c.writebacks::total 9940 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36457 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23816 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60273 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60273 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60273 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 958559384 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 888663772 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1847223156 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1847223156 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 735013046 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1939097223 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2674110269 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805324 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.954549 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858345 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858345 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 26292.876101 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37313.729090 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 30647.605993 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 30647.605993 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98252 # number of read accesses completed -system.cpu3.num_writes 55235 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22381 # number of replacements -system.cpu3.l1c.tags.tagsinuse 396.107709 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13213 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 22778 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580077 # Average number of references to valid blocks. +system.cpu3.num_reads 99869 # number of read accesses completed +system.cpu3.num_writes 54874 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22370 # number of replacements +system.cpu3.l1c.tags.tagsinuse 393.431339 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13240 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22771 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.581441 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 396.107709 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.773648 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 282 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 335638 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 335638 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8470 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8470 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1156 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1156 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9626 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9626 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9626 # number of overall hits -system.cpu3.l1c.overall_hits::total 9626 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36183 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36183 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23969 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23969 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60152 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60152 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60152 # number of overall misses -system.cpu3.l1c.overall_misses::total 60152 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 2454128819 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1887224651 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 4341353470 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 4341353470 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 4341353470 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44653 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25125 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69778 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69778 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69778 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69778 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.810315 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.953990 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.862048 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.862048 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.862048 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.862048 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 67825.465522 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 78736.061204 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 72173.052766 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 72173.052766 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 2184377 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 393.431339 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.768421 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 401 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.783203 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 336829 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 336829 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8648 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8648 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1128 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1128 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9776 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9776 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9776 # number of overall hits +system.cpu3.l1c.overall_hits::total 9776 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36458 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36458 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23788 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23788 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60246 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60246 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60246 # number of overall misses +system.cpu3.l1c.overall_misses::total 60246 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1012578921 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 920459168 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1933038089 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1933038089 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1933038089 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45106 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24916 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70022 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70022 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70022 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70022 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808274 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954728 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860387 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860387 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860387 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860387 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 27773.847194 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38694.264671 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 32085.749909 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 32085.749909 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1072737 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 59819 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 61848 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 36.516441 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 17.344732 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu3.l1c.writebacks::total 9931 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36183 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23969 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60152 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60152 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60152 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 2377731501 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1837004571 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 4214736072 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 4214736072 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1072192160 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 4016794612 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 5088986772 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.810315 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953990 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.862048 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.862048 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 65714.050825 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 76640.851558 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 70068.095358 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 70068.095358 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9757 # number of writebacks +system.cpu3.l1c.writebacks::total 9757 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36458 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23788 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60246 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60246 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60246 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 956791627 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 884289164 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1841080791 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1841080791 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 756050699 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1926314708 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2682365407 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808274 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954728 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860387 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860387 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 26243.667426 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37173.749958 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 30559.386366 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 30559.386366 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99562 # number of read accesses completed -system.cpu4.num_writes 54813 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22626 # number of replacements -system.cpu4.l1c.tags.tagsinuse 395.713168 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13359 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 23019 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.580347 # Average number of references to valid blocks. +system.cpu4.num_reads 98774 # number of read accesses completed +system.cpu4.num_writes 54829 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22505 # number of replacements +system.cpu4.l1c.tags.tagsinuse 395.050000 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13373 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22916 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.583566 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 395.713168 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.772877 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 273 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 337886 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 337886 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8660 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1130 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9790 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9790 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9790 # number of overall hits -system.cpu4.l1c.overall_hits::total 9790 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36748 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36748 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23725 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23725 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60473 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60473 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60473 # number of overall misses -system.cpu4.l1c.overall_misses::total 60473 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 2479360793 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1851125976 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 4330486769 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 4330486769 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 4330486769 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45408 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24855 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 70263 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 70263 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 70263 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 70263 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809285 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.954536 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.860666 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.860666 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.860666 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.860666 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 67469.271607 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 78024.277176 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 71610.251997 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 71610.251997 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 2193235 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 395.050000 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.771582 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 411 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.802734 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 337873 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 337873 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8531 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8531 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1209 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1209 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9740 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9740 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9740 # number of overall hits +system.cpu4.l1c.overall_hits::total 9740 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36518 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36518 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 24001 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 24001 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60519 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60519 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60519 # number of overall misses +system.cpu4.l1c.overall_misses::total 60519 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1017641988 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 934552595 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1952194583 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1952194583 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1952194583 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45049 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 25210 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70259 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70259 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70259 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70259 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.810628 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952043 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.861370 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.861370 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.861370 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.861370 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 27866.859850 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38938.069039 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 32257.548588 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 32257.548588 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1063629 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 60223 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 61473 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 36.418561 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 17.302377 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9708 # number of writebacks -system.cpu4.l1c.writebacks::total 9708 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36748 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23725 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60473 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60473 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60473 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 2401684855 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1801504708 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 4203189563 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 4203189563 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1091799507 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 4121360584 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 5213160091 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809285 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.954536 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.860666 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.860666 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 65355.525607 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 75932.759031 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 69505.226514 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 69505.226514 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9914 # number of writebacks +system.cpu4.l1c.writebacks::total 9914 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36518 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 24001 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60519 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60519 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60519 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 961775196 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 898026173 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1859801369 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1859801369 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 728267014 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1921671690 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2649938704 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.810628 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952043 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.861370 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.861370 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 26337.017252 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37416.198200 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 30730.867480 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 30730.867480 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98672 # number of read accesses completed -system.cpu5.num_writes 54809 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22472 # number of replacements -system.cpu5.l1c.tags.tagsinuse 396.252013 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13351 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22867 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.583854 # Average number of references to valid blocks. +system.cpu5.num_reads 99305 # number of read accesses completed +system.cpu5.num_writes 54996 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22529 # number of replacements +system.cpu5.l1c.tags.tagsinuse 394.380527 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13364 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22931 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.582792 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 396.252013 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.773930 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 261 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.771484 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 336301 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 336301 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8563 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8563 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1084 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1084 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9647 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9647 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9647 # number of overall hits -system.cpu5.l1c.overall_hits::total 9647 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36411 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36411 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23882 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23882 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60293 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60293 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60293 # number of overall misses -system.cpu5.l1c.overall_misses::total 60293 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 2486246489 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1881159650 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 4367406139 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 4367406139 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 4367406139 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44974 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24966 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69940 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69940 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69940 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69940 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.809601 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.956581 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.862067 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.862067 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.862067 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.862067 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 68282.840048 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 78768.932669 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 72436.371370 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 72436.371370 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 2200429 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 394.380527 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.770274 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 402 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.785156 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337468 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337468 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8640 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8640 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1161 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1161 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9801 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9801 # number of overall hits +system.cpu5.l1c.overall_hits::total 9801 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36580 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36580 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23798 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23798 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60378 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60378 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60378 # number of overall misses +system.cpu5.l1c.overall_misses::total 60378 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1015127570 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 927119253 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1942246823 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1942246823 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1942246823 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45220 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70179 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70179 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70179 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70179 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808934 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953484 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860343 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860343 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860343 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860343 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 27750.890377 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38957.864232 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 32168.121220 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 32168.121220 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1066593 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 60083 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 61522 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 36.623155 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 17.336774 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9941 # number of writebacks -system.cpu5.l1c.writebacks::total 9941 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36411 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23882 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60293 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60293 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60293 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 2409268523 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1831238342 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 4240506865 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 4240506865 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1068031665 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 3938248323 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 5006279988 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.809601 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956581 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.862067 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.862067 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 66168.699651 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 76678.600703 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 70331.661470 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 70331.661470 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu5.l1c.writebacks::total 9775 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36580 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23798 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60378 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60378 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60378 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 959195658 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 890981649 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1850177307 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1850177307 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 738489342 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1963680665 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2702170007 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808934 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953484 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860343 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860343 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 26221.860525 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37439.349903 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 30643.236063 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 30643.236063 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99484 # number of read accesses completed -system.cpu6.num_writes 54995 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22115 # number of replacements -system.cpu6.l1c.tags.tagsinuse 396.164371 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13666 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22491 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.607621 # Average number of references to valid blocks. +system.cpu6.num_reads 99342 # number of read accesses completed +system.cpu6.num_writes 54737 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22276 # number of replacements +system.cpu6.l1c.tags.tagsinuse 393.125800 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13636 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22683 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.601155 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 396.164371 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.773759 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 376 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 247 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 338129 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 338129 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8797 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8797 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1207 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1207 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 10004 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 10004 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 10004 # number of overall hits -system.cpu6.l1c.overall_hits::total 10004 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36456 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36456 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23912 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23912 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60368 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60368 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60368 # number of overall misses -system.cpu6.l1c.overall_misses::total 60368 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 2466938162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1877191258 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 4344129420 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 4344129420 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 4344129420 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45253 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 25119 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70372 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70372 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70372 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70372 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805604 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951949 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.857841 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.857841 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.857841 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.857841 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 67668.920397 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 78504.150970 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 71960.797442 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 71960.797442 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 2202006 # number of cycles access was blocked +system.cpu6.l1c.tags.occ_blocks::cpu6 393.125800 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.767824 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 407 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337855 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337855 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8799 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8799 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1154 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1154 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9953 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9953 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9953 # number of overall hits +system.cpu6.l1c.overall_hits::total 9953 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36552 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36552 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23805 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23805 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60357 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60357 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60357 # number of overall misses +system.cpu6.l1c.overall_misses::total 60357 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1017275565 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 923819144 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1941094709 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1941094709 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1941094709 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45351 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24959 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70310 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70310 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805980 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953764 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858441 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858441 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858441 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858441 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 27830.913903 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38807.777526 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 32160.225144 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 32160.225144 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1069531 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 60316 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 61695 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 36.507825 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 17.335781 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9723 # number of writebacks -system.cpu6.l1c.writebacks::total 9723 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36456 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23912 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60368 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60368 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60368 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 2389944958 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1827130108 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 4217075066 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 4217075066 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1090860454 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 4034817264 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 5125677718 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805604 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951949 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.857841 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.857841 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 65556.971637 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 76410.593342 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69856.133481 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 69856.133481 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9809 # number of writebacks +system.cpu6.l1c.writebacks::total 9809 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36552 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23805 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60357 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60357 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60357 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 961362717 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 887609672 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1848972389 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1848972389 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 744037855 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1951627727 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2695665582 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805980 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953764 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858441 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858441 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 26301.234324 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37286.690695 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 30633.934573 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 30633.934573 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98571 # number of read accesses completed -system.cpu7.num_writes 54904 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22064 # number of replacements -system.cpu7.l1c.tags.tagsinuse 394.954913 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13425 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22470 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.597463 # Average number of references to valid blocks. +system.cpu7.num_reads 99062 # number of read accesses completed +system.cpu7.num_writes 54686 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22200 # number of replacements +system.cpu7.l1c.tags.tagsinuse 394.753023 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13454 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 22591 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.595547 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 394.954913 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.771396 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 406 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 274 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 132 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 334895 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 334895 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8604 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8604 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1157 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1157 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9761 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9761 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9761 # number of overall hits -system.cpu7.l1c.overall_hits::total 9761 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35973 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35973 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23939 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23939 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59912 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59912 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59912 # number of overall misses -system.cpu7.l1c.overall_misses::total 59912 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 2452832630 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1890055104 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 4342887734 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 4342887734 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 4342887734 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44577 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25096 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69673 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69673 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69673 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69673 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806986 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953897 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859903 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859903 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859903 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859903 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 68185.378756 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 78952.968127 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 72487.777641 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 72487.777641 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 2195658 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 394.753023 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.771002 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 354 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 337139 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 337139 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8690 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8690 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1182 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9872 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9872 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9872 # number of overall hits +system.cpu7.l1c.overall_hits::total 9872 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36466 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36466 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23790 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23790 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60256 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60256 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60256 # number of overall misses +system.cpu7.l1c.overall_misses::total 60256 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1009807130 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 916976125 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1926783255 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1926783255 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1926783255 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24972 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70128 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70128 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70128 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70128 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807556 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.952667 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859229 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859229 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859229 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859229 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 27691.743816 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 38544.603825 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 31976.620668 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 31976.620668 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1063264 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 59807 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 61445 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 36.712392 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 17.304321 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9796 # number of writebacks -system.cpu7.l1c.writebacks::total 9796 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35973 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23939 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59912 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59912 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59912 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2376889288 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1839857154 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 4216746442 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 4216746442 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1084884512 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 4029557689 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5114442201 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806986 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953897 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859903 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859903 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 66074.258138 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76856.057229 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 70382.334791 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 70382.334791 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9819 # number of writebacks +system.cpu7.l1c.writebacks::total 9819 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36466 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23790 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60256 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60256 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60256 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 953998318 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 880753723 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1834752041 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1834752041 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 752742732 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1947143716 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2699886448 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807556 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952667 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859229 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859229 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 26161.309658 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 37022.014418 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 30449.283739 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 30449.283739 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,566 +1037,565 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 12730 # number of replacements -system.l2c.tags.tagsinuse 780.951688 # Cycle average of tags in use -system.l2c.tags.total_refs 149721 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 13527 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 11.068308 # Average number of references to valid blocks. +system.l2c.tags.replacements 13121 # number of replacements +system.l2c.tags.tagsinuse 779.163229 # Cycle average of tags in use +system.l2c.tags.total_refs 150276 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 13897 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.813557 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 730.352338 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 5.728717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 6.680211 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 7.211499 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 5.648633 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.142733 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 5.860524 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.858945 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.468088 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.713235 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.005594 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006524 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.007042 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.005516 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.005999 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005723 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006698 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.006316 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.762648 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 424 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.778320 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1954074 # Number of tag accesses -system.l2c.tags.data_accesses 1954074 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10705 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10659 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10665 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10689 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10673 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10679 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10651 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10616 # number of ReadReq hits -system.l2c.ReadReq_hits::total 85337 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 75478 # number of Writeback hits -system.l2c.Writeback_hits::total 75478 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 365 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 349 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 333 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 340 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 338 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 343 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2772 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1956 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1860 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1936 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1874 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1916 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1840 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1899 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1911 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15192 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12661 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12601 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12563 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12589 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12519 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12550 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12527 # number of demand (read+write) hits -system.l2c.demand_hits::total 100529 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12661 # number of overall hits -system.l2c.overall_hits::cpu1 12519 # number of overall hits -system.l2c.overall_hits::cpu2 12601 # number of overall hits -system.l2c.overall_hits::cpu3 12563 # number of overall hits -system.l2c.overall_hits::cpu4 12589 # number of overall hits -system.l2c.overall_hits::cpu5 12519 # number of overall hits -system.l2c.overall_hits::cpu6 12550 # number of overall hits -system.l2c.overall_hits::cpu7 12527 # number of overall hits -system.l2c.overall_hits::total 100529 # number of overall hits -system.l2c.ReadReq_misses::cpu0 637 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 698 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 649 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 657 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 655 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 700 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 686 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5400 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1869 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1879 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1945 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1927 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1931 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 2008 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1996 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1999 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15554 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4327 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4376 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4482 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4415 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4364 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4427 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4401 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35152 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5025 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5094 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5131 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5072 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5019 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5127 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5087 # number of demand (read+write) misses -system.l2c.demand_misses::total 40552 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 4997 # number of overall misses -system.l2c.overall_misses::cpu1 5025 # number of overall misses -system.l2c.overall_misses::cpu2 5094 # number of overall misses -system.l2c.overall_misses::cpu3 5131 # number of overall misses -system.l2c.overall_misses::cpu4 5072 # number of overall misses -system.l2c.overall_misses::cpu5 5019 # number of overall misses -system.l2c.overall_misses::cpu6 5127 # number of overall misses -system.l2c.overall_misses::cpu7 5087 # number of overall misses -system.l2c.overall_misses::total 40552 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 37351962 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 41387952 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 42368449 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 38023954 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 38587461 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 38640955 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 40955466 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 40550959 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 317867158 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 53532000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 54034500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 55090000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 53743000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53806000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57327000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 56366500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57375499 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 441274499 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 232668482 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231079974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 233454479 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 239997471 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 235674978 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 232806977 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 236584974 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 235413970 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1877681305 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 270020444 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 272467926 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 275822928 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278021425 # 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number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2234 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2220 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2308 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2276 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2348 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2334 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2342 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18326 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6316 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6187 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6356 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6331 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6204 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6326 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6312 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50344 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17658 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17544 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17695 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17694 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17661 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17677 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17614 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 141081 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17658 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17544 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17695 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17694 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17661 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17677 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17614 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 141081 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.056163 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.061460 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.063077 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.057241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.057988 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.057791 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.061669 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.060697 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.059513 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.836616 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.846396 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842721 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.846661 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852915 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.855196 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.855184 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.853544 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.848739 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.690310 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.699370 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.693283 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.705160 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.697362 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.703417 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.699810 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.697243 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.698236 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.282988 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.286423 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.287878 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289985 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.287186 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.286179 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.290038 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.288804 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.287438 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.282988 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.286423 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.287878 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.289985 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.287186 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.286179 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.290038 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.288804 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.287438 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 58637.302983 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 59295.060172 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 59008.981894 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 58588.526965 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 58732.817352 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 58993.824427 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 58507.808571 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59112.185131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58864.288519 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28642.054575 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28757.051623 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28323.907455 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27889.465490 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 27864.319006 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28549.302789 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28239.729459 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28702.100550 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28370.483413 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53364.330734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53404.200139 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53348.829753 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53546.959170 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53380.515968 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53347.153300 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53441.376553 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53491.017950 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53416.058972 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54036.510706 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54222.472836 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54146.628975 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54184.647242 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54073.824724 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54084.066946 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54133.107080 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54249.052290 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54141.558074 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 6543 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.457797 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 6.718013 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 6.568954 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 6.219418 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 6.731947 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.474998 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 6.998802 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 6.991847 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.001453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708455 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.006561 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006415 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.006074 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.006574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006323 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.006835 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.006828 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.006837 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.760902 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 776 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 566 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 210 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1961425 # Number of tag accesses +system.l2c.tags.data_accesses 1961425 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10794 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10766 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10683 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10661 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10671 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10889 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10673 # number of ReadReq hits +system.l2c.ReadReq_hits::total 85829 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 75598 # number of Writeback hits +system.l2c.Writeback_hits::total 75598 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 323 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 342 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 334 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 356 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2745 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1821 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1892 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1893 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1947 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1922 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1886 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1863 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15171 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12615 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12658 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12630 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12554 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12639 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12593 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12775 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12536 # number of demand (read+write) hits +system.l2c.demand_hits::total 101000 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12615 # number of overall hits +system.l2c.overall_hits::cpu1 12658 # number of overall hits +system.l2c.overall_hits::cpu2 12630 # number of overall hits +system.l2c.overall_hits::cpu3 12554 # number of overall hits +system.l2c.overall_hits::cpu4 12639 # number of overall hits +system.l2c.overall_hits::cpu5 12593 # number of overall hits +system.l2c.overall_hits::cpu6 12775 # number of overall hits +system.l2c.overall_hits::cpu7 12536 # number of overall hits +system.l2c.overall_hits::total 101000 # number of overall hits +system.l2c.ReadReq_misses::cpu0 705 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 721 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 716 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 685 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 690 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 691 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 715 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5617 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1952 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1935 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1832 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1968 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1954 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1963 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15493 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4418 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4338 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4348 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4457 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4447 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4501 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4407 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35289 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5059 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5064 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5142 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5141 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5191 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5098 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5088 # number of demand (read+write) misses +system.l2c.demand_misses::total 40906 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5123 # number of overall misses +system.l2c.overall_misses::cpu1 5059 # number of overall misses +system.l2c.overall_misses::cpu2 5064 # number of overall misses +system.l2c.overall_misses::cpu3 5142 # number of overall misses +system.l2c.overall_misses::cpu4 5141 # number of overall misses +system.l2c.overall_misses::cpu5 5191 # number of overall misses +system.l2c.overall_misses::cpu6 5098 # number of overall misses +system.l2c.overall_misses::cpu7 5088 # number of overall misses +system.l2c.overall_misses::total 40906 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 42571447 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 44584934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 43709432 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42098938 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 42802932 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 42467936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 42434429 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44394419 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 345064467 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 57799000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 58024000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 57179999 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53990500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 56201500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 57084499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 56659000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56222499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 453160997 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 241579958 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 237098460 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 238347956 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 243950461 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 243322462 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 246152957 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 241076464 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 238492966 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1930021684 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 284151405 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 281683394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 282057388 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 286049399 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 286125394 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 288620893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 283510893 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282887385 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2275086151 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 284151405 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 281683394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 282057388 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 286049399 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 286125394 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 288620893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 283510893 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282887385 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2275086151 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11499 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11487 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11346 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11386 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11361 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11388 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91446 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75598 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75598 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2305 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2258 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2312 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2166 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2284 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2324 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2265 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18238 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6239 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6230 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6295 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6350 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6394 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6423 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6293 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6236 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50460 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17738 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17694 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17780 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17784 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17873 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17624 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 141906 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17738 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17694 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17780 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17784 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17873 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17624 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 141906 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.061310 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.062767 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.062813 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060374 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060952 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.060734 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.059672 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.062785 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.061424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.846855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.856953 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.852076 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.845799 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.846816 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.855517 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.844664 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.847241 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849490 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.708126 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.696308 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.690707 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.701890 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.695496 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.700763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.700302 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.701251 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.699346 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.288815 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.285545 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286199 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.290574 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.289145 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291892 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.285235 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288697 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288261 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.288815 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.285545 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286199 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.290574 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.289145 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291892 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.285235 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288697 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288261 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60385.031206 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61837.633842 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 61046.692737 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61458.303650 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61675.694524 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61547.733333 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61410.172214 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 62090.096503 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61432.164323 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29610.143443 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 29986.563307 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29025.380203 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29470.796943 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28557.672764 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 29214.175537 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28863.474274 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29297.810839 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29249.402763 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 54680.841557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 54656.168741 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 54817.837167 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 54734.229527 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 54716.092197 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54688.504110 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 54703.077831 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54537.609421 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 54691.878036 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 55465.821784 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 55679.658826 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 55698.536335 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55629.988137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55655.591130 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55600.249085 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 55612.179874 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55598.935731 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55617.419229 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10446 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 914 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1464 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.158643 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.135246 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6000 # number of writebacks -system.l2c.writebacks::total 6000 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 4 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 14 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 2 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 1 # number of demand (read+write) MSHR hits +system.l2c.writebacks::writebacks 6250 # number of writebacks +system.l2c.writebacks::total 6250 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 1 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 15 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 4 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 35 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 2 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 1 # number of overall MSHR hits +system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 64 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 4 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 35 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 635 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 695 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 716 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 643 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 657 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 651 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 698 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 684 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5379 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1869 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1879 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1943 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1926 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1931 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 2008 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1995 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1999 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15550 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4360 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4323 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4482 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4414 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4363 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4425 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4399 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 35138 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 4995 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5018 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5088 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5125 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5071 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5014 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5123 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40517 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 4995 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5018 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5088 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5125 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5071 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5014 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5123 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5083 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40517 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 29596962 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 32869452 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 33629449 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 29976455 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 30615961 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 30583955 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 32395466 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32146959 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 251814659 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76123000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76358500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 79146000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78403000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 78530000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81677500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 81182000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81450499 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 632870499 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 179654482 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178405975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 180144979 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 185516471 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 181991978 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 179667478 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182702975 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 181859470 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1449943808 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 209251444 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 211275427 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 213774428 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 215492926 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 212607939 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 210251433 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 215098441 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 214006429 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1701758467 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 209251444 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 211275427 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 213774428 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 215492926 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 212607939 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 210251433 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 215098441 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 214006429 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1701758467 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 401930986 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 402911994 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 395709487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 399023483 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405620989 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 396449489 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 404605985 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 402179993 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3208432406 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 228006492 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 223295497 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 223196996 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 228513495 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 229209992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 220676995 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 224532992 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 222245997 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1799678456 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 629937478 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 626207491 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 618906483 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 627536978 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 634830981 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 617126484 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629138977 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 624425990 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5008110862 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.061196 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062901 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.056712 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.057988 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.057438 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.061492 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.060520 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.059281 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.836616 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.846396 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841854 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.846221 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852915 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855196 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.854756 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853544 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848521 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.690310 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.698723 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.692649 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.705160 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.697204 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.703256 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.699494 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696926 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.697958 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.287190 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.282875 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.286024 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.287539 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.289646 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.287130 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.285893 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.289812 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288577 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.287190 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 46609.388976 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 47294.175540 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46968.504190 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 46619.681182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46599.636225 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 46979.961598 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46411.842407 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 46998.478070 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46814.400260 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40729.266988 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40637.839276 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40733.916624 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40707.684320 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40668.047644 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40676.045817 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40692.731830 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40745.622311 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40699.067460 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41205.156422 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41269.020356 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41204.249543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41391.448237 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41230.624830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41179.802430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41288.807910 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41341.093430 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41264.266834 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 41892.180981 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42103.512754 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42015.414308 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42047.400195 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 41926.235259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 41932.874551 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 41986.812610 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42102.386189 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42001.097490 # average overall mshr miss latency +system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 64 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 698 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 712 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 676 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 688 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 687 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 684 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 709 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5568 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1951 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1935 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1832 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1968 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1954 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1963 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1919 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15492 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4416 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4335 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4345 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4456 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4447 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4499 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4370 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35274 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5114 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5049 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5057 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5132 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5135 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5186 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5090 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5079 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40842 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5114 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5049 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5057 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5132 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5135 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5186 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5090 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5079 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40842 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 33845945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 35679430 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 34970423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 33623934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34265930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 34048934 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 33977929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 35572914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 275985439 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81779494 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81207491 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 82576991 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76840996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 82448987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81922493 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82161995 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80384488 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 649322935 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 187970446 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 184467447 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 185588937 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189921941 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 189397436 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 191605943 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 187621956 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 185423942 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1501998048 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 221816391 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220146877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 220559360 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223545875 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 223663366 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 225654877 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 221599885 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 220996856 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1777983487 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 221816391 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220146877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 220559360 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223545875 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 223663366 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 225654877 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 221599885 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 220996856 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1777983487 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 420548415 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 410318426 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 408411942 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 419559934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 403725937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410458428 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 413026934 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 417703437 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3303753453 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230815972 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 233216955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 233429960 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229986451 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230895448 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 235553969 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233378955 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230983963 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1858261673 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 651364387 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 643535381 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 641841902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 649546385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634621385 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 646012397 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 646405889 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 648687400 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5162015126 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.060701 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.062462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059580 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.060425 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.060470 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059067 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.062259 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.060888 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.846421 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.856953 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.852076 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.845799 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.846816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.855517 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.844664 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.847241 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849435 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.707806 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.695827 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.690230 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.701732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695496 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.700452 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.700143 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.700770 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.699049 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.287810 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.288308 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.284981 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.285803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.290009 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288808 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.291610 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.284787 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.288187 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.287810 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48489.892550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49971.190476 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49115.762640 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49739.547337 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49805.130814 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49561.767103 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49675.334795 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 50173.362482 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49566.350395 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41916.706304 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41967.695607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41917.254315 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.775109 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41894.810467 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41925.533777 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41855.320937 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41888.737884 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41913.434999 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 42565.771286 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42553.044291 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42713.219102 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42621.620512 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42589.933888 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42588.562569 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42583.285520 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42431.108009 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 42580.882463 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 43374.343176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 43602.075064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 43614.664821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43559.211808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43556.643817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43512.317200 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 43536.323183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43511.883442 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43533.213040 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1625,109 +1624,108 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.snoop_filter.tot_requests 122833 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 120785 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.tot_requests 123722 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 121674 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.trans_dist::ReadReq 83923 # Transaction distribution -system.membus.trans_dist::ReadResp 83923 # Transaction distribution -system.membus.trans_dist::WriteReq 43483 # Transaction distribution -system.membus.trans_dist::WriteResp 43481 # Transaction distribution -system.membus.trans_dist::Writeback 6000 # Transaction distribution +system.membus.trans_dist::ReadReq 84424 # Transaction distribution +system.membus.trans_dist::ReadResp 84420 # Transaction distribution +system.membus.trans_dist::WriteReq 43379 # Transaction distribution +system.membus.trans_dist::WriteResp 43377 # Transaction distribution +system.membus.trans_dist::Writeback 6250 # Transaction distribution system.membus.trans_dist::UpgradeReq 58661 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47607 # Transaction distribution -system.membus.trans_dist::ReadExReq 50527 # Transaction distribution -system.membus.trans_dist::ReadExResp 3086 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 420691 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1047472 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 58495 # Total snoops (count) -system.membus.snoop_fanout::samples 122833 # Request fanout histogram +system.membus.trans_dist::UpgradeResp 47649 # Transaction distribution +system.membus.trans_dist::ReadExReq 50299 # Transaction distribution +system.membus.trans_dist::ReadExResp 3116 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 421575 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1077818 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 58193 # Total snoops (count) +system.membus.snoop_fanout::samples 123722 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 122833 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 123722 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 122833 # Request fanout histogram -system.membus.reqLayer0.occupancy 472878500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 31.7 # Layer utilization (%) -system.membus.respLayer0.occupancy 318922500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 21.4 # Layer utilization (%) -system.toL2Bus.snoop_filter.tot_requests 559080 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 259825 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 297207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.membus.snoop_fanout::total 123722 # Request fanout histogram +system.membus.reqLayer0.occupancy 350831336 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 48.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 312389376 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 42.9 # Layer utilization (%) +system.toL2Bus.snoop_filter.tot_requests 560254 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 259972 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 298234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 370692 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 370683 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43483 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43481 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 75478 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29380 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29380 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161449 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120700 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120296 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120254 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119815 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120341 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 119764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 961915 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1743799 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1739946 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1755311 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1759542 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1742748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1748105 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1744654 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1747573 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 13981678 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 323561 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 559080 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.688315 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 1.176863 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 371185 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371180 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43379 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43375 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 75598 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29248 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29247 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 161278 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 161272 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120544 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120292 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120322 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120179 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120443 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120589 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 963055 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1746802 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1746902 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1761658 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751012 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1764505 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756981 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1763838 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1750408 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14042106 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 560254 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.690126 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 1.177666 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 52722 9.43% 9.43% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 250233 44.76% 54.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 141253 25.27% 79.45% # Request fanout histogram -system.toL2Bus.snoop_fanout::3 69107 12.36% 91.81% # Request fanout histogram -system.toL2Bus.snoop_fanout::4 29981 5.36% 97.18% # Request fanout histogram -system.toL2Bus.snoop_fanout::5 11505 2.06% 99.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::6 3559 0.64% 99.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 720 0.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 52995 9.46% 9.46% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 250263 44.67% 54.13% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 141259 25.21% 79.34% # Request fanout histogram +system.toL2Bus.snoop_fanout::3 69446 12.40% 91.74% # Request fanout histogram +system.toL2Bus.snoop_fanout::4 30460 5.44% 97.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::5 11695 2.09% 99.26% # Request fanout histogram +system.toL2Bus.snoop_fanout::6 3486 0.62% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 650 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 559080 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1490758741 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 99.8 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160617515 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 10.8 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 159518006 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 159700003 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 158882050 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 159826982 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 158824012 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 10.6 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 159298538 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 158114013 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 10.6 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 560254 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 719277462 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 100586935 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 100589620 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 100255865 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 100593415 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 100466351 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 100465013 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 100397923 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 100485866 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt index f348549bd..b29e580fa 100644 --- a/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt @@ -1,195 +1,195 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000667 # Number of seconds simulated -sim_ticks 667077000 # Number of ticks simulated -final_tick 667077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000476 # Number of seconds simulated +sim_ticks 475552000 # Number of ticks simulated +final_tick 475552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 152389795 # Simulator tick rate (ticks/s) -host_mem_usage 222064 # Number of bytes of host memory used -host_seconds 4.38 # Real time elapsed on the host +host_tick_rate 102852654 # Simulator tick rate (ticks/s) +host_mem_usage 276856 # Number of bytes of host memory used +host_seconds 4.62 # Real time elapsed on the host system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0 82891 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 81142 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 81431 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 77551 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 82816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 77581 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 78240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 78400 # Number of bytes read from this memory -system.physmem.bytes_read::total 640052 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 398656 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5632 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5599 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5418 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5496 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5436 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5531 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5426 # Number of bytes written to this memory -system.physmem.bytes_written::total 442654 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11008 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10834 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 10745 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 10897 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10996 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 10990 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10956 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 10927 # Number of read requests responded to by this memory -system.physmem.num_reads::total 87353 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 6229 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5632 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5599 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5418 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5496 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5436 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5531 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50227 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124260018 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 121638132 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 122071365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 116254945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 124147587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 116299917 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 117287809 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 117527662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 959487435 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 597616167 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 8184962 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 8442803 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 8393334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 8122001 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 8238929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 8148984 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 8291397 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 8133994 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 663572571 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 597616167 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 132444980 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 130080935 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130464699 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 124376946 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 132386516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 124448902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 125579206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 125661655 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1623060007 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu0 82626 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 79372 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 82635 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 78892 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 79911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 82560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 82806 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 80499 # Number of bytes read from this memory +system.physmem.bytes_read::total 649301 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 411072 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5529 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5498 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5527 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5416 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5415 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5350 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5500 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5539 # Number of bytes written to this memory +system.physmem.bytes_written::total 454846 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 10995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 10954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 10941 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 10978 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11115 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11118 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11112 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 10947 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88160 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6423 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5529 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5527 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5416 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5415 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5350 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5500 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5539 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50197 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 173747561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 166904986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 173766486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 165895633 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 168038406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 173608775 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 174126068 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 169274864 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1365362778 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 864410201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 11626489 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 11561301 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 11622283 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 11388870 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 11386767 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 11250084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 11565507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 11647517 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 956459020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 864410201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 185374050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 178466288 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 185388769 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 177284503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 179425173 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 184858859 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 185691575 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 180922381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2321821799 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.num_reads 100000 # number of read accesses completed -system.cpu0.num_writes 55151 # number of write accesses completed -system.cpu0.l1c.tags.replacements 22523 # number of replacements -system.cpu0.l1c.tags.tagsinuse 393.206747 # Cycle average of tags in use -system.cpu0.l1c.tags.total_refs 13668 # Total number of references to valid blocks. -system.cpu0.l1c.tags.sampled_refs 22921 # Sample count of references to valid blocks. -system.cpu0.l1c.tags.avg_refs 0.596309 # Average number of references to valid blocks. +system.cpu0.num_writes 55373 # number of write accesses completed +system.cpu0.l1c.tags.replacements 22370 # number of replacements +system.cpu0.l1c.tags.tagsinuse 390.859535 # Cycle average of tags in use +system.cpu0.l1c.tags.total_refs 13365 # Total number of references to valid blocks. +system.cpu0.l1c.tags.sampled_refs 22757 # Sample count of references to valid blocks. +system.cpu0.l1c.tags.avg_refs 0.587292 # Average number of references to valid blocks. system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.tags.occ_blocks::cpu0 393.206747 # Average occupied blocks per requestor -system.cpu0.l1c.tags.occ_percent::cpu0 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_percent::total 0.767982 # Average percentage of cache occupancy -system.cpu0.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::0 378 # Occupied blocks per task id -system.cpu0.l1c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id -system.cpu0.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu0.l1c.tags.tag_accesses 338453 # Number of tag accesses -system.cpu0.l1c.tags.data_accesses 338453 # Number of data accesses -system.cpu0.l1c.ReadReq_hits::cpu0 8785 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8785 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1208 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1208 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9993 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9993 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9993 # number of overall hits -system.cpu0.l1c.overall_hits::total 9993 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36702 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36702 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23741 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23741 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60443 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60443 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60443 # number of overall misses -system.cpu0.l1c.overall_misses::total 60443 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 964033198 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 878854454 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1842887652 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1842887652 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1842887652 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 45487 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24949 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 70436 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 70436 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 70436 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 70436 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.806868 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.951581 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.858127 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.858127 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.858127 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.858127 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 26266.503133 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 37018.426098 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30489.678739 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30489.678739 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1018774 # number of cycles access was blocked +system.cpu0.l1c.tags.occ_blocks::cpu0 390.859535 # Average occupied blocks per requestor +system.cpu0.l1c.tags.occ_percent::cpu0 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_percent::total 0.763398 # Average percentage of cache occupancy +system.cpu0.l1c.tags.occ_task_id_blocks::1024 387 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::0 381 # Occupied blocks per task id +system.cpu0.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu0.l1c.tags.occ_task_id_percent::1024 0.755859 # Percentage of cache occupancy per task id +system.cpu0.l1c.tags.tag_accesses 338979 # Number of tag accesses +system.cpu0.l1c.tags.data_accesses 338979 # Number of data accesses +system.cpu0.l1c.ReadReq_hits::cpu0 8642 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8642 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1137 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1137 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9779 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9779 # number of overall hits +system.cpu0.l1c.overall_hits::total 9779 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36791 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36791 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23910 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23910 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 60701 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 60701 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 60701 # number of overall misses +system.cpu0.l1c.overall_misses::total 60701 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 598271123 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 653921249 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1252192372 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1252192372 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1252192372 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 45433 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 25047 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 70480 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 70480 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 70480 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 70480 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.809786 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954605 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.861251 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.861251 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.861251 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.861251 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 16261.344432 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 27349.278503 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 20628.859030 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 20628.859030 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 775639 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63007 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66482 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 16.169219 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 11.666902 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9806 # number of writebacks -system.cpu0.l1c.writebacks::total 9806 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36702 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23741 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60443 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60443 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60443 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 885636434 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 828679478 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1714315912 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1714315912 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 700887059 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 1711925608 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2412812667 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806868 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.951581 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.858127 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.858127 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24130.467931 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34904.994651 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28362.521913 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28362.521913 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9788 # number of writebacks +system.cpu0.l1c.writebacks::total 9788 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36791 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23910 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 60701 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 60701 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 60701 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 540766367 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 617095733 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1157862100 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1157862100 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 641214054 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 990476120 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1631690174 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809786 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954605 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.861251 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.861251 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 14698.332935 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 25809.106357 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 19074.843907 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 19074.843907 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -197,119 +197,119 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99761 # number of read accesses completed -system.cpu1.num_writes 55328 # number of write accesses completed -system.cpu1.l1c.tags.replacements 22642 # number of replacements -system.cpu1.l1c.tags.tagsinuse 394.589952 # Cycle average of tags in use -system.cpu1.l1c.tags.total_refs 13581 # Total number of references to valid blocks. -system.cpu1.l1c.tags.sampled_refs 23033 # Sample count of references to valid blocks. -system.cpu1.l1c.tags.avg_refs 0.589632 # Average number of references to valid blocks. +system.cpu1.num_reads 99552 # number of read accesses completed +system.cpu1.num_writes 55312 # number of write accesses completed +system.cpu1.l1c.tags.replacements 22247 # number of replacements +system.cpu1.l1c.tags.tagsinuse 391.170580 # Cycle average of tags in use +system.cpu1.l1c.tags.total_refs 13534 # Total number of references to valid blocks. +system.cpu1.l1c.tags.sampled_refs 22643 # Sample count of references to valid blocks. +system.cpu1.l1c.tags.avg_refs 0.597712 # Average number of references to valid blocks. system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.tags.occ_blocks::cpu1 394.589952 # Average occupied blocks per requestor -system.cpu1.l1c.tags.occ_percent::cpu1 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_percent::total 0.770684 # Average percentage of cache occupancy -system.cpu1.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::0 376 # Occupied blocks per task id -system.cpu1.l1c.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id -system.cpu1.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id -system.cpu1.l1c.tags.tag_accesses 339246 # Number of tag accesses -system.cpu1.l1c.tags.data_accesses 339246 # Number of data accesses -system.cpu1.l1c.ReadReq_hits::cpu1 8788 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8788 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1121 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1121 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9909 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9909 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9909 # number of overall hits -system.cpu1.l1c.overall_hits::total 9909 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36866 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36866 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23806 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23806 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60672 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60672 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60672 # number of overall misses -system.cpu1.l1c.overall_misses::total 60672 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 969094954 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 879252966 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1848347920 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1848347920 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1848347920 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 45654 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24927 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 70581 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 70581 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 70581 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 70581 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.807509 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955029 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.859608 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.859608 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.859608 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.859608 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 26286.956925 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 36934.090817 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30464.595200 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30464.595200 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1015089 # number of cycles access was blocked +system.cpu1.l1c.tags.occ_blocks::cpu1 391.170580 # Average occupied blocks per requestor +system.cpu1.l1c.tags.occ_percent::cpu1 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_percent::total 0.764005 # Average percentage of cache occupancy +system.cpu1.l1c.tags.occ_task_id_blocks::1024 396 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::0 389 # Occupied blocks per task id +system.cpu1.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu1.l1c.tags.occ_task_id_percent::1024 0.773438 # Percentage of cache occupancy per task id +system.cpu1.l1c.tags.tag_accesses 338702 # Number of tag accesses +system.cpu1.l1c.tags.data_accesses 338702 # Number of data accesses +system.cpu1.l1c.ReadReq_hits::cpu1 8670 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8670 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1145 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1145 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9815 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9815 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9815 # number of overall hits +system.cpu1.l1c.overall_hits::total 9815 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36464 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36464 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 24184 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 24184 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 60648 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 60648 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 60648 # number of overall misses +system.cpu1.l1c.overall_misses::total 60648 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 591998971 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 660686123 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1252685094 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1252685094 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1252685094 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 45134 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 25329 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 70463 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 70463 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 70463 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 70463 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807905 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954795 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.860707 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.860707 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.860707 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.860707 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 16235.162654 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 27319.141705 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 20655.010784 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 20655.010784 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 776857 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62996 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66458 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 16.113547 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 11.689443 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9956 # number of writebacks -system.cpu1.l1c.writebacks::total 9956 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36866 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23806 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60672 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60672 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60672 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 890415084 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 828850208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1719265292 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1719265292 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 690509167 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 1720529946 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2411039113 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807509 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955029 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.859608 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.859608 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24152.744643 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34816.861632 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28337.046611 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28337.046611 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9776 # number of writebacks +system.cpu1.l1c.writebacks::total 9776 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36464 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 24184 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 60648 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 60648 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 60648 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 534984781 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 623377675 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1158362456 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1158362456 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 640712682 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 989782156 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1630494838 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807905 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954795 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.860707 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.860707 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 14671.587895 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 25776.450339 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 19099.763488 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 19099.763488 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -317,119 +317,119 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99243 # number of read accesses completed -system.cpu2.num_writes 55132 # number of write accesses completed -system.cpu2.l1c.tags.replacements 22573 # number of replacements -system.cpu2.l1c.tags.tagsinuse 394.676253 # Cycle average of tags in use -system.cpu2.l1c.tags.total_refs 13694 # Total number of references to valid blocks. -system.cpu2.l1c.tags.sampled_refs 22978 # Sample count of references to valid blocks. -system.cpu2.l1c.tags.avg_refs 0.595961 # Average number of references to valid blocks. +system.cpu2.num_reads 99606 # number of read accesses completed +system.cpu2.num_writes 55482 # number of write accesses completed +system.cpu2.l1c.tags.replacements 22450 # number of replacements +system.cpu2.l1c.tags.tagsinuse 391.646892 # Cycle average of tags in use +system.cpu2.l1c.tags.total_refs 13596 # Total number of references to valid blocks. +system.cpu2.l1c.tags.sampled_refs 22843 # Sample count of references to valid blocks. +system.cpu2.l1c.tags.avg_refs 0.595193 # Average number of references to valid blocks. system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.tags.occ_blocks::cpu2 394.676253 # Average occupied blocks per requestor -system.cpu2.l1c.tags.occ_percent::cpu2 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_percent::total 0.770852 # Average percentage of cache occupancy -system.cpu2.l1c.tags.occ_task_id_blocks::1024 405 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::0 383 # Occupied blocks per task id -system.cpu2.l1c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.cpu2.l1c.tags.occ_task_id_percent::1024 0.791016 # Percentage of cache occupancy per task id -system.cpu2.l1c.tags.tag_accesses 338823 # Number of tag accesses -system.cpu2.l1c.tags.data_accesses 338823 # Number of data accesses -system.cpu2.l1c.ReadReq_hits::cpu2 8940 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8940 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1180 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1180 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 10120 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 10120 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 10120 # number of overall hits -system.cpu2.l1c.overall_hits::total 10120 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36529 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36529 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23864 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23864 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60393 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60393 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60393 # number of overall misses -system.cpu2.l1c.overall_misses::total 60393 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 963156898 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 890183991 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1853340889 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1853340889 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1853340889 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45469 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 25044 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 70513 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 70513 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 70513 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 70513 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.803383 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.952883 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.856480 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.856480 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.856480 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.856480 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26366.911166 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 37302.379777 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30688.008362 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30688.008362 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1016015 # number of cycles access was blocked +system.cpu2.l1c.tags.occ_blocks::cpu2 391.646892 # Average occupied blocks per requestor +system.cpu2.l1c.tags.occ_percent::cpu2 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_percent::total 0.764935 # Average percentage of cache occupancy +system.cpu2.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::0 384 # Occupied blocks per task id +system.cpu2.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu2.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id +system.cpu2.l1c.tags.tag_accesses 338700 # Number of tag accesses +system.cpu2.l1c.tags.data_accesses 338700 # Number of data accesses +system.cpu2.l1c.ReadReq_hits::cpu2 8761 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8761 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1179 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1179 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9940 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9940 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9940 # number of overall hits +system.cpu2.l1c.overall_hits::total 9940 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36421 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36421 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 24109 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 24109 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 60530 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 60530 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 60530 # number of overall misses +system.cpu2.l1c.overall_misses::total 60530 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 592390101 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 664239589 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1256629690 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1256629690 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1256629690 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45182 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 25288 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 70470 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 70470 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 70470 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 70470 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806095 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953377 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.858947 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.858947 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.858947 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.858947 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 16265.069630 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 27551.519723 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 20760.444243 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 20760.444243 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 773028 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 62631 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66120 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 16.222238 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 11.691289 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9915 # number of writebacks -system.cpu2.l1c.writebacks::total 9915 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36529 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23864 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60393 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60393 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60393 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 885079158 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 839760037 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1724839195 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1724839195 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 685753748 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 1712116464 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2397870212 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.803383 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.952883 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.856480 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.856480 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 24229.493225 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 35189.408188 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 28560.250277 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 28560.250277 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9975 # number of writebacks +system.cpu2.l1c.writebacks::total 9975 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36421 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 24109 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 60530 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 60530 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 60530 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 535479769 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 627082203 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1162561972 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1162561972 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 634925616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 991782664 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1626708280 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806095 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953377 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.858947 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.858947 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 14702.500453 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 26010.295035 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 19206.376541 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 19206.376541 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -437,119 +437,119 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99256 # number of read accesses completed -system.cpu3.num_writes 54955 # number of write accesses completed -system.cpu3.l1c.tags.replacements 22662 # number of replacements -system.cpu3.l1c.tags.tagsinuse 394.489449 # Cycle average of tags in use -system.cpu3.l1c.tags.total_refs 13390 # Total number of references to valid blocks. -system.cpu3.l1c.tags.sampled_refs 23054 # Sample count of references to valid blocks. -system.cpu3.l1c.tags.avg_refs 0.580810 # Average number of references to valid blocks. +system.cpu3.num_reads 99549 # number of read accesses completed +system.cpu3.num_writes 55104 # number of write accesses completed +system.cpu3.l1c.tags.replacements 22310 # number of replacements +system.cpu3.l1c.tags.tagsinuse 391.032656 # Cycle average of tags in use +system.cpu3.l1c.tags.total_refs 13513 # Total number of references to valid blocks. +system.cpu3.l1c.tags.sampled_refs 22709 # Sample count of references to valid blocks. +system.cpu3.l1c.tags.avg_refs 0.595050 # Average number of references to valid blocks. system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.tags.occ_blocks::cpu3 394.489449 # Average occupied blocks per requestor -system.cpu3.l1c.tags.occ_percent::cpu3 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_percent::total 0.770487 # Average percentage of cache occupancy -system.cpu3.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu3.l1c.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id -system.cpu3.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id -system.cpu3.l1c.tags.tag_accesses 337690 # Number of tag accesses -system.cpu3.l1c.tags.data_accesses 337690 # Number of data accesses -system.cpu3.l1c.ReadReq_hits::cpu3 8629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1137 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1137 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9766 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9766 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9766 # number of overall hits -system.cpu3.l1c.overall_hits::total 9766 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36563 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36563 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23903 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23903 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60466 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60466 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60466 # number of overall misses -system.cpu3.l1c.overall_misses::total 60466 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 960736157 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 887839747 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1848575904 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1848575904 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1848575904 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 45192 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 25040 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 70232 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 70232 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 70232 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 70232 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809059 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954593 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.860947 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.860947 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.860947 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.860947 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 26276.185133 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 37143.444212 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30572.154665 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30572.154665 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1022448 # number of cycles access was blocked +system.cpu3.l1c.tags.occ_blocks::cpu3 391.032656 # Average occupied blocks per requestor +system.cpu3.l1c.tags.occ_percent::cpu3 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_percent::total 0.763736 # Average percentage of cache occupancy +system.cpu3.l1c.tags.occ_task_id_blocks::1024 399 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::0 393 # Occupied blocks per task id +system.cpu3.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu3.l1c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id +system.cpu3.l1c.tags.tag_accesses 338332 # Number of tag accesses +system.cpu3.l1c.tags.data_accesses 338332 # Number of data accesses +system.cpu3.l1c.ReadReq_hits::cpu3 8654 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8654 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1182 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1182 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9836 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9836 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9836 # number of overall hits +system.cpu3.l1c.overall_hits::total 9836 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 36530 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 36530 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 24013 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 24013 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 60543 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 60543 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 60543 # number of overall misses +system.cpu3.l1c.overall_misses::total 60543 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 590001438 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 660132360 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1250133798 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1250133798 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1250133798 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 45184 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 25195 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 70379 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 70379 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 70379 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 70379 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.808472 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.953086 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.860242 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.860242 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.860242 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.860242 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 16151.148043 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 27490.624245 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 20648.692632 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 20648.692632 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 774871 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63227 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66332 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 16.171066 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 11.681707 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9928 # number of writebacks -system.cpu3.l1c.writebacks::total 9928 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36563 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23903 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60466 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60466 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60466 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 882571457 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 837312821 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1719884278 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1719884278 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 700068981 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 1667398980 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2367467961 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809059 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954593 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.860947 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.860947 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24138.376419 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 35029.612224 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28443.824265 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28443.824265 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9907 # number of writebacks +system.cpu3.l1c.writebacks::total 9907 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 36530 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 24013 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 60543 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 60543 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 60543 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 532881722 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 623079094 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1155960816 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1155960816 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 642783574 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 972713175 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1615496749 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.808472 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.953086 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.860242 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.860242 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 14587.509499 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 25947.573981 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 19093.219959 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 19093.219959 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -557,119 +557,119 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99292 # number of read accesses completed -system.cpu4.num_writes 54781 # number of write accesses completed -system.cpu4.l1c.tags.replacements 22192 # number of replacements -system.cpu4.l1c.tags.tagsinuse 393.392100 # Cycle average of tags in use -system.cpu4.l1c.tags.total_refs 13471 # Total number of references to valid blocks. -system.cpu4.l1c.tags.sampled_refs 22589 # Sample count of references to valid blocks. -system.cpu4.l1c.tags.avg_refs 0.596352 # Average number of references to valid blocks. +system.cpu4.num_reads 99755 # number of read accesses completed +system.cpu4.num_writes 55257 # number of write accesses completed +system.cpu4.l1c.tags.replacements 22302 # number of replacements +system.cpu4.l1c.tags.tagsinuse 391.084224 # Cycle average of tags in use +system.cpu4.l1c.tags.total_refs 13540 # Total number of references to valid blocks. +system.cpu4.l1c.tags.sampled_refs 22693 # Sample count of references to valid blocks. +system.cpu4.l1c.tags.avg_refs 0.596660 # Average number of references to valid blocks. system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.tags.occ_blocks::cpu4 393.392100 # Average occupied blocks per requestor -system.cpu4.l1c.tags.occ_percent::cpu4 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_percent::total 0.768344 # Average percentage of cache occupancy -system.cpu4.l1c.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::0 369 # Occupied blocks per task id -system.cpu4.l1c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.cpu4.l1c.tags.occ_task_id_percent::1024 0.775391 # Percentage of cache occupancy per task id -system.cpu4.l1c.tags.tag_accesses 336466 # Number of tag accesses -system.cpu4.l1c.tags.data_accesses 336466 # Number of data accesses -system.cpu4.l1c.ReadReq_hits::cpu4 8698 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8698 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1159 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1159 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9857 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9857 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9857 # number of overall hits -system.cpu4.l1c.overall_hits::total 9857 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36438 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36438 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23701 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23701 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60139 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60139 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60139 # number of overall misses -system.cpu4.l1c.overall_misses::total 60139 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 959750489 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883613878 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1843364367 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1843364367 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1843364367 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 45136 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24860 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 69996 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 69996 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 69996 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 69996 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807294 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953379 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859178 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859178 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859178 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859178 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 26339.274631 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 37281.712924 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30651.729610 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30651.729610 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1023771 # number of cycles access was blocked +system.cpu4.l1c.tags.occ_blocks::cpu4 391.084224 # Average occupied blocks per requestor +system.cpu4.l1c.tags.occ_percent::cpu4 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_percent::total 0.763836 # Average percentage of cache occupancy +system.cpu4.l1c.tags.occ_task_id_blocks::1024 391 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id +system.cpu4.l1c.tags.age_task_id_blocks_1024::1 9 # Occupied blocks per task id +system.cpu4.l1c.tags.occ_task_id_percent::1024 0.763672 # Percentage of cache occupancy per task id +system.cpu4.l1c.tags.tag_accesses 338305 # Number of tag accesses +system.cpu4.l1c.tags.data_accesses 338305 # Number of data accesses +system.cpu4.l1c.ReadReq_hits::cpu4 8852 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8852 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1084 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1084 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9936 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9936 # number of overall hits +system.cpu4.l1c.overall_hits::total 9936 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36600 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36600 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23847 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23847 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 60447 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 60447 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 60447 # number of overall misses +system.cpu4.l1c.overall_misses::total 60447 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 590829220 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 656323200 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1247152420 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1247152420 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1247152420 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45452 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24931 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 70383 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 70383 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 70383 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 70383 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805245 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956520 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858830 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858830 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858830 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858830 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 16142.874863 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 27522.254372 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 20632.164045 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 20632.164045 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 780817 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62867 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66569 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 16.284712 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 11.729439 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9698 # number of writebacks -system.cpu4.l1c.writebacks::total 9698 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36438 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23701 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60139 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60139 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60139 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 881959493 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 833428166 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1715387659 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1715387659 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 703007482 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 1705988496 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2408995978 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807294 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953379 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859178 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859178 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24204.388084 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 35164.261677 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 28523.714378 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 28523.714378 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9856 # number of writebacks +system.cpu4.l1c.writebacks::total 9856 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36600 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23847 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 60447 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 60447 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 60447 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 533635904 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 619552810 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1153188714 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1153188714 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 651255905 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 973411350 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1624667255 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805245 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956520 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858830 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858830 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 14580.215956 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 25980.324988 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 19077.683160 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 19077.683160 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -677,119 +677,119 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 99672 # number of read accesses completed -system.cpu5.num_writes 54824 # number of write accesses completed -system.cpu5.l1c.tags.replacements 22459 # number of replacements -system.cpu5.l1c.tags.tagsinuse 393.671106 # Cycle average of tags in use -system.cpu5.l1c.tags.total_refs 13533 # Total number of references to valid blocks. -system.cpu5.l1c.tags.sampled_refs 22853 # Sample count of references to valid blocks. -system.cpu5.l1c.tags.avg_refs 0.592176 # Average number of references to valid blocks. +system.cpu5.num_reads 99495 # number of read accesses completed +system.cpu5.num_writes 54912 # number of write accesses completed +system.cpu5.l1c.tags.replacements 22132 # number of replacements +system.cpu5.l1c.tags.tagsinuse 389.508075 # Cycle average of tags in use +system.cpu5.l1c.tags.total_refs 13369 # Total number of references to valid blocks. +system.cpu5.l1c.tags.sampled_refs 22545 # Sample count of references to valid blocks. +system.cpu5.l1c.tags.avg_refs 0.592992 # Average number of references to valid blocks. system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.tags.occ_blocks::cpu5 393.671106 # Average occupied blocks per requestor -system.cpu5.l1c.tags.occ_percent::cpu5 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_percent::total 0.768889 # Average percentage of cache occupancy -system.cpu5.l1c.tags.occ_task_id_blocks::1024 394 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::0 371 # Occupied blocks per task id -system.cpu5.l1c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id -system.cpu5.l1c.tags.occ_task_id_percent::1024 0.769531 # Percentage of cache occupancy per task id -system.cpu5.l1c.tags.tag_accesses 337969 # Number of tag accesses -system.cpu5.l1c.tags.data_accesses 337969 # Number of data accesses -system.cpu5.l1c.ReadReq_hits::cpu5 8696 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8696 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1170 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1170 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9866 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9866 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9866 # number of overall hits -system.cpu5.l1c.overall_hits::total 9866 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36658 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36658 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23786 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23786 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60444 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60444 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60444 # number of overall misses -system.cpu5.l1c.overall_misses::total 60444 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 958216057 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 885896912 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1844112969 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1844112969 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1844112969 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 45354 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24956 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 70310 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 70310 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 70310 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 70310 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.808264 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953117 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859679 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859679 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859679 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859679 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26139.343581 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 37244.467838 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30509.446248 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30509.446248 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1026604 # number of cycles access was blocked +system.cpu5.l1c.tags.occ_blocks::cpu5 389.508075 # Average occupied blocks per requestor +system.cpu5.l1c.tags.occ_percent::cpu5 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_percent::total 0.760758 # Average percentage of cache occupancy +system.cpu5.l1c.tags.occ_task_id_blocks::1024 413 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::0 409 # Occupied blocks per task id +system.cpu5.l1c.tags.age_task_id_blocks_1024::1 4 # Occupied blocks per task id +system.cpu5.l1c.tags.occ_task_id_percent::1024 0.806641 # Percentage of cache occupancy per task id +system.cpu5.l1c.tags.tag_accesses 337023 # Number of tag accesses +system.cpu5.l1c.tags.data_accesses 337023 # Number of data accesses +system.cpu5.l1c.ReadReq_hits::cpu5 8615 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8615 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1193 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1193 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9808 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9808 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9808 # number of overall hits +system.cpu5.l1c.overall_hits::total 9808 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36426 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36426 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23853 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23853 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 60279 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 60279 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 60279 # number of overall misses +system.cpu5.l1c.overall_misses::total 60279 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 593740716 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 656837719 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1250578435 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1250578435 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1250578435 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 45041 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 25046 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 70087 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 70087 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 70087 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 70087 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.808730 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.952368 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.860060 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.860060 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.860060 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.860060 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 16299.915335 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 27536.901815 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 20746.502679 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 20746.502679 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 781949 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63359 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66475 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 16.202970 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 11.763054 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9812 # number of writebacks -system.cpu5.l1c.writebacks::total 9812 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36658 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23786 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60444 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60444 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60444 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 879872261 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 835586106 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1715458367 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1715458367 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 707107291 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 1680181552 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2387288843 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808264 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953117 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859679 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859679 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 24002.189454 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 35129.324224 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28380.953726 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28380.953726 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9742 # number of writebacks +system.cpu5.l1c.writebacks::total 9742 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36426 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23853 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 60279 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 60279 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 60279 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 536794980 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 620108209 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1156903189 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1156903189 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 648821919 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 955346733 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1604168652 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.808730 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952368 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.860060 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.860060 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 14736.588700 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 25997.074121 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 19192.474809 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 19192.474809 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -797,119 +797,119 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99511 # number of read accesses completed -system.cpu6.num_writes 54977 # number of write accesses completed -system.cpu6.l1c.tags.replacements 22541 # number of replacements -system.cpu6.l1c.tags.tagsinuse 393.448229 # Cycle average of tags in use -system.cpu6.l1c.tags.total_refs 13464 # Total number of references to valid blocks. -system.cpu6.l1c.tags.sampled_refs 22939 # Sample count of references to valid blocks. -system.cpu6.l1c.tags.avg_refs 0.586948 # Average number of references to valid blocks. +system.cpu6.num_reads 99492 # number of read accesses completed +system.cpu6.num_writes 55188 # number of write accesses completed +system.cpu6.l1c.tags.replacements 22041 # number of replacements +system.cpu6.l1c.tags.tagsinuse 390.749630 # Cycle average of tags in use +system.cpu6.l1c.tags.total_refs 13460 # Total number of references to valid blocks. +system.cpu6.l1c.tags.sampled_refs 22445 # Sample count of references to valid blocks. +system.cpu6.l1c.tags.avg_refs 0.599688 # Average number of references to valid blocks. system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.tags.occ_blocks::cpu6 393.448229 # Average occupied blocks per requestor -system.cpu6.l1c.tags.occ_percent::cpu6 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_percent::total 0.768454 # Average percentage of cache occupancy -system.cpu6.l1c.tags.occ_task_id_blocks::1024 398 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::0 372 # Occupied blocks per task id -system.cpu6.l1c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id -system.cpu6.l1c.tags.occ_task_id_percent::1024 0.777344 # Percentage of cache occupancy per task id -system.cpu6.l1c.tags.tag_accesses 337704 # Number of tag accesses -system.cpu6.l1c.tags.data_accesses 337704 # Number of data accesses -system.cpu6.l1c.ReadReq_hits::cpu6 8641 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8641 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1220 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1220 # number of WriteReq hits +system.cpu6.l1c.tags.occ_blocks::cpu6 390.749630 # Average occupied blocks per requestor +system.cpu6.l1c.tags.occ_percent::cpu6 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_percent::total 0.763183 # Average percentage of cache occupancy +system.cpu6.l1c.tags.occ_task_id_blocks::1024 404 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu6.l1c.tags.age_task_id_blocks_1024::1 7 # Occupied blocks per task id +system.cpu6.l1c.tags.occ_task_id_percent::1024 0.789062 # Percentage of cache occupancy per task id +system.cpu6.l1c.tags.tag_accesses 337459 # Number of tag accesses +system.cpu6.l1c.tags.data_accesses 337459 # Number of data accesses +system.cpu6.l1c.ReadReq_hits::cpu6 8703 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1158 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1158 # number of WriteReq hits system.cpu6.l1c.demand_hits::cpu6 9861 # number of demand (read+write) hits system.cpu6.l1c.demand_hits::total 9861 # number of demand (read+write) hits system.cpu6.l1c.overall_hits::cpu6 9861 # number of overall hits system.cpu6.l1c.overall_hits::total 9861 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36671 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36671 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23713 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23713 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60384 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60384 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60384 # number of overall misses -system.cpu6.l1c.overall_misses::total 60384 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 960694665 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 879536054 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1840230719 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1840230719 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1840230719 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 45312 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24933 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 70245 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 70245 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 70245 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 70245 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.809300 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.951069 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.859620 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.859620 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26197.667503 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 37090.880698 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30475.468982 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30475.468982 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1019991 # number of cycles access was blocked +system.cpu6.l1c.ReadReq_misses::cpu6 36430 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36430 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23907 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23907 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 60337 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 60337 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 60337 # number of overall misses +system.cpu6.l1c.overall_misses::total 60337 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 592106528 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 650271582 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1242378110 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1242378110 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1242378110 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45133 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 25065 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 70198 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 70198 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 70198 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 70198 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.807170 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953800 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.859526 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.859526 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.859526 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.859526 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 16253.267307 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 27200.049442 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 20590.651010 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 20590.651010 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 773385 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62969 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66167 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 16.198304 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 11.688379 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9771 # number of writebacks -system.cpu6.l1c.writebacks::total 9771 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36671 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23713 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60384 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60384 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60384 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 882425777 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 829351266 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1711777043 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1711777043 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702299487 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 1717296024 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2419595511 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.809300 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.951069 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24063.313708 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34974.539957 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 28348.188974 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 28348.188974 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9775 # number of writebacks +system.cpu6.l1c.writebacks::total 9775 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36430 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23907 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 60337 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 60337 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 60337 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 535158836 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 613445646 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1148604482 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1148604482 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 648116847 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 997038722 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1645155569 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.807170 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953800 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.859526 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.859526 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 14690.058633 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 25659.666458 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 19036.486435 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 19036.486435 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -917,119 +917,119 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98836 # number of read accesses completed -system.cpu7.num_writes 54806 # number of write accesses completed -system.cpu7.l1c.tags.replacements 22352 # number of replacements -system.cpu7.l1c.tags.tagsinuse 393.572142 # Cycle average of tags in use -system.cpu7.l1c.tags.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.tags.sampled_refs 22745 # Sample count of references to valid blocks. -system.cpu7.l1c.tags.avg_refs 0.589140 # Average number of references to valid blocks. +system.cpu7.num_reads 99953 # number of read accesses completed +system.cpu7.num_writes 55743 # number of write accesses completed +system.cpu7.l1c.tags.replacements 22636 # number of replacements +system.cpu7.l1c.tags.tagsinuse 393.668569 # Cycle average of tags in use +system.cpu7.l1c.tags.total_refs 13591 # Total number of references to valid blocks. +system.cpu7.l1c.tags.sampled_refs 23039 # Sample count of references to valid blocks. +system.cpu7.l1c.tags.avg_refs 0.589913 # Average number of references to valid blocks. system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.tags.occ_blocks::cpu7 393.572142 # Average occupied blocks per requestor -system.cpu7.l1c.tags.occ_percent::cpu7 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_percent::total 0.768696 # Average percentage of cache occupancy -system.cpu7.l1c.tags.occ_task_id_blocks::1024 393 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::0 363 # Occupied blocks per task id -system.cpu7.l1c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.cpu7.l1c.tags.occ_task_id_percent::1024 0.767578 # Percentage of cache occupancy per task id -system.cpu7.l1c.tags.tag_accesses 336509 # Number of tag accesses -system.cpu7.l1c.tags.data_accesses 336509 # Number of data accesses -system.cpu7.l1c.ReadReq_hits::cpu7 8699 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8699 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1106 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1106 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9805 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9805 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9805 # number of overall hits -system.cpu7.l1c.overall_hits::total 9805 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36228 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36228 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23958 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23958 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60186 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60186 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60186 # number of overall misses -system.cpu7.l1c.overall_misses::total 60186 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 952764751 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 890612165 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1843376916 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1843376916 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1843376916 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44927 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 25064 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69991 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69991 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69991 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69991 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.806375 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.955873 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859911 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859911 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859911 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859911 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 26299.126394 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37173.894524 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30628.001794 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30628.001794 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1021665 # number of cycles access was blocked +system.cpu7.l1c.tags.occ_blocks::cpu7 393.668569 # Average occupied blocks per requestor +system.cpu7.l1c.tags.occ_percent::cpu7 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_percent::total 0.768884 # Average percentage of cache occupancy +system.cpu7.l1c.tags.occ_task_id_blocks::1024 403 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::0 397 # Occupied blocks per task id +system.cpu7.l1c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.cpu7.l1c.tags.occ_task_id_percent::1024 0.787109 # Percentage of cache occupancy per task id +system.cpu7.l1c.tags.tag_accesses 340053 # Number of tag accesses +system.cpu7.l1c.tags.data_accesses 340053 # Number of data accesses +system.cpu7.l1c.ReadReq_hits::cpu7 8802 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8802 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1188 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1188 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9990 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9990 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9990 # number of overall hits +system.cpu7.l1c.overall_hits::total 9990 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36601 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36601 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 24152 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 24152 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 60753 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 60753 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 60753 # number of overall misses +system.cpu7.l1c.overall_misses::total 60753 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 595212008 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 656742976 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1251954984 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1251954984 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1251954984 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45403 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 25340 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 70743 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 70743 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 70743 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 70743 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.806136 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953118 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858785 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858785 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858785 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858785 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 16262.178848 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 27192.074197 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 20607.294850 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 20607.294850 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 772653 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 62785 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66243 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 16.272438 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 11.663919 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9931 # number of writebacks -system.cpu7.l1c.writebacks::total 9931 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36228 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23958 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60186 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60186 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60186 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 875407713 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 839967251 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1715374964 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1715374964 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 702238586 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 1694350083 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2396588669 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806375 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.955873 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859911 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859911 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24163.843243 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 35059.990442 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 28501.228924 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 28501.228924 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9979 # number of writebacks +system.cpu7.l1c.writebacks::total 9979 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36601 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 24152 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 60753 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 60753 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 60753 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 538040158 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 619565494 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1157605652 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1157605652 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 639132078 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 986824111 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1625956189 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.806136 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953118 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858785 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858785 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 14700.149122 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 25652.761428 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 19054.296117 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 19054.296117 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency @@ -1037,567 +1037,566 @@ system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 13277 # number of replacements -system.l2c.tags.tagsinuse 783.059977 # Cycle average of tags in use -system.l2c.tags.total_refs 151520 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 14056 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 10.779738 # Average number of references to valid blocks. +system.l2c.tags.replacements 13510 # number of replacements +system.l2c.tags.tagsinuse 783.849989 # Cycle average of tags in use +system.l2c.tags.total_refs 151949 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 14294 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 10.630264 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 729.095705 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0 7.040995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1 7.066153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2 6.783419 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3 7.143521 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu4 6.879919 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu5 6.083313 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu6 6.867349 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu7 6.099602 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.712008 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0 0.006876 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1 0.006901 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2 0.006624 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3 0.006976 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu4 0.006719 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu5 0.005941 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu6 0.006706 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu7 0.005957 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.764707 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1024 779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 598 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 181 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1024 0.760742 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 1976800 # Number of tag accesses -system.l2c.tags.data_accesses 1976800 # Number of data accesses -system.l2c.ReadReq_hits::cpu0 10744 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10861 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10670 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10810 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10859 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10920 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10735 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86470 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76237 # number of Writeback hits -system.l2c.Writeback_hits::total 76237 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 344 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 346 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 369 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 358 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 342 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 326 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 336 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 356 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2777 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1915 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1982 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 1977 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1900 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1958 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 1937 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 1931 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 15500 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12853 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12710 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12817 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12857 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12666 # number of demand (read+write) hits -system.l2c.demand_hits::total 101970 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12644 # number of overall hits -system.l2c.overall_hits::cpu1 12776 # number of overall hits -system.l2c.overall_hits::cpu2 12853 # number of overall hits -system.l2c.overall_hits::cpu3 12647 # number of overall hits -system.l2c.overall_hits::cpu4 12710 # number of overall hits -system.l2c.overall_hits::cpu5 12817 # number of overall hits -system.l2c.overall_hits::cpu6 12857 # number of overall hits -system.l2c.overall_hits::cpu7 12666 # number of overall hits -system.l2c.overall_hits::total 101970 # number of overall hits -system.l2c.ReadReq_misses::cpu0 765 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 729 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 708 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 735 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 684 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 695 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 674 # number of ReadReq misses -system.l2c.ReadReq_misses::total 5719 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1992 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1980 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1951 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1975 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1990 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 2015 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15885 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4350 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4268 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4431 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4387 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4476 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 35010 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4997 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5100 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5076 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5166 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5071 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5054 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5150 # number of demand (read+write) misses -system.l2c.demand_misses::total 40729 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5115 # number of overall misses -system.l2c.overall_misses::cpu1 4997 # number of overall misses -system.l2c.overall_misses::cpu2 5100 # number of overall misses -system.l2c.overall_misses::cpu3 5076 # number of overall misses -system.l2c.overall_misses::cpu4 5166 # number of overall misses -system.l2c.overall_misses::cpu5 5071 # number of overall misses -system.l2c.overall_misses::cpu6 5054 # number of overall misses -system.l2c.overall_misses::cpu7 5150 # number of overall misses -system.l2c.overall_misses::total 40729 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 46620930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 44960918 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 44432427 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 43382432 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 44487433 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 41294425 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 42419930 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 41189936 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 348788431 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 57711996 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 58106496 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 57659498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57666495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 55433497 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 57841495 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 59041000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 57235498 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 460695975 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 234061451 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 229252453 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 235963436 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 234901447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 238651447 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 236178452 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 234894949 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 241135947 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1885039582 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 280682381 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 274213371 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 280395863 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 278283879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 283138880 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 277472877 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 277314879 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 282325883 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2233828013 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 280682381 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 274213371 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 280395863 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 278283879 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92189 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76237 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76237 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2336 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2320 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2370 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2317 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2351 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2326 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18662 # 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number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17723 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17876 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17888 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17911 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17816 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142699 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17759 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17773 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17953 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17723 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17876 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17888 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17911 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17816 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142699 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.066470 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.062899 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.062845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.062225 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.063664 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.059257 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.059836 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.059076 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.062036 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852740 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.851247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.840948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.848945 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852395 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.859240 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.857082 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.846948 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.851195 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.696000 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.690280 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.688021 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.688416 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.699889 # 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average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 60527.119728 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 60371.966374 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 61035.870504 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 61112.664688 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60987.660605 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28971.885542 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 29346.715152 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 29553.817529 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 28661.279821 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28067.593418 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29066.077889 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 29300.744417 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29053.552284 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 29001.949953 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53807.230115 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53714.257966 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53983.856326 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53777.803800 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53859.500564 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 53835.981764 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53887.347786 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53873.089142 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53842.890089 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 54874.365787 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54875.599560 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54979.580980 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54823.459220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54808.145567 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 54717.585683 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54870.375742 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54820.559806 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54846.129613 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 11130 # number of cycles access was blocked +system.l2c.tags.occ_blocks::writebacks 725.717756 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0 7.606207 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1 7.042760 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2 7.314362 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3 7.280142 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu4 6.903512 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu5 7.337678 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu6 7.211948 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu7 7.435623 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.708709 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0 0.007428 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1 0.006878 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2 0.007143 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3 0.007110 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu4 0.006742 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu5 0.007166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu6 0.007043 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu7 0.007261 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.765479 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1024 784 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 680 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 1986932 # Number of tag accesses +system.l2c.tags.data_accesses 1986932 # Number of data accesses +system.l2c.ReadReq_hits::cpu0 10772 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10720 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10796 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10828 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10876 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10784 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10741 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86242 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77037 # number of Writeback hits +system.l2c.Writeback_hits::total 77037 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 331 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 373 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 353 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 321 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 363 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 366 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2816 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2031 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1999 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1974 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2000 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1993 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1967 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1970 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15914 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12803 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12719 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12770 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12828 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12869 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12711 # number of demand (read+write) hits +system.l2c.demand_hits::total 102156 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12803 # number of overall hits +system.l2c.overall_hits::cpu1 12719 # number of overall hits +system.l2c.overall_hits::cpu2 12770 # number of overall hits +system.l2c.overall_hits::cpu3 12828 # number of overall hits +system.l2c.overall_hits::cpu4 12869 # number of overall hits +system.l2c.overall_hits::cpu5 12764 # number of overall hits +system.l2c.overall_hits::cpu6 12692 # number of overall hits +system.l2c.overall_hits::cpu7 12711 # number of overall hits +system.l2c.overall_hits::total 102156 # number of overall hits +system.l2c.ReadReq_misses::cpu0 731 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 674 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 694 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 702 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 746 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 722 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 727 # number of ReadReq misses +system.l2c.ReadReq_misses::total 5742 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1949 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 2075 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 2001 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2024 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1976 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1982 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1991 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1901 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15899 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4324 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4508 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4451 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4429 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4229 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4405 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 35131 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5104 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 4998 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5254 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5106 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5153 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5175 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 4951 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5132 # number of demand (read+write) misses +system.l2c.demand_misses::total 40873 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5104 # number of overall misses +system.l2c.overall_misses::cpu1 4998 # number of overall misses +system.l2c.overall_misses::cpu2 5254 # number of overall misses +system.l2c.overall_misses::cpu3 5106 # number of overall misses +system.l2c.overall_misses::cpu4 5153 # number of overall misses +system.l2c.overall_misses::cpu5 5175 # number of overall misses +system.l2c.overall_misses::cpu6 4951 # number of overall misses +system.l2c.overall_misses::cpu7 5132 # number of overall misses +system.l2c.overall_misses::total 40873 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 45095926 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 41549422 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 46449929 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 42922928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 43252423 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 45919927 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 44260438 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 44979437 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 354430430 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 56379995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 59258495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 58685995 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 56511495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 59771492 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 56753497 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 61514994 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54850495 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 463726458 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 240858936 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 238452262 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 247966448 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 242840437 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 244973443 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 243557270 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 233129438 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 242077945 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1933856179 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 285954862 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 280001684 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 294416377 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 285763365 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288225866 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 289477197 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 277389876 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 287057382 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2288286609 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 285954862 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 280001684 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 294416377 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 285763365 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288225866 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 289477197 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 277389876 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 287057382 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2288286609 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11503 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11394 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11542 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11578 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11530 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11447 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91984 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77037 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77037 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2280 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2448 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2364 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2377 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2345 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2337 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2267 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18715 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6404 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6482 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6444 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6409 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6196 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6375 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 51045 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17907 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17717 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18024 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17934 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18022 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17939 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17643 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17843 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143029 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17907 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17717 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18024 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17934 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18022 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17939 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17643 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17843 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143029 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063549 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.059154 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.064634 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.060233 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.060632 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.064701 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.063073 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063394 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.062424 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.854825 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.847631 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.846447 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851493 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.860253 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.845203 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.851947 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.838553 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849532 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.682854 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.683853 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.695464 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.688085 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.690720 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691059 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.682537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.690980 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.688236 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.285028 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282102 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.291500 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.284711 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.288478 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.280621 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.287620 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285767 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.285028 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282102 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.291500 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.284711 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.285928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.288478 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.280621 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.287620 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285767 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 61690.733242 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 61646.026706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 62265.320375 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 61848.599424 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 61613.138177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 61554.861930 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 61302.545706 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 61869.927098 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 61725.954371 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28927.652642 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28558.310843 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29328.333333 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27920.699111 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 30248.730769 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28634.458628 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 30896.531391 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28853.495529 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 29167.020442 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 55078.649897 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 55146.221554 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 55005.866903 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 55040.896872 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 55037.843855 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 54991.481147 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 55126.374557 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 54955.265607 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 55047.000626 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 56025.639107 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 56022.745898 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 56036.615341 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 55966.189777 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 55933.604890 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 55937.622609 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 56027.040194 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 55934.797740 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 55985.286350 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 17581 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1567 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 3250 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.102744 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5.409538 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 6229 # number of writebacks -system.l2c.writebacks::total 6229 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 11 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 6423 # number of writebacks +system.l2c.writebacks::total 6423 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu3 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 11 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 1 # number of UpgradeReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 11 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 4 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 1 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 21 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 39 # number of ReadExReq MSHR hits system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 13 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 15 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 4 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 20 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 19 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 11 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 13 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 15 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 4 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 20 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 19 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 11 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 758 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 722 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 718 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 704 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 730 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 673 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 692 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 669 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 5666 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1992 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1980 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1951 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2012 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1974 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1990 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 2015 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1969 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15883 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4346 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4265 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4369 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4364 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4383 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4358 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4474 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34989 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4987 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5087 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5068 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5160 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5056 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5050 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5143 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40655 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4987 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5087 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5068 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5160 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5056 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5050 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5143 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40655 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 37179930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 35966920 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 35314428 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 34763932 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 35492434 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 32731425 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 33928930 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 32969437 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 278347436 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 81798995 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 81126494 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80135996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 82599489 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 81068996 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 81609993 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 82618495 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80871496 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 651829954 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 181281952 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 177509453 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 183001436 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 181913947 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 184978447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 182997452 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 182077949 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 186899447 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1460660083 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218461882 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 213476373 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 218315864 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 216677879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 220470881 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 215728877 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 216006879 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 219868884 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1739007519 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218461882 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 213476373 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 218315864 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 216677879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 220470881 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 215728877 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 216006879 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 219868884 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1739007519 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 407707447 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 401123946 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 397019445 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 405812955 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 407128948 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 410535950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408564954 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406637950 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3244531595 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 230392811 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 237768794 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 237208468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 229246463 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 232269476 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230268468 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 234242974 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227836970 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1859234424 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 638100258 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 638892740 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 634227913 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 635059418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 639398424 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 640804418 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 642807928 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 634474920 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5103766019 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.065861 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.062295 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.061897 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.061874 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.063231 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058304 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059578 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.058638 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.061461 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852740 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.851247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.840948 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.848945 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.851964 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.859240 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.857082 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.846518 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.851088 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.695360 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.689795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.687707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687786 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.699731 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690780 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.692186 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.698299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.692714 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284900 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.287404 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.280594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.283351 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.285956 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.288655 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.282648 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281950 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.288673 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284900 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49050.039578 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49815.678670 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 49184.440111 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49380.585227 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48619.772603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48635.104012 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49030.245665 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49281.669656 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 49125.915284 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41063.752510 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40972.976768 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41074.318811 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41053.423956 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41068.387031 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41010.046734 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41001.734491 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41072.369731 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41039.473273 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41712.368155 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41620.035873 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41886.343786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41685.139093 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41755.857111 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41751.643167 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41780.162689 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41774.574654 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41746.265483 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42802.092868 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42806.571686 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42916.426971 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42754.119771 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42726.914922 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42667.894976 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42773.639406 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42751.095470 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42774.751420 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 100 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 725 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 661 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 738 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 690 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 692 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 741 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 711 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 723 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5681 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1949 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 2074 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2001 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2023 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1976 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1982 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1991 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1901 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15897 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4368 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4505 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4406 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4442 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4423 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4402 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 35092 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5093 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 4978 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5243 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5096 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5134 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5164 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 4940 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5125 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40773 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5093 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 4978 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5243 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5096 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5134 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5164 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 4940 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5125 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40773 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 36140918 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 33131910 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37333917 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 34463914 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 34507911 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 36862423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 35293427 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 36098935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 283833355 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 82188451 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 87682473 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 84603955 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 85652462 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 83560954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 83969963 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 84367474 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 80329284 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 672355016 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 188025870 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 186115345 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 193429372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 189404867 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 191140359 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 189945201 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 182082372 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 188836863 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1508980249 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 224166788 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 219247255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 230763289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 223868781 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 225648270 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 226807624 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 217375799 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 224935798 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1792813604 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 224166788 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 219247255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 230763289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 223868781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 225648270 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 226807624 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 217375799 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 224935798 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1792813604 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 419997297 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 420394389 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 416554764 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 421667758 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 426680271 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 424776767 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 425015068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419160275 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3374246589 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 245735705 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 245037892 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 243130891 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 240328902 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 241689545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 236933897 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 244635896 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 245230718 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1942723446 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 665733002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 665432281 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 659685655 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 661996660 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 668369816 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 661710664 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 669650964 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 664390993 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5316970035 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.063027 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.058013 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.063940 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.059885 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.059769 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.064267 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.062112 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063045 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.061761 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.854825 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.847222 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.846447 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851073 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.860253 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.845203 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.851947 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.838553 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.849426 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.682074 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.682746 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.695002 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.687149 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.689323 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.690123 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.682537 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.690510 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687472 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285068 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.284414 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.280973 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.290890 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284153 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284874 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.287864 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.279998 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287227 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285068 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 49849.542069 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 50123.918306 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 50587.963415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 49947.701449 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49866.923410 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 49746.859649 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 49639.137834 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 49929.370678 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 49961.864989 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42169.548999 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42276.987946 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 42280.837081 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 42339.328720 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42287.932186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 42366.278002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 42374.421899 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 42256.330352 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 42294.459080 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 43046.215659 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 43112.194811 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 42936.597558 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42987.940763 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 43030.247411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42944.879267 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 43055.656656 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42897.969786 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 43000.691012 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 44014.684469 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 44043.241262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 44013.596986 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 43930.294545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 43951.747176 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 43920.918668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 44003.198178 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 43889.911805 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 43970.608098 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -1626,64 +1625,64 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 84242 # Transaction distribution -system.membus.trans_dist::ReadResp 84239 # Transaction distribution -system.membus.trans_dist::WriteReq 43998 # Transaction distribution -system.membus.trans_dist::WriteResp 43998 # Transaction distribution -system.membus.trans_dist::Writeback 6229 # Transaction distribution -system.membus.trans_dist::UpgradeReq 58563 # Transaction distribution -system.membus.trans_dist::UpgradeResp 47765 # Transaction distribution -system.membus.trans_dist::ReadExReq 50044 # Transaction distribution -system.membus.trans_dist::ReadExResp 3111 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 422189 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 1082703 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 57731 # Total snoops (count) -system.membus.snoop_fanout::samples 123701 # Request fanout histogram +system.membus.trans_dist::ReadReq 84922 # Transaction distribution +system.membus.trans_dist::ReadResp 84916 # Transaction distribution +system.membus.trans_dist::WriteReq 43774 # Transaction distribution +system.membus.trans_dist::WriteResp 43771 # Transaction distribution +system.membus.trans_dist::Writeback 6423 # Transaction distribution +system.membus.trans_dist::UpgradeReq 58524 # Transaction distribution +system.membus.trans_dist::UpgradeResp 47755 # Transaction distribution +system.membus.trans_dist::ReadExReq 50059 # Transaction distribution +system.membus.trans_dist::ReadExResp 3238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 423382 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1104141 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 57586 # Total snoops (count) +system.membus.snoop_fanout::samples 124108 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 123701 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 124108 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 123701 # Request fanout histogram -system.membus.reqLayer0.occupancy 290076020 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 43.5 # Layer utilization (%) -system.membus.respLayer0.occupancy 312416500 # Layer occupancy (ticks) -system.membus.respLayer0.utilization 46.8 # Layer utilization (%) -system.toL2Bus.trans_dist::ReadReq 371224 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 371216 # Transaction distribution -system.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 43998 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 43997 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 76237 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 29460 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 29459 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 161009 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 161004 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120675 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121112 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120671 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120387 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120891 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120940 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120505 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 965857 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1759071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1770038 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1776630 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1763929 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1758071 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1768584 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1767034 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1770802 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 14134159 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 321748 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 561380 # Request fanout histogram +system.membus.snoop_fanout::total 124108 # Request fanout histogram +system.membus.reqLayer0.occupancy 285888056 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 60.1 # Layer utilization (%) +system.membus.respLayer0.occupancy 306910429 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 64.5 # Layer utilization (%) +system.toL2Bus.trans_dist::ReadReq 371514 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 371497 # Transaction distribution +system.toL2Bus.trans_dist::ReadRespWithInvalidate 4 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 43774 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 43771 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 77037 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 29480 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 29478 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 162492 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 162484 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 121222 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 121108 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 121316 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 121170 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 121269 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120825 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 121366 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 969045 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1773466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1761542 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1792162 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1783057 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785037 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1774053 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1756466 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1780883 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 14206666 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 322486 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 565861 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1694,29 +1693,29 @@ system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Re system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::7 561380 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::7 565861 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 561380 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 655414034 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 98.3 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 160915376 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 161401861 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 24.2 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 160885313 # Layer occupancy (ticks) -system.toL2Bus.respLayer2.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 160977419 # Layer occupancy (ticks) -system.toL2Bus.respLayer3.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 160313901 # Layer occupancy (ticks) -system.toL2Bus.respLayer4.utilization 24.0 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 161018393 # Layer occupancy (ticks) -system.toL2Bus.respLayer5.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 160998320 # Layer occupancy (ticks) -system.toL2Bus.respLayer6.utilization 24.1 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 160391036 # Layer occupancy (ticks) -system.toL2Bus.respLayer7.utilization 24.0 # Layer utilization (%) +system.toL2Bus.snoop_fanout::total 565861 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 447470354 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 94.1 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 102002382 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 101806870 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer2.occupancy 101634818 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer3.occupancy 101702738 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer4.occupancy 101696707 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%) +system.toL2Bus.respLayer5.occupancy 101422885 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer6.occupancy 101516818 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.utilization 21.3 # Layer utilization (%) +system.toL2Bus.respLayer7.occupancy 101999422 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |