diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-06-05 01:23:16 -0400 |
| commit | c49e739352b6d6bd665c78c560602d0cff1e6a1a (patch) | |
| tree | 5d32efd82f884376573604727d971a80458ed04a /tests/quick/se/50.memtest | |
| parent | e5f0d6016ba768c06b36d8b3d54f3ea700a4aa58 (diff) | |
| download | gem5-c49e739352b6d6bd665c78c560602d0cff1e6a1a.tar.xz | |
all: Update stats for memory per master and total fix.
Diffstat (limited to 'tests/quick/se/50.memtest')
19 files changed, 359 insertions, 194 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats index b44d5a4c2..1cbda9483 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:27 +Real time: Jun/04/2012 14:41:50 Profiler Stats -------------- -Elapsed_time_in_seconds: 113 -Elapsed_time_in_minutes: 1.88333 -Elapsed_time_in_hours: 0.0313889 -Elapsed_time_in_days: 0.00130787 +Elapsed_time_in_seconds: 88 +Elapsed_time_in_minutes: 1.46667 +Elapsed_time_in_hours: 0.0244444 +Elapsed_time_in_days: 0.00101852 -Virtual_time_in_seconds: 112.14 -Virtual_time_in_minutes: 1.869 -Virtual_time_in_hours: 0.03115 -Virtual_time_in_days: 0.00129792 +Virtual_time_in_seconds: 87.84 +Virtual_time_in_minutes: 1.464 +Virtual_time_in_hours: 0.0244 +Virtual_time_in_days: 0.00101667 Ruby_current_time: 22495354 Ruby_start_time: 0 Ruby_cycles: 22495354 -mbytes_resident: 60.2695 -mbytes_total: 361.398 -resident_ratio: 0.166768 +mbytes_resident: 61.2852 +mbytes_total: 361.766 +resident_ratio: 0.169406 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 | Resource Usage -------------- page_size: 4096 -user_time: 112 +user_time: 87 system_time: 0 -page_reclaims: 15932 +page_reclaims: 16135 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 232 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index 26548e28d..4c179bc95 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:08:30 -gem5 started May 8 2012 15:36:34 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:22 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index 1ae2ff15c..c7afc7b3a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.022495 # Nu sim_ticks 22495354 # Number of ticks simulated final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 200233 # Simulator tick rate (ticks/s) -host_mem_usage 370076 # Number of bytes of host memory used -host_seconds 112.35 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 256726 # Simulator tick rate (ticks/s) +host_mem_usage 370452 # Number of bytes of host memory used +host_seconds 87.62 # Real time elapsed on the host system.cpu0.num_reads 99326 # number of read accesses completed system.cpu0.num_writes 53132 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index af42ad0ff..e3b9d4def 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -14,7 +14,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing -memories=system.funcmem system.physmem +memories=system.physmem system.funcmem num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats index cb3fdaf16..c5ae1c27c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:43 +Real time: Jun/04/2012 14:45:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 365 -Elapsed_time_in_minutes: 6.08333 -Elapsed_time_in_hours: 0.101389 -Elapsed_time_in_days: 0.00422454 +Elapsed_time_in_seconds: 244 +Elapsed_time_in_minutes: 4.06667 +Elapsed_time_in_hours: 0.0677778 +Elapsed_time_in_days: 0.00282407 -Virtual_time_in_seconds: 361.58 -Virtual_time_in_minutes: 6.02633 -Virtual_time_in_hours: 0.100439 -Virtual_time_in_days: 0.00418495 +Virtual_time_in_seconds: 244.12 +Virtual_time_in_minutes: 4.06867 +Virtual_time_in_hours: 0.0678111 +Virtual_time_in_days: 0.00282546 Ruby_current_time: 19400856 Ruby_start_time: 0 Ruby_cycles: 19400856 -mbytes_resident: 60.2344 -mbytes_total: 361.566 -resident_ratio: 0.166593 +mbytes_resident: 61.3008 +mbytes_total: 361.941 +resident_ratio: 0.169367 ruby_cycles_executed: [ 19400857 19400857 19400857 19400857 19400857 19400857 19400857 19400857 ] @@ -116,13 +116,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 361 +user_time: 244 system_time: 0 -page_reclaims: 15956 +page_reclaims: 16161 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 448 +block_outputs: 216 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 403e6654c..ca77e3fc7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:14:18 -gem5 started May 8 2012 15:36:38 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:26 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index 9aec04ac2..fcc191198 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019401 # Nu sim_ticks 19400856 # Number of ticks simulated final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 53186 # Simulator tick rate (ticks/s) -host_mem_usage 370248 # Number of bytes of host memory used -host_seconds 364.77 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 79524 # Simulator tick rate (ticks/s) +host_mem_usage 370632 # Number of bytes of host memory used +host_seconds 243.96 # Real time elapsed on the host system.cpu0.num_reads 98844 # number of read accesses completed system.cpu0.num_writes 53478 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats index ab5cb8e9e..fe9a9f183 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:39:26 +Real time: Jun/04/2012 14:44:30 Profiler Stats -------------- -Elapsed_time_in_seconds: 164 -Elapsed_time_in_minutes: 2.73333 -Elapsed_time_in_hours: 0.0455556 -Elapsed_time_in_days: 0.00189815 +Elapsed_time_in_seconds: 117 +Elapsed_time_in_minutes: 1.95 +Elapsed_time_in_hours: 0.0325 +Elapsed_time_in_days: 0.00135417 -Virtual_time_in_seconds: 163.7 -Virtual_time_in_minutes: 2.72833 -Virtual_time_in_hours: 0.0454722 -Virtual_time_in_days: 0.00189468 +Virtual_time_in_seconds: 117.17 +Virtual_time_in_minutes: 1.95283 +Virtual_time_in_hours: 0.0325472 +Virtual_time_in_days: 0.00135613 Ruby_current_time: 19665440 Ruby_start_time: 0 Ruby_cycles: 19665440 -mbytes_resident: 60.0117 -mbytes_total: 361.082 -resident_ratio: 0.1662 +mbytes_resident: 61.0625 +mbytes_total: 361.484 +resident_ratio: 0.168922 ruby_cycles_executed: [ 19665441 19665441 19665441 19665441 19665441 19665441 19665441 19665441 ] @@ -125,13 +125,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 163 +user_time: 117 system_time: 0 -page_reclaims: 15846 +page_reclaims: 16038 page_faults: 0 swaps: 0 block_inputs: 0 -block_outputs: 288 +block_outputs: 232 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 7601ab137..4dc86aa94 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:11:25 -gem5 started May 8 2012 15:36:42 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:33 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index d352be3a5..284e6ab5c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019665 # Nu sim_ticks 19665440 # Number of ticks simulated final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 119847 # Simulator tick rate (ticks/s) -host_mem_usage 369752 # Number of bytes of host memory used -host_seconds 164.09 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 168119 # Simulator tick rate (ticks/s) +host_mem_usage 370164 # Number of bytes of host memory used +host_seconds 116.97 # Real time elapsed on the host system.cpu0.num_reads 99534 # number of read accesses completed system.cpu0.num_writes 53920 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats index 08a16b146..f9a059734 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:38:42 +Real time: Jun/04/2012 13:44:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 131 -Elapsed_time_in_minutes: 2.18333 -Elapsed_time_in_hours: 0.0363889 -Elapsed_time_in_days: 0.0015162 +Elapsed_time_in_seconds: 111 +Elapsed_time_in_minutes: 1.85 +Elapsed_time_in_hours: 0.0308333 +Elapsed_time_in_days: 0.00128472 -Virtual_time_in_seconds: 129.82 -Virtual_time_in_minutes: 2.16367 -Virtual_time_in_hours: 0.0360611 -Virtual_time_in_days: 0.00150255 +Virtual_time_in_seconds: 111.55 +Virtual_time_in_minutes: 1.85917 +Virtual_time_in_hours: 0.0309861 +Virtual_time_in_days: 0.00129109 Ruby_current_time: 19129199 Ruby_start_time: 0 Ruby_cycles: 19129199 -mbytes_resident: 59.6641 -mbytes_total: 360.938 -resident_ratio: 0.165303 +mbytes_resident: 60.7188 +mbytes_total: 361.293 +resident_ratio: 0.16806 ruby_cycles_executed: [ 19129200 19129200 19129200 19129200 19129200 19129200 19129200 19129200 ] @@ -124,13 +124,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard dev Resource Usage -------------- page_size: 4096 -user_time: 129 +user_time: 111 system_time: 0 -page_reclaims: 15794 +page_reclaims: 15994 page_faults: 0 swaps: 0 -block_inputs: 16 -block_outputs: 256 +block_inputs: 0 +block_outputs: 224 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index 9fc5d7446..bc60d72d3 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:12:50 -gem5 started May 8 2012 15:36:31 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index cad2377ee..7c588684e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.019129 # Nu sim_ticks 19129199 # Number of ticks simulated final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 146249 # Simulator tick rate (ticks/s) -host_mem_usage 369604 # Number of bytes of host memory used -host_seconds 130.80 # Real time elapsed on the host -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 171697 # Simulator tick rate (ticks/s) +host_mem_usage 369968 # Number of bytes of host memory used +host_seconds 111.41 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53893 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats index 379029232..ceb7b2a64 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats @@ -34,27 +34,27 @@ periodic_stats_period: 1000000 ================ End RubySystem Configuration Print ================ -Real time: May/08/2012 15:42:37 +Real time: Jun/04/2012 14:22:53 Profiler Stats -------------- -Elapsed_time_in_seconds: 69 -Elapsed_time_in_minutes: 1.15 -Elapsed_time_in_hours: 0.0191667 -Elapsed_time_in_days: 0.000798611 +Elapsed_time_in_seconds: 41 +Elapsed_time_in_minutes: 0.683333 +Elapsed_time_in_hours: 0.0113889 +Elapsed_time_in_days: 0.000474537 -Virtual_time_in_seconds: 68.73 -Virtual_time_in_minutes: 1.1455 -Virtual_time_in_hours: 0.0190917 -Virtual_time_in_days: 0.000795486 +Virtual_time_in_seconds: 41.24 +Virtual_time_in_minutes: 0.687333 +Virtual_time_in_hours: 0.0114556 +Virtual_time_in_days: 0.000477315 Ruby_current_time: 28725020 Ruby_start_time: 0 Ruby_cycles: 28725020 -mbytes_resident: 59.4102 -mbytes_total: 360.535 -resident_ratio: 0.164783 +mbytes_resident: 60.7461 +mbytes_total: 361.262 +resident_ratio: 0.16815 ruby_cycles_executed: [ 28725021 28725021 28725021 28725021 28725021 28725021 28725021 28725021 ] @@ -118,13 +118,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 22 count: 1233888 average: 0.00745367 Resource Usage -------------- page_size: 4096 -user_time: 68 +user_time: 41 system_time: 0 -page_reclaims: 15745 -page_faults: 0 +page_reclaims: 15955 +page_faults: 2 swaps: 0 -block_inputs: 0 -block_outputs: 256 +block_inputs: 128 +block_outputs: 184 Network Stats ------------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout index 4cb3155a6..19534930d 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:41:28 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:22:12 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt index 12fdf4aa3..fbf03980e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt @@ -4,21 +4,9 @@ sim_seconds 0.028725 # Nu sim_ticks 28725020 # Number of ticks simulated final_tick 28725020 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 417169 # Simulator tick rate (ticks/s) -host_mem_usage 369192 # Number of bytes of host memory used -host_seconds 68.86 # Real time elapsed on the host -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bytes_read 0 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 0 # Number of bytes written to this memory -system.physmem.num_reads 0 # Number of read requests responded to by this memory -system.physmem.num_writes 0 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 699351 # Simulator tick rate (ticks/s) +host_mem_usage 369936 # Number of bytes of host memory used +host_seconds 41.07 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53147 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index dfa7c1d18..db9f08590 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -417,9 +417,8 @@ cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[0] [system.membus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false @@ -440,9 +439,8 @@ zero=false port=system.membus.master[0] [system.toL2Bus] -type=Bus +type=CoherentBus block_size=64 -bus_id=0 clock=2 header_cycles=1 use_default_range=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index cd078a3a4..4cc5a9b4f 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled May 8 2012 15:36:31 -gem5 started May 8 2012 15:37:08 -gem5 executing on piton +gem5 compiled Jun 4 2012 11:50:11 +gem5 started Jun 4 2012 14:15:53 +gem5 executing on zizzer command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 58bdafd11..9aa493322 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -4,24 +4,76 @@ sim_seconds 0.000263 # Nu sim_ticks 263488655 # Number of ticks simulated final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1217695 # Simulator tick rate (ticks/s) -host_mem_usage 343548 # Number of bytes of host memory used -host_seconds 216.38 # Real time elapsed on the host -system.physmem.bytes_read 4057580 # Number of bytes read from this memory -system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.physmem.bytes_written 2644316 # Number of bytes written to this memory -system.physmem.num_reads 141878 # Number of read requests responded to by this memory -system.physmem.num_writes 83744 # Number of write requests responded to by this memory -system.physmem.num_other 0 # Number of other requests responded to by this memory -system.physmem.bw_read 15399448602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write 10035786930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total 25435235532 # Total bandwidth to/from this memory (bytes/s) -system.funcmem.bytes_read 0 # Number of bytes read from this memory -system.funcmem.bytes_inst_read 0 # Number of instructions bytes read from this memory -system.funcmem.bytes_written 0 # Number of bytes written to this memory -system.funcmem.num_reads 0 # Number of read requests responded to by this memory -system.funcmem.num_writes 0 # Number of write requests responded to by this memory -system.funcmem.num_other 0 # Number of other requests responded to by this memory +host_tick_rate 1558675 # Simulator tick rate (ticks/s) +host_mem_usage 343952 # Number of bytes of host memory used +host_seconds 169.05 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 504730 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 513456 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 503221 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 509883 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 511138 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 501110 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 514161 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 499881 # Number of bytes read from this memory +system.physmem.bytes_read::total 4057580 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 2601216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5426 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5325 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5406 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5472 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5419 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5298 # Number of bytes written to this memory +system.physmem.bytes_written::total 2644316 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 17740 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 17646 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 17743 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 17727 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 17848 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 17774 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 17658 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 17742 # Number of read requests responded to by this memory +system.physmem.num_reads::total 141878 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 40644 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5325 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5406 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5472 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5419 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5298 # Number of write requests responded to by this memory +system.physmem.num_writes::total 83744 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 1915566346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 1948683521 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 1909839344 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 1935123165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 1939886178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 1901827614 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 1951359158 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 1897163276 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 15399448602 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 9872212525 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 20463879 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 20592917 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 20209599 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 20517012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 20767498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 20350022 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 20566350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 20107128 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 10035786930 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 9872212525 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 1936030225 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 1969276438 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 1930048943 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 1955640177 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 1960653676 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 1922177636 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 1971925509 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 1917270404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 25435235532 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 76856 # number of replacements system.l2c.tagsinuse 657.714518 # Cycle average of tags in use system.l2c.total_refs 139150 # Total number of references to valid blocks. @@ -239,6 +291,7 @@ system.l2c.ReadReq_miss_rate::cpu4 0.333248 # mi system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.329797 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses @@ -247,6 +300,7 @@ system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # mi system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.786224 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses @@ -255,6 +309,7 @@ system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # mi system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.662584 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses @@ -263,6 +318,7 @@ system.l2c.demand_miss_rate::cpu4 0.449498 # mi system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.446844 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses @@ -271,6 +327,7 @@ system.l2c.overall_miss_rate::cpu4 0.449498 # mi system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.446844 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency @@ -279,6 +336,7 @@ system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # a system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49615.022334 # average ReadReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency @@ -287,6 +345,7 @@ system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323 # average UpgradeReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency @@ -295,6 +354,7 @@ system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49817.112873 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -303,6 +363,7 @@ system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # av system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency @@ -311,6 +372,7 @@ system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # a system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49720.418420 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -491,6 +553,7 @@ system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # ms system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.322103 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses @@ -499,6 +562,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.783235 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses @@ -507,6 +571,7 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # m system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.655102 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses @@ -515,6 +580,7 @@ system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.439225 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses @@ -523,6 +589,7 @@ system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # ms system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.439225 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency @@ -531,6 +598,7 @@ system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency @@ -539,6 +607,7 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency @@ -547,6 +616,7 @@ system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -555,6 +625,7 @@ system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency @@ -563,6 +634,7 @@ system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -571,6 +643,7 @@ system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -579,6 +652,7 @@ system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency @@ -587,6 +661,7 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.num_reads 99815 # number of read accesses completed system.cpu0.num_writes 53929 # number of write accesses completed @@ -633,13 +708,21 @@ system.cpu0.l1c.demand_accesses::total 69070 # nu system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.831953 # miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956350 # miss rate for WriteReq accesses system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.875648 # miss rate for demand accesses system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.875648 # miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698 # average ReadReq miss latency system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144 # average WriteReq miss latency system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822 # average overall miss latency system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked @@ -673,16 +756,27 @@ system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.831953 # mshr miss rate for ReadReq accesses system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956350 # mshr miss rate for WriteReq accesses system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.875648 # mshr miss rate for demand accesses system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.875648 # mshr miss rate for overall accesses system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373 # average ReadReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007 # average WriteReq mshr miss latency system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency +system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency +system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency +system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.num_reads 98493 # number of read accesses completed system.cpu1.num_writes 53671 # number of write accesses completed @@ -729,13 +823,21 @@ system.cpu1.l1c.demand_accesses::total 68880 # nu system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.833202 # miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956206 # miss rate for WriteReq accesses system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.876670 # miss rate for demand accesses system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.876670 # miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375 # average ReadReq miss latency system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690 # average WriteReq miss latency system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291 # average overall miss latency system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked @@ -769,16 +871,27 @@ system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.833202 # mshr miss rate for ReadReq accesses system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956206 # mshr miss rate for WriteReq accesses system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.876670 # mshr miss rate for demand accesses system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.876670 # mshr miss rate for overall accesses system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410 # average ReadReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825 # average WriteReq mshr miss latency system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency +system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency +system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency +system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.num_reads 99149 # number of read accesses completed system.cpu2.num_writes 53185 # number of write accesses completed @@ -825,13 +938,21 @@ system.cpu2.l1c.demand_accesses::total 68674 # nu system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.830590 # miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955373 # miss rate for WriteReq accesses system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.874115 # miss rate for demand accesses system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.874115 # miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314 # average ReadReq miss latency system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535 # average WriteReq miss latency system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080 # average overall miss latency system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked @@ -865,16 +986,27 @@ system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.830590 # mshr miss rate for ReadReq accesses system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955373 # mshr miss rate for WriteReq accesses system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.874115 # mshr miss rate for demand accesses system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.874115 # mshr miss rate for overall accesses system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684 # average ReadReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409 # average WriteReq mshr miss latency system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency +system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency +system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency +system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.num_reads 99588 # number of read accesses completed system.cpu3.num_writes 53645 # number of write accesses completed @@ -921,13 +1053,21 @@ system.cpu3.l1c.demand_accesses::total 69040 # nu system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.831214 # miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.955632 # miss rate for WriteReq accesses system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.875000 # miss rate for demand accesses system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.875000 # miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452 # average ReadReq miss latency system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470 # average WriteReq miss latency system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340 # average overall miss latency system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked @@ -961,16 +1101,27 @@ system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.831214 # mshr miss rate for ReadReq accesses system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955632 # mshr miss rate for WriteReq accesses system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.875000 # mshr miss rate for demand accesses system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.875000 # mshr miss rate for overall accesses system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970 # average ReadReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641 # average WriteReq mshr miss latency system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency +system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency +system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency +system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu4.num_reads 99725 # number of read accesses completed system.cpu4.num_writes 53533 # number of write accesses completed @@ -1017,13 +1168,21 @@ system.cpu4.l1c.demand_accesses::total 68997 # nu system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.828961 # miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.953325 # miss rate for WriteReq accesses system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.872328 # miss rate for demand accesses system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.872328 # miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149 # average ReadReq miss latency system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302 # average WriteReq miss latency system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970 # average overall miss latency system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked @@ -1057,16 +1216,27 @@ system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.828961 # mshr miss rate for ReadReq accesses system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953325 # mshr miss rate for WriteReq accesses system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.872328 # mshr miss rate for demand accesses system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.872328 # mshr miss rate for overall accesses system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817 # average ReadReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864 # average WriteReq mshr miss latency system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency +system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency +system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency +system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu5.num_reads 100000 # number of read accesses completed system.cpu5.num_writes 53710 # number of write accesses completed @@ -1113,13 +1283,21 @@ system.cpu5.l1c.demand_accesses::total 69080 # nu system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.831067 # miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.953353 # miss rate for WriteReq accesses system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.873798 # miss rate for demand accesses system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.873798 # miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352 # average ReadReq miss latency system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563 # average WriteReq miss latency system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625 # average overall miss latency system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked @@ -1153,16 +1331,27 @@ system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.831067 # mshr miss rate for ReadReq accesses system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953353 # mshr miss rate for WriteReq accesses system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.873798 # mshr miss rate for demand accesses system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.873798 # mshr miss rate for overall accesses system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160 # average ReadReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397 # average WriteReq mshr miss latency system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency +system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency +system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency +system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu6.num_reads 99389 # number of read accesses completed system.cpu6.num_writes 53686 # number of write accesses completed @@ -1209,13 +1398,21 @@ system.cpu6.l1c.demand_accesses::total 68913 # nu system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.831071 # miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.953877 # miss rate for WriteReq accesses system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.874305 # miss rate for demand accesses system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.874305 # miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844 # average ReadReq miss latency system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019 # average WriteReq miss latency system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740 # average overall miss latency system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked @@ -1249,16 +1446,27 @@ system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.831071 # mshr miss rate for ReadReq accesses system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953877 # mshr miss rate for WriteReq accesses system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.874305 # mshr miss rate for demand accesses system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.874305 # mshr miss rate for overall accesses system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723 # average ReadReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809 # average WriteReq mshr miss latency system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency +system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency +system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency +system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu7.num_reads 99694 # number of read accesses completed system.cpu7.num_writes 53501 # number of write accesses completed @@ -1305,13 +1513,21 @@ system.cpu7.l1c.demand_accesses::total 68980 # nu system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.830316 # miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954152 # miss rate for WriteReq accesses system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.873818 # miss rate for demand accesses system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.873818 # miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409 # average ReadReq miss latency system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916 # average WriteReq miss latency system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147 # average overall miss latency system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked @@ -1345,16 +1561,27 @@ system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.830316 # mshr miss rate for ReadReq accesses system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954152 # mshr miss rate for WriteReq accesses system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.873818 # mshr miss rate for demand accesses system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.873818 # mshr miss rate for overall accesses system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764 # average ReadReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466 # average WriteReq mshr miss latency system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency +system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency +system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency +system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |