diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:41 -0400 |
| commit | fda338f8d3ba6f6cb271e2c10cb880ff064edb61 (patch) | |
| tree | 20a91f6acacb2cb40967ce56a539d8444b744b9e /tests/quick/se/50.memtest | |
| parent | b265d9925c123f0df50db98cf56dab6a3596b54b (diff) | |
| download | gem5-fda338f8d3ba6f6cb271e2c10cb880ff064edb61.tar.xz | |
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Diffstat (limited to 'tests/quick/se/50.memtest')
3 files changed, 1507 insertions, 1504 deletions
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index a874a3f37..b8bd8a115 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read, 5380 write accesses @22344646 -system.cpu6: completed 10000 read, 5214 write accesses @22747629 -system.cpu7: completed 10000 read, 5415 write accesses @22929508 -system.cpu2: completed 10000 read, 5407 write accesses @23019836 -system.cpu5: completed 10000 read, 5331 write accesses @23061044 -system.cpu0: completed 10000 read, 5432 write accesses @23140146 -system.cpu3: completed 10000 read, 5376 write accesses @23188049 -system.cpu1: completed 10000 read, 5387 write accesses @23350185 -system.cpu4: completed 20000 read, 10814 write accesses @44761691 -system.cpu7: completed 20000 read, 10827 write accesses @45213444 -system.cpu1: completed 20000 read, 10711 write accesses @45275122 -system.cpu6: completed 20000 read, 10548 write accesses @45324102 -system.cpu3: completed 20000 read, 10701 write accesses @45506880 -system.cpu2: completed 20000 read, 10922 write accesses @45734056 -system.cpu5: completed 20000 read, 10686 write accesses @45942373 -system.cpu0: completed 20000 read, 10937 write accesses @46044746 -system.cpu7: completed 30000 read, 16167 write accesses @66979485 -system.cpu4: completed 30000 read, 16361 write accesses @67223162 -system.cpu6: completed 30000 read, 15931 write accesses @67873351 -system.cpu3: completed 30000 read, 16353 write accesses @68348826 -system.cpu5: completed 30000 read, 16080 write accesses @68377482 -system.cpu1: completed 30000 read, 16196 write accesses @68419268 -system.cpu0: completed 30000 read, 16219 write accesses @68619325 -system.cpu2: completed 30000 read, 16526 write accesses @68648506 -system.cpu4: completed 40000 read, 21581 write accesses @88592659 -system.cpu7: completed 40000 read, 21651 write accesses @88863809 -system.cpu6: completed 40000 read, 21187 write accesses @89230569 -system.cpu1: completed 40000 read, 21556 write accesses @89813083 -system.cpu2: completed 40000 read, 21771 write accesses @90046604 -system.cpu3: completed 40000 read, 21725 write accesses @90210729 -system.cpu5: completed 40000 read, 21435 write accesses @90283858 -system.cpu0: completed 40000 read, 21836 write accesses @90947960 -system.cpu4: completed 50000 read, 27034 write accesses @111338978 -system.cpu6: completed 50000 read, 26346 write accesses @111492478 -system.cpu1: completed 50000 read, 26820 write accesses @112199634 -system.cpu7: completed 50000 read, 27390 write accesses @112358430 -system.cpu5: completed 50000 read, 26711 write accesses @112747804 -system.cpu3: completed 50000 read, 27030 write accesses @113062631 -system.cpu2: completed 50000 read, 27246 write accesses @113387493 -system.cpu0: completed 50000 read, 27088 write accesses @113621350 -system.cpu4: completed 60000 read, 32322 write accesses @134108306 -system.cpu6: completed 60000 read, 31811 write accesses @134700049 -system.cpu2: completed 60000 read, 32452 write accesses @135470855 -system.cpu1: completed 60000 read, 32239 write accesses @135474213 -system.cpu7: completed 60000 read, 32783 write accesses @135487924 -system.cpu5: completed 60000 read, 32297 write accesses @135551091 -system.cpu3: completed 60000 read, 32475 write accesses @135953364 -system.cpu0: completed 60000 read, 32594 write accesses @136506452 -system.cpu4: completed 70000 read, 37624 write accesses @156509147 -system.cpu6: completed 70000 read, 37191 write accesses @157507230 -system.cpu2: completed 70000 read, 37791 write accesses @158024045 -system.cpu7: completed 70000 read, 38252 write accesses @158415918 -system.cpu1: completed 70000 read, 37644 write accesses @158423190 -system.cpu5: completed 70000 read, 37691 write accesses @158678523 -system.cpu3: completed 70000 read, 38021 write accesses @158813067 -system.cpu0: completed 70000 read, 37965 write accesses @159679646 -system.cpu4: completed 80000 read, 42948 write accesses @178855235 -system.cpu6: completed 80000 read, 42510 write accesses @180069540 -system.cpu2: completed 80000 read, 43201 write accesses @180702038 -system.cpu1: completed 80000 read, 43267 write accesses @181114200 -system.cpu7: completed 80000 read, 43705 write accesses @181378010 -system.cpu3: completed 80000 read, 43552 write accesses @181443642 -system.cpu5: completed 80000 read, 43080 write accesses @181574154 -system.cpu0: completed 80000 read, 43418 write accesses @182451715 -system.cpu4: completed 90000 read, 48279 write accesses @201435873 -system.cpu6: completed 90000 read, 47918 write accesses @202390012 -system.cpu2: completed 90000 read, 48513 write accesses @203087400 -system.cpu1: completed 90000 read, 48611 write accesses @203141768 -system.cpu7: completed 90000 read, 48973 write accesses @204050544 -system.cpu5: completed 90000 read, 48423 write accesses @204299514 -system.cpu0: completed 90000 read, 48663 write accesses @204396348 -system.cpu3: completed 90000 read, 48999 write accesses @204475748 -system.cpu4: completed 100000 read, 53697 write accesses @224044586 +system.cpu3: completed 10000 read, 5269 write accesses @22241329 +system.cpu6: completed 10000 read, 5339 write accesses @22510874 +system.cpu4: completed 10000 read, 5452 write accesses @22618520 +system.cpu2: completed 10000 read, 5274 write accesses @22652245 +system.cpu5: completed 10000 read, 5225 write accesses @22698654 +system.cpu0: completed 10000 read, 5313 write accesses @22972460 +system.cpu1: completed 10000 read, 5425 write accesses @23112052 +system.cpu7: completed 10000 read, 5664 write accesses @23303588 +system.cpu3: completed 20000 read, 10591 write accesses @44494817 +system.cpu6: completed 20000 read, 10810 write accesses @44620430 +system.cpu2: completed 20000 read, 10802 write accesses @45009184 +system.cpu0: completed 20000 read, 10643 write accesses @45009224 +system.cpu5: completed 20000 read, 10647 write accesses @45039314 +system.cpu1: completed 20000 read, 10757 write accesses @45068735 +system.cpu4: completed 20000 read, 10808 write accesses @45199458 +system.cpu7: completed 20000 read, 11080 write accesses @45757070 +system.cpu2: completed 30000 read, 16115 write accesses @67069204 +system.cpu3: completed 30000 read, 16110 write accesses @67286000 +system.cpu5: completed 30000 read, 16163 write accesses @67388496 +system.cpu4: completed 30000 read, 16262 write accesses @67495238 +system.cpu6: completed 30000 read, 16234 write accesses @67566368 +system.cpu0: completed 30000 read, 16102 write accesses @67625583 +system.cpu1: completed 30000 read, 16288 write accesses @67665372 +system.cpu7: completed 30000 read, 16608 write accesses @68406261 +system.cpu4: completed 40000 read, 21521 write accesses @88522458 +system.cpu2: completed 40000 read, 21461 write accesses @88760475 +system.cpu5: completed 40000 read, 21540 write accesses @88851958 +system.cpu3: completed 40000 read, 21536 write accesses @88901742 +system.cpu6: completed 40000 read, 21498 write accesses @88910943 +system.cpu1: completed 40000 read, 21730 write accesses @89071047 +system.cpu0: completed 40000 read, 21414 write accesses @89232143 +system.cpu7: completed 40000 read, 22063 write accesses @90453997 +system.cpu4: completed 50000 read, 26910 write accesses @111349230 +system.cpu1: completed 50000 read, 26996 write accesses @111399385 +system.cpu2: completed 50000 read, 26807 write accesses @111571994 +system.cpu6: completed 50000 read, 26876 write accesses @111619105 +system.cpu3: completed 50000 read, 27009 write accesses @111789131 +system.cpu0: completed 50000 read, 26777 write accesses @111829265 +system.cpu5: completed 50000 read, 26952 write accesses @111861140 +system.cpu7: completed 50000 read, 27397 write accesses @112901639 +system.cpu1: completed 60000 read, 32331 write accesses @134016224 +system.cpu2: completed 60000 read, 32246 write accesses @134236668 +system.cpu4: completed 60000 read, 32290 write accesses @134236929 +system.cpu5: completed 60000 read, 32370 write accesses @134256674 +system.cpu6: completed 60000 read, 32444 write accesses @134707450 +system.cpu0: completed 60000 read, 32183 write accesses @134767456 +system.cpu3: completed 60000 read, 32423 write accesses @134996472 +system.cpu7: completed 60000 read, 32735 write accesses @135678114 +system.cpu2: completed 70000 read, 37600 write accesses @156516476 +system.cpu1: completed 70000 read, 37730 write accesses @156721328 +system.cpu5: completed 70000 read, 37748 write accesses @156805205 +system.cpu6: completed 70000 read, 37760 write accesses @156910635 +system.cpu4: completed 70000 read, 37725 write accesses @156961462 +system.cpu0: completed 70000 read, 37635 write accesses @158012668 +system.cpu3: completed 70000 read, 37942 write accesses @158279756 +system.cpu7: completed 70000 read, 38031 write accesses @158283192 +system.cpu5: completed 80000 read, 43255 write accesses @179067469 +system.cpu2: completed 80000 read, 43125 write accesses @179091672 +system.cpu1: completed 80000 read, 43134 write accesses @179182044 +system.cpu6: completed 80000 read, 43119 write accesses @179350821 +system.cpu4: completed 80000 read, 43054 write accesses @179621308 +system.cpu7: completed 80000 read, 43393 write accesses @180749386 +system.cpu0: completed 80000 read, 43229 write accesses @180793374 +system.cpu3: completed 80000 read, 43339 write accesses @180920432 +system.cpu6: completed 90000 read, 48363 write accesses @201441693 +system.cpu2: completed 90000 read, 48516 write accesses @201463344 +system.cpu5: completed 90000 read, 48731 write accesses @201471872 +system.cpu1: completed 90000 read, 48576 write accesses @201752753 +system.cpu4: completed 90000 read, 48432 write accesses @201853284 +system.cpu7: completed 90000 read, 48666 write accesses @202980078 +system.cpu3: completed 90000 read, 48647 write accesses @203163876 +system.cpu0: completed 90000 read, 48482 write accesses @203365064 +system.cpu6: completed 100000 read, 53510 write accesses @223713460 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 2045d5848..ed860ddcf 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:09:54 +gem5 compiled Jul 2 2012 08:30:56 +gem5 started Jul 2 2012 09:08:41 gem5 executing on zizzer command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 224044586 because maximum number of loads reached +Exiting @ tick 223713460 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9c1b7f7cc..1fe48d0c8 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,637 +1,640 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000224 # Number of seconds simulated -sim_ticks 224044586 # Number of ticks simulated -final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 223713460 # Number of ticks simulated +final_tick 223713460 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1786168 # Simulator tick rate (ticks/s) -host_mem_usage 347548 # Number of bytes of host memory used -host_seconds 125.43 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory -system.physmem.bytes_read::total 700372 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory -system.physmem.bytes_written::total 498192 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory -system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 14607 # number of replacements -system.l2c.tagsinuse 798.832185 # Cycle average of tags in use -system.l2c.total_refs 150557 # Total number of references to valid blocks. -system.l2c.sampled_refs 15432 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.756156 # Average number of references to valid blocks. +host_tick_rate 1721618 # Simulator tick rate (ticks/s) +host_mem_usage 347508 # Number of bytes of host memory used +host_seconds 129.94 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 81065 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 82807 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 84800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 80115 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 83878 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 83050 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 84723 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 83101 # Number of bytes read from this memory +system.physmem.bytes_read::total 663539 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 423360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5290 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5393 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5404 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5324 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5344 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5398 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5445 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5412 # Number of bytes written to this memory +system.physmem.bytes_written::total 466370 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11135 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11050 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11041 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11139 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11029 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88727 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 6615 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5290 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5393 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5404 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5324 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5344 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5398 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5445 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5412 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49625 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 362360852 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 370147599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 379056316 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 358114349 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 374934973 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 371233810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 378712126 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 371461780 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2966021803 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1892420778 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 23646320 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 24106730 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 24155900 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 23798300 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 23887700 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 24129080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 24339170 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 24191660 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2084675638 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1892420778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 386007172 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 394254329 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 403212216 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 381912648 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 398822673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 395362890 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 403051296 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 395653440 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5050697441 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 13635 # number of replacements +system.l2c.tagsinuse 790.382632 # Cycle average of tags in use +system.l2c.total_refs 148986 # Total number of references to valid blocks. +system.l2c.sampled_refs 14447 # Sample count of references to valid blocks. +system.l2c.avg_refs 10.312591 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 740.812109 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.661361 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.247095 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.177515 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 6.855610 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.321397 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.120032 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.753138 # 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number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1932 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15459 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4394 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4308 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4316 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4354 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4292 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4233 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4328 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34517 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5228 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5140 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5138 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5134 # 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number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2213 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18202 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6374 # number of ReadExReq accesses(hits+misses) +system.l2c.occ_blocks::writebacks 735.582494 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 6.455373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 6.652747 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 6.865494 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 6.639169 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.152690 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.266868 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 7.044725 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 6.723074 # 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number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 255947766 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 254683944 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 251418591 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 251636922 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2027376776 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11468 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11360 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11385 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11392 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11418 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11270 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11586 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11524 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 91403 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 74602 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 74602 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2318 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2266 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2344 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2304 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2287 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2380 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2276 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2218 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18393 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6269 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1 6191 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6240 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6357 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6269 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6212 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6215 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6224 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50082 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17846 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17696 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 17933 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17750 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17813 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17960 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17904 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 17849 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142751 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17846 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17696 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 17933 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17750 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17813 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17960 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17904 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 17849 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142751 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.072699 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.072316 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.070298 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.068463 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068434 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.067586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.071691 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.063312 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.069344 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.852876 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.843146 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.842244 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.851820 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.857572 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.849801 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.852689 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.844037 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.849302 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.689363 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.695849 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.691667 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.684914 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.684639 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.690921 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.681094 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.695373 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.689210 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.292951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.290461 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286511 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.289239 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.285297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.283185 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.283233 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.283713 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.286814 # 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average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49607.316993 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49963.417504 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49887.468630 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49885.922957 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49900.924290 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49870.753214 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49939.188902 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49945.125049 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49929.225991 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49902.884281 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49907.527563 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49887.468630 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49885.922957 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49900.924290 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49870.753214 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49939.188902 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49945.125049 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49929.225991 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49902.884281 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49907.527563 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked +system.l2c.ReadExReq_accesses::cpu2 6083 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6238 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6234 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6272 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6117 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6137 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 49541 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17737 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17551 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17468 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17630 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17652 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17542 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17703 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17661 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 140944 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17737 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17551 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17468 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17630 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17652 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17542 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17703 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17661 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 140944 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.063830 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.065669 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.069126 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.064607 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068226 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.068146 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.069221 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.065602 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.066803 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.842968 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.853486 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.856229 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851128 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.839965 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.843697 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.842267 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.855726 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.848149 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.693572 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.708932 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.699819 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.692530 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.697786 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.691486 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.692169 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.699039 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.696898 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.286407 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.292576 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.288757 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.286784 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.290562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.291016 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.284472 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.285714 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.288278 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.286407 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.292576 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.288757 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.286784 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.290562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.291016 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.284472 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.285714 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.288278 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 49429.372951 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 49725.445040 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 49351.857687 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 49348.440217 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 49620.612323 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 49455.048177 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 49767.672070 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 49497.575397 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49526.305437 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 26392.335722 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27313.714581 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27448.613852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 27559.738909 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 26774.917231 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 27613.063745 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 26643.425143 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 26896.813488 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 27085.680128 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 49986.975621 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 49971.519481 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 49975.390886 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 49962.522685 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 49952.484828 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 49965.982707 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 49953.924894 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 49933.975524 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49962.900941 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 49906.628150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 49935.770399 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 49878.102895 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 49873.130934 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 49902.079548 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 49889.117336 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 49924.263503 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 49868.593341 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49897.289656 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 49906.628150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 49935.770399 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 49878.102895 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 49873.130934 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 49902.079548 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 49889.117336 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 49924.263503 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 49868.593341 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49897.289656 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 96627 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 19 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 5085.631579 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7115 # number of writebacks -system.l2c.writebacks::total 7115 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 23 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 22 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 13 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 15 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 19 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 17 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 6616 # number of writebacks +system.l2c.writebacks::total 6616 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 18 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 157 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu0 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 9 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 13 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 8 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 13 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 15 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 12 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 31 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 35 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 39 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 28 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 23 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 29 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 244 # 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number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 779 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 819 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 719 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6271 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1913 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1872 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1921 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 2011 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1998 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1916 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1887 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1932 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15450 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4381 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4300 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4303 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4339 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4277 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4283 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4316 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34428 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5193 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5109 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5103 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5095 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 212842079 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215082041 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 209602015 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 213002165 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213521784 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214681989 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217761849 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216562185 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1713056107 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 606447147 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 612246481 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 605686840 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 608567052 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 610366975 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 607566690 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 617686786 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 614168014 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4882735985 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070781 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070317 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068417 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066357 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067308 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066309 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.070066 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061849 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.067671 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852876 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841348 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841805 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851397 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.857143 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.848914 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.852689 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844037 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.848808 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.687324 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.694557 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.689583 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.682555 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.682246 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689472 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680451 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.693445 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.687433 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.285105 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.285105 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency +system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu7 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 12 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 11 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 10 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 85 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 33 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 32 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 34 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 30 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 27 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 242 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 33 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 32 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 34 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 30 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 27 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 242 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 714 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 736 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 763 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 713 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 757 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 749 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 785 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 732 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 5949 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1952 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1933 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 2006 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1960 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1920 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 2007 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1916 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1894 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15588 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4342 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4376 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4248 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4311 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4338 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4326 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4224 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4275 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34440 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5056 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5112 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5011 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5024 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5075 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5009 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5007 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40389 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5056 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5112 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5011 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5024 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5075 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5009 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5007 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40389 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 28564754 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 29444935 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 30526423 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 28524830 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 30284517 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 29963728 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 31404851 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 29284664 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 237998702 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78081132 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 77281042 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80241204 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78401138 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76801198 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 80241160 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76640992 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75761030 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 623448896 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 173685720 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 175005460 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 169924253 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 172445652 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 173444745 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 173045540 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 168925276 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 170965174 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1377441820 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 202250474 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 204450395 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 200450676 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 200970482 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 203729262 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 203009268 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 200330127 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 200249838 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1615440522 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 202250474 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 204450395 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 200450676 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 200970482 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 203729262 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 203009268 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 200330127 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 200249838 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1615440522 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400927744 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 396406972 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396807484 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 398767759 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400808423 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 395927220 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 398767355 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 395367613 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3183780570 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 211603917 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215684252 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 216163665 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 212923402 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213723846 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 215924115 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217803639 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216444289 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1720271125 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 612531661 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 612091224 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 612971149 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 611691161 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 614532269 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 611851335 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 616570994 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 611811902 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4904051695 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.062260 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.064789 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.067018 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.062588 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.066299 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066460 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.067754 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.063520 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.065085 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842105 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.853045 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.855802 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.850694 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.839528 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.843277 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.841828 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.853922 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.847496 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.692614 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.706832 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.698340 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.691087 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.695861 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689732 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.690535 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.696594 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.695182 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.286561 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.285054 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.291265 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.286867 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.284969 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.288636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.289306 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.282946 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.283506 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.286561 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40006.658263 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40006.705163 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40008.418087 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40006.774194 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40005.966975 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40004.977303 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40006.179618 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 40006.371585 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40006.505631 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.579918 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39979.845835 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.600199 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.580612 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40000.623958 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39980.647733 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40000.517745 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.543823 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39995.438542 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40001.317365 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39992.106947 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 40001.001177 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40001.311065 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 39982.652144 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40001.280629 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 39991.779356 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.853567 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39995.407085 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.071598 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 39994.208725 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 40002.130513 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.086385 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 39986.116192 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.826207 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 39994.036135 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 39993.976034 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39997.041818 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -660,114 +663,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98637 # number of read accesses completed -system.cpu0.num_writes 53345 # number of write accesses completed +system.cpu0.num_reads 99016 # number of read accesses completed +system.cpu0.num_writes 53340 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22018 # number of replacements -system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21906 # number of replacements +system.cpu0.l1c.tagsinuse 396.590239 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13140 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22312 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.588921 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 396.710521 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.774825 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8580 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1119 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9699 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9699 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9699 # number of overall hits -system.cpu0.l1c.overall_hits::total 9699 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35932 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35932 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23215 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23215 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59147 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59147 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59147 # number of overall misses -system.cpu0.l1c.overall_misses::total 59147 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 928213854 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 928213854 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 888665457 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 888665457 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 1816879311 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 1816879311 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 1816879311 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 1816879311 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44512 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44512 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24334 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24334 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68846 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68846 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68846 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68846 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807243 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.807243 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954015 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.954015 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859120 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859120 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859120 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859120 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 213519076 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.590239 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.774590 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.774590 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8561 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8561 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1051 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1051 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9612 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9612 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9612 # number of overall hits +system.cpu0.l1c.overall_hits::total 9612 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35875 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35875 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23186 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23186 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59061 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59061 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59061 # number of overall misses +system.cpu0.l1c.overall_misses::total 59061 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 894906998 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 894906998 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 820039819 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 820039819 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1714946817 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1714946817 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1714946817 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1714946817 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44436 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44436 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24237 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24237 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68673 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68673 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68673 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68673 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807341 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807341 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956637 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.956637 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.860032 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.860032 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.860032 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.860032 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 24945.142801 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 24945.142801 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 35367.886613 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 35367.886613 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 29036.874029 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 29036.874029 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 29036.874029 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 29036.874029 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 154642800 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3177.792800 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 2910.978089 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks -system.cpu0.l1c.writebacks::total 9668 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35932 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23215 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23215 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59147 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59147 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59147 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59147 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 892144080 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 892144080 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 865359572 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 865359572 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1757503652 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 1757503652 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1757503652 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 897451639 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 561857596 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 561857596 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1459309235 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1459309235 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807243 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807243 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954015 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954015 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859120 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859120 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks +system.cpu0.l1c.writebacks::total 9551 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35875 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35875 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23186 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59061 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59061 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59061 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59061 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 858892486 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 858892486 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 796764078 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 796764078 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1655656564 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1655656564 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1655656564 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1655656564 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 681029068 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 681029068 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 670499371 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 670499371 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1351528439 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1351528439 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807341 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807341 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956637 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956637 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.860032 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860032 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.860032 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 23941.253965 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 23941.253965 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 34364.016130 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 34364.016130 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 28032.992398 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 28032.992398 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -775,114 +778,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 99346 # number of read accesses completed -system.cpu1.num_writes 53405 # number of write accesses completed +system.cpu1.num_reads 99689 # number of read accesses completed +system.cpu1.num_writes 53832 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21836 # number of replacements -system.cpu1.l1c.tagsinuse 395.252412 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13010 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22258 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.584509 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21971 # number of replacements +system.cpu1.l1c.tagsinuse 397.434568 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13255 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22377 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.592349 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 395.252412 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.771977 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.771977 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8468 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8468 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9513 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9513 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9513 # number of overall hits -system.cpu1.l1c.overall_hits::total 9513 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 36170 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 36170 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22843 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22843 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 59013 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 59013 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 59013 # number of overall misses -system.cpu1.l1c.overall_misses::total 59013 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 930956991 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 930956991 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 873445374 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 873445374 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 1804402365 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 1804402365 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 1804402365 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 1804402365 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44638 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44638 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23888 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23888 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68526 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68526 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68526 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68526 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.810296 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.810296 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956254 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.956254 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.861177 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.861177 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.861177 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.861177 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 212850460 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 397.434568 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.776239 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.776239 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8630 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8630 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1103 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1103 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9733 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9733 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9733 # number of overall hits +system.cpu1.l1c.overall_hits::total 9733 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36139 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36139 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23155 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23155 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59294 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59294 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59294 # number of overall misses +system.cpu1.l1c.overall_misses::total 59294 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 902705787 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 902705787 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 819450505 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 819450505 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1722156292 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1722156292 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1722156292 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1722156292 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44769 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44769 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24258 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24258 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 69027 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 69027 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 69027 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 69027 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.807233 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.807233 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954530 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.954530 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.858997 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.858997 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.858997 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.858997 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 24978.715155 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 24978.715155 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 35389.786439 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 35389.786439 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 29044.360171 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 29044.360171 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 29044.360171 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 29044.360171 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 155390130 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 67062 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 53247 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3173.935463 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 2918.288918 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9414 # number of writebacks -system.cpu1.l1c.writebacks::total 9414 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36170 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22843 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22843 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 59013 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 59013 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 59013 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 59013 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 894646237 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 894646237 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 850514976 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 850514976 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1745161213 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 1745161213 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1745161213 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 1745161213 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 906808922 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 906808922 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 573615954 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 573615954 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480424876 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480424876 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.810296 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.810296 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956254 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956254 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.861177 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.861177 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9603 # number of writebacks +system.cpu1.l1c.writebacks::total 9603 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36139 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36139 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23155 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23155 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59294 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59294 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59294 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59294 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 866427236 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 866427236 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 796207895 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 796207895 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1662635131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1662635131 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1662635131 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1662635131 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 674093801 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 674093801 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 675943433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 675943433 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1350037234 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1350037234 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.807233 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.807233 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954530 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954530 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.858997 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.858997 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.858997 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 23974.853648 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 23974.853648 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 34386.002807 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 34386.002807 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 28040.529075 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 28040.529075 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -890,114 +893,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99179 # number of read accesses completed -system.cpu2.num_writes 53408 # number of write accesses completed +system.cpu2.num_reads 99864 # number of read accesses completed +system.cpu2.num_writes 53679 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 21970 # number of replacements -system.cpu2.l1c.tagsinuse 396.422513 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13458 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22394 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.600965 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22117 # number of replacements +system.cpu2.l1c.tagsinuse 397.846327 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13470 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22518 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.598188 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 396.422513 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.774263 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.774263 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8875 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8875 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1083 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1083 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9958 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9958 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9958 # number of overall hits -system.cpu2.l1c.overall_hits::total 9958 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 35921 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 35921 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 23014 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 23014 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 58935 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 58935 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 58935 # number of overall misses -system.cpu2.l1c.overall_misses::total 58935 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 936514854 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 936514854 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 882688372 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 882688372 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 1819203226 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 1819203226 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 1819203226 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 1819203226 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44796 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44796 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 24097 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 24097 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68893 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68893 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68893 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68893 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.801880 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.801880 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955057 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955057 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.855457 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.855457 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.855457 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.855457 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 215347558 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 397.846327 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.777044 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.777044 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8720 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8720 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1090 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1090 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9810 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9810 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9810 # number of overall hits +system.cpu2.l1c.overall_hits::total 9810 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36026 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36026 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23186 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23186 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59212 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59212 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59212 # number of overall misses +system.cpu2.l1c.overall_misses::total 59212 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 899117648 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 899117648 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 813653609 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 813653609 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1712771257 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1712771257 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1712771257 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1712771257 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44746 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44746 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24276 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24276 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69022 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69022 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69022 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69022 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805122 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.805122 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955100 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955100 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857871 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857871 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857871 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857871 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 24957.465386 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 24957.465386 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 35092.452730 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 35092.452730 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 28926.083513 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 28926.083513 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 28926.083513 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 28926.083513 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 153072251 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 67274 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 52648 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3201.051788 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 2907.465640 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9572 # number of writebacks -system.cpu2.l1c.writebacks::total 9572 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35921 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35921 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23014 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 23014 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58935 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58935 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 900454097 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 900454097 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 859588304 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 859588304 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1760042401 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 1760042401 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1760042401 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 1760042401 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 903394412 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 903394412 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 551786925 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 551786925 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1455181337 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1455181337 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.801880 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.801880 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955057 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955057 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.855457 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.855457 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9600 # number of writebacks +system.cpu2.l1c.writebacks::total 9600 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36026 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36026 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23186 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23186 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59212 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59212 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59212 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59212 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 862954550 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 862954550 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 790376865 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 790376865 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1653331415 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1653331415 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1653331415 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1653331415 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 676110998 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 676110998 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 681557695 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 681557695 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1357668693 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1357668693 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805122 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805122 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955100 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955100 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857871 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857871 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857871 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 23953.659857 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 23953.659857 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 34088.538989 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 34088.538989 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 27922.235611 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 27922.235611 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1005,114 +1008,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98310 # number of read accesses completed -system.cpu3.num_writes 53451 # number of write accesses completed +system.cpu3.num_reads 98954 # number of read accesses completed +system.cpu3.num_writes 53519 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 21775 # number of replacements -system.cpu3.l1c.tagsinuse 395.971374 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13179 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22179 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.594211 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21866 # number of replacements +system.cpu3.l1c.tagsinuse 395.683419 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13218 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22277 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.593347 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.971374 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.773382 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.773382 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8374 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8374 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1100 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1100 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9474 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9474 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9474 # number of overall hits -system.cpu3.l1c.overall_hits::total 9474 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35667 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35667 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23305 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23305 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58972 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58972 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58972 # number of overall misses -system.cpu3.l1c.overall_misses::total 58972 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 919630073 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 919630073 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 893117472 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 893117472 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 1812747545 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 1812747545 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 1812747545 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 1812747545 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44041 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44041 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24405 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24405 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68446 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68446 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68446 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68446 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809859 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.809859 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954927 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.954927 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.861584 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.861584 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.861584 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.861584 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 213693223 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.683419 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.772819 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.772819 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1098 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1098 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9660 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9660 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9660 # number of overall hits +system.cpu3.l1c.overall_hits::total 9660 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35996 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35996 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23029 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23029 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59025 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59025 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59025 # number of overall misses +system.cpu3.l1c.overall_misses::total 59025 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 899058428 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 899058428 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 817455350 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 817455350 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1716513778 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1716513778 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1716513778 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1716513778 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44558 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44558 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24127 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24127 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68685 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68685 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68685 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68685 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807846 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.807846 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954491 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954491 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859358 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859358 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859358 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859358 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 24976.620402 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 24976.620402 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 35496.780147 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 35496.780147 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 29081.131351 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 29081.131351 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 29081.131351 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 29081.131351 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 155038956 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 67039 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 53124 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3187.595623 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 2918.435283 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9546 # number of writebacks -system.cpu3.l1c.writebacks::total 9546 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35667 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35667 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23305 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23305 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58972 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58972 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58972 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58972 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 883822339 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 883822339 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869724232 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869724232 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1753546571 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 1753546571 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1753546571 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 1753546571 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 901886993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 901886993 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 561139437 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 561139437 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1463026430 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1463026430 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809859 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809859 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954927 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954927 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.861584 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.861584 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9442 # number of writebacks +system.cpu3.l1c.writebacks::total 9442 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35996 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35996 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23029 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23029 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59025 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59025 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59025 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59025 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 862924447 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 862924447 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 794336234 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 794336234 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1657260681 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1657260681 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1657260681 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1657260681 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 680106792 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 680106792 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 674669668 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 674669668 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1354776460 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1354776460 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807846 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807846 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954491 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954491 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859358 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859358 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859358 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 23972.787171 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 23972.787171 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 34492.866994 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 34492.866994 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 28077.266938 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 28077.266938 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1120,114 +1123,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53697 # number of write accesses completed +system.cpu4.num_reads 99591 # number of read accesses completed +system.cpu4.num_writes 53646 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22069 # number of replacements -system.cpu4.l1c.tagsinuse 396.565187 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13244 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22293 # number of replacements +system.cpu4.l1c.tagsinuse 397.816545 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13327 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22684 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.587507 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 396.565187 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.774541 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.774541 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8614 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8614 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1053 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1053 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9667 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9667 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9667 # number of overall hits -system.cpu4.l1c.overall_hits::total 9667 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36078 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36078 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 23045 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 23045 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59123 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59123 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59123 # number of overall misses -system.cpu4.l1c.overall_misses::total 59123 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 933502205 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 933502205 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 883607398 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 883607398 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 1817109603 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 1817109603 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 1817109603 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 1817109603 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44692 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24098 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24098 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68790 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68790 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68790 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68790 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807259 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.807259 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956303 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.956303 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.859471 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.859471 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.859471 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.859471 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 213249503 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 397.816545 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.776985 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.776985 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8743 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8743 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1036 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1036 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9779 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9779 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9779 # number of overall hits +system.cpu4.l1c.overall_hits::total 9779 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 35998 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 35998 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23232 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23232 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59230 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59230 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59230 # number of overall misses +system.cpu4.l1c.overall_misses::total 59230 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 899681935 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 899681935 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 816003996 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 816003996 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1715685931 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1715685931 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1715685931 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1715685931 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44741 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44741 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24268 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24268 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69009 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69009 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69009 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69009 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804586 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804586 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957310 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.957310 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858294 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858294 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858294 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858294 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 24992.553336 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 24992.553336 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 35124.138946 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 35124.138946 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 28966.502296 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 28966.502296 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 28966.502296 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 28966.502296 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 154355931 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67264 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 53171 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3170.336331 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 2903.009742 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9627 # number of writebacks -system.cpu4.l1c.writebacks::total 9627 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36078 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36078 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23045 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 23045 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59123 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59123 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59123 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59123 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 897285830 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 897285830 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 860474190 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 860474190 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1757760020 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 1757760020 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1757760020 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 1757760020 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 897898466 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 897898466 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 564390024 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 564390024 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1462288490 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1462288490 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807259 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807259 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956303 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956303 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.859471 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.859471 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9702 # number of writebacks +system.cpu4.l1c.writebacks::total 9702 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 35998 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 35998 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23232 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23232 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59230 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59230 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59230 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59230 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 863541936 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 863541936 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 792684079 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 792684079 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1656226015 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1656226015 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1656226015 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1656226015 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 681350371 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 681350371 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 669996228 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 669996228 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1351346599 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1351346599 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804586 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804586 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957310 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957310 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858294 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858294 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858294 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 23988.608700 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 23988.608700 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 34120.354640 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 34120.354640 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 27962.620547 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 27962.620547 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1235,114 +1238,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98755 # number of read accesses completed -system.cpu5.num_writes 53000 # number of write accesses completed +system.cpu5.num_reads 99523 # number of read accesses completed +system.cpu5.num_writes 53948 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 21964 # number of replacements -system.cpu5.l1c.tagsinuse 395.335157 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13162 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22364 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.588535 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22088 # number of replacements +system.cpu5.l1c.tagsinuse 397.555659 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13442 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22486 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.597794 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 395.335157 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.772139 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.772139 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8580 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8580 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1063 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1063 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9643 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9643 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9643 # number of overall hits -system.cpu5.l1c.overall_hits::total 9643 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 36060 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 36060 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22989 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22989 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 59049 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 59049 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 59049 # number of overall misses -system.cpu5.l1c.overall_misses::total 59049 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 944228607 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 944228607 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 875107262 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 875107262 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 1819335869 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 1819335869 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 1819335869 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 1819335869 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44640 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44640 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24052 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24052 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68692 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68692 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68692 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68692 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807796 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.807796 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955804 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.955804 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.859620 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.859620 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 213071792 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 397.555659 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.776476 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.776476 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8700 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8700 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1066 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1066 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9766 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9766 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9766 # number of overall hits +system.cpu5.l1c.overall_hits::total 9766 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36016 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36016 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 23333 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 23333 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59349 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59349 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59349 # number of overall misses +system.cpu5.l1c.overall_misses::total 59349 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 899040098 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 899040098 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 826704780 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 826704780 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1725744878 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1725744878 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1725744878 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1725744878 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44716 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44716 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24399 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24399 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 69115 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 69115 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 69115 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 69115 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805439 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805439 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956310 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.956310 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858699 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858699 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858699 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858699 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 24962.241726 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 24962.241726 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 35430.711010 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 35430.711010 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 29077.909956 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 29077.909956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 29077.909956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 29077.909956 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 155795508 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 67023 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 53352 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3179.084672 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 2920.143725 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9605 # number of writebacks -system.cpu5.l1c.writebacks::total 9605 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36060 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 36060 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22989 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22989 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 59049 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 59049 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 59049 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 59049 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 908030320 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 908030320 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 852027269 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 852027269 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1760057589 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 1760057589 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1760057589 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 1760057589 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 893562759 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 893562759 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567489251 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567489251 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1461052010 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1461052010 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807796 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955804 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9610 # number of writebacks +system.cpu5.l1c.writebacks::total 9610 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36016 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36016 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23333 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 23333 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59349 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59349 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59349 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59349 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 862885041 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 862885041 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 803284460 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 803284460 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1666169501 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1666169501 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1666169501 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1666169501 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 674425818 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 674425818 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 675374924 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 675374924 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1349800742 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1349800742 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805439 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805439 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956310 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956310 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858699 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858699 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858699 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 23958.380747 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 23958.380747 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 34426.968671 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 34426.968671 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 28074.095621 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 28074.095621 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1350,114 +1353,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99515 # number of read accesses completed -system.cpu6.num_writes 53091 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53510 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21875 # number of replacements -system.cpu6.l1c.tagsinuse 395.073790 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13163 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22301 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22177 # number of replacements +system.cpu6.l1c.tagsinuse 397.660479 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13364 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22573 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.592035 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 395.073790 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.771628 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.771628 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8660 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8660 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1070 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1070 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9730 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9730 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9730 # number of overall hits -system.cpu6.l1c.overall_hits::total 9730 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 36079 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 36079 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22730 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22730 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58809 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58809 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58809 # number of overall misses -system.cpu6.l1c.overall_misses::total 58809 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 942403765 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 942403765 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 866225957 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 866225957 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 1808629722 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 1808629722 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 1808629722 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 1808629722 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44739 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44739 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23800 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23800 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68539 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68539 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68539 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68539 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806433 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806433 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955042 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.955042 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858037 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858037 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858037 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858037 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 212806358 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 397.660479 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.776681 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.776681 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8760 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8760 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1035 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1035 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9795 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9795 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9795 # number of overall hits +system.cpu6.l1c.overall_hits::total 9795 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36279 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36279 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59312 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59312 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59312 # number of overall misses +system.cpu6.l1c.overall_misses::total 59312 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 908517794 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 908517794 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 809582336 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 809582336 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1718100130 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1718100130 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1718100130 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1718100130 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45039 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45039 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24068 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24068 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69107 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69107 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69107 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69107 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805502 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805502 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.956997 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.956997 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858263 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858263 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858263 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858263 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 25042.525814 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 25042.525814 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 35148.801111 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 35148.801111 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 28967.158922 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 28967.158922 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 28967.158922 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 28967.158922 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 154185284 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66914 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 52977 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3180.296470 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 2910.419314 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9438 # number of writebacks -system.cpu6.l1c.writebacks::total 9438 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36079 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 36079 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22730 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22730 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58809 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58809 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58809 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58809 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 906189412 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 906189412 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 843405989 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 843405989 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1749595401 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 1749595401 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1749595401 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 1749595401 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 905213986 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 905213986 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 576398345 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 576398345 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1481612331 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1481612331 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806433 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955042 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955042 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858037 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858037 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9564 # number of writebacks +system.cpu6.l1c.writebacks::total 9564 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36279 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36279 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59312 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59312 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59312 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59312 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 872097671 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 872097671 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 786461211 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 786461211 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1658558882 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1658558882 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1658558882 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1658558882 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 680107967 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 680107967 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 681972539 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 681972539 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1362080506 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1362080506 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805502 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805502 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.956997 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.956997 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858263 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858263 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858263 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 24038.635878 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 24038.635878 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 34144.975079 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 34144.975079 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 27963.293802 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 27963.293802 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1465,114 +1468,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98608 # number of read accesses completed -system.cpu7.num_writes 53688 # number of write accesses completed +system.cpu7.num_reads 99201 # number of read accesses completed +system.cpu7.num_writes 53497 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 21767 # number of replacements -system.cpu7.l1c.tagsinuse 394.473547 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13199 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22218 # number of replacements +system.cpu7.l1c.tagsinuse 396.828031 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13271 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22622 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.586641 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 394.473547 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.770456 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.770456 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8649 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8649 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 995 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 995 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9644 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9644 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9644 # number of overall hits -system.cpu7.l1c.overall_hits::total 9644 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35884 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35884 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23099 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23099 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58983 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58983 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58983 # number of overall misses -system.cpu7.l1c.overall_misses::total 58983 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 932010776 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 932010776 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 877703149 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 877703149 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 1809713925 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 1809713925 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 1809713925 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 1809713925 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44533 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44533 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24094 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24094 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68627 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68627 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68627 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68627 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805784 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805784 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.958703 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.958703 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.859472 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.859472 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.859472 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.859472 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 213241981 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 396.828031 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.775055 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.775055 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8703 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8703 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1096 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1096 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9799 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9799 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9799 # number of overall hits +system.cpu7.l1c.overall_hits::total 9799 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36453 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36453 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 22910 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 22910 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59363 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59363 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59363 # number of overall misses +system.cpu7.l1c.overall_misses::total 59363 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 908883238 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 908883238 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 808946616 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 808946616 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1717829854 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1717829854 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1717829854 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1717829854 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 45156 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69162 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69162 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69162 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69162 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807268 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807268 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954345 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954345 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858318 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858318 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858318 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858318 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 24933.016158 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 24933.016158 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 35309.760629 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 35309.760629 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 28937.719691 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 28937.719691 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 28937.719691 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 28937.719691 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 153732048 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 53029 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 2899.018424 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9457 # number of writebacks -system.cpu7.l1c.writebacks::total 9457 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35884 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23099 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58983 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58983 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 895990178 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 854514720 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1750504898 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9581 # number of writebacks +system.cpu7.l1c.writebacks::total 9581 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36453 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36453 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22910 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 22910 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59363 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59363 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59363 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59363 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 872289420 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 872289420 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 785947981 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 785947981 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1658237401 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1658237401 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1658237401 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1658237401 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 674384984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 674384984 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 681937361 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 681937361 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1356322345 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1356322345 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807268 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807268 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954345 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954345 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858318 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858318 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858318 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 23929.153156 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 23929.153156 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 34305.891794 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 34305.891794 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 27933.854438 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 27933.854438 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |