stats: Update stats to reflect cache changes

Removed unused stats, now counting WriteLineReq, and changed how
uncacheable writes are handled while responses are outstanding.

1 files changed, 5 insertions, 14 deletions

diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 8e6ab353a..e76d0cce6 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.134742                       # Nu
 sim_ticks                                134741611500                       # Number of ticks simulated
 final_tick                               134741611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 536259                       # Simulator instruction rate (inst/s)
-host_op_rate                                   536259                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              817928903                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239376                       # Number of bytes of host memory used
-host_seconds                                   164.74                       # Real time elapsed on the host
+host_inst_rate                                1303886                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1303885                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1988750581                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 260188                       # Number of bytes of host memory used
+host_seconds                                    67.75                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -198,8 +198,6 @@ system.cpu.dcache.blocked::no_mshrs                 0                       # nu
 system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       168278                       # number of writebacks
 system.cpu.dcache.writebacks::total            168278                       # number of writebacks
 system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
@@ -234,7 +232,6 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements             74391                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1870.507754                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
@@ -294,8 +291,6 @@ system.cpu.icache.blocked::no_mshrs                 0                       # nu
 system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
 system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.writebacks::writebacks        74391                       # number of writebacks
 system.cpu.icache.writebacks::total             74391                       # number of writebacks
 system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
@@ -322,7 +317,6 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements           131998                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30708.485304                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             247404                       # Total number of references to valid blocks.
@@ -431,8 +425,6 @@ system.cpu.l2cache.blocked::no_mshrs                0                       # nu
 system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
 system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks       114382                       # number of writebacks
 system.cpu.l2cache.writebacks::total           114382                       # number of writebacks
 system.cpu.l2cache.CleanEvict_mshr_misses::writebacks          105                       # number of CleanEvict MSHR misses
@@ -487,7 +479,6 @@ system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49503.609547
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49558.536585                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.619236                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49503.609547                       # average overall mshr miss latency
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.snoop_filter.tot_requests       555419                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests       274639                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.