stats: Update stats to reflect snoop-filter changes

1 files changed, 91 insertions, 85 deletions

diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index e9eb9ae35..9438e6b22 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -1,14 +1,14 @@
 
 ---------- Begin Simulation Statistics ----------
 sim_seconds                                  0.202233                       # Number of seconds simulated
-sim_ticks                                202232894500                       # Number of ticks simulated
-final_tick                               202232894500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks                                202232960500                       # Number of ticks simulated
+final_tick                               202232960500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1204132                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1219723                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1811881435                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 302340                       # Number of bytes of host memory used
-host_seconds                                   111.61                       # Real time elapsed on the host
+host_inst_rate                                1135828                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1150535                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1709104516                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 304720                       # Number of bytes of host memory used
+host_seconds                                   118.33                       # Real time elapsed on the host
 sim_insts                                   134398962                       # Number of instructions simulated
 sim_ops                                     136139190                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -25,20 +25,20 @@ system.physmem.num_reads::cpu.data             122297                       # Nu
 system.physmem.num_reads::total                131292                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks           85205                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total                85205                       # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst              2846619                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data             38702942                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                41549561                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst         2846619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total            2846619                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks          26964555                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total               26964555                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks          26964555                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             2846619                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data            38702942                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total               68514116                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst              2846618                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data             38702929                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                41549548                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst         2846618                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total            2846618                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks          26964546                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total               26964546                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks          26964546                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst             2846618                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data            38702929                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total               68514094                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
-system.cpu.numCycles                        404465789                       # number of cpu cycles simulated
+system.cpu.numCycles                        404465921                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   134398962                       # Number of instructions committed
@@ -57,7 +57,7 @@ system.cpu.num_mem_refs                      58160248                       # nu
 system.cpu.num_load_insts                    37275867                       # Number of load instructions
 system.cpu.num_store_insts                   20884381                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               404465788.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               404465920.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          12719095                       # Number of branches fetched
@@ -97,12 +97,12 @@ system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Cl
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  136293798                       # Class of executed instruction
 system.cpu.dcache.tags.replacements            146582                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          4087.647933                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          4087.647896                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            57960842                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs            384.666919                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle         769041500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  4087.647933                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.warmup_cycle         769043500                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data  4087.647896                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.997961                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         4096                       # Occupied blocks per task id
@@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data       150663                       # n
 system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
 system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data   1475169000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total   1475169000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1475184000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1475184000                       # number of ReadReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::cpu.data   5620115500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total   5620115500                       # number of WriteReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::cpu.data       405000                       # number of SwapReq miss cycles
 system.cpu.dcache.SwapReq_miss_latency::total       405000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data   7095284500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total   7095284500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data   7095284500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total   7095284500                       # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7095299500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7095299500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7095299500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7095299500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     37231300                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
@@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_miss_rate::total     0.002593                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.338953                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.338953                       # average ReadReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086                       # average WriteReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        27000                       # average SwapReq miss latency
 system.cpu.dcache.SwapReq_avg_miss_latency::total        27000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 47093.742326                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 47093.742326                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.841886                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 47093.841886                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.841886                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 47093.841886                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data       150663
 system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1429670000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total   1429670000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1429685000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1429685000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5514951500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total   5514951500                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       390000                       # number of SwapReq MSHR miss cycles
 system.cpu.dcache.SwapReq_mshr_miss_latency::total       390000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6944621500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total   6944621500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6944621500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total   6944621500                       # number of overall MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6944636500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6944636500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6944636500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6944636500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.001222                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
@@ -212,24 +212,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593
 system.cpu.dcache.demand_mshr_miss_rate::total     0.002593                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.338953                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.338953                       # average ReadReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086                       # average WriteReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        26000                       # average SwapReq mshr miss latency
 system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total        26000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.841886                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.841886                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.841886                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.841886                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements            184976                       # number of replacements
-system.cpu.icache.tags.tagsinuse          2004.814775                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          2004.814767                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366547                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs            187024                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs            718.445478                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle      143962972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  2004.814775                       # Average occupied blocks per requestor
+system.cpu.icache.tags.warmup_cycle      143963003500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst  2004.814767                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.978913                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.978913                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         2048                       # Occupied blocks per task id
@@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst       187024                       # n
 system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
 system.cpu.icache.overall_misses::total        187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst   2809817000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total   2809817000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst   2809817000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total   2809817000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst   2809817000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total   2809817000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2809868000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2809868000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2809868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2809868000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2809868000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2809868000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    134553571                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    134553571                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    134553571                       # number of demand (read+write) accesses
@@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.001390
 system.cpu.icache.demand_miss_rate::total     0.001390                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 15023.831166                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 15023.831166                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15024.103858                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 15024.103858                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15024.103858                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 15024.103858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15024.103858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 15024.103858                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -291,34 +291,34 @@ system.cpu.icache.demand_mshr_misses::cpu.inst       187024
 system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2622793000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total   2622793000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2622793000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total   2622793000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2622793000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total   2622793000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2622844000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2622844000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2622844000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2622844000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2622844000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2622844000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.001390                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.001390                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14024.103858                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14024.103858                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14024.103858                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 14024.103858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14024.103858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 14024.103858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.tags.replacements            98298                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse        30848.444766                       # Cycle average of tags in use
+system.cpu.l2cache.tags.tagsinuse        30848.444719                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             433066                       # Total number of references to valid blocks.
 system.cpu.l2cache.tags.sampled_refs           129294                       # Sample count of references to valid blocks.
 system.cpu.l2cache.tags.avg_refs             3.349467                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828940                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  3594.810202                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data  1299.805624                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::writebacks 25953.828709                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  3594.810369                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1299.805642                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.792048                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.109705                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.039667                       # Average percentage of cache occupancy
@@ -471,6 +471,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.toL2Bus.snoop_filter.tot_requests       669260                       # Total number of requests made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_requests       331558                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_requests           66                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.snoop_filter.tot_snoops         3540                       # Total number of snoops made to the snoop filter.
+system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3540                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.trans_dist::ReadResp        232523                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::Writeback       209101                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::CleanEvict       220689                       # Transaction distribution
@@ -486,15 +492,15 @@ system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_s
 system.cpu.toL2Bus.pkt_size::total           29542272                       # Cumulative packet size per connected master and slave (bytes)
 system.cpu.toL2Bus.snoops                       98298                       # Total snoops (count)
 system.cpu.toL2Bus.snoop_fanout::samples       767558                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean        1.128066                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev       0.334163                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean        0.004784                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev       0.069001                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0                  0      0.00%      0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1             669260     87.19%     87.19% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2              98298     12.81%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0             763886     99.52%     99.52% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1               3672      0.48%    100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2                  0      0.00%    100.00% # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value            1                       # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value            1                       # Request fanout histogram
 system.cpu.toL2Bus.snoop_fanout::total         767558                       # Request fanout histogram
 system.cpu.toL2Bus.reqLayer0.occupancy      458526000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.reqLayer0.utilization          0.2                       # Layer utilization (%)