diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/quick/se/50.vortex/ref | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/quick/se/50.vortex/ref')
3 files changed, 833 insertions, 782 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt index 987ba828d..8965da370 100644 --- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.133634 # Number of seconds simulated -sim_ticks 133634149500 # Number of ticks simulated -final_tick 133634149500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.133625 # Number of seconds simulated +sim_ticks 133625300500 # Number of ticks simulated +final_tick 133625300500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1329181 # Simulator instruction rate (inst/s) -host_op_rate 1329181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2010669405 # Simulator tick rate (ticks/s) -host_mem_usage 301232 # Number of bytes of host memory used -host_seconds 66.46 # Real time elapsed on the host +host_inst_rate 1195401 # Simulator instruction rate (inst/s) +host_op_rate 1195401 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808178963 # Simulator tick rate (ticks/s) +host_mem_usage 302688 # Number of bytes of host memory used +host_seconds 73.90 # Real time elapsed on the host sim_insts 88340673 # Number of instructions simulated sim_ops 88340673 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 432896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 10136896 # Number of bytes read from this memory -system.physmem.bytes_read::total 10569792 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 432896 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7294848 # Number of bytes written to this memory -system.physmem.bytes_written::total 7294848 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 6764 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 158389 # Number of read requests responded to by this memory -system.physmem.num_reads::total 165153 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 113982 # Number of write requests responded to by this memory -system.physmem.num_writes::total 113982 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 3239411 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 75855581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 79094992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 3239411 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 54588202 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 54588202 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3239411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 75855581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 133683195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 419712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 10136000 # Number of bytes read from this memory +system.physmem.bytes_read::total 10555712 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 419712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 419712 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7316416 # Number of bytes written to this memory +system.physmem.bytes_written::total 7316416 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 6558 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 158375 # Number of read requests responded to by this memory +system.physmem.num_reads::total 164933 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 114319 # Number of write requests responded to by this memory +system.physmem.num_writes::total 114319 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 3140962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 75853899 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 78994861 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 3140962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 3140962 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 54753224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 54753224 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 54753224 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3140962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 75853899 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 133748085 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -70,7 +70,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4583 # Number of system calls -system.cpu.numCycles 267268299 # number of cpu cycles simulated +system.cpu.numCycles 267250601 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 88340673 # Number of instructions committed @@ -89,7 +89,7 @@ system.cpu.num_mem_refs 34987415 # nu system.cpu.num_load_insts 20366786 # Number of load instructions system.cpu.num_store_insts 14620629 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 267268299 # Number of busy cycles +system.cpu.num_busy_cycles 267250601 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.Branches 13754477 # Number of branches fetched @@ -129,12 +129,12 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 88438073 # Class of executed instruction system.cpu.dcache.tags.replacements 200248 # number of replacements -system.cpu.dcache.tags.tagsinuse 4078.863526 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4078.862376 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 34685671 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 169.741568 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 936464000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4078.863526 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 936464500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4078.862376 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995816 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995816 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -160,14 +160,14 @@ system.cpu.dcache.demand_misses::cpu.data 204344 # n system.cpu.dcache.demand_misses::total 204344 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 204344 # number of overall misses system.cpu.dcache.overall_misses::total 204344 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1945427000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 7363527000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 9308954000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 9308954000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 9308954000 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1944960000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1944960000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7363504500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7363504500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9308464500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9308464500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9308464500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9308464500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses) @@ -184,14 +184,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_miss_rate::total 0.005857 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.005857 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.005857 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32015.057763 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32015.057763 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.900347 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.900347 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45555.308695 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45555.308695 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32007.372544 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32007.372544 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 51285.743638 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 51285.743638 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45552.913225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45552.913225 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45552.913225 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -200,8 +200,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 168375 # number of writebacks -system.cpu.dcache.writebacks::total 168375 # number of writebacks +system.cpu.dcache.writebacks::writebacks 168314 # number of writebacks +system.cpu.dcache.writebacks::total 168314 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60766 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143578 # number of WriteReq MSHR misses @@ -210,14 +210,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 204344 system.cpu.dcache.demand_mshr_misses::total 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 204344 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1854278000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 7148160000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9002438000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9002438000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9002438000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1884194000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1884194000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7219926500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7219926500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9104120500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9104120500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9104120500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9104120500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses @@ -226,27 +226,27 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30515.057763 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 49785.900347 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44055.308695 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44055.308695 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31007.372544 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31007.372544 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50285.743638 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50285.743638 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44552.913225 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44552.913225 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 74391 # number of replacements -system.cpu.icache.tags.tagsinuse 1871.686268 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1871.687345 # Cycle average of tags in use system.cpu.icache.tags.total_refs 88361638 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 76436 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 1156.021220 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1871.686268 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.913909 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.913909 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 1871.687345 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.913910 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.913910 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2045 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1708 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.998535 # Percentage of cache occupancy per task id @@ -264,12 +264,12 @@ system.cpu.icache.demand_misses::cpu.inst 76436 # n system.cpu.icache.demand_misses::total 76436 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 76436 # number of overall misses system.cpu.icache.overall_misses::total 76436 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 1277887500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 1277887500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 1277887500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 1277887500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 1277887500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 1269528000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 1269528000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 1269528000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 1269528000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 1269528000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 1269528000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 88438074 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 88438074 # number of demand (read+write) accesses @@ -282,12 +282,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000864 system.cpu.icache.demand_miss_rate::total 0.000864 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000864 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000864 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16718.398399 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 16718.398399 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 16718.398399 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 16718.398399 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16609.032393 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 16609.032393 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 16609.032393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 16609.032393 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 16609.032393 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,117 +302,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 76436 system.cpu.icache.demand_mshr_misses::total 76436 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 76436 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 76436 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 1163233500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 1163233500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1163233500 # 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Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 654 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 655 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::2 9977 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21193 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 117 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 21188 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 122 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978271 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3900109 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3900109 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 69672 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.911567 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.911567 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.088492 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.775110 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.588194 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.088492 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.775110 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.588194 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.441159 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52504.834957 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52507.717670 # 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number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 130881 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 6764 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 158389 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 165153 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 6764 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 158389 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 165153 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 274073000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1114207000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1388280000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5300691500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5300691500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 274073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6414898500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 6688971500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 274073000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6414898500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 6688971500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.452687 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.249792 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911567 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.588194 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.088492 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775110 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.588194 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40519.367238 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40504.834957 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40507.703081 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.084046 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.084046 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40519.367238 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500.909154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40501.665123 # average overall mshr miss latency +system.cpu.l2cache.writebacks::writebacks 114319 # number of writebacks +system.cpu.l2cache.writebacks::total 114319 # number of writebacks +system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 1879 # number of CleanEvict MSHR misses +system.cpu.l2cache.CleanEvict_mshr_misses::total 1879 # number of CleanEvict MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130880 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 130880 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 6558 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 6558 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 27495 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 27495 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 6558 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 158375 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 164933 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 6558 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 158375 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 164933 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5562430500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5562430500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 279096500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 279096500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1168749500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1168749500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 279096500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6731180000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 7010276500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 279096500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6731180000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 7010276500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.911560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.911560 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.085797 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.452473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.452473 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.587410 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.085797 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775041 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.587410 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42500.233038 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42500.233038 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42558.173224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42558.173224 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42507.710493 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42507.710493 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42558.173224 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42501.531176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42503.783354 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 137202 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 137202 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 168375 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 282633 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 123022 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 143578 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 143578 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 152872 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577063 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 729935 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 76436 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 60766 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 227263 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 608936 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 836199 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 4891904 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23854016 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28745920 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 449155 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23850112 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 28742016 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 131016 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 686435 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.190864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.392983 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 449155 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 555419 80.91% 80.91% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 131016 19.09% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 449155 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 392952500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 686435 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 446023500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 114654000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 306516000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 34272 # Transaction distribution -system.membus.trans_dist::ReadResp 34272 # Transaction distribution -system.membus.trans_dist::Writeback 113982 # Transaction distribution -system.membus.trans_dist::ReadExReq 130881 # Transaction distribution -system.membus.trans_dist::ReadExResp 130881 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 444288 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17864640 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 17864640 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 34053 # Transaction distribution +system.membus.trans_dist::Writeback 114319 # Transaction distribution +system.membus.trans_dist::CleanEvict 14713 # Transaction distribution +system.membus.trans_dist::ReadExReq 130880 # Transaction distribution +system.membus.trans_dist::ReadExResp 130880 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34053 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 458898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 458898 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17872128 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 17872128 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 279135 # Request fanout histogram +system.membus.snoop_fanout::samples 294098 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 279135 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 294098 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 279135 # Request fanout histogram -system.membus.reqLayer0.occupancy 748161500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 294098 # Request fanout histogram +system.membus.reqLayer0.occupancy 751484676 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 825765500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 824727676 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.6 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 90d753109..22fc38403 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,41 +1,41 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127293406500 # Number of ticks simulated -final_tick 127293406500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 127292683500 # Number of ticks simulated +final_tick 127292683500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 627920 # Simulator instruction rate (inst/s) -host_op_rate 801678 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1135795886 # Simulator tick rate (ticks/s) -host_mem_usage 312172 # Number of bytes of host memory used -host_seconds 112.07 # Real time elapsed on the host +host_inst_rate 884807 # Simulator instruction rate (inst/s) +host_op_rate 1129650 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1600449674 # Simulator tick rate (ticks/s) +host_mem_usage 320712 # Number of bytes of host memory used +host_seconds 79.54 # Real time elapsed on the host sim_insts 70373629 # Number of instructions simulated sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 252800 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7924480 # Number of bytes read from this memory -system.physmem.bytes_read::total 8179968 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 255488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5370176 # Number of bytes written to this memory -system.physmem.bytes_written::total 5370176 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 3992 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 8177280 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 252800 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5511360 # Number of bytes written to this memory +system.physmem.bytes_written::total 5511360 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 3950 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 123820 # Number of read requests responded to by this memory -system.physmem.num_reads::total 127812 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253656 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260736 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187385 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187385 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253656 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106448121 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 127770 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 86115 # Number of write requests responded to by this memory +system.physmem.num_writes::total 86115 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 1985974 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62254010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64239984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1985974 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 43296754 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 43296754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1985974 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62254010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 107536738 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,7 +154,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254586813 # number of cpu cycles simulated +system.cpu.numCycles 254585367 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 70373629 # Number of instructions committed @@ -175,7 +175,7 @@ system.cpu.num_mem_refs 43422001 # nu system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254586812.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254585366.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 13741486 # Number of branches fetched @@ -215,53 +215,53 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389329 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 4076.389202 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42608158 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061071000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389329 # Average occupied blocks per requestor +system.cpu.dcache.tags.avg_refs 266.304316 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 1061071500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389202 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 856 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3191 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 857 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3190 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 85731098 # Number of tag accesses system.cpu.dcache.tags.data_accesses 85731098 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 22749839 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 22749839 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 22749833 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 22749833 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 19742869 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 19742869 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 83623 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 83623 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 83618 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 83618 # number of SoftPFReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 42492708 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 42492708 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 42576331 # number of overall hits -system.cpu.dcache.overall_hits::total 42576331 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 30228 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 30228 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 42492702 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 42492702 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 42576320 # number of overall hits +system.cpu.dcache.overall_hits::total 42576320 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 30234 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 30234 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 107032 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 107032 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 40121 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 40121 # number of SoftPFReq misses -system.cpu.dcache.demand_misses::cpu.data 137260 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 137260 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 177381 # number of overall misses -system.cpu.dcache.overall_misses::total 177381 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 517066000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 517066000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5689116000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6206182000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6206182000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6206182000 # number of overall miss cycles +system.cpu.dcache.SoftPFReq_misses::cpu.data 40126 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 40126 # number of SoftPFReq misses +system.cpu.dcache.demand_misses::cpu.data 137266 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137266 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 177392 # number of overall misses +system.cpu.dcache.overall_misses::total 177392 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 516863000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 516863000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5689129500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 6205992500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 6205992500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 6205992500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22780067 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) @@ -280,20 +280,20 @@ system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.001327 system.cpu.dcache.ReadReq_miss_rate::total 0.001327 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.005392 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.005392 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324226 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.324226 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.324266 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.324266 # miss rate for SoftPFReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.003220 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.003220 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.004149 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.004149 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17105.531295 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 17105.531295 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.412064 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.412064 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45214.789451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45214.789451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34987.862285 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34987.862285 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17095.422372 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 17095.422372 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53153.538194 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53153.538194 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45211.432547 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45211.432547 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34984.624448 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34984.624448 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -302,14 +302,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 128239 # number of writebacks -system.cpu.dcache.writebacks::total 128239 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1120 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 1120 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 1120 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 1120 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 1120 # number of overall MSHR hits +system.cpu.dcache.writebacks::writebacks 128193 # number of writebacks +system.cpu.dcache.writebacks::total 128193 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 1126 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 1126 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 1126 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 1126 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29108 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 29108 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107032 # number of WriteReq MSHR misses @@ -320,16 +320,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 136140 system.cpu.dcache.demand_mshr_misses::total 136140 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 159998 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 159998 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 457995500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5528568000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1058278000 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5986563500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7044841500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7044841500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 472117000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5582097500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1070376500 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6054214500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7124591000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7124591000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001278 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses @@ -340,24 +340,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003194 system.cpu.dcache.demand_mshr_miss_rate::total 0.003194 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15734.351381 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51653.412064 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44357.364406 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 43973.582342 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 43973.582342 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 16219.492923 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52153.538194 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 44864.468941 # average SoftPFReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44470.504628 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 44470.504628 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44529.250366 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 44529.250366 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672960 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 1733.672092 # Cycle average of tags in use system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672960 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672092 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -380,12 +380,12 @@ system.cpu.icache.demand_misses::cpu.inst 18908 # n system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses system.cpu.icache.overall_misses::total 18908 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 413935000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 413935000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 412325000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 412325000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 412325000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 412325000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 412325000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses @@ -398,12 +398,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 system.cpu.icache.demand_miss_rate::total 0.000242 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000242 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21892.056272 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 21892.056272 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 21892.056272 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 21892.056272 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21806.907129 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 21806.907129 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 21806.907129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 21806.907129 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -418,117 +418,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 18908 system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 18908 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 385573000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 385573000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 385573000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 385573000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 393417000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 393417000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 393417000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 393417000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000242 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000242 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000242 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000242 # 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Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1197.496373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1482.597680 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.844433 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.036545 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.045245 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.926223 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 31095 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1359 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15103 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13917 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 607 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1360 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 15122 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13873 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 632 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.948944 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 2689980 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 2689980 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 14916 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 31426 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 46342 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 128239 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5016336000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5178114000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 161778000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5016336000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5178114000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.355233 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 127770 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4348853500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4348853500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 168471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 168471500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 917668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 917668500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168471500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5266522000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5434993500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168471500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5266522000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5434993500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955602 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955602 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for demand accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.208906 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.406676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.406676 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.714409 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.211128 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.714174 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.208906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.773885 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.714409 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40525.551102 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40575.185701 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40567.425192 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500.063551 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40525.551102 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40513.131966 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40513.519857 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.714174 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42519.099531 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42651.012658 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42602.994429 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42651.012658 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42533.694072 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42537.320967 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 71874 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 71874 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 128239 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 214308 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 49439 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 107032 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 107032 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 37816 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 448235 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 486051 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 18908 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 52966 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 53606 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 473302 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 526908 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1210112 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18447168 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18444224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 19654336 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 94651 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 446349 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.212056 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.408765 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 351698 78.79% 78.79% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 94651 21.21% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 446349 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 304042000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 28362000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 239997000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.trans_dist::ReadReq 25532 # Transaction distribution -system.membus.trans_dist::ReadResp 25532 # Transaction distribution -system.membus.trans_dist::Writeback 83909 # Transaction distribution +system.membus.trans_dist::ReadResp 25490 # Transaction distribution +system.membus.trans_dist::Writeback 86115 # Transaction distribution +system.membus.trans_dist::CleanEvict 6526 # Transaction distribution system.membus.trans_dist::ReadExReq 102280 # Transaction distribution system.membus.trans_dist::ReadExResp 102280 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 339533 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13550144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13550144 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadSharedReq 25490 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 348181 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13688640 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13688640 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214640 # Request fanout histogram +system.membus.snoop_fanout::samples 220592 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214640 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 220592 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214640 # Request fanout histogram -system.membus.reqLayer0.occupancy 566253984 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 220592 # Request fanout histogram +system.membus.reqLayer0.occupancy 568748288 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 642220500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 641607492 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.5 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt index 718e317fa..e9eb9ae35 100644 --- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt @@ -1,44 +1,44 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.202242 # Number of seconds simulated -sim_ticks 202242028500 # Number of ticks simulated -final_tick 202242028500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.202233 # Number of seconds simulated +sim_ticks 202232894500 # Number of ticks simulated +final_tick 202232894500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1201078 # Simulator instruction rate (inst/s) -host_op_rate 1216630 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1807368744 # Simulator tick rate (ticks/s) -host_mem_usage 300888 # Number of bytes of host memory used -host_seconds 111.90 # Real time elapsed on the host +host_inst_rate 1204132 # Simulator instruction rate (inst/s) +host_op_rate 1219723 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1811881435 # Simulator tick rate (ticks/s) +host_mem_usage 302340 # Number of bytes of host memory used +host_seconds 111.61 # Real time elapsed on the host sim_insts 134398962 # Number of instructions simulated sim_ops 136139190 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 591488 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7826624 # Number of bytes read from this memory -system.physmem.bytes_read::total 8418112 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 591488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 5303552 # Number of bytes written to this memory -system.physmem.bytes_written::total 5303552 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 9242 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 122291 # Number of read requests responded to by this memory -system.physmem.num_reads::total 131533 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 82868 # Number of write requests responded to by this memory -system.physmem.num_writes::total 82868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 2924654 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 38699295 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 41623950 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2924654 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 26223788 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 26223788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2924654 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 38699295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 67847737 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 575680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7827008 # Number of bytes read from this memory +system.physmem.bytes_read::total 8402688 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 575680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 575680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 5453120 # Number of bytes written to this memory +system.physmem.bytes_written::total 5453120 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 8995 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 122297 # Number of read requests responded to by this memory +system.physmem.num_reads::total 131292 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 85205 # Number of write requests responded to by this memory +system.physmem.num_writes::total 85205 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.inst 2846619 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 38702942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 41549561 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2846619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2846619 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 26964555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 26964555 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 26964555 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2846619 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 38702942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 68514116 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 404484057 # number of cpu cycles simulated +system.cpu.numCycles 404465789 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 134398962 # Number of instructions committed @@ -57,7 +57,7 @@ system.cpu.num_mem_refs 58160248 # nu system.cpu.num_load_insts 37275867 # Number of load instructions system.cpu.num_store_insts 20884381 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 404484056.998000 # Number of busy cycles +system.cpu.num_busy_cycles 404465788.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.Branches 12719095 # Number of branches fetched @@ -97,18 +97,18 @@ system.cpu.op_class::IprAccess 0 0.00% 100.00% # Cl system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 136293798 # Class of executed instruction system.cpu.dcache.tags.replacements 146582 # number of replacements -system.cpu.dcache.tags.tagsinuse 4087.648320 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4087.647933 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 57960842 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 150678 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 384.666919 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 769041000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4087.648320 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 769041500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4087.647933 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.997961 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 3530 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 530 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 3529 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 116373718 # Number of tag accesses system.cpu.dcache.tags.data_accesses 116373718 # Number of data accesses @@ -132,16 +132,16 @@ system.cpu.dcache.demand_misses::cpu.data 150663 # n system.cpu.dcache.demand_misses::total 150663 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 150663 # number of overall misses system.cpu.dcache.overall_misses::total 150663 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 1475000000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 5619674000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 5619674000 # number of WriteReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 1475169000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5620115500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5620115500 # number of WriteReq miss cycles system.cpu.dcache.SwapReq_miss_latency::cpu.data 405000 # number of SwapReq miss cycles system.cpu.dcache.SwapReq_miss_latency::total 405000 # number of SwapReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 7094674000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 7094674000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 7094674000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 7095284500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 7095284500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 7095284500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 7095284500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 37231300 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 20864304 # number of WriteReq accesses(hits+misses) @@ -162,16 +162,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_miss_rate::total 0.002593 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.002593 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.002593 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32418.294908 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32418.294908 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53437.240881 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 53437.240881 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32422.009275 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32422.009275 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53441.439086 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 53441.439086 # average WriteReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 27000 # average SwapReq miss latency system.cpu.dcache.SwapReq_avg_miss_latency::total 27000 # average SwapReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47089.690236 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47089.690236 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47093.742326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47093.742326 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47093.742326 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -180,8 +180,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 123970 # number of writebacks -system.cpu.dcache.writebacks::total 123970 # number of writebacks +system.cpu.dcache.writebacks::writebacks 123896 # number of writebacks +system.cpu.dcache.writebacks::total 123896 # number of writebacks system.cpu.dcache.ReadReq_mshr_misses::cpu.data 45499 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 45499 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 105164 # number of WriteReq MSHR misses @@ -192,16 +192,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 150663 system.cpu.dcache.demand_mshr_misses::total 150663 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 150663 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 150663 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1406751500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5461928000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.SwapReq_mshr_miss_latency::total 382500 # number of SwapReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6868679500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6868679500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6868679500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1429670000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5514951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5514951500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 390000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.SwapReq_mshr_miss_latency::total 390000 # number of SwapReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6944621500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6944621500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6944621500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6944621500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001222 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005040 # mshr miss rate for WriteReq accesses @@ -212,29 +212,29 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002593 system.cpu.dcache.demand_mshr_miss_rate::total 0.002593 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002593 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.002593 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 30918.294908 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51937.240881 # average WriteReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 25500 # average SwapReq mshr miss latency -system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 25500 # average SwapReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45589.690236 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 45589.690236 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31422.009275 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52441.439086 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52441.439086 # average WriteReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 26000 # average SwapReq mshr miss latency +system.cpu.dcache.SwapReq_avg_mshr_miss_latency::total 26000 # average SwapReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46093.742326 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 46093.742326 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 184976 # number of replacements -system.cpu.icache.tags.tagsinuse 2004.815289 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 2004.814775 # Cycle average of tags in use system.cpu.icache.tags.total_refs 134366547 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 187024 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 718.445478 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 143972077000 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 2004.815289 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.978914 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.978914 # Average percentage of cache occupancy +system.cpu.icache.tags.warmup_cycle 143962972500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 2004.814775 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.978913 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.978913 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2048 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 89 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 88 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 75 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 456 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1427 # Occupied blocks per task id @@ -253,12 +253,12 @@ system.cpu.icache.demand_misses::cpu.inst 187024 # n system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 187024 # number of overall misses system.cpu.icache.overall_misses::total 187024 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 2819561500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 2819561500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 2819561500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 2819561500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 2819561500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 2809817000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 2809817000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 2809817000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 2809817000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 2809817000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 2809817000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 134553571 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 134553571 # number of demand (read+write) accesses @@ -271,12 +271,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.001390 system.cpu.icache.demand_miss_rate::total 0.001390 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.001390 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.001390 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15075.934105 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 15075.934105 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 15075.934105 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 15075.934105 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15023.831166 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 15023.831166 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 15023.831166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 15023.831166 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 15023.831166 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -291,117 +291,123 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187024 system.cpu.icache.demand_mshr_misses::total 187024 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187024 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187024 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 2539025500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 2539025500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2539025500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 2539025500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 2622793000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 2622793000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 2622793000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 2622793000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 2622793000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 2622793000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001390 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.001390 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001390 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.001390 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 13575.934105 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13575.934105 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 13575.934105 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 14023.831166 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 14023.831166 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14023.831166 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 14023.831166 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 98540 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30850.758845 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 226933 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129534 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 1.751918 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 98298 # number of replacements +system.cpu.l2cache.tags.tagsinuse 30848.444766 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 433066 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 129294 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 3.349467 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 26245.549112 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 3385.945467 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1219.264265 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.800951 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.103331 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.037209 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.941490 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 30994 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 533 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12212 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17536 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 585 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.945862 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3928089 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3928089 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 177782 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 24464 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 202246 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 123970 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 123970 # number of Writeback hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 3923 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 3923 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 177782 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 28387 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 206169 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 177782 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 28387 # number of overall hits -system.cpu.l2cache.overall_hits::total 206169 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 9242 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 21035 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 30277 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 101256 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 101256 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 9242 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 122291 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 131533 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 9242 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 122291 # number of overall misses -system.cpu.l2cache.overall_misses::total 131533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 485290500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1104380500 # 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number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 382644500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5198024000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5580668500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 382644500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5198024000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5580668500 # number of overall MSHR miss cycles +system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.962730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.962730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.048095 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.462384 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.462384 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.388781 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.048095 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811645 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.388781 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42503.115772 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42503.115772 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 42539.688716 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42539.688716 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 42504.087841 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42504.087841 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42539.688716 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42503.282991 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42505.777199 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 232523 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 232523 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 123970 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 209101 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 220689 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 105179 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 105179 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 374048 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 425326 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 799374 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.trans_dist::ReadCleanReq 187024 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 45499 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 558971 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 447925 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 1006896 # Packet count per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 11969536 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17577472 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 29547008 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 461672 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17572736 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 29542272 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 98298 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 767558 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.128066 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.334163 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 461672 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 669260 87.19% 87.19% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 98298 12.81% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 461672 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 354806000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 767558 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 458526000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 280536000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 226017000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.trans_dist::ReadReq 30277 # Transaction distribution -system.membus.trans_dist::ReadResp 30277 # Transaction distribution -system.membus.trans_dist::Writeback 82868 # Transaction distribution -system.membus.trans_dist::ReadExReq 101256 # Transaction distribution -system.membus.trans_dist::ReadExResp 101256 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 345934 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13721664 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 13721664 # Cumulative packet size per connected master and slave (bytes) +system.membus.trans_dist::ReadResp 30033 # Transaction distribution +system.membus.trans_dist::Writeback 85205 # Transaction distribution +system.membus.trans_dist::CleanEvict 11182 # Transaction distribution +system.membus.trans_dist::ReadExReq 101259 # Transaction distribution +system.membus.trans_dist::ReadExResp 101259 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 30033 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 358971 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 358971 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13855808 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 13855808 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 214401 # Request fanout histogram +system.membus.snoop_fanout::samples 227790 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 214401 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 227790 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 214401 # Request fanout histogram -system.membus.reqLayer0.occupancy 558284500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 227790 # Request fanout histogram +system.membus.reqLayer0.occupancy 569073488 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.membus.respLayer1.occupancy 657665500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 656842488 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.3 # Layer utilization (%) ---------- End Simulation Statistics ---------- |