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authorCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
committerCurtis Dunham <Curtis.Dunham@arm.com>2016-07-21 17:19:18 +0100
commit84f138ba96201431513eb2ae5f847389ac731aa2 (patch)
tree3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/quick/se/50.vortex
parenta288c94387b110112461ff5686fa727a43ddbe9c (diff)
downloadgem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz
stats: update references
Diffstat (limited to 'tests/quick/se/50.vortex')
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini22
-rwxr-xr-xtests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout10
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt11
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini57
-rwxr-xr-xtests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout10
-rw-r--r--tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini42
-rwxr-xr-xtests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt11
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini77
-rwxr-xr-xtests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt12
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini22
-rwxr-xr-xtests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout8
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt11
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini57
-rwxr-xr-xtests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr1
-rwxr-xr-xtests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout8
-rw-r--r--tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt12
24 files changed, 344 insertions, 60 deletions
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index c720d6208..2d4d209f1 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -118,7 +128,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
@@ -150,10 +160,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -168,11 +183,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index 222f46a4b..0d37b2b08 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:01
-gem5 executing on zizzer, pid 33985
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:27
+gem5 executing on e108600-lin, pid 4293
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index f25ed6812..a2e00980d 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.044221 # Nu
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3085186 # Simulator instruction rate (inst/s)
-host_op_rate 3085185 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1544361453 # Simulator tick rate (ticks/s)
-host_mem_usage 293364 # Number of bytes of host memory used
-host_seconds 28.63 # Real time elapsed on the host
+host_inst_rate 1536521 # Simulator instruction rate (inst/s)
+host_op_rate 1536520 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 769141125 # Simulator tick rate (ticks/s)
+host_mem_usage 247596 # Number of bytes of host memory used
+host_seconds 57.49 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -142,6 +142,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 353752292
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 218355543 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 572107835 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 123328088 # Request fanout histogram
system.membus.snoop_fanout::mean 0.717096 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.450410 # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 5de9bc371..d07d610d6 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -112,8 +127,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -153,8 +178,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -179,12 +209,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -203,8 +238,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
@@ -212,10 +252,15 @@ size=2097152
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -246,7 +291,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
kvmInSE=false
@@ -278,10 +323,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -296,11 +346,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
index de77515a1..96524c915 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index d1b551788..d72d31595 100755
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 21 2016 13:49:21
-gem5 started Jan 21 2016 13:50:00
-gem5 executing on zizzer, pid 33970
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /z/atgutier/gem5/gem5-commit/tests/run.py build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing
+gem5 compiled Jul 19 2016 12:23:51
+gem5 started Jul 21 2016 14:09:27
+gem5 executing on e108600-lin, pid 4294
+command line: /work/curdun01/gem5-external.hg/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.vortex/alpha/tru64/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index b00dd906e..51d70d56c 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.134742 # Nu
sim_ticks 134741611500 # Number of ticks simulated
final_tick 134741611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1731648 # Simulator instruction rate (inst/s)
-host_op_rate 1731647 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2641194476 # Simulator tick rate (ticks/s)
-host_mem_usage 302344 # Number of bytes of host memory used
-host_seconds 51.02 # Real time elapsed on the host
+host_inst_rate 968280 # Simulator instruction rate (inst/s)
+host_op_rate 968280 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1476869211 # Simulator tick rate (ticks/s)
+host_mem_usage 256564 # Number of bytes of host memory used
+host_seconds 91.23 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -510,6 +510,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23847808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 33500736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 131998 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 7320448 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 412778 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.009388 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.096434 # Request fanout histogram
@@ -539,6 +540,7 @@ system.membus.pkt_count::total 456523 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 17825920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 292375 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index 7e0b9adf7..f1a56a700 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -73,6 +79,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -106,9 +116,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -122,9 +137,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.membus.slave[4]
@@ -182,9 +202,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -198,9 +223,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.membus.slave[3]
@@ -218,7 +248,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
@@ -250,10 +280,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -268,11 +303,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simerr
@@ -1 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
index 315146752..99c3eacd0 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-at
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 17:50:51
-gem5 started Mar 14 2016 18:07:36
-gem5 executing on phenom, pid 27152
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 15:01:37
+gem5 executing on e108600-lin, pid 24147
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 00bb71a79..4508adaf3 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.048960 # Nu
sim_ticks 48960022500 # Number of ticks simulated
final_tick 48960022500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1718625 # Simulator instruction rate (inst/s)
-host_op_rate 2197882 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1186575552 # Simulator tick rate (ticks/s)
-host_mem_usage 310104 # Number of bytes of host memory used
-host_seconds 41.26 # Real time elapsed on the host
+host_inst_rate 832939 # Simulator instruction rate (inst/s)
+host_op_rate 1065213 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 575079073 # Simulator tick rate (ticks/s)
+host_mem_usage 264380 # Number of bytes of host memory used
+host_seconds 85.14 # Real time elapsed on the host
sim_insts 70913204 # Number of instructions simulated
sim_ops 90688159 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -237,6 +237,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580364
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 497813920 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 120930641 # Request fanout histogram
system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index c84baeb43..e7e819a35 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -72,6 +78,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -90,12 +100,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -114,8 +129,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -138,9 +158,14 @@ walker=system.cpu.dstage2_mmu.stage2_tlb.walker
[system.cpu.dstage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.dtb]
@@ -154,9 +179,14 @@ walker=system.cpu.dtb.walker
[system.cpu.dtb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[3]
@@ -167,12 +197,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -191,8 +226,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -250,9 +290,14 @@ walker=system.cpu.istage2_mmu.stage2_tlb.walker
[system.cpu.istage2_mmu.stage2_tlb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=true
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
[system.cpu.itb]
@@ -266,9 +311,14 @@ walker=system.cpu.itb.walker
[system.cpu.itb.walker]
type=ArmTableWalker
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
is_stage2=false
num_squash_per_cycle=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sys=system
port=system.cpu.toL2Bus.slave[2]
@@ -279,12 +329,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -303,8 +358,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
@@ -312,10 +372,15 @@ size=2097152
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -346,7 +411,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/arm/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
kvmInSE=false
@@ -378,10 +443,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -396,11 +466,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
index 1a4f96712..aadc3d011 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simerr
@@ -1 +1,2 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
index 6b39172d0..34991f400 100755
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-ti
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 17:50:51
-gem5 started Mar 14 2016 18:03:19
-gem5 executing on phenom, pid 27037
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing
+gem5 compiled Jul 21 2016 14:37:41
+gem5 started Jul 21 2016 14:38:22
+gem5 executing on e108600-lin, pid 23076
+command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/50.vortex/arm/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index b2023c05c..60128a0c8 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.128077 # Nu
sim_ticks 128076834500 # Number of ticks simulated
final_tick 128076834500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1093594 # Simulator instruction rate (inst/s)
-host_op_rate 1396212 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1990290276 # Simulator tick rate (ticks/s)
-host_mem_usage 320240 # Number of bytes of host memory used
-host_seconds 64.35 # Real time elapsed on the host
+host_inst_rate 523174 # Simulator instruction rate (inst/s)
+host_op_rate 667947 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 952153159 # Simulator tick rate (ticks/s)
+host_mem_usage 273092 # Number of bytes of host memory used
+host_seconds 134.51 # Real time elapsed on the host
sim_insts 70373651 # Number of instructions simulated
sim_ops 89847385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -630,6 +630,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18443072 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 20734144 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 95333 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 5513600 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 274239 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.025051 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.156979 # Request fanout histogram
@@ -659,6 +660,7 @@ system.membus.pkt_count::total 347268 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13672000 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 219817 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 61556605d..3a4f61f9d 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -71,6 +77,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -117,7 +127,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
@@ -149,10 +159,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -167,11 +182,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
index 7405f50a8..e38712610 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ignoring syscall time(4026527848, ...)
warn: ignoring syscall time(4026527400, ...)
warn: ignoring syscall time(4026527312, ...)
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 98ece2f0d..09707d695 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 17:46:51
-gem5 started Mar 14 2016 17:54:20
-gem5 executing on phenom, pid 26843
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:35
+gem5 executing on e108600-lin, pid 38667
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-atomic -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index ff66806fe..5541d62f0 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.068149 # Nu
sim_ticks 68148677000 # Number of ticks simulated
final_tick 68148677000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2845356 # Simulator instruction rate (inst/s)
-host_op_rate 2882198 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1442772972 # Simulator tick rate (ticks/s)
-host_mem_usage 292276 # Number of bytes of host memory used
-host_seconds 47.23 # Real time elapsed on the host
+host_inst_rate 1812136 # Simulator instruction rate (inst/s)
+host_op_rate 1835600 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 918865875 # Simulator tick rate (ticks/s)
+host_mem_usage 247504 # Number of bytes of host memory used
+host_seconds 74.17 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -114,6 +114,7 @@ system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 538214320
system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 237569638 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 775783958 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 192665100 # Request fanout histogram
system.membus.snoop_fanout::mean 0.698381 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.458961 # Request fanout histogram
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index f020fab37..14d66f92a 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -14,6 +14,7 @@ children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domai
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
exit_on_work_items=false
init_param=0
@@ -27,6 +28,10 @@ memories=system.physmem
mmap_using_noreserve=false
multi_thread=false
num_work_ids=16
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
readfile=
symbolfile=
thermal_components=
@@ -55,6 +60,7 @@ branchPred=Null
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
+default_p_state=UNDEFINED
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
@@ -70,6 +76,10 @@ max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
numThreads=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
profile=0
progress_interval=0
simpoint_start_insts=
@@ -88,12 +98,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=false
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -112,8 +127,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=262144
@@ -129,12 +149,17 @@ addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=2
is_read_only=true
max_miss_count=0
mshrs=4
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=2
@@ -153,8 +178,13 @@ type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=2
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=131072
@@ -178,12 +208,17 @@ addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
clusivity=mostly_incl
+default_p_state=UNDEFINED
demand_mshr_reserve=1
eventq_index=0
hit_latency=20
is_read_only=false
max_miss_count=0
mshrs=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
prefetch_on_access=false
prefetcher=Null
response_latency=20
@@ -202,8 +237,13 @@ type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
hit_latency=20
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
sequential_access=false
size=2097152
@@ -211,10 +251,15 @@ size=2097152
type=CoherentXBar
children=snoop_filter
clk_domain=system.cpu_clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=0
frontend_latency=1
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=false
+power_model=Null
response_latency=1
snoop_filter=system.cpu.toL2Bus.snoop_filter
snoop_response_latency=1
@@ -245,7 +290,7 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
+executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex
gid=100
input=cin
kvmInSE=false
@@ -277,10 +322,15 @@ transition_latency=100000000
[system.membus]
type=CoherentXBar
clk_domain=system.clk_domain
+default_p_state=UNDEFINED
eventq_index=0
forward_latency=4
frontend_latency=3
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
point_of_coherency=true
+power_model=Null
response_latency=2
snoop_filter=Null
snoop_response_latency=4
@@ -295,11 +345,16 @@ type=SimpleMemory
bandwidth=73.000000
clk_domain=system.clk_domain
conf_table_reported=true
+default_p_state=UNDEFINED
eventq_index=0
in_addr_map=true
latency=30000
latency_var=0
null=false
+p_state_clk_gate_bins=20
+p_state_clk_gate_max=1000000000000
+p_state_clk_gate_min=1000
+power_model=Null
range=0:134217727
port=system.membus.master[0]
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
index 7405f50a8..e38712610 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simerr
@@ -1,4 +1,5 @@
warn: Sockets disabled, not accepting gdb connections
+warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ignoring syscall time(4026527848, ...)
warn: ignoring syscall time(4026527400, ...)
warn: ignoring syscall time(4026527312, ...)
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
index d24399f8c..8920b4c6b 100755
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simpl
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 14 2016 17:46:51
-gem5 started Mar 14 2016 17:55:53
-gem5 executing on phenom, pid 26906
-command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
+gem5 compiled Jul 21 2016 14:30:06
+gem5 started Jul 21 2016 14:30:38
+gem5 executing on e108600-lin, pid 38688
+command line: /work/curdun01/gem5-external.hg/build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index be1596583..e21e8eadd 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,11 +4,11 @@ sim_seconds 0.203116 # Nu
sim_ticks 203115946500 # Number of ticks simulated
final_tick 203115946500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1546845 # Simulator instruction rate (inst/s)
-host_op_rate 1566874 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2337732587 # Simulator tick rate (ticks/s)
-host_mem_usage 302284 # Number of bytes of host memory used
-host_seconds 86.89 # Real time elapsed on the host
+host_inst_rate 1206960 # Simulator instruction rate (inst/s)
+host_op_rate 1222588 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1824068108 # Simulator tick rate (ticks/s)
+host_mem_usage 256216 # Number of bytes of host memory used
+host_seconds 111.35 # Real time elapsed on the host
sim_insts 134398959 # Number of instructions simulated
sim_ops 136139187 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
@@ -499,6 +499,7 @@ system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_s
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 17570816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 41378816 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 99022 # Total snoops (count)
+system.cpu.toL2Bus.snoopTraffic 5457280 # Total snoop traffic (bytes)
system.cpu.toL2Bus.snoop_fanout::samples 436725 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 0.008273 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.090579 # Request fanout histogram
@@ -528,6 +529,7 @@ system.membus.pkt_count::total 356615 # Pa
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 13810688 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
+system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples 226093 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram