stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee

6 files changed, 83 insertions, 30 deletions

diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
index d7757f328..f25ed6812 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1535738                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1535737                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              768748978                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246592                       # Number of bytes of host memory used
-host_seconds                                    57.52                       # Real time elapsed on the host
+host_inst_rate                                3085186                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3085185                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1544361453                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293364                       # Number of bytes of host memory used
+host_seconds                                    28.63                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED  44221003000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst         353752292                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         126702647                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            480454939                       # Number of bytes read from this memory
@@ -35,6 +36,7 @@ system.physmem.bw_write::total             2072610067                       # Wr
 system.physmem.bw_total::cpu.inst          7999644241                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          4937824296                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            12937468537                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED  44221003000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -69,6 +71,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON     44221003000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   88438073                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED  44221003000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq           108714711                       # Transaction distribution
 system.membus.trans_dist::ReadResp          108714711                       # Transaction distribution
 system.membus.trans_dist::WriteReq           14613377                       # Transaction distribution
diff --git a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
index 4daa87195..b00dd906e 100644
--- a/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.134742                       # Nu
 sim_ticks                                134741611500                       # Number of ticks simulated
 final_tick                               134741611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 882134                       # Simulator instruction rate (inst/s)
-host_op_rate                                   882134                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1345475029                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 255564                       # Number of bytes of host memory used
-host_seconds                                   100.14                       # Real time elapsed on the host
+host_inst_rate                                1731648                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1731647                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2641194476                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302344                       # Number of bytes of host memory used
+host_seconds                                    51.02                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
 sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            367360                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data          10138112                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10505472                       # Number of bytes read from this memory
@@ -36,6 +37,7 @@ system.physmem.bw_total::writebacks          54329527                       # To
 system.physmem.bw_total::cpu.inst             2726403                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            75241137                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              132297067                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
@@ -70,6 +72,7 @@ system.cpu.itb.data_misses                          0                       # DT
 system.cpu.itb.data_acv                             0                       # DTB access violations
 system.cpu.itb.data_accesses                        0                       # DTB accesses
 system.cpu.workload.num_syscalls                 4583                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        269483223                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -128,6 +131,7 @@ system.cpu.op_class::MemWrite                14620629     16.53%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   88438073                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            200248                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4078.397630                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            34685671                       # Total number of references to valid blocks.
@@ -144,6 +148,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3595
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          69984374                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         69984374                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
@@ -232,6 +237,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49986.498258
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49986.498258                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49986.498258                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             74391                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1870.507754                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            88361638                       # Total number of references to valid blocks.
@@ -249,6 +255,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1708
 system.cpu.icache.tags.occ_task_id_percent::1024     0.998535                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         176952584                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        176952584                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
@@ -317,6 +324,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15687.405149
 system.cpu.icache.demand_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15687.405149                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 15687.405149                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements           131998                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30708.485304                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             247404                       # Total number of references to valid blocks.
@@ -339,6 +347,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          122
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.978882                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          4751004                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         4751004                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       168278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       168278                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        74391                       # number of WritebackClean hits
@@ -485,6 +494,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests            0
 system.cpu.toL2Bus.snoop_filter.tot_snoops         3875                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3875                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        137202                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       282660                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        74391                       # Transaction distribution
@@ -517,6 +527,7 @@ system.cpu.toL2Bus.respLayer0.occupancy     114654000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     306516000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 134741611500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              33266                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty       114382                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            13845                       # Transaction distribution
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
index 545d841c6..00bb71a79 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.048960                       # Nu
 sim_ticks                                 48960022500                       # Number of ticks simulated
 final_tick                                48960022500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1798045                       # Simulator instruction rate (inst/s)
-host_op_rate                                  2299450                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1241408996                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 309432                       # Number of bytes of host memory used
-host_seconds                                    39.44                       # Real time elapsed on the host
+host_inst_rate                                1718625                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2197882                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1186575552                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 310104                       # Number of bytes of host memory used
+host_seconds                                    41.26                       # Real time elapsed on the host
 sim_insts                                    70913204                       # Number of instructions simulated
 sim_ops                                      90688159                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst         312580364                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         106573345                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            419153709                       # Number of bytes read from this memory
@@ -35,7 +36,9 @@ system.physmem.bw_write::total             1606621218                       # Wr
 system.physmem.bw_total::cpu.inst          6384399925                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3783363376                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            10167763301                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -153,6 +159,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON     48960022500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                         97920046                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   90690106                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED  48960022500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq           100925158                       # Transaction distribution
 system.membus.trans_dist::ReadResp          100941077                       # Transaction distribution
 system.membus.trans_dist::WriteReq           19849901                       # Transaction distribution
diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
index f303216c1..b2023c05c 100644
--- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.128077                       # Nu
 sim_ticks                                128076834500                       # Number of ticks simulated
 final_tick                               128076834500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1113892                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1422128                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             2027232976                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 319564                       # Number of bytes of host memory used
-host_seconds                                    63.18                       # Real time elapsed on the host
+host_inst_rate                                1093594                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1396212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1990290276                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 320240                       # Number of bytes of host memory used
+host_seconds                                    64.35                       # Real time elapsed on the host
 sim_insts                                    70373651                       # Number of instructions simulated
 sim_ops                                      89847385                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            233152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7925248                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8158400                       # Number of bytes read from this memory
@@ -36,7 +37,9 @@ system.physmem.bw_total::writebacks          43049159                       # To
 system.physmem.bw_total::cpu.inst             1820407                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            61878856                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total              106748422                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -66,6 +69,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -95,6 +99,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -124,6 +129,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -154,6 +160,7 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        256153669                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -214,6 +221,7 @@ system.cpu.op_class::MemWrite                20555739     22.67%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                   90690106                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            155902                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4075.927155                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            42601677                       # Total number of references to valid blocks.
@@ -230,6 +238,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3263
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          85731098                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         85731098                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     22743361                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        22743361                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
@@ -348,6 +357,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49898.108565
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 49898.108565                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49964.608933                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 49964.608933                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements             16890                       # number of replacements
 system.cpu.icache.tags.tagsinuse          1732.356634                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs            78126184                       # Total number of references to valid blocks.
@@ -365,6 +375,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1645
 system.cpu.icache.tags.occ_task_id_percent::1024     0.985352                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         156309092                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        156309092                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst     78126184                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        78126184                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      78126184                       # number of demand (read+write) hits
@@ -433,6 +444,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21540.749947
 system.cpu.icache.demand_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21540.749947                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 21540.749947                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements            95333                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30336.891531                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             114380                       # Total number of references to valid blocks.
@@ -455,6 +467,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          624
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.949768                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          3017503                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         3017503                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       128175                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       128175                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks        15790                       # number of WritebackClean hits
@@ -601,6 +614,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests         3696
 system.cpu.toL2Bus.snoop_filter.tot_snoops         3119                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3089                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops           30                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp         71874                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       214325                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean        16890                       # Transaction distribution
@@ -633,6 +647,7 @@ system.cpu.toL2Bus.respLayer0.occupancy      28362000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     239997000                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.2                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 128076834500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              25194                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        86150                       # Transaction distribution
 system.membus.trans_dist::CleanEvict             6168                       # Transaction distribution
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
index 75464de1f..ff66806fe 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148677000                       # Number of ticks simulated
 final_tick                                68148677000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1339454                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1356797                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              679186650                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 246572                       # Number of bytes of host memory used
-host_seconds                                   100.34                       # Real time elapsed on the host
+host_inst_rate                                2845356                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2882198                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1442772972                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292276                       # Number of bytes of host memory used
+host_seconds                                    47.23                       # Real time elapsed on the host
 sim_insts                                   134398959                       # Number of instructions simulated
 sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED  68148677000                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst         538214320                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data         147559360                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            685773680                       # Number of bytes read from this memory
@@ -37,8 +38,10 @@ system.physmem.bw_write::total             1318924357                       # Wr
 system.physmem.bw_total::cpu.inst          7897648842                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data          3484180771                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total            11381829614                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED  68148677000                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON     68148677000                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        136297355                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite                20884397     15.32%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  136293808                       # Class of executed instruction
+system.membus.pwrStateResidencyTicks::UNDEFINED  68148677000                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadReq           171784880                       # Transaction distribution
 system.membus.trans_dist::ReadResp          171784880                       # Transaction distribution
 system.membus.trans_dist::WriteReq           20864304                       # Transaction distribution
diff --git a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
index 18f2ca2b3..be1596583 100644
--- a/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
+++ b/tests/quick/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
@@ -4,15 +4,16 @@ sim_seconds                                  0.203116                       # Nu
 sim_ticks                                203115946500                       # Number of ticks simulated
 final_tick                               203115946500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 790551                       # Simulator instruction rate (inst/s)
-host_op_rate                                   800787                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1194752753                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 255284                       # Number of bytes of host memory used
-host_seconds                                   170.01                       # Real time elapsed on the host
+host_inst_rate                                1546845                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1566874                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2337732587                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 302284                       # Number of bytes of host memory used
+host_seconds                                    86.89                       # Real time elapsed on the host
 sim_insts                                   134398959                       # Number of instructions simulated
 sim_ops                                     136139187                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
+system.physmem.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            525056                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data           7828352                       # Number of bytes read from this memory
 system.physmem.bytes_read::total              8353408                       # Number of bytes read from this memory
@@ -36,8 +37,10 @@ system.physmem.bw_total::writebacks          26867807                       # To
 system.physmem.bw_total::cpu.inst             2585006                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.data            38541297                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total               67994110                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.workload.num_syscalls                 1946                       # Number of system calls
+system.cpu.pwrStateResidencyTicks::ON    203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.numCycles                        406231893                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
@@ -96,6 +99,7 @@ system.cpu.op_class::MemWrite                20884397     15.32%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  136293808                       # Class of executed instruction
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements            146583                       # number of replacements
 system.cpu.dcache.tags.tagsinuse          4087.268923                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            57960841                       # Total number of references to valid blocks.
@@ -112,6 +116,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2         3586
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         116373719                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        116373719                       # Number of data accesses
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     37185800                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        37185800                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
@@ -220,6 +225,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51785.466336
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51785.466336                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 51785.466336                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements            184976                       # number of replacements
 system.cpu.icache.tags.tagsinuse          2004.181265                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           134366557                       # Total number of references to valid blocks.
@@ -238,6 +244,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4         1427
 system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         269294186                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        269294186                       # Number of data accesses
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    134366557                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       134366557                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     134366557                       # number of demand (read+write) hits
@@ -306,6 +313,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 14159.760245
 system.cpu.icache.demand_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 14159.760245                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_miss_latency::total 14159.760245                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements            99022                       # number of replacements
 system.cpu.l2cache.tags.tagsinuse        30843.699683                       # Cycle average of tags in use
 system.cpu.l2cache.tags.total_refs             433832                       # Total number of references to valid blocks.
@@ -328,6 +336,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4          557
 system.cpu.l2cache.tags.occ_task_id_percent::1024     0.947357                       # Percentage of cache occupancy per task id
 system.cpu.l2cache.tags.tag_accesses          5588812                       # Number of tag accesses
 system.cpu.l2cache.tags.data_accesses         5588812                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks       123865                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total       123865                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks       184923                       # number of WritebackClean hits
@@ -474,6 +483,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests           66
 system.cpu.toL2Bus.snoop_filter.tot_snoops         3547                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3547                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp        232524                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty       209135                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean       184976                       # Transaction distribution
@@ -506,6 +516,7 @@ system.cpu.toL2Bus.respLayer0.occupancy     280536000                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy     226018500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
+system.membus.pwrStateResidencyTicks::UNDEFINED 203115946500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp              29258                       # Transaction distribution
 system.membus.trans_dist::WritebackDirty        85270                       # Transaction distribution
 system.membus.trans_dist::CleanEvict            10301                       # Transaction distribution