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author | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-28 13:48:04 -0400 |
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committer | Ali Saidi <saidi@eecs.umich.edu> | 2012-07-28 13:48:04 -0400 |
commit | 19cc023cf51268f3c4f3a83d95319f37660d94f7 (patch) | |
tree | c6ffa5082e735787c7f2e55c45eedc3116f8e952 /tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt | |
parent | fe2faa1975fb2c03ad7e493489d62ea06767f52f (diff) | |
download | gem5-19cc023cf51268f3c4f3a83d95319f37660d94f7.tar.xz |
stats: fix some miss-committed changes from the icache change
Diffstat (limited to 'tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt')
-rw-r--r-- | tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index f6f4e6847..7224a1c96 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,8 +4,26 @@ sim_seconds 0.000350 # Nu sim_ticks 349711 # Number of ticks simulated final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 2288501 # Simulator tick rate (ticks/s) -host_mem_usage 221264 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_tick_rate 2474351 # Simulator tick rate (ticks/s) +host_mem_usage 229272 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads +system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads +system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads +system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes +system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array +system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array ---------- End Simulation Statistics ---------- |