stats: updates due to changes to ruby

Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.

2 files changed, 115 insertions, 1262 deletions

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 6a1258780..b47558017 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,26 +1,24 @@
-Real time: Feb/02/2013 08:16:59
+Real time: Jun/08/2013 14:14:03
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.74
-Virtual_time_in_minutes: 0.0123333
-Virtual_time_in_hours:   0.000205556
-Virtual_time_in_days:    8.56481e-06
+Virtual_time_in_seconds: 0.8
+Virtual_time_in_minutes: 0.0133333
+Virtual_time_in_hours:   0.000222222
+Virtual_time_in_days:    9.25926e-06
 
 Ruby_current_time: 327361
 Ruby_start_time: 0
 Ruby_cycles: 327361
 
-mbytes_resident: 49.6445
-mbytes_total: 265.777
-resident_ratio: 0.186849
-
-ruby_cycles_executed: [ 327362 ]
+mbytes_resident: 52.7734
+mbytes_total: 140.672
+resident_ratio: 0.375208
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -61,7 +59,6 @@ Request vs. RubySystem State Profile
 --------------------------------
 
 
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Message Delayed Cycles
 ----------------------
@@ -82,7 +79,7 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9414
+page_reclaims: 10707
 page_faults: 0
 swaps: 0
 block_inputs: 0
@@ -164,1246 +161,3 @@ links_utilized_percent_switch_3: 1.93247
   outgoing_messages_switch_3_link_2_Writeback_Control: 925 7400 [ 0 845 80 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_3_link_2_Unblock_Control: 852 6816 [ 0 0 852 0 0 0 0 0 0 0 ] base_latency: 1
 
- --- L1Cache ---
- - Event Counts -
-Load [44 ] 44
-Ifetch [192 ] 192
-Store [1001 ] 1001
-L1_Replacement [465203 ] 465203
-Own_GETX [0 ] 0
-Fwd_GETX [0 ] 0
-Fwd_GETS [0 ] 0
-Fwd_DMA [0 ] 0
-Inv [0 ] 0
-Ack [0 ] 0
-Data [0 ] 0
-Exclusive_Data [907 ] 907
-Writeback_Ack [0 ] 0
-Writeback_Ack_Data [903 ] 903
-Writeback_Nack [0 ] 0
-All_acks [813 ] 813
-Use_Timeout [905 ] 905
-
- - Transitions -
-I  Load [38 ] 38
-I  Ifetch [56 ] 56
-I  Store [814 ] 814
-I  L1_Replacement [0 ] 0
-I  Inv [0 ] 0
-
-S  Load [0 ] 0
-S  Ifetch [0 ] 0
-S  Store [0 ] 0
-S  L1_Replacement [0 ] 0
-S  Fwd_GETS [0 ] 0
-S  Fwd_DMA [0 ] 0
-S  Inv [0 ] 0
-
-O  Load [0 ] 0
-O  Ifetch [0 ] 0
-O  Store [0 ] 0
-O  L1_Replacement [0 ] 0
-O  Fwd_GETX [0 ] 0
-O  Fwd_GETS [0 ] 0
-O  Fwd_DMA [0 ] 0
-
-M  Load [0 ] 0
-M  Ifetch [0 ] 0
-M  Store [0 ] 0
-M  L1_Replacement [92 ] 92
-M  Fwd_GETX [0 ] 0
-M  Fwd_GETS [0 ] 0
-M  Fwd_DMA [0 ] 0
-
-M_W  Load [0 ] 0
-M_W  Ifetch [0 ] 0
-M_W  Store [0 ] 0
-M_W  L1_Replacement [1319 ] 1319
-M_W  Own_GETX [0 ] 0
-M_W  Fwd_GETX [0 ] 0
-M_W  Fwd_GETS [0 ] 0
-M_W  Fwd_DMA [0 ] 0
-M_W  Inv [0 ] 0
-M_W  Use_Timeout [93 ] 93
-
-MM  Load [6 ] 6
-MM  Ifetch [0 ] 0
-MM  Store [66 ] 66
-MM  L1_Replacement [811 ] 811
-MM  Fwd_GETX [0 ] 0
-MM  Fwd_GETS [0 ] 0
-MM  Fwd_DMA [0 ] 0
-
-MM_W  Load [0 ] 0
-MM_W  Ifetch [0 ] 0
-MM_W  Store [6 ] 6
-MM_W  L1_Replacement [29843 ] 29843
-MM_W  Own_GETX [0 ] 0
-MM_W  Fwd_GETX [0 ] 0
-MM_W  Fwd_GETS [0 ] 0
-MM_W  Fwd_DMA [0 ] 0
-MM_W  Inv [0 ] 0
-MM_W  Use_Timeout [812 ] 812
-
-IM  Load [0 ] 0
-IM  Ifetch [0 ] 0
-IM  Store [0 ] 0
-IM  L1_Replacement [399867 ] 399867
-IM  Inv [0 ] 0
-IM  Ack [0 ] 0
-IM  Data [0 ] 0
-IM  Exclusive_Data [813 ] 813
-
-SM  Load [0 ] 0
-SM  Ifetch [0 ] 0
-SM  Store [0 ] 0
-SM  L1_Replacement [0 ] 0
-SM  Fwd_GETS [0 ] 0
-SM  Fwd_DMA [0 ] 0
-SM  Inv [0 ] 0
-SM  Ack [0 ] 0
-SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
-
-OM  Load [0 ] 0
-OM  Ifetch [0 ] 0
-OM  Store [0 ] 0
-OM  L1_Replacement [17168 ] 17168
-OM  Own_GETX [0 ] 0
-OM  Fwd_GETX [0 ] 0
-OM  Fwd_GETS [0 ] 0
-OM  Fwd_DMA [0 ] 0
-OM  Ack [0 ] 0
-OM  All_acks [813 ] 813
-
-IS  Load [0 ] 0
-IS  Ifetch [0 ] 0
-IS  Store [0 ] 0
-IS  L1_Replacement [16103 ] 16103
-IS  Inv [0 ] 0
-IS  Data [0 ] 0
-IS  Exclusive_Data [94 ] 94
-
-SI  Load [0 ] 0
-SI  Ifetch [0 ] 0
-SI  Store [0 ] 0
-SI  L1_Replacement [0 ] 0
-SI  Fwd_GETS [0 ] 0
-SI  Fwd_DMA [0 ] 0
-SI  Inv [0 ] 0
-SI  Writeback_Ack [0 ] 0
-SI  Writeback_Ack_Data [0 ] 0
-SI  Writeback_Nack [0 ] 0
-
-OI  Load [0 ] 0
-OI  Ifetch [0 ] 0
-OI  Store [0 ] 0
-OI  L1_Replacement [0 ] 0
-OI  Fwd_GETX [0 ] 0
-OI  Fwd_GETS [0 ] 0
-OI  Fwd_DMA [0 ] 0
-OI  Writeback_Ack [0 ] 0
-OI  Writeback_Ack_Data [0 ] 0
-OI  Writeback_Nack [0 ] 0
-
-MI  Load [0 ] 0
-MI  Ifetch [136 ] 136
-MI  Store [115 ] 115
-MI  L1_Replacement [0 ] 0
-MI  Fwd_GETX [0 ] 0
-MI  Fwd_GETS [0 ] 0
-MI  Fwd_DMA [0 ] 0
-MI  Writeback_Ack [0 ] 0
-MI  Writeback_Ack_Data [903 ] 903
-MI  Writeback_Nack [0 ] 0
-
-II  Load [0 ] 0
-II  Ifetch [0 ] 0
-II  Store [0 ] 0
-II  L1_Replacement [0 ] 0
-II  Inv [0 ] 0
-II  Writeback_Ack [0 ] 0
-II  Writeback_Ack_Data [0 ] 0
-II  Writeback_Nack [0 ] 0
-
- --- L2Cache ---
- - Event Counts -
-L1_GETS [127 ] 127
-L1_GETX [895 ] 895
-L1_PUTO [0 ] 0
-L1_PUTX [2308 ] 2308
-L1_PUTS_only [0 ] 0
-L1_PUTS [0 ] 0
-Fwd_GETX [0 ] 0
-Fwd_GETS [0 ] 0
-Fwd_DMA [0 ] 0
-Own_GETX [0 ] 0
-Inv [0 ] 0
-IntAck [0 ] 0
-ExtAck [0 ] 0
-All_Acks [766 ] 766
-Data [766 ] 766
-Data_Exclusive [88 ] 88
-L1_WBCLEANDATA [86 ] 86
-L1_WBDIRTYDATA [817 ] 817
-Writeback_Ack [845 ] 845
-Writeback_Nack [0 ] 0
-Unblock [0 ] 0
-Exclusive_Unblock [906 ] 906
-DmaAck [0 ] 0
-L2_Replacement [847 ] 847
-
- - Transitions -
-NP  L1_GETS [88 ] 88
-NP  L1_GETX [767 ] 767
-NP  L1_PUTO [0 ] 0
-NP  L1_PUTX [0 ] 0
-NP  L1_PUTS [0 ] 0
-NP  Inv [0 ] 0
-
-I  L1_GETS [0 ] 0
-I  L1_GETX [0 ] 0
-I  L1_PUTO [0 ] 0
-I  L1_PUTX [0 ] 0
-I  L1_PUTS [0 ] 0
-I  Inv [0 ] 0
-I  L2_Replacement [0 ] 0
-
-ILS  L1_GETS [0 ] 0
-ILS  L1_GETX [0 ] 0
-ILS  L1_PUTO [0 ] 0
-ILS  L1_PUTX [0 ] 0
-ILS  L1_PUTS_only [0 ] 0
-ILS  L1_PUTS [0 ] 0
-ILS  Inv [0 ] 0
-ILS  L2_Replacement [0 ] 0
-
-ILX  L1_GETS [0 ] 0
-ILX  L1_GETX [0 ] 0
-ILX  L1_PUTO [0 ] 0
-ILX  L1_PUTX [903 ] 903
-ILX  L1_PUTS_only [0 ] 0
-ILX  L1_PUTS [0 ] 0
-ILX  Fwd_GETX [0 ] 0
-ILX  Fwd_GETS [0 ] 0
-ILX  Fwd_DMA [0 ] 0
-ILX  Inv [0 ] 0
-ILX  Data [0 ] 0
-ILX  L2_Replacement [0 ] 0
-
-ILO  L1_GETS [0 ] 0
-ILO  L1_GETX [0 ] 0
-ILO  L1_PUTO [0 ] 0
-ILO  L1_PUTX [0 ] 0
-ILO  L1_PUTS [0 ] 0
-ILO  Fwd_GETX [0 ] 0
-ILO  Fwd_GETS [0 ] 0
-ILO  Fwd_DMA [0 ] 0
-ILO  Inv [0 ] 0
-ILO  Data [0 ] 0
-ILO  L2_Replacement [0 ] 0
-
-ILOX  L1_GETS [0 ] 0
-ILOX  L1_GETX [0 ] 0
-ILOX  L1_PUTO [0 ] 0
-ILOX  L1_PUTX [0 ] 0
-ILOX  L1_PUTS [0 ] 0
-ILOX  Fwd_GETX [0 ] 0
-ILOX  Fwd_GETS [0 ] 0
-ILOX  Fwd_DMA [0 ] 0
-ILOX  Data [0 ] 0
-
-ILOS  L1_GETS [0 ] 0
-ILOS  L1_GETX [0 ] 0
-ILOS  L1_PUTO [0 ] 0
-ILOS  L1_PUTX [0 ] 0
-ILOS  L1_PUTS_only [0 ] 0
-ILOS  L1_PUTS [0 ] 0
-ILOS  Fwd_GETX [0 ] 0
-ILOS  Fwd_GETS [0 ] 0
-ILOS  Fwd_DMA [0 ] 0
-ILOS  Data [0 ] 0
-ILOS  L2_Replacement [0 ] 0
-
-ILOSX  L1_GETS [0 ] 0
-ILOSX  L1_GETX [0 ] 0
-ILOSX  L1_PUTO [0 ] 0
-ILOSX  L1_PUTX [0 ] 0
-ILOSX  L1_PUTS_only [0 ] 0
-ILOSX  L1_PUTS [0 ] 0
-ILOSX  Fwd_GETX [0 ] 0
-ILOSX  Fwd_GETS [0 ] 0
-ILOSX  Fwd_DMA [0 ] 0
-ILOSX  Data [0 ] 0
-
-S  L1_GETS [0 ] 0
-S  L1_GETX [0 ] 0
-S  L1_PUTX [0 ] 0
-S  L1_PUTS [0 ] 0
-S  Inv [0 ] 0
-S  L2_Replacement [0 ] 0
-
-O  L1_GETS [0 ] 0
-O  L1_GETX [0 ] 0
-O  L1_PUTX [0 ] 0
-O  Fwd_GETX [0 ] 0
-O  Fwd_GETS [0 ] 0
-O  Fwd_DMA [0 ] 0
-O  L2_Replacement [0 ] 0
-
-OLS  L1_GETS [0 ] 0
-OLS  L1_GETX [0 ] 0
-OLS  L1_PUTX [0 ] 0
-OLS  L1_PUTS_only [0 ] 0
-OLS  L1_PUTS [0 ] 0
-OLS  Fwd_GETX [0 ] 0
-OLS  Fwd_GETS [0 ] 0
-OLS  Fwd_DMA [0 ] 0
-OLS  L2_Replacement [0 ] 0
-
-OLSX  L1_GETS [0 ] 0
-OLSX  L1_GETX [0 ] 0
-OLSX  L1_PUTO [0 ] 0
-OLSX  L1_PUTX [0 ] 0
-OLSX  L1_PUTS_only [0 ] 0
-OLSX  L1_PUTS [0 ] 0
-OLSX  Fwd_GETX [0 ] 0
-OLSX  Fwd_GETS [0 ] 0
-OLSX  Fwd_DMA [0 ] 0
-OLSX  L2_Replacement [0 ] 0
-
-SLS  L1_GETS [0 ] 0
-SLS  L1_GETX [0 ] 0
-SLS  L1_PUTX [0 ] 0
-SLS  L1_PUTS_only [0 ] 0
-SLS  L1_PUTS [0 ] 0
-SLS  Inv [0 ] 0
-SLS  L2_Replacement [0 ] 0
-
-M  L1_GETS [6 ] 6
-M  L1_GETX [47 ] 47
-M  L1_PUTO [0 ] 0
-M  L1_PUTX [0 ] 0
-M  L1_PUTS [0 ] 0
-M  Fwd_GETX [0 ] 0
-M  Fwd_GETS [0 ] 0
-M  Fwd_DMA [0 ] 0
-M  L2_Replacement [847 ] 847
-
-IFGX  L1_GETS [0 ] 0
-IFGX  L1_GETX [0 ] 0
-IFGX  L1_PUTO [0 ] 0
-IFGX  L1_PUTX [0 ] 0
-IFGX  L1_PUTS_only [0 ] 0
-IFGX  L1_PUTS [0 ] 0
-IFGX  Fwd_GETX [0 ] 0
-IFGX  Fwd_GETS [0 ] 0
-IFGX  Fwd_DMA [0 ] 0
-IFGX  Inv [0 ] 0
-IFGX  Data [0 ] 0
-IFGX  Data_Exclusive [0 ] 0
-IFGX  L2_Replacement [0 ] 0
-
-IFGS  L1_GETS [0 ] 0
-IFGS  L1_GETX [0 ] 0
-IFGS  L1_PUTO [0 ] 0
-IFGS  L1_PUTX [0 ] 0
-IFGS  L1_PUTS_only [0 ] 0
-IFGS  L1_PUTS [0 ] 0
-IFGS  Fwd_GETX [0 ] 0
-IFGS  Fwd_GETS [0 ] 0
-IFGS  Fwd_DMA [0 ] 0
-IFGS  Inv [0 ] 0
-IFGS  Data [0 ] 0
-IFGS  Data_Exclusive [0 ] 0
-IFGS  L2_Replacement [0 ] 0
-
-ISFGS  L1_GETS [0 ] 0
-ISFGS  L1_GETX [0 ] 0
-ISFGS  L1_PUTO [0 ] 0
-ISFGS  L1_PUTX [0 ] 0
-ISFGS  L1_PUTS_only [0 ] 0
-ISFGS  L1_PUTS [0 ] 0
-ISFGS  Fwd_GETX [0 ] 0
-ISFGS  Fwd_GETS [0 ] 0
-ISFGS  Fwd_DMA [0 ] 0
-ISFGS  Inv [0 ] 0
-ISFGS  Data [0 ] 0
-ISFGS  L2_Replacement [0 ] 0
-
-IFGXX  L1_GETS [0 ] 0
-IFGXX  L1_GETX [0 ] 0
-IFGXX  L1_PUTO [0 ] 0
-IFGXX  L1_PUTX [0 ] 0
-IFGXX  L1_PUTS_only [0 ] 0
-IFGXX  L1_PUTS [0 ] 0
-IFGXX  Fwd_GETX [0 ] 0
-IFGXX  Fwd_GETS [0 ] 0
-IFGXX  Fwd_DMA [0 ] 0
-IFGXX  Inv [0 ] 0
-IFGXX  IntAck [0 ] 0
-IFGXX  All_Acks [0 ] 0
-IFGXX  Data_Exclusive [0 ] 0
-IFGXX  L2_Replacement [0 ] 0
-
-OFGX  L1_GETS [0 ] 0
-OFGX  L1_GETX [0 ] 0
-OFGX  L1_PUTO [0 ] 0
-OFGX  L1_PUTX [0 ] 0
-OFGX  L1_PUTS_only [0 ] 0
-OFGX  L1_PUTS [0 ] 0
-OFGX  Fwd_GETX [0 ] 0
-OFGX  Fwd_GETS [0 ] 0
-OFGX  Fwd_DMA [0 ] 0
-OFGX  Inv [0 ] 0
-OFGX  L2_Replacement [0 ] 0
-
-OLSF  L1_GETS [0 ] 0
-OLSF  L1_GETX [0 ] 0
-OLSF  L1_PUTO [0 ] 0
-OLSF  L1_PUTX [0 ] 0
-OLSF  L1_PUTS_only [0 ] 0
-OLSF  L1_PUTS [0 ] 0
-OLSF  Fwd_GETX [0 ] 0
-OLSF  Fwd_GETS [0 ] 0
-OLSF  Fwd_DMA [0 ] 0
-OLSF  Inv [0 ] 0
-OLSF  IntAck [0 ] 0
-OLSF  All_Acks [0 ] 0
-OLSF  L2_Replacement [0 ] 0
-
-ILOW  L1_GETS [0 ] 0
-ILOW  L1_GETX [0 ] 0
-ILOW  L1_PUTO [0 ] 0
-ILOW  L1_PUTX [0 ] 0
-ILOW  L1_PUTS_only [0 ] 0
-ILOW  L1_PUTS [0 ] 0
-ILOW  Fwd_GETX [0 ] 0
-ILOW  Fwd_GETS [0 ] 0
-ILOW  Fwd_DMA [0 ] 0
-ILOW  Inv [0 ] 0
-ILOW  L1_WBCLEANDATA [0 ] 0
-ILOW  L1_WBDIRTYDATA [0 ] 0
-ILOW  Unblock [0 ] 0
-ILOW  L2_Replacement [0 ] 0
-
-ILOXW  L1_GETS [0 ] 0
-ILOXW  L1_GETX [0 ] 0
-ILOXW  L1_PUTO [0 ] 0
-ILOXW  L1_PUTX [0 ] 0
-ILOXW  L1_PUTS_only [0 ] 0
-ILOXW  L1_PUTS [0 ] 0
-ILOXW  Fwd_GETX [0 ] 0
-ILOXW  Fwd_GETS [0 ] 0
-ILOXW  Fwd_DMA [0 ] 0
-ILOXW  Inv [0 ] 0
-ILOXW  L1_WBCLEANDATA [0 ] 0
-ILOXW  L1_WBDIRTYDATA [0 ] 0
-ILOXW  Unblock [0 ] 0
-ILOXW  L2_Replacement [0 ] 0
-
-ILOSW  L1_GETS [0 ] 0
-ILOSW  L1_GETX [0 ] 0
-ILOSW  L1_PUTO [0 ] 0
-ILOSW  L1_PUTX [0 ] 0
-ILOSW  L1_PUTS_only [0 ] 0
-ILOSW  L1_PUTS [0 ] 0
-ILOSW  Fwd_GETX [0 ] 0
-ILOSW  Fwd_GETS [0 ] 0
-ILOSW  Fwd_DMA [0 ] 0
-ILOSW  Inv [0 ] 0
-ILOSW  L1_WBCLEANDATA [0 ] 0
-ILOSW  L1_WBDIRTYDATA [0 ] 0
-ILOSW  Unblock [0 ] 0
-ILOSW  L2_Replacement [0 ] 0
-
-ILOSXW  L1_GETS [0 ] 0
-ILOSXW  L1_GETX [0 ] 0
-ILOSXW  L1_PUTO [0 ] 0
-ILOSXW  L1_PUTX [0 ] 0
-ILOSXW  L1_PUTS_only [0 ] 0
-ILOSXW  L1_PUTS [0 ] 0
-ILOSXW  Fwd_GETX [0 ] 0
-ILOSXW  Fwd_GETS [0 ] 0
-ILOSXW  Fwd_DMA [0 ] 0
-ILOSXW  Inv [0 ] 0
-ILOSXW  L1_WBCLEANDATA [0 ] 0
-ILOSXW  L1_WBDIRTYDATA [0 ] 0
-ILOSXW  Unblock [0 ] 0
-ILOSXW  L2_Replacement [0 ] 0
-
-SLSW  L1_GETS [0 ] 0
-SLSW  L1_GETX [0 ] 0
-SLSW  L1_PUTO [0 ] 0
-SLSW  L1_PUTX [0 ] 0
-SLSW  L1_PUTS_only [0 ] 0
-SLSW  L1_PUTS [0 ] 0
-SLSW  Fwd_GETX [0 ] 0
-SLSW  Fwd_GETS [0 ] 0
-SLSW  Fwd_DMA [0 ] 0
-SLSW  Inv [0 ] 0
-SLSW  Unblock [0 ] 0
-SLSW  L2_Replacement [0 ] 0
-
-OLSW  L1_GETS [0 ] 0
-OLSW  L1_GETX [0 ] 0
-OLSW  L1_PUTO [0 ] 0
-OLSW  L1_PUTX [0 ] 0
-OLSW  L1_PUTS_only [0 ] 0
-OLSW  L1_PUTS [0 ] 0
-OLSW  Fwd_GETX [0 ] 0
-OLSW  Fwd_GETS [0 ] 0
-OLSW  Fwd_DMA [0 ] 0
-OLSW  Inv [0 ] 0
-OLSW  Unblock [0 ] 0
-OLSW  L2_Replacement [0 ] 0
-
-ILSW  L1_GETS [0 ] 0
-ILSW  L1_GETX [0 ] 0
-ILSW  L1_PUTO [0 ] 0
-ILSW  L1_PUTX [0 ] 0
-ILSW  L1_PUTS_only [0 ] 0
-ILSW  L1_PUTS [0 ] 0
-ILSW  Fwd_GETX [0 ] 0
-ILSW  Fwd_GETS [0 ] 0
-ILSW  Fwd_DMA [0 ] 0
-ILSW  Inv [0 ] 0
-ILSW  L1_WBCLEANDATA [0 ] 0
-ILSW  Unblock [0 ] 0
-ILSW  L2_Replacement [0 ] 0
-
-IW  L1_GETS [0 ] 0
-IW  L1_GETX [0 ] 0
-IW  L1_PUTO [0 ] 0
-IW  L1_PUTX [0 ] 0
-IW  L1_PUTS_only [0 ] 0
-IW  L1_PUTS [0 ] 0
-IW  Fwd_GETX [0 ] 0
-IW  Fwd_GETS [0 ] 0
-IW  Fwd_DMA [0 ] 0
-IW  Inv [0 ] 0
-IW  L1_WBCLEANDATA [0 ] 0
-IW  L2_Replacement [0 ] 0
-
-OW  L1_GETS [0 ] 0
-OW  L1_GETX [0 ] 0
-OW  L1_PUTO [0 ] 0
-OW  L1_PUTX [0 ] 0
-OW  L1_PUTS_only [0 ] 0
-OW  L1_PUTS [0 ] 0
-OW  Fwd_GETX [0 ] 0
-OW  Fwd_GETS [0 ] 0
-OW  Fwd_DMA [0 ] 0
-OW  Inv [0 ] 0
-OW  Unblock [0 ] 0
-OW  L2_Replacement [0 ] 0
-
-SW  L1_GETS [0 ] 0
-SW  L1_GETX [0 ] 0
-SW  L1_PUTO [0 ] 0
-SW  L1_PUTX [0 ] 0
-SW  L1_PUTS_only [0 ] 0
-SW  L1_PUTS [0 ] 0
-SW  Fwd_GETX [0 ] 0
-SW  Fwd_GETS [0 ] 0
-SW  Fwd_DMA [0 ] 0
-SW  Inv [0 ] 0
-SW  Unblock [0 ] 0
-SW  L2_Replacement [0 ] 0
-
-OXW  L1_GETS [0 ] 0
-OXW  L1_GETX [0 ] 0
-OXW  L1_PUTO [0 ] 0
-OXW  L1_PUTX [0 ] 0
-OXW  L1_PUTS_only [0 ] 0
-OXW  L1_PUTS [0 ] 0
-OXW  Fwd_GETX [0 ] 0
-OXW  Fwd_GETS [0 ] 0
-OXW  Fwd_DMA [0 ] 0
-OXW  Inv [0 ] 0
-OXW  Unblock [0 ] 0
-OXW  L2_Replacement [0 ] 0
-
-OLSXW  L1_GETS [0 ] 0
-OLSXW  L1_GETX [0 ] 0
-OLSXW  L1_PUTO [0 ] 0
-OLSXW  L1_PUTX [0 ] 0
-OLSXW  L1_PUTS_only [0 ] 0
-OLSXW  L1_PUTS [0 ] 0
-OLSXW  Fwd_GETX [0 ] 0
-OLSXW  Fwd_GETS [0 ] 0
-OLSXW  Fwd_DMA [0 ] 0
-OLSXW  Inv [0 ] 0
-OLSXW  Unblock [0 ] 0
-OLSXW  L2_Replacement [0 ] 0
-
-ILXW  L1_GETS [33 ] 33
-ILXW  L1_GETX [0 ] 0
-ILXW  L1_PUTO [0 ] 0
-ILXW  L1_PUTX [0 ] 0
-ILXW  L1_PUTS_only [0 ] 0
-ILXW  L1_PUTS [0 ] 0
-ILXW  Fwd_GETX [0 ] 0
-ILXW  Fwd_GETS [0 ] 0
-ILXW  Fwd_DMA [0 ] 0
-ILXW  Inv [0 ] 0
-ILXW  Data [0 ] 0
-ILXW  L1_WBCLEANDATA [86 ] 86
-ILXW  L1_WBDIRTYDATA [817 ] 817
-ILXW  Unblock [0 ] 0
-ILXW  L2_Replacement [0 ] 0
-
-IFLS  L1_GETS [0 ] 0
-IFLS  L1_GETX [0 ] 0
-IFLS  L1_PUTO [0 ] 0
-IFLS  L1_PUTX [0 ] 0
-IFLS  L1_PUTS_only [0 ] 0
-IFLS  L1_PUTS [0 ] 0
-IFLS  Fwd_GETX [0 ] 0
-IFLS  Fwd_GETS [0 ] 0
-IFLS  Fwd_DMA [0 ] 0
-IFLS  Inv [0 ] 0
-IFLS  Unblock [0 ] 0
-IFLS  L2_Replacement [0 ] 0
-
-IFLO  L1_GETS [0 ] 0
-IFLO  L1_GETX [0 ] 0
-IFLO  L1_PUTO [0 ] 0
-IFLO  L1_PUTX [0 ] 0
-IFLO  L1_PUTS_only [0 ] 0
-IFLO  L1_PUTS [0 ] 0
-IFLO  Fwd_GETX [0 ] 0
-IFLO  Fwd_GETS [0 ] 0
-IFLO  Fwd_DMA [0 ] 0
-IFLO  Inv [0 ] 0
-IFLO  Unblock [0 ] 0
-IFLO  L2_Replacement [0 ] 0
-
-IFLOX  L1_GETS [0 ] 0
-IFLOX  L1_GETX [0 ] 0
-IFLOX  L1_PUTO [0 ] 0
-IFLOX  L1_PUTX [0 ] 0
-IFLOX  L1_PUTS_only [0 ] 0
-IFLOX  L1_PUTS [0 ] 0
-IFLOX  Fwd_GETX [0 ] 0
-IFLOX  Fwd_GETS [0 ] 0
-IFLOX  Fwd_DMA [0 ] 0
-IFLOX  Inv [0 ] 0
-IFLOX  Unblock [0 ] 0
-IFLOX  Exclusive_Unblock [0 ] 0
-IFLOX  L2_Replacement [0 ] 0
-
-IFLOXX  L1_GETS [0 ] 0
-IFLOXX  L1_GETX [0 ] 0
-IFLOXX  L1_PUTO [0 ] 0
-IFLOXX  L1_PUTX [0 ] 0
-IFLOXX  L1_PUTS_only [0 ] 0
-IFLOXX  L1_PUTS [0 ] 0
-IFLOXX  Fwd_GETX [0 ] 0
-IFLOXX  Fwd_GETS [0 ] 0
-IFLOXX  Fwd_DMA [0 ] 0
-IFLOXX  Inv [0 ] 0
-IFLOXX  Unblock [0 ] 0
-IFLOXX  Exclusive_Unblock [0 ] 0
-IFLOXX  L2_Replacement [0 ] 0
-
-IFLOSX  L1_GETS [0 ] 0
-IFLOSX  L1_GETX [0 ] 0
-IFLOSX  L1_PUTO [0 ] 0
-IFLOSX  L1_PUTX [0 ] 0
-IFLOSX  L1_PUTS_only [0 ] 0
-IFLOSX  L1_PUTS [0 ] 0
-IFLOSX  Fwd_GETX [0 ] 0
-IFLOSX  Fwd_GETS [0 ] 0
-IFLOSX  Fwd_DMA [0 ] 0
-IFLOSX  Inv [0 ] 0
-IFLOSX  Unblock [0 ] 0
-IFLOSX  Exclusive_Unblock [0 ] 0
-IFLOSX  L2_Replacement [0 ] 0
-
-IFLXO  L1_GETS [0 ] 0
-IFLXO  L1_GETX [0 ] 0
-IFLXO  L1_PUTO [0 ] 0
-IFLXO  L1_PUTX [0 ] 0
-IFLXO  L1_PUTS_only [0 ] 0
-IFLXO  L1_PUTS [0 ] 0
-IFLXO  Fwd_GETX [0 ] 0
-IFLXO  Fwd_GETS [0 ] 0
-IFLXO  Fwd_DMA [0 ] 0
-IFLXO  Inv [0 ] 0
-IFLXO  Exclusive_Unblock [0 ] 0
-IFLXO  L2_Replacement [0 ] 0
-
-IGS  L1_GETS [0 ] 0
-IGS  L1_GETX [0 ] 0
-IGS  L1_PUTO [0 ] 0
-IGS  L1_PUTX [65 ] 65
-IGS  L1_PUTS_only [0 ] 0
-IGS  L1_PUTS [0 ] 0
-IGS  Fwd_GETX [0 ] 0
-IGS  Fwd_GETS [0 ] 0
-IGS  Fwd_DMA [0 ] 0
-IGS  Own_GETX [0 ] 0
-IGS  Inv [0 ] 0
-IGS  Data [0 ] 0
-IGS  Data_Exclusive [88 ] 88
-IGS  Unblock [0 ] 0
-IGS  Exclusive_Unblock [87 ] 87
-IGS  L2_Replacement [0 ] 0
-
-IGM  L1_GETS [0 ] 0
-IGM  L1_GETX [0 ] 0
-IGM  L1_PUTO [0 ] 0
-IGM  L1_PUTX [0 ] 0
-IGM  L1_PUTS_only [0 ] 0
-IGM  L1_PUTS [0 ] 0
-IGM  Fwd_GETX [0 ] 0
-IGM  Fwd_GETS [0 ] 0
-IGM  Fwd_DMA [0 ] 0
-IGM  Own_GETX [0 ] 0
-IGM  Inv [0 ] 0
-IGM  ExtAck [0 ] 0
-IGM  Data [766 ] 766
-IGM  Data_Exclusive [0 ] 0
-IGM  L2_Replacement [0 ] 0
-
-IGMLS  L1_GETS [0 ] 0
-IGMLS  L1_GETX [0 ] 0
-IGMLS  L1_PUTO [0 ] 0
-IGMLS  L1_PUTX [0 ] 0
-IGMLS  L1_PUTS_only [0 ] 0
-IGMLS  L1_PUTS [0 ] 0
-IGMLS  Inv [0 ] 0
-IGMLS  IntAck [0 ] 0
-IGMLS  ExtAck [0 ] 0
-IGMLS  All_Acks [0 ] 0
-IGMLS  Data [0 ] 0
-IGMLS  Data_Exclusive [0 ] 0
-IGMLS  L2_Replacement [0 ] 0
-
-IGMO  L1_GETS [0 ] 0
-IGMO  L1_GETX [0 ] 0
-IGMO  L1_PUTO [0 ] 0
-IGMO  L1_PUTX [1324 ] 1324
-IGMO  L1_PUTS_only [0 ] 0
-IGMO  L1_PUTS [0 ] 0
-IGMO  Fwd_GETX [0 ] 0
-IGMO  Fwd_GETS [0 ] 0
-IGMO  Fwd_DMA [0 ] 0
-IGMO  Own_GETX [0 ] 0
-IGMO  ExtAck [0 ] 0
-IGMO  All_Acks [766 ] 766
-IGMO  Exclusive_Unblock [766 ] 766
-IGMO  L2_Replacement [0 ] 0
-
-IGMIO  L1_GETS [0 ] 0
-IGMIO  L1_GETX [0 ] 0
-IGMIO  L1_PUTO [0 ] 0
-IGMIO  L1_PUTX [0 ] 0
-IGMIO  L1_PUTS_only [0 ] 0
-IGMIO  L1_PUTS [0 ] 0
-IGMIO  Fwd_GETX [0 ] 0
-IGMIO  Fwd_GETS [0 ] 0
-IGMIO  Fwd_DMA [0 ] 0
-IGMIO  Own_GETX [0 ] 0
-IGMIO  ExtAck [0 ] 0
-IGMIO  All_Acks [0 ] 0
-
-OGMIO  L1_GETS [0 ] 0
-OGMIO  L1_GETX [0 ] 0
-OGMIO  L1_PUTO [0 ] 0
-OGMIO  L1_PUTX [0 ] 0
-OGMIO  L1_PUTS_only [0 ] 0
-OGMIO  L1_PUTS [0 ] 0
-OGMIO  Fwd_GETX [0 ] 0
-OGMIO  Fwd_GETS [0 ] 0
-OGMIO  Fwd_DMA [0 ] 0
-OGMIO  Own_GETX [0 ] 0
-OGMIO  ExtAck [0 ] 0
-OGMIO  All_Acks [0 ] 0
-
-IGMIOF  L1_GETS [0 ] 0
-IGMIOF  L1_GETX [0 ] 0
-IGMIOF  L1_PUTO [0 ] 0
-IGMIOF  L1_PUTX [0 ] 0
-IGMIOF  L1_PUTS_only [0 ] 0
-IGMIOF  L1_PUTS [0 ] 0
-IGMIOF  IntAck [0 ] 0
-IGMIOF  All_Acks [0 ] 0
-IGMIOF  Data_Exclusive [0 ] 0
-
-IGMIOFS  L1_GETS [0 ] 0
-IGMIOFS  L1_GETX [0 ] 0
-IGMIOFS  L1_PUTO [0 ] 0
-IGMIOFS  L1_PUTX [0 ] 0
-IGMIOFS  L1_PUTS_only [0 ] 0
-IGMIOFS  L1_PUTS [0 ] 0
-IGMIOFS  Fwd_GETX [0 ] 0
-IGMIOFS  Fwd_GETS [0 ] 0
-IGMIOFS  Fwd_DMA [0 ] 0
-IGMIOFS  Inv [0 ] 0
-IGMIOFS  Data [0 ] 0
-IGMIOFS  L2_Replacement [0 ] 0
-
-OGMIOF  L1_GETS [0 ] 0
-OGMIOF  L1_GETX [0 ] 0
-OGMIOF  L1_PUTO [0 ] 0
-OGMIOF  L1_PUTX [0 ] 0
-OGMIOF  L1_PUTS_only [0 ] 0
-OGMIOF  L1_PUTS [0 ] 0
-OGMIOF  IntAck [0 ] 0
-OGMIOF  All_Acks [0 ] 0
-
-II  L1_GETS [0 ] 0
-II  L1_GETX [0 ] 0
-II  L1_PUTO [0 ] 0
-II  L1_PUTX [0 ] 0
-II  L1_PUTS_only [0 ] 0
-II  L1_PUTS [0 ] 0
-II  IntAck [0 ] 0
-II  All_Acks [0 ] 0
-
-MM  L1_GETS [0 ] 0
-MM  L1_GETX [0 ] 0
-MM  L1_PUTO [0 ] 0
-MM  L1_PUTX [5 ] 5
-MM  L1_PUTS_only [0 ] 0
-MM  L1_PUTS [0 ] 0
-MM  Fwd_GETX [0 ] 0
-MM  Fwd_GETS [0 ] 0
-MM  Fwd_DMA [0 ] 0
-MM  Inv [0 ] 0
-MM  Exclusive_Unblock [47 ] 47
-MM  L2_Replacement [0 ] 0
-
-SS  L1_GETS [0 ] 0
-SS  L1_GETX [0 ] 0
-SS  L1_PUTO [0 ] 0
-SS  L1_PUTX [0 ] 0
-SS  L1_PUTS_only [0 ] 0
-SS  L1_PUTS [0 ] 0
-SS  Fwd_GETX [0 ] 0
-SS  Fwd_GETS [0 ] 0
-SS  Fwd_DMA [0 ] 0
-SS  Inv [0 ] 0
-SS  Unblock [0 ] 0
-SS  L2_Replacement [0 ] 0
-
-OO  L1_GETS [0 ] 0
-OO  L1_GETX [0 ] 0
-OO  L1_PUTO [0 ] 0
-OO  L1_PUTX [11 ] 11
-OO  L1_PUTS_only [0 ] 0
-OO  L1_PUTS [0 ] 0
-OO  Fwd_GETX [0 ] 0
-OO  Fwd_GETS [0 ] 0
-OO  Fwd_DMA [0 ] 0
-OO  Inv [0 ] 0
-OO  Unblock [0 ] 0
-OO  Exclusive_Unblock [6 ] 6
-OO  L2_Replacement [0 ] 0
-
-OLSS  L1_GETS [0 ] 0
-OLSS  L1_GETX [0 ] 0
-OLSS  L1_PUTO [0 ] 0
-OLSS  L1_PUTX [0 ] 0
-OLSS  L1_PUTS_only [0 ] 0
-OLSS  L1_PUTS [0 ] 0
-OLSS  Fwd_GETX [0 ] 0
-OLSS  Fwd_GETS [0 ] 0
-OLSS  Fwd_DMA [0 ] 0
-OLSS  Inv [0 ] 0
-OLSS  Unblock [0 ] 0
-OLSS  L2_Replacement [0 ] 0
-
-OLSXS  L1_GETS [0 ] 0
-OLSXS  L1_GETX [0 ] 0
-OLSXS  L1_PUTO [0 ] 0
-OLSXS  L1_PUTX [0 ] 0
-OLSXS  L1_PUTS_only [0 ] 0
-OLSXS  L1_PUTS [0 ] 0
-OLSXS  Fwd_GETX [0 ] 0
-OLSXS  Fwd_GETS [0 ] 0
-OLSXS  Fwd_DMA [0 ] 0
-OLSXS  Inv [0 ] 0
-OLSXS  Unblock [0 ] 0
-OLSXS  L2_Replacement [0 ] 0
-
-SLSS  L1_GETS [0 ] 0
-SLSS  L1_GETX [0 ] 0
-SLSS  L1_PUTO [0 ] 0
-SLSS  L1_PUTX [0 ] 0
-SLSS  L1_PUTS_only [0 ] 0
-SLSS  L1_PUTS [0 ] 0
-SLSS  Fwd_GETX [0 ] 0
-SLSS  Fwd_GETS [0 ] 0
-SLSS  Fwd_DMA [0 ] 0
-SLSS  Inv [0 ] 0
-SLSS  Unblock [0 ] 0
-SLSS  L2_Replacement [0 ] 0
-
-OI  L1_GETS [0 ] 0
-OI  L1_GETX [0 ] 0
-OI  L1_PUTO [0 ] 0
-OI  L1_PUTX [0 ] 0
-OI  L1_PUTS_only [0 ] 0
-OI  L1_PUTS [0 ] 0
-OI  Fwd_GETX [0 ] 0
-OI  Fwd_GETS [0 ] 0
-OI  Fwd_DMA [0 ] 0
-OI  Writeback_Ack [0 ] 0
-OI  Writeback_Nack [0 ] 0
-OI  L2_Replacement [0 ] 0
-
-MI  L1_GETS [0 ] 0
-MI  L1_GETX [81 ] 81
-MI  L1_PUTO [0 ] 0
-MI  L1_PUTX [0 ] 0
-MI  L1_PUTS_only [0 ] 0
-MI  L1_PUTS [0 ] 0
-MI  Fwd_GETX [0 ] 0
-MI  Fwd_GETS [0 ] 0
-MI  Fwd_DMA [0 ] 0
-MI  Writeback_Ack [845 ] 845
-MI  L2_Replacement [0 ] 0
-
-MII  L1_GETS [0 ] 0
-MII  L1_GETX [0 ] 0
-MII  L1_PUTO [0 ] 0
-MII  L1_PUTX [0 ] 0
-MII  L1_PUTS_only [0 ] 0
-MII  L1_PUTS [0 ] 0
-MII  Writeback_Ack [0 ] 0
-MII  Writeback_Nack [0 ] 0
-MII  L2_Replacement [0 ] 0
-
-OLSI  L1_GETS [0 ] 0
-OLSI  L1_GETX [0 ] 0
-OLSI  L1_PUTO [0 ] 0
-OLSI  L1_PUTX [0 ] 0
-OLSI  L1_PUTS_only [0 ] 0
-OLSI  L1_PUTS [0 ] 0
-OLSI  Fwd_GETX [0 ] 0
-OLSI  Fwd_GETS [0 ] 0
-OLSI  Fwd_DMA [0 ] 0
-OLSI  Writeback_Ack [0 ] 0
-OLSI  L2_Replacement [0 ] 0
-
-ILSI  L1_GETS [0 ] 0
-ILSI  L1_GETX [0 ] 0
-ILSI  L1_PUTO [0 ] 0
-ILSI  L1_PUTX [0 ] 0
-ILSI  L1_PUTS_only [0 ] 0
-ILSI  L1_PUTS [0 ] 0
-ILSI  IntAck [0 ] 0
-ILSI  All_Acks [0 ] 0
-ILSI  Writeback_Ack [0 ] 0
-ILSI  L2_Replacement [0 ] 0
-
-ILOSD  L1_GETS [0 ] 0
-ILOSD  L1_GETX [0 ] 0
-ILOSD  L1_PUTO [0 ] 0
-ILOSD  L1_PUTX [0 ] 0
-ILOSD  L1_PUTS_only [0 ] 0
-ILOSD  L1_PUTS [0 ] 0
-ILOSD  Fwd_GETX [0 ] 0
-ILOSD  Fwd_GETS [0 ] 0
-ILOSD  Fwd_DMA [0 ] 0
-ILOSD  Own_GETX [0 ] 0
-ILOSD  Inv [0 ] 0
-ILOSD  DmaAck [0 ] 0
-ILOSD  L2_Replacement [0 ] 0
-
-ILOSXD  L1_GETS [0 ] 0
-ILOSXD  L1_GETX [0 ] 0
-ILOSXD  L1_PUTO [0 ] 0
-ILOSXD  L1_PUTX [0 ] 0
-ILOSXD  L1_PUTS_only [0 ] 0
-ILOSXD  L1_PUTS [0 ] 0
-ILOSXD  Fwd_GETX [0 ] 0
-ILOSXD  Fwd_GETS [0 ] 0
-ILOSXD  Fwd_DMA [0 ] 0
-ILOSXD  Own_GETX [0 ] 0
-ILOSXD  Inv [0 ] 0
-ILOSXD  DmaAck [0 ] 0
-ILOSXD  L2_Replacement [0 ] 0
-
-ILOD  L1_GETS [0 ] 0
-ILOD  L1_GETX [0 ] 0
-ILOD  L1_PUTO [0 ] 0
-ILOD  L1_PUTX [0 ] 0
-ILOD  L1_PUTS_only [0 ] 0
-ILOD  L1_PUTS [0 ] 0
-ILOD  Fwd_GETX [0 ] 0
-ILOD  Fwd_GETS [0 ] 0
-ILOD  Fwd_DMA [0 ] 0
-ILOD  Own_GETX [0 ] 0
-ILOD  Inv [0 ] 0
-ILOD  DmaAck [0 ] 0
-ILOD  L2_Replacement [0 ] 0
-
-ILXD  L1_GETS [0 ] 0
-ILXD  L1_GETX [0 ] 0
-ILXD  L1_PUTO [0 ] 0
-ILXD  L1_PUTX [0 ] 0
-ILXD  L1_PUTS_only [0 ] 0
-ILXD  L1_PUTS [0 ] 0
-ILXD  Fwd_GETX [0 ] 0
-ILXD  Fwd_GETS [0 ] 0
-ILXD  Fwd_DMA [0 ] 0
-ILXD  Own_GETX [0 ] 0
-ILXD  Inv [0 ] 0
-ILXD  DmaAck [0 ] 0
-ILXD  L2_Replacement [0 ] 0
-
-ILOXD  L1_GETS [0 ] 0
-ILOXD  L1_GETX [0 ] 0
-ILOXD  L1_PUTO [0 ] 0
-ILOXD  L1_PUTX [0 ] 0
-ILOXD  L1_PUTS_only [0 ] 0
-ILOXD  L1_PUTS [0 ] 0
-ILOXD  Fwd_GETX [0 ] 0
-ILOXD  Fwd_GETS [0 ] 0
-ILOXD  Fwd_DMA [0 ] 0
-ILOXD  Own_GETX [0 ] 0
-ILOXD  Inv [0 ] 0
-ILOXD  DmaAck [0 ] 0
-ILOXD  L2_Replacement [0 ] 0
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 1619
-  memory_reads: 854
-  memory_writes: 765
-  memory_refreshes: 2273
-  memory_total_request_delays: 446
-  memory_delays_per_request: 0.275479
-  memory_delays_in_input_queue: 26
-  memory_delays_behind_head_of_bank_queue: 0
-  memory_delays_stalled_at_head_of_bank_queue: 420
-  memory_stalls_for_bank_busy: 163
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 32
-  memory_stalls_for_bus: 144
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 21
-  memory_stalls_for_read_read_turnaround: 60
-  accesses_per_bank: 49  44  48  84  49  52  64  51  40  45  48  41  74  47  51  38  56  62  37  58  46  50  55  36  49  71  52  40  42  33  48  59  
-
- --- Directory ---
- - Event Counts -
-GETX [837 ] 837
-GETS [88 ] 88
-PUTX [845 ] 845
-PUTO [0 ] 0
-PUTO_SHARERS [0 ] 0
-Unblock [0 ] 0
-Last_Unblock [0 ] 0
-Exclusive_Unblock [852 ] 852
-Clean_Writeback [80 ] 80
-Dirty_Writeback [765 ] 765
-Memory_Data [854 ] 854
-Memory_Ack [765 ] 765
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-DMA_ACK [0 ] 0
-Data [0 ] 0
-
- - Transitions -
-I  GETX [766 ] 766
-I  GETS [88 ] 88
-I  PUTX [0 ] 0
-I  PUTO [0 ] 0
-I  Memory_Data [0 ] 0
-I  Memory_Ack [760 ] 760
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-S  GETX [0 ] 0
-S  GETS [0 ] 0
-S  PUTX [0 ] 0
-S  PUTO [0 ] 0
-S  Memory_Data [0 ] 0
-S  Memory_Ack [0 ] 0
-S  DMA_READ [0 ] 0
-S  DMA_WRITE [0 ] 0
-
-O  GETX [0 ] 0
-O  GETS [0 ] 0
-O  PUTX [0 ] 0
-O  PUTO [0 ] 0
-O  PUTO_SHARERS [0 ] 0
-O  Memory_Data [0 ] 0
-O  Memory_Ack [0 ] 0
-O  DMA_READ [0 ] 0
-O  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  GETS [0 ] 0
-M  PUTX [845 ] 845
-M  PUTO [0 ] 0
-M  PUTO_SHARERS [0 ] 0
-M  Memory_Data [0 ] 0
-M  Memory_Ack [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-IS  GETX [0 ] 0
-IS  GETS [0 ] 0
-IS  PUTX [0 ] 0
-IS  PUTO [0 ] 0
-IS  PUTO_SHARERS [0 ] 0
-IS  Unblock [0 ] 0
-IS  Exclusive_Unblock [87 ] 87
-IS  Memory_Data [88 ] 88
-IS  Memory_Ack [1 ] 1
-IS  DMA_READ [0 ] 0
-IS  DMA_WRITE [0 ] 0
-
-SS  GETX [0 ] 0
-SS  GETS [0 ] 0
-SS  PUTX [0 ] 0
-SS  PUTO [0 ] 0
-SS  PUTO_SHARERS [0 ] 0
-SS  Unblock [0 ] 0
-SS  Last_Unblock [0 ] 0
-SS  Memory_Data [0 ] 0
-SS  Memory_Ack [0 ] 0
-SS  DMA_READ [0 ] 0
-SS  DMA_WRITE [0 ] 0
-
-OO  GETX [0 ] 0
-OO  GETS [0 ] 0
-OO  PUTX [0 ] 0
-OO  PUTO [0 ] 0
-OO  PUTO_SHARERS [0 ] 0
-OO  Unblock [0 ] 0
-OO  Last_Unblock [0 ] 0
-OO  Memory_Data [0 ] 0
-OO  Memory_Ack [0 ] 0
-OO  DMA_READ [0 ] 0
-OO  DMA_WRITE [0 ] 0
-
-MO  GETX [0 ] 0
-MO  GETS [0 ] 0
-MO  PUTX [0 ] 0
-MO  PUTO [0 ] 0
-MO  PUTO_SHARERS [0 ] 0
-MO  Unblock [0 ] 0
-MO  Exclusive_Unblock [0 ] 0
-MO  Memory_Data [0 ] 0
-MO  Memory_Ack [0 ] 0
-MO  DMA_READ [0 ] 0
-MO  DMA_WRITE [0 ] 0
-
-MM  GETX [0 ] 0
-MM  GETS [0 ] 0
-MM  PUTX [0 ] 0
-MM  PUTO [0 ] 0
-MM  PUTO_SHARERS [0 ] 0
-MM  Exclusive_Unblock [765 ] 765
-MM  Memory_Data [766 ] 766
-MM  Memory_Ack [4 ] 4
-MM  DMA_READ [0 ] 0
-MM  DMA_WRITE [0 ] 0
-
-
-MI  GETX [71 ] 71
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTO [0 ] 0
-MI  PUTO_SHARERS [0 ] 0
-MI  Unblock [0 ] 0
-MI  Clean_Writeback [80 ] 80
-MI  Dirty_Writeback [765 ] 765
-MI  Memory_Data [0 ] 0
-MI  Memory_Ack [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-
-MIS  GETX [0 ] 0
-MIS  GETS [0 ] 0
-MIS  PUTX [0 ] 0
-MIS  PUTO [0 ] 0
-MIS  PUTO_SHARERS [0 ] 0
-MIS  Unblock [0 ] 0
-MIS  Clean_Writeback [0 ] 0
-MIS  Dirty_Writeback [0 ] 0
-MIS  Memory_Data [0 ] 0
-MIS  Memory_Ack [0 ] 0
-MIS  DMA_READ [0 ] 0
-MIS  DMA_WRITE [0 ] 0
-
-OS  GETX [0 ] 0
-OS  GETS [0 ] 0
-OS  PUTX [0 ] 0
-OS  PUTO [0 ] 0
-OS  PUTO_SHARERS [0 ] 0
-OS  Unblock [0 ] 0
-OS  Clean_Writeback [0 ] 0
-OS  Dirty_Writeback [0 ] 0
-OS  Memory_Data [0 ] 0
-OS  Memory_Ack [0 ] 0
-OS  DMA_READ [0 ] 0
-OS  DMA_WRITE [0 ] 0
-
-OSS  GETX [0 ] 0
-OSS  GETS [0 ] 0
-OSS  PUTX [0 ] 0
-OSS  PUTO [0 ] 0
-OSS  PUTO_SHARERS [0 ] 0
-OSS  Unblock [0 ] 0
-OSS  Clean_Writeback [0 ] 0
-OSS  Dirty_Writeback [0 ] 0
-OSS  Memory_Data [0 ] 0
-OSS  Memory_Ack [0 ] 0
-OSS  DMA_READ [0 ] 0
-OSS  DMA_WRITE [0 ] 0
-
-XI_M  GETX [0 ] 0
-XI_M  GETS [0 ] 0
-XI_M  PUTX [0 ] 0
-XI_M  PUTO [0 ] 0
-XI_M  PUTO_SHARERS [0 ] 0
-XI_M  Memory_Data [0 ] 0
-XI_M  Memory_Ack [0 ] 0
-XI_M  DMA_READ [0 ] 0
-XI_M  DMA_WRITE [0 ] 0
-
-XI_U  GETX [0 ] 0
-XI_U  GETS [0 ] 0
-XI_U  PUTX [0 ] 0
-XI_U  PUTO [0 ] 0
-XI_U  PUTO_SHARERS [0 ] 0
-XI_U  Exclusive_Unblock [0 ] 0
-XI_U  Memory_Ack [0 ] 0
-XI_U  DMA_READ [0 ] 0
-XI_U  DMA_WRITE [0 ] 0
-
-OI_D  GETX [0 ] 0
-OI_D  GETS [0 ] 0
-OI_D  PUTX [0 ] 0
-OI_D  PUTO [0 ] 0
-OI_D  PUTO_SHARERS [0 ] 0
-OI_D  DMA_READ [0 ] 0
-OI_D  DMA_WRITE [0 ] 0
-OI_D  Data [0 ] 0
-
-OD  GETX [0 ] 0
-OD  GETS [0 ] 0
-OD  PUTX [0 ] 0
-OD  PUTO [0 ] 0
-OD  PUTO_SHARERS [0 ] 0
-OD  DMA_READ [0 ] 0
-OD  DMA_WRITE [0 ] 0
-OD  DMA_ACK [0 ] 0
-
-MD  GETX [0 ] 0
-MD  GETS [0 ] 0
-MD  PUTX [0 ] 0
-MD  PUTO [0 ] 0
-MD  PUTO_SHARERS [0 ] 0
-MD  DMA_READ [0 ] 0
-MD  DMA_WRITE [0 ] 0
-MD  DMA_ACK [0 ] 0
-
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 18d6ea72e..619c6b01e 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000327                       # Nu
 sim_ticks                                      327361                       # Number of ticks simulated
 final_tick                                     327361                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 517762                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 149964                       # Number of bytes of host memory used
-host_seconds                                     0.63                       # Real time elapsed on the host
+host_tick_rate                                 849675                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 144052                       # Number of bytes of host memory used
+host_seconds                                     0.39                       # Real time elapsed on the host
 system.ruby.l2_cntrl0.L2cache.demand_hits           53                       # Number of cache demand hits
 system.ruby.l2_cntrl0.L2cache.demand_misses          855                       # Number of cache demand misses
 system.ruby.l2_cntrl0.L2cache.demand_accesses          908                       # Number of cache demand accesses
@@ -16,5 +16,104 @@ system.ruby.l1_cntrl0.L1Dcache.demand_accesses          930
 system.ruby.l1_cntrl0.L1Icache.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses           56                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Icache.demand_accesses           56                       # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq          1619                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          854                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          765                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         2273                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          420                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           26                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          446                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.275479                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          163                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          144                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           21                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           60                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           32                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          49      3.03%      3.03% |          44      2.72%      5.74% |          48      2.96%      8.71% |          84      5.19%     13.90% |          49      3.03%     16.92% |          52      3.21%     20.14% |          64      3.95%     24.09% |          51      3.15%     27.24% |          40      2.47%     29.71% |          45      2.78%     32.49% |          48      2.96%     35.45% |          41      2.53%     37.99% |          74      4.57%     42.56% |          47      2.90%     45.46% |          51      3.15%     48.61% |          38      2.35%     50.96% |          56      3.46%     54.42% |          62      3.83%     58.25% |          37      2.29%     60.53% |          58      3.58%     64.11% |          46      2.84%     66.95% |          50      3.09%     70.04% |          55      3.40%     73.44% |          36      2.22%     75.66% |          49      3.03%     78.69% |          71      4.39%     83.08% |          52      3.21%     86.29% |          40      2.47%     88.76% |          42      2.59%     91.35% |          33      2.04%     93.39% |          48      2.96%     96.36% |          59      3.64%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1619                       # Number of accesses per bank
+
+system.ruby.l2_cntrl0.L1_GETS                     127      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_GETX                     895      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_PUTX                    2308      0.00%      0.00%
+system.ruby.l2_cntrl0.All_Acks                    766      0.00%      0.00%
+system.ruby.l2_cntrl0.Data                        766      0.00%      0.00%
+system.ruby.l2_cntrl0.Data_Exclusive               88      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_WBCLEANDATA               86      0.00%      0.00%
+system.ruby.l2_cntrl0.L1_WBDIRTYDATA              817      0.00%      0.00%
+system.ruby.l2_cntrl0.Writeback_Ack               845      0.00%      0.00%
+system.ruby.l2_cntrl0.Exclusive_Unblock           906      0.00%      0.00%
+system.ruby.l2_cntrl0.L2_Replacement              847      0.00%      0.00%
+system.ruby.l2_cntrl0.NP.L1_GETS                   88      0.00%      0.00%
+system.ruby.l2_cntrl0.NP.L1_GETX                  767      0.00%      0.00%
+system.ruby.l2_cntrl0.ILX.L1_PUTX                 903      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L1_GETS                     6      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L1_GETX                    47      0.00%      0.00%
+system.ruby.l2_cntrl0.M.L2_Replacement            847      0.00%      0.00%
+system.ruby.l2_cntrl0.ILXW.L1_GETS                 33      0.00%      0.00%
+system.ruby.l2_cntrl0.ILXW.L1_WBCLEANDATA           86      0.00%      0.00%
+system.ruby.l2_cntrl0.ILXW.L1_WBDIRTYDATA          817      0.00%      0.00%
+system.ruby.l2_cntrl0.IGS.L1_PUTX                  65      0.00%      0.00%
+system.ruby.l2_cntrl0.IGS.Data_Exclusive           88      0.00%      0.00%
+system.ruby.l2_cntrl0.IGS.Exclusive_Unblock           87      0.00%      0.00%
+system.ruby.l2_cntrl0.IGM.Data                    766      0.00%      0.00%
+system.ruby.l2_cntrl0.IGMO.L1_PUTX               1324      0.00%      0.00%
+system.ruby.l2_cntrl0.IGMO.All_Acks               766      0.00%      0.00%
+system.ruby.l2_cntrl0.IGMO.Exclusive_Unblock          766      0.00%      0.00%
+system.ruby.l2_cntrl0.MM.L1_PUTX                    5      0.00%      0.00%
+system.ruby.l2_cntrl0.MM.Exclusive_Unblock           47      0.00%      0.00%
+system.ruby.l2_cntrl0.OO.L1_PUTX                   11      0.00%      0.00%
+system.ruby.l2_cntrl0.OO.Exclusive_Unblock            6      0.00%      0.00%
+system.ruby.l2_cntrl0.MI.L1_GETX                   81      0.00%      0.00%
+system.ruby.l2_cntrl0.MI.Writeback_Ack            845      0.00%      0.00%
+system.ruby.l1_cntrl0.Load                         44      0.00%      0.00%
+system.ruby.l1_cntrl0.Ifetch                      192      0.00%      0.00%
+system.ruby.l1_cntrl0.Store                      1001      0.00%      0.00%
+system.ruby.l1_cntrl0.L1_Replacement           465203      0.00%      0.00%
+system.ruby.l1_cntrl0.Exclusive_Data              907      0.00%      0.00%
+system.ruby.l1_cntrl0.Writeback_Ack_Data          903      0.00%      0.00%
+system.ruby.l1_cntrl0.All_acks                    813      0.00%      0.00%
+system.ruby.l1_cntrl0.Use_Timeout                 905      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Load                       38      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Ifetch                     56      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Store                     814      0.00%      0.00%
+system.ruby.l1_cntrl0.M.L1_Replacement             92      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.L1_Replacement         1319      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.Use_Timeout              93      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Load                       6      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Store                     66      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.L1_Replacement           811      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Store                    6      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.L1_Replacement        29843      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Use_Timeout            812      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.L1_Replacement        399867      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.Exclusive_Data           813      0.00%      0.00%
+system.ruby.l1_cntrl0.OM.L1_Replacement         17168      0.00%      0.00%
+system.ruby.l1_cntrl0.OM.All_acks                 813      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.L1_Replacement         16103      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.Exclusive_Data            94      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Ifetch                   136      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Store                    115      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack_Data          903      0.00%      0.00%
+system.ruby.dir_cntrl0.GETX                       837      0.00%      0.00%
+system.ruby.dir_cntrl0.GETS                        88      0.00%      0.00%
+system.ruby.dir_cntrl0.PUTX                       845      0.00%      0.00%
+system.ruby.dir_cntrl0.Exclusive_Unblock          852      0.00%      0.00%
+system.ruby.dir_cntrl0.Clean_Writeback             80      0.00%      0.00%
+system.ruby.dir_cntrl0.Dirty_Writeback            765      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Data                854      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Ack                 765      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETX                     766      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETS                      88      0.00%      0.00%
+system.ruby.dir_cntrl0.I.Memory_Ack               760      0.00%      0.00%
+system.ruby.dir_cntrl0.M.PUTX                     845      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Exclusive_Unblock           87      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Memory_Data              88      0.00%      0.00%
+system.ruby.dir_cntrl0.IS.Memory_Ack                1      0.00%      0.00%
+system.ruby.dir_cntrl0.MM.Exclusive_Unblock          765      0.00%      0.00%
+system.ruby.dir_cntrl0.MM.Memory_Data             766      0.00%      0.00%
+system.ruby.dir_cntrl0.MM.Memory_Ack                4      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.GETX                     71      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Clean_Writeback           80      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Dirty_Writeback          765      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------