stats: updates due to changes to ruby

Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.

2 files changed, 113 insertions, 764 deletions

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 3336c8aea..822026fbf 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Feb/02/2013 08:11:05
+Real time: Jun/08/2013 13:29:50
 
 Profiler Stats
 --------------
@@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.52
-Virtual_time_in_minutes: 0.00866667
-Virtual_time_in_hours:   0.000144444
-Virtual_time_in_days:    6.01852e-06
+Virtual_time_in_seconds: 0.5
+Virtual_time_in_minutes: 0.00833333
+Virtual_time_in_hours:   0.000138889
+Virtual_time_in_days:    5.78704e-06
 
 Ruby_current_time: 172201
 Ruby_start_time: 0
 Ruby_cycles: 172201
 
-mbytes_resident: 49.1211
-mbytes_total: 265.684
-resident_ratio: 0.18493
-
-ruby_cycles_executed: [ 172202 ]
+mbytes_resident: 51.9141
+mbytes_total: 139.598
+resident_ratio: 0.371939
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -69,7 +67,6 @@ Request vs. RubySystem State Profile
 --------------------------------
 
 
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Message Delayed Cycles
 ----------------------
@@ -90,11 +87,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 10236
-page_faults: 0
+page_reclaims: 13998
+page_faults: 36
 swaps: 0
-block_inputs: 0
-block_outputs: 96
+block_inputs: 4432
+block_outputs: 88
 
 Network Stats
 -------------
@@ -145,749 +142,3 @@ links_utilized_percent_switch_2: 2.61613
   outgoing_messages_switch_2_link_1_Writeback_Control: 918 7344 [ 0 0 843 0 0 75 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Unblock_Control: 845 6760 [ 0 0 0 0 0 845 0 0 0 0 ] base_latency: 1
 
- --- L1Cache ---
- - Event Counts -
-Load [52 ] 52
-Ifetch [53 ] 53
-Store [888 ] 888
-L2_Replacement [840 ] 840
-L1_to_L2 [16587 ] 16587
-Trigger_L2_to_L1D [41 ] 41
-Trigger_L2_to_L1I [9 ] 9
-Complete_L2_to_L1 [50 ] 50
-Other_GETX [0 ] 0
-Other_GETS [0 ] 0
-Merged_GETS [0 ] 0
-Other_GETS_No_Mig [0 ] 0
-NC_DMA_GETS [0 ] 0
-Invalidate [0 ] 0
-Ack [0 ] 0
-Shared_Ack [0 ] 0
-Data [0 ] 0
-Shared_Data [0 ] 0
-Exclusive_Data [850 ] 850
-Writeback_Ack [843 ] 843
-Writeback_Nack [0 ] 0
-All_acks [0 ] 0
-All_acks_no_sharers [850 ] 850
-Flush_line [5 ] 5
-Block_Ack [1 ] 1
-
- - Transitions -
-I  Load [46 ] 46
-I  Ifetch [40 ] 40
-I  Store [762 ] 762
-I  L2_Replacement [0 ] 0
-I  L1_to_L2 [0 ] 0
-I  Trigger_L2_to_L1D [0 ] 0
-I  Trigger_L2_to_L1I [0 ] 0
-I  Other_GETX [0 ] 0
-I  Other_GETS [0 ] 0
-I  Other_GETS_No_Mig [0 ] 0
-I  NC_DMA_GETS [0 ] 0
-I  Invalidate [0 ] 0
-I  Flush_line [4 ] 4
-
-S  Load [0 ] 0
-S  Ifetch [0 ] 0
-S  Store [0 ] 0
-S  L2_Replacement [0 ] 0
-S  L1_to_L2 [0 ] 0
-S  Trigger_L2_to_L1D [0 ] 0
-S  Trigger_L2_to_L1I [0 ] 0
-S  Other_GETX [0 ] 0
-S  Other_GETS [0 ] 0
-S  Other_GETS_No_Mig [0 ] 0
-S  NC_DMA_GETS [0 ] 0
-S  Invalidate [0 ] 0
-S  Flush_line [0 ] 0
-
-O  Load [0 ] 0
-O  Ifetch [0 ] 0
-O  Store [0 ] 0
-O  L2_Replacement [0 ] 0
-O  L1_to_L2 [0 ] 0
-O  Trigger_L2_to_L1D [0 ] 0
-O  Trigger_L2_to_L1I [0 ] 0
-O  Other_GETX [0 ] 0
-O  Other_GETS [0 ] 0
-O  Merged_GETS [0 ] 0
-O  Other_GETS_No_Mig [0 ] 0
-O  NC_DMA_GETS [0 ] 0
-O  Invalidate [0 ] 0
-O  Flush_line [0 ] 0
-
-M  Load [0 ] 0
-M  Ifetch [1 ] 1
-M  Store [0 ] 0
-M  L2_Replacement [71 ] 71
-M  L1_to_L2 [83 ] 83
-M  Trigger_L2_to_L1D [11 ] 11
-M  Trigger_L2_to_L1I [0 ] 0
-M  Other_GETX [0 ] 0
-M  Other_GETS [0 ] 0
-M  Merged_GETS [0 ] 0
-M  Other_GETS_No_Mig [0 ] 0
-M  NC_DMA_GETS [0 ] 0
-M  Invalidate [0 ] 0
-M  Flush_line [0 ] 0
-
-MM  Load [5 ] 5
-MM  Ifetch [0 ] 0
-MM  Store [62 ] 62
-MM  L2_Replacement [769 ] 769
-MM  L1_to_L2 [809 ] 809
-MM  Trigger_L2_to_L1D [30 ] 30
-MM  Trigger_L2_to_L1I [9 ] 9
-MM  Other_GETX [0 ] 0
-MM  Other_GETS [0 ] 0
-MM  Merged_GETS [0 ] 0
-MM  Other_GETS_No_Mig [0 ] 0
-MM  NC_DMA_GETS [0 ] 0
-MM  Invalidate [0 ] 0
-MM  Flush_line [0 ] 0
-
-IR  Load [0 ] 0
-IR  Ifetch [0 ] 0
-IR  Store [0 ] 0
-IR  L1_to_L2 [0 ] 0
-IR  Flush_line [0 ] 0
-
-SR  Load [0 ] 0
-SR  Ifetch [0 ] 0
-SR  Store [0 ] 0
-SR  L1_to_L2 [0 ] 0
-SR  Flush_line [0 ] 0
-
-OR  Load [0 ] 0
-OR  Ifetch [0 ] 0
-OR  Store [0 ] 0
-OR  L1_to_L2 [0 ] 0
-OR  Flush_line [0 ] 0
-
-MR  Load [0 ] 0
-MR  Ifetch [0 ] 0
-MR  Store [11 ] 11
-MR  L1_to_L2 [90 ] 90
-MR  Flush_line [0 ] 0
-
-MMR  Load [0 ] 0
-MMR  Ifetch [9 ] 9
-MMR  Store [29 ] 29
-MMR  L1_to_L2 [25 ] 25
-MMR  Flush_line [1 ] 1
-
-IM  Load [0 ] 0
-IM  Ifetch [0 ] 0
-IM  Store [0 ] 0
-IM  L2_Replacement [0 ] 0
-IM  L1_to_L2 [9996 ] 9996
-IM  Other_GETX [0 ] 0
-IM  Other_GETS [0 ] 0
-IM  Other_GETS_No_Mig [0 ] 0
-IM  NC_DMA_GETS [0 ] 0
-IM  Invalidate [0 ] 0
-IM  Ack [0 ] 0
-IM  Data [0 ] 0
-IM  Exclusive_Data [761 ] 761
-IM  Flush_line [0 ] 0
-
-SM  Load [0 ] 0
-SM  Ifetch [0 ] 0
-SM  Store [0 ] 0
-SM  L2_Replacement [0 ] 0
-SM  L1_to_L2 [0 ] 0
-SM  Other_GETX [0 ] 0
-SM  Other_GETS [0 ] 0
-SM  Other_GETS_No_Mig [0 ] 0
-SM  NC_DMA_GETS [0 ] 0
-SM  Invalidate [0 ] 0
-SM  Ack [0 ] 0
-SM  Data [0 ] 0
-SM  Exclusive_Data [0 ] 0
-SM  Flush_line [0 ] 0
-
-OM  Load [0 ] 0
-OM  Ifetch [0 ] 0
-OM  Store [0 ] 0
-OM  L2_Replacement [0 ] 0
-OM  L1_to_L2 [0 ] 0
-OM  Other_GETX [0 ] 0
-OM  Other_GETS [0 ] 0
-OM  Merged_GETS [0 ] 0
-OM  Other_GETS_No_Mig [0 ] 0
-OM  NC_DMA_GETS [0 ] 0
-OM  Invalidate [0 ] 0
-OM  Ack [0 ] 0
-OM  All_acks [0 ] 0
-OM  All_acks_no_sharers [0 ] 0
-OM  Flush_line [0 ] 0
-
-ISM  Load [0 ] 0
-ISM  Ifetch [0 ] 0
-ISM  Store [0 ] 0
-ISM  L2_Replacement [0 ] 0
-ISM  L1_to_L2 [0 ] 0
-ISM  Ack [0 ] 0
-ISM  All_acks_no_sharers [0 ] 0
-ISM  Flush_line [0 ] 0
-
-M_W  Load [0 ] 0
-M_W  Ifetch [0 ] 0
-M_W  Store [0 ] 0
-M_W  L2_Replacement [0 ] 0
-M_W  L1_to_L2 [306 ] 306
-M_W  Ack [0 ] 0
-M_W  All_acks_no_sharers [85 ] 85
-M_W  Flush_line [0 ] 0
-
-MM_W  Load [0 ] 0
-MM_W  Ifetch [0 ] 0
-MM_W  Store [3 ] 3
-MM_W  L2_Replacement [0 ] 0
-MM_W  L1_to_L2 [4592 ] 4592
-MM_W  Ack [0 ] 0
-MM_W  All_acks_no_sharers [761 ] 761
-MM_W  Flush_line [0 ] 0
-
-IS  Load [0 ] 0
-IS  Ifetch [0 ] 0
-IS  Store [0 ] 0
-IS  L2_Replacement [0 ] 0
-IS  L1_to_L2 [529 ] 529
-IS  Other_GETX [0 ] 0
-IS  Other_GETS [0 ] 0
-IS  Other_GETS_No_Mig [0 ] 0
-IS  NC_DMA_GETS [0 ] 0
-IS  Invalidate [0 ] 0
-IS  Ack [0 ] 0
-IS  Shared_Ack [0 ] 0
-IS  Data [0 ] 0
-IS  Shared_Data [0 ] 0
-IS  Exclusive_Data [85 ] 85
-IS  Flush_line [0 ] 0
-
-SS  Load [0 ] 0
-SS  Ifetch [0 ] 0
-SS  Store [0 ] 0
-SS  L2_Replacement [0 ] 0
-SS  L1_to_L2 [0 ] 0
-SS  Ack [0 ] 0
-SS  Shared_Ack [0 ] 0
-SS  All_acks [0 ] 0
-SS  All_acks_no_sharers [0 ] 0
-SS  Flush_line [0 ] 0
-
-OI  Load [0 ] 0
-OI  Ifetch [0 ] 0
-OI  Store [0 ] 0
-OI  L2_Replacement [0 ] 0
-OI  L1_to_L2 [0 ] 0
-OI  Other_GETX [0 ] 0
-OI  Other_GETS [0 ] 0
-OI  Merged_GETS [0 ] 0
-OI  Other_GETS_No_Mig [0 ] 0
-OI  NC_DMA_GETS [0 ] 0
-OI  Invalidate [0 ] 0
-OI  Writeback_Ack [0 ] 0
-OI  Flush_line [0 ] 0
-
-MI  Load [1 ] 1
-MI  Ifetch [3 ] 3
-MI  Store [1 ] 1
-MI  L2_Replacement [0 ] 0
-MI  L1_to_L2 [0 ] 0
-MI  Other_GETX [0 ] 0
-MI  Other_GETS [0 ] 0
-MI  Merged_GETS [0 ] 0
-MI  Other_GETS_No_Mig [0 ] 0
-MI  NC_DMA_GETS [0 ] 0
-MI  Invalidate [0 ] 0
-MI  Writeback_Ack [838 ] 838
-MI  Flush_line [0 ] 0
-
-II  Load [0 ] 0
-II  Ifetch [0 ] 0
-II  Store [0 ] 0
-II  L2_Replacement [0 ] 0
-II  L1_to_L2 [0 ] 0
-II  Other_GETX [0 ] 0
-II  Other_GETS [0 ] 0
-II  Other_GETS_No_Mig [0 ] 0
-II  NC_DMA_GETS [0 ] 0
-II  Invalidate [0 ] 0
-II  Writeback_Ack [0 ] 0
-II  Writeback_Nack [0 ] 0
-II  Flush_line [0 ] 0
-
-IT  Load [0 ] 0
-IT  Ifetch [0 ] 0
-IT  Store [0 ] 0
-IT  L2_Replacement [0 ] 0
-IT  L1_to_L2 [0 ] 0
-IT  Complete_L2_to_L1 [0 ] 0
-
-ST  Load [0 ] 0
-ST  Ifetch [0 ] 0
-ST  Store [0 ] 0
-ST  L2_Replacement [0 ] 0
-ST  L1_to_L2 [0 ] 0
-ST  Complete_L2_to_L1 [0 ] 0
-
-OT  Load [0 ] 0
-OT  Ifetch [0 ] 0
-OT  Store [0 ] 0
-OT  L2_Replacement [0 ] 0
-OT  L1_to_L2 [0 ] 0
-OT  Complete_L2_to_L1 [0 ] 0
-
-MT  Load [0 ] 0
-MT  Ifetch [0 ] 0
-MT  Store [2 ] 2
-MT  L2_Replacement [0 ] 0
-MT  L1_to_L2 [54 ] 54
-MT  Complete_L2_to_L1 [11 ] 11
-
-MMT  Load [0 ] 0
-MMT  Ifetch [0 ] 0
-MMT  Store [18 ] 18
-MMT  L2_Replacement [0 ] 0
-MMT  L1_to_L2 [103 ] 103
-MMT  Complete_L2_to_L1 [39 ] 39
-
-MI_F  Load [0 ] 0
-MI_F  Ifetch [0 ] 0
-MI_F  Store [0 ] 0
-MI_F  L1_to_L2 [0 ] 0
-MI_F  Writeback_Ack [5 ] 5
-MI_F  Flush_line [0 ] 0
-
-MM_F  Load [0 ] 0
-MM_F  Ifetch [0 ] 0
-MM_F  Store [0 ] 0
-MM_F  L1_to_L2 [0 ] 0
-MM_F  Other_GETX [0 ] 0
-MM_F  Other_GETS [0 ] 0
-MM_F  Merged_GETS [0 ] 0
-MM_F  Other_GETS_No_Mig [0 ] 0
-MM_F  NC_DMA_GETS [0 ] 0
-MM_F  Invalidate [0 ] 0
-MM_F  Ack [0 ] 0
-MM_F  All_acks [0 ] 0
-MM_F  All_acks_no_sharers [0 ] 0
-MM_F  Flush_line [0 ] 0
-MM_F  Block_Ack [1 ] 1
-
-IM_F  Load [0 ] 0
-IM_F  Ifetch [0 ] 0
-IM_F  Store [0 ] 0
-IM_F  L2_Replacement [0 ] 0
-IM_F  L1_to_L2 [0 ] 0
-IM_F  Other_GETX [0 ] 0
-IM_F  Other_GETS [0 ] 0
-IM_F  Other_GETS_No_Mig [0 ] 0
-IM_F  NC_DMA_GETS [0 ] 0
-IM_F  Invalidate [0 ] 0
-IM_F  Ack [0 ] 0
-IM_F  Data [0 ] 0
-IM_F  Exclusive_Data [4 ] 4
-IM_F  Flush_line [0 ] 0
-
-ISM_F  Load [0 ] 0
-ISM_F  Ifetch [0 ] 0
-ISM_F  Store [0 ] 0
-ISM_F  L2_Replacement [0 ] 0
-ISM_F  L1_to_L2 [0 ] 0
-ISM_F  Ack [0 ] 0
-ISM_F  All_acks_no_sharers [0 ] 0
-ISM_F  Flush_line [0 ] 0
-
-SM_F  Load [0 ] 0
-SM_F  Ifetch [0 ] 0
-SM_F  Store [0 ] 0
-SM_F  L2_Replacement [0 ] 0
-SM_F  L1_to_L2 [0 ] 0
-SM_F  Other_GETX [0 ] 0
-SM_F  Other_GETS [0 ] 0
-SM_F  Other_GETS_No_Mig [0 ] 0
-SM_F  NC_DMA_GETS [0 ] 0
-SM_F  Invalidate [0 ] 0
-SM_F  Ack [0 ] 0
-SM_F  Data [0 ] 0
-SM_F  Exclusive_Data [0 ] 0
-SM_F  Flush_line [0 ] 0
-
-OM_F  Load [0 ] 0
-OM_F  Ifetch [0 ] 0
-OM_F  Store [0 ] 0
-OM_F  L2_Replacement [0 ] 0
-OM_F  L1_to_L2 [0 ] 0
-OM_F  Other_GETX [0 ] 0
-OM_F  Other_GETS [0 ] 0
-OM_F  Merged_GETS [0 ] 0
-OM_F  Other_GETS_No_Mig [0 ] 0
-OM_F  NC_DMA_GETS [0 ] 0
-OM_F  Invalidate [0 ] 0
-OM_F  Ack [0 ] 0
-OM_F  All_acks [0 ] 0
-OM_F  All_acks_no_sharers [0 ] 0
-OM_F  Flush_line [0 ] 0
-
-MM_WF  Load [0 ] 0
-MM_WF  Ifetch [0 ] 0
-MM_WF  Store [0 ] 0
-MM_WF  L2_Replacement [0 ] 0
-MM_WF  L1_to_L2 [0 ] 0
-MM_WF  Ack [0 ] 0
-MM_WF  All_acks_no_sharers [4 ] 4
-MM_WF  Flush_line [0 ] 0
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 1617
-  memory_reads: 850
-  memory_writes: 767
-  memory_refreshes: 1196
-  memory_total_request_delays: 599
-  memory_delays_per_request: 0.370439
-  memory_delays_in_input_queue: 48
-  memory_delays_behind_head_of_bank_queue: 1
-  memory_delays_stalled_at_head_of_bank_queue: 550
-  memory_stalls_for_bank_busy: 172
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 40
-  memory_stalls_for_bus: 204
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 52
-  memory_stalls_for_read_read_turnaround: 82
-  accesses_per_bank: 60  50  58  80  69  77  71  48  48  38  42  44  39  57  47  44  42  45  53  54  55  41  48  56  29  45  43  51  47  51  42  43  
-
- --- Directory ---
- - Event Counts -
-GETX [761 ] 761
-GETS [87 ] 87
-PUT [913 ] 913
-Unblock [0 ] 0
-UnblockS [0 ] 0
-UnblockM [845 ] 845
-Writeback_Clean [0 ] 0
-Writeback_Dirty [0 ] 0
-Writeback_Exclusive_Clean [75 ] 75
-Writeback_Exclusive_Dirty [767 ] 767
-Pf_Replacement [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [850 ] 850
-Memory_Ack [767 ] 767
-Ack [0 ] 0
-Shared_Ack [0 ] 0
-Shared_Data [0 ] 0
-Data [0 ] 0
-Exclusive_Data [0 ] 0
-All_acks_and_shared_data [0 ] 0
-All_acks_and_owner_data [0 ] 0
-All_acks_and_data_no_sharers [0 ] 0
-All_Unblocks [0 ] 0
-GETF [5 ] 5
-PUTF [5 ] 5
-
- - Transitions -
-NX  GETX [0 ] 0
-NX  GETS [0 ] 0
-NX  PUT [0 ] 0
-NX  Pf_Replacement [0 ] 0
-NX  DMA_READ [0 ] 0
-NX  DMA_WRITE [0 ] 0
-NX  GETF [0 ] 0
-
-NO  GETX [0 ] 0
-NO  GETS [0 ] 0
-NO  PUT [838 ] 838
-NO  Pf_Replacement [0 ] 0
-NO  DMA_READ [0 ] 0
-NO  DMA_WRITE [0 ] 0
-NO  GETF [1 ] 1
-
-S  GETX [0 ] 0
-S  GETS [0 ] 0
-S  PUT [0 ] 0
-S  Pf_Replacement [0 ] 0
-S  DMA_READ [0 ] 0
-S  DMA_WRITE [0 ] 0
-S  GETF [0 ] 0
-
-O  GETX [0 ] 0
-O  GETS [0 ] 0
-O  PUT [0 ] 0
-O  Pf_Replacement [0 ] 0
-O  DMA_READ [0 ] 0
-O  DMA_WRITE [0 ] 0
-O  GETF [0 ] 0
-
-E  GETX [761 ] 761
-E  GETS [85 ] 85
-E  PUT [0 ] 0
-E  DMA_READ [0 ] 0
-E  DMA_WRITE [0 ] 0
-E  GETF [4 ] 4
-
-O_R  GETX [0 ] 0
-O_R  GETS [0 ] 0
-O_R  PUT [0 ] 0
-O_R  Pf_Replacement [0 ] 0
-O_R  DMA_READ [0 ] 0
-O_R  DMA_WRITE [0 ] 0
-O_R  Ack [0 ] 0
-O_R  All_acks_and_data_no_sharers [0 ] 0
-O_R  GETF [0 ] 0
-
-S_R  GETX [0 ] 0
-S_R  GETS [0 ] 0
-S_R  PUT [0 ] 0
-S_R  Pf_Replacement [0 ] 0
-S_R  DMA_READ [0 ] 0
-S_R  DMA_WRITE [0 ] 0
-S_R  Ack [0 ] 0
-S_R  Data [0 ] 0
-S_R  All_acks_and_data_no_sharers [0 ] 0
-S_R  GETF [0 ] 0
-
-NO_R  GETX [0 ] 0
-NO_R  GETS [0 ] 0
-NO_R  PUT [0 ] 0
-NO_R  Pf_Replacement [0 ] 0
-NO_R  DMA_READ [0 ] 0
-NO_R  DMA_WRITE [0 ] 0
-NO_R  Ack [0 ] 0
-NO_R  Data [0 ] 0
-NO_R  Exclusive_Data [0 ] 0
-NO_R  All_acks_and_data_no_sharers [0 ] 0
-NO_R  GETF [0 ] 0
-
-NO_B  GETX [0 ] 0
-NO_B  GETS [0 ] 0
-NO_B  PUT [75 ] 75
-NO_B  UnblockS [0 ] 0
-NO_B  UnblockM [845 ] 845
-NO_B  Pf_Replacement [0 ] 0
-NO_B  DMA_READ [0 ] 0
-NO_B  DMA_WRITE [0 ] 0
-NO_B  GETF [0 ] 0
-
-NO_B_X  GETX [0 ] 0
-NO_B_X  GETS [0 ] 0
-NO_B_X  PUT [0 ] 0
-NO_B_X  UnblockS [0 ] 0
-NO_B_X  UnblockM [0 ] 0
-NO_B_X  Pf_Replacement [0 ] 0
-NO_B_X  DMA_READ [0 ] 0
-NO_B_X  DMA_WRITE [0 ] 0
-NO_B_X  GETF [0 ] 0
-
-NO_B_S  GETX [0 ] 0
-NO_B_S  GETS [0 ] 0
-NO_B_S  PUT [0 ] 0
-NO_B_S  UnblockS [0 ] 0
-NO_B_S  UnblockM [0 ] 0
-NO_B_S  Pf_Replacement [0 ] 0
-NO_B_S  DMA_READ [0 ] 0
-NO_B_S  DMA_WRITE [0 ] 0
-NO_B_S  GETF [0 ] 0
-
-NO_B_S_W  GETX [0 ] 0
-NO_B_S_W  GETS [0 ] 0
-NO_B_S_W  PUT [0 ] 0
-NO_B_S_W  UnblockS [0 ] 0
-NO_B_S_W  Pf_Replacement [0 ] 0
-NO_B_S_W  DMA_READ [0 ] 0
-NO_B_S_W  DMA_WRITE [0 ] 0
-NO_B_S_W  All_Unblocks [0 ] 0
-NO_B_S_W  GETF [0 ] 0
-
-O_B  GETX [0 ] 0
-O_B  GETS [0 ] 0
-O_B  PUT [0 ] 0
-O_B  UnblockS [0 ] 0
-O_B  UnblockM [0 ] 0
-O_B  Pf_Replacement [0 ] 0
-O_B  DMA_READ [0 ] 0
-O_B  DMA_WRITE [0 ] 0
-O_B  GETF [0 ] 0
-
-NO_B_W  GETX [0 ] 0
-NO_B_W  GETS [0 ] 0
-NO_B_W  PUT [0 ] 0
-NO_B_W  UnblockS [0 ] 0
-NO_B_W  UnblockM [0 ] 0
-NO_B_W  Pf_Replacement [0 ] 0
-NO_B_W  DMA_READ [0 ] 0
-NO_B_W  DMA_WRITE [0 ] 0
-NO_B_W  Memory_Data [846 ] 846
-NO_B_W  GETF [0 ] 0
-
-O_B_W  GETX [0 ] 0
-O_B_W  GETS [0 ] 0
-O_B_W  PUT [0 ] 0
-O_B_W  UnblockS [0 ] 0
-O_B_W  Pf_Replacement [0 ] 0
-O_B_W  DMA_READ [0 ] 0
-O_B_W  DMA_WRITE [0 ] 0
-O_B_W  Memory_Data [0 ] 0
-O_B_W  GETF [0 ] 0
-
-NO_W  GETX [0 ] 0
-NO_W  GETS [0 ] 0
-NO_W  PUT [0 ] 0
-NO_W  Pf_Replacement [0 ] 0
-NO_W  DMA_READ [0 ] 0
-NO_W  DMA_WRITE [0 ] 0
-NO_W  Memory_Data [0 ] 0
-NO_W  GETF [0 ] 0
-
-O_W  GETX [0 ] 0
-O_W  GETS [0 ] 0
-O_W  PUT [0 ] 0
-O_W  Pf_Replacement [0 ] 0
-O_W  DMA_READ [0 ] 0
-O_W  DMA_WRITE [0 ] 0
-O_W  Memory_Data [0 ] 0
-O_W  GETF [0 ] 0
-
-NO_DW_B_W  GETX [0 ] 0
-NO_DW_B_W  GETS [0 ] 0
-NO_DW_B_W  PUT [0 ] 0
-NO_DW_B_W  Pf_Replacement [0 ] 0
-NO_DW_B_W  DMA_READ [0 ] 0
-NO_DW_B_W  DMA_WRITE [0 ] 0
-NO_DW_B_W  Ack [0 ] 0
-NO_DW_B_W  Data [0 ] 0
-NO_DW_B_W  Exclusive_Data [0 ] 0
-NO_DW_B_W  All_acks_and_data_no_sharers [0 ] 0
-NO_DW_B_W  GETF [0 ] 0
-
-NO_DR_B_W  GETX [0 ] 0
-NO_DR_B_W  GETS [0 ] 0
-NO_DR_B_W  PUT [0 ] 0
-NO_DR_B_W  Pf_Replacement [0 ] 0
-NO_DR_B_W  DMA_READ [0 ] 0
-NO_DR_B_W  DMA_WRITE [0 ] 0
-NO_DR_B_W  Memory_Data [0 ] 0
-NO_DR_B_W  Ack [0 ] 0
-NO_DR_B_W  Shared_Ack [0 ] 0
-NO_DR_B_W  Shared_Data [0 ] 0
-NO_DR_B_W  Data [0 ] 0
-NO_DR_B_W  Exclusive_Data [0 ] 0
-NO_DR_B_W  GETF [0 ] 0
-
-NO_DR_B_D  GETX [0 ] 0
-NO_DR_B_D  GETS [0 ] 0
-NO_DR_B_D  PUT [0 ] 0
-NO_DR_B_D  Pf_Replacement [0 ] 0
-NO_DR_B_D  DMA_READ [0 ] 0
-NO_DR_B_D  DMA_WRITE [0 ] 0
-NO_DR_B_D  Ack [0 ] 0
-NO_DR_B_D  Shared_Ack [0 ] 0
-NO_DR_B_D  Shared_Data [0 ] 0
-NO_DR_B_D  Data [0 ] 0
-NO_DR_B_D  Exclusive_Data [0 ] 0
-NO_DR_B_D  All_acks_and_shared_data [0 ] 0
-NO_DR_B_D  All_acks_and_owner_data [0 ] 0
-NO_DR_B_D  All_acks_and_data_no_sharers [0 ] 0
-NO_DR_B_D  GETF [0 ] 0
-
-NO_DR_B  GETX [0 ] 0
-NO_DR_B  GETS [0 ] 0
-NO_DR_B  PUT [0 ] 0
-NO_DR_B  Pf_Replacement [0 ] 0
-NO_DR_B  DMA_READ [0 ] 0
-NO_DR_B  DMA_WRITE [0 ] 0
-NO_DR_B  Ack [0 ] 0
-NO_DR_B  Shared_Ack [0 ] 0
-NO_DR_B  Shared_Data [0 ] 0
-NO_DR_B  Data [0 ] 0
-NO_DR_B  Exclusive_Data [0 ] 0
-NO_DR_B  All_acks_and_shared_data [0 ] 0
-NO_DR_B  All_acks_and_owner_data [0 ] 0
-NO_DR_B  All_acks_and_data_no_sharers [0 ] 0
-NO_DR_B  GETF [0 ] 0
-
-NO_DW_W  GETX [0 ] 0
-NO_DW_W  GETS [0 ] 0
-NO_DW_W  PUT [0 ] 0
-NO_DW_W  Pf_Replacement [0 ] 0
-NO_DW_W  DMA_READ [0 ] 0
-NO_DW_W  DMA_WRITE [0 ] 0
-NO_DW_W  Memory_Ack [0 ] 0
-NO_DW_W  GETF [0 ] 0
-
-O_DR_B_W  GETX [0 ] 0
-O_DR_B_W  GETS [0 ] 0
-O_DR_B_W  PUT [0 ] 0
-O_DR_B_W  Pf_Replacement [0 ] 0
-O_DR_B_W  DMA_READ [0 ] 0
-O_DR_B_W  DMA_WRITE [0 ] 0
-O_DR_B_W  Memory_Data [0 ] 0
-O_DR_B_W  Ack [0 ] 0
-O_DR_B_W  Shared_Ack [0 ] 0
-O_DR_B_W  GETF [0 ] 0
-
-O_DR_B  GETX [0 ] 0
-O_DR_B  GETS [0 ] 0
-O_DR_B  PUT [0 ] 0
-O_DR_B  Pf_Replacement [0 ] 0
-O_DR_B  DMA_READ [0 ] 0
-O_DR_B  DMA_WRITE [0 ] 0
-O_DR_B  Ack [0 ] 0
-O_DR_B  Shared_Ack [0 ] 0
-O_DR_B  All_acks_and_owner_data [0 ] 0
-O_DR_B  All_acks_and_data_no_sharers [0 ] 0
-O_DR_B  GETF [0 ] 0
-
-WB  GETX [0 ] 0
-WB  GETS [1 ] 1
-WB  PUT [0 ] 0
-WB  Unblock [0 ] 0
-WB  Writeback_Clean [0 ] 0
-WB  Writeback_Dirty [0 ] 0
-WB  Writeback_Exclusive_Clean [75 ] 75
-WB  Writeback_Exclusive_Dirty [767 ] 767
-WB  Pf_Replacement [0 ] 0
-WB  DMA_READ [0 ] 0
-WB  DMA_WRITE [0 ] 0
-WB  GETF [0 ] 0
-
-WB_O_W  GETX [0 ] 0
-WB_O_W  GETS [0 ] 0
-WB_O_W  PUT [0 ] 0
-WB_O_W  Pf_Replacement [0 ] 0
-WB_O_W  DMA_READ [0 ] 0
-WB_O_W  DMA_WRITE [0 ] 0
-WB_O_W  Memory_Ack [0 ] 0
-WB_O_W  GETF [0 ] 0
-
-WB_E_W  GETX [0 ] 0
-WB_E_W  GETS [1 ] 1
-WB_E_W  PUT [0 ] 0
-WB_E_W  Pf_Replacement [0 ] 0
-WB_E_W  DMA_READ [0 ] 0
-WB_E_W  DMA_WRITE [0 ] 0
-WB_E_W  Memory_Ack [767 ] 767
-WB_E_W  GETF [0 ] 0
-
-NO_F  GETX [0 ] 0
-NO_F  GETS [0 ] 0
-NO_F  PUT [0 ] 0
-NO_F  UnblockM [0 ] 0
-NO_F  Pf_Replacement [0 ] 0
-NO_F  GETF [0 ] 0
-NO_F  PUTF [5 ] 5
-
-NO_F_W  GETX [0 ] 0
-NO_F_W  GETS [0 ] 0
-NO_F_W  PUT [0 ] 0
-NO_F_W  Pf_Replacement [0 ] 0
-NO_F_W  DMA_READ [0 ] 0
-NO_F_W  DMA_WRITE [0 ] 0
-NO_F_W  Memory_Data [4 ] 4
-NO_F_W  GETF [0 ] 0
-
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index ea7e7e040..446bded29 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000172                       # Nu
 sim_ticks                                      172201                       # Number of ticks simulated
 final_tick                                     172201                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1283391                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 149864                       # Number of bytes of host memory used
-host_seconds                                     0.13                       # Real time elapsed on the host
+host_tick_rate                                1943490                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 142952                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           70                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          848                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          918                       # Number of cache demand accesses
@@ -16,8 +16,106 @@ system.ruby.l1_cntrl0.L1Icache.demand_accesses           50
 system.ruby.l1_cntrl0.L2cache.demand_hits           49                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L2cache.demand_misses          848                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L2cache.demand_accesses          897                       # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq          1617                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          850                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          767                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         1196                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles          550                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ           48                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ            1                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls          599                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     0.370439                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          172                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          204                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy           52                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           82                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait           40                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          60      3.71%      3.71% |          50      3.09%      6.80% |          58      3.59%     10.39% |          80      4.95%     15.34% |          69      4.27%     19.60% |          77      4.76%     24.37% |          71      4.39%     28.76% |          48      2.97%     31.73% |          48      2.97%     34.69% |          38      2.35%     37.04% |          42      2.60%     39.64% |          44      2.72%     42.36% |          39      2.41%     44.77% |          57      3.53%     48.30% |          47      2.91%     51.21% |          44      2.72%     53.93% |          42      2.60%     56.52% |          45      2.78%     59.31% |          53      3.28%     62.59% |          54      3.34%     65.92% |          55      3.40%     69.33% |          41      2.54%     71.86% |          48      2.97%     74.83% |          56      3.46%     78.29% |          29      1.79%     80.09% |          45      2.78%     82.87% |          43      2.66%     85.53% |          51      3.15%     88.68% |          47      2.91%     91.59% |          51      3.15%     94.74% |          42      2.60%     97.34% |          43      2.66%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1617                       # Number of accesses per bank
+
 system.ruby.dir_cntrl0.probeFilter.demand_hits            0                       # Number of cache demand hits
 system.ruby.dir_cntrl0.probeFilter.demand_misses            0                       # Number of cache demand misses
 system.ruby.dir_cntrl0.probeFilter.demand_accesses            0                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.Load                         52      0.00%      0.00%
+system.ruby.l1_cntrl0.Ifetch                       53      0.00%      0.00%
+system.ruby.l1_cntrl0.Store                       888      0.00%      0.00%
+system.ruby.l1_cntrl0.L2_Replacement              840      0.00%      0.00%
+system.ruby.l1_cntrl0.L1_to_L2                  16587      0.00%      0.00%
+system.ruby.l1_cntrl0.Trigger_L2_to_L1D            41      0.00%      0.00%
+system.ruby.l1_cntrl0.Trigger_L2_to_L1I             9      0.00%      0.00%
+system.ruby.l1_cntrl0.Complete_L2_to_L1            50      0.00%      0.00%
+system.ruby.l1_cntrl0.Exclusive_Data              850      0.00%      0.00%
+system.ruby.l1_cntrl0.Writeback_Ack               843      0.00%      0.00%
+system.ruby.l1_cntrl0.All_acks_no_sharers          850      0.00%      0.00%
+system.ruby.l1_cntrl0.Flush_line                    5      0.00%      0.00%
+system.ruby.l1_cntrl0.Block_Ack                     1      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Load                       46      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Ifetch                     40      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Store                     762      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Flush_line                  4      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Ifetch                      1      0.00%      0.00%
+system.ruby.l1_cntrl0.M.L2_Replacement             71      0.00%      0.00%
+system.ruby.l1_cntrl0.M.L1_to_L2                   83      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Trigger_L2_to_L1D           11      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Load                       5      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Store                     62      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.L2_Replacement           769      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.L1_to_L2                 809      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1D           30      0.00%      0.00%
+system.ruby.l1_cntrl0.MM.Trigger_L2_to_L1I            9      0.00%      0.00%
+system.ruby.l1_cntrl0.MR.Store                     11      0.00%      0.00%
+system.ruby.l1_cntrl0.MR.L1_to_L2                  90      0.00%      0.00%
+system.ruby.l1_cntrl0.MMR.Ifetch                    9      0.00%      0.00%
+system.ruby.l1_cntrl0.MMR.Store                    29      0.00%      0.00%
+system.ruby.l1_cntrl0.MMR.L1_to_L2                 25      0.00%      0.00%
+system.ruby.l1_cntrl0.MMR.Flush_line                1      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.L1_to_L2                9996      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.Exclusive_Data           761      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.L1_to_L2                306      0.00%      0.00%
+system.ruby.l1_cntrl0.M_W.All_acks_no_sharers           85      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.Store                    3      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.L1_to_L2              4592      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_W.All_acks_no_sharers          761      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.L1_to_L2                 529      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.Exclusive_Data            85      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Load                       1      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Ifetch                     3      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Store                      1      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack            838      0.00%      0.00%
+system.ruby.l1_cntrl0.MT.Store                      2      0.00%      0.00%
+system.ruby.l1_cntrl0.MT.L1_to_L2                  54      0.00%      0.00%
+system.ruby.l1_cntrl0.MT.Complete_L2_to_L1           11      0.00%      0.00%
+system.ruby.l1_cntrl0.MMT.Store                    18      0.00%      0.00%
+system.ruby.l1_cntrl0.MMT.L1_to_L2                103      0.00%      0.00%
+system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1           39      0.00%      0.00%
+system.ruby.l1_cntrl0.MI_F.Writeback_Ack            5      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_F.Block_Ack                1      0.00%      0.00%
+system.ruby.l1_cntrl0.IM_F.Exclusive_Data            4      0.00%      0.00%
+system.ruby.l1_cntrl0.MM_WF.All_acks_no_sharers            4      0.00%      0.00%
+system.ruby.dir_cntrl0.GETX                       761      0.00%      0.00%
+system.ruby.dir_cntrl0.GETS                        87      0.00%      0.00%
+system.ruby.dir_cntrl0.PUT                        913      0.00%      0.00%
+system.ruby.dir_cntrl0.UnblockM                   845      0.00%      0.00%
+system.ruby.dir_cntrl0.Writeback_Exclusive_Clean           75      0.00%      0.00%
+system.ruby.dir_cntrl0.Writeback_Exclusive_Dirty          767      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Data                850      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Ack                 767      0.00%      0.00%
+system.ruby.dir_cntrl0.GETF                         5      0.00%      0.00%
+system.ruby.dir_cntrl0.PUTF                         5      0.00%      0.00%
+system.ruby.dir_cntrl0.NO.PUT                     838      0.00%      0.00%
+system.ruby.dir_cntrl0.NO.GETF                      1      0.00%      0.00%
+system.ruby.dir_cntrl0.E.GETX                     761      0.00%      0.00%
+system.ruby.dir_cntrl0.E.GETS                      85      0.00%      0.00%
+system.ruby.dir_cntrl0.E.GETF                       4      0.00%      0.00%
+system.ruby.dir_cntrl0.NO_B.PUT                    75      0.00%      0.00%
+system.ruby.dir_cntrl0.NO_B.UnblockM              845      0.00%      0.00%
+system.ruby.dir_cntrl0.NO_B_W.Memory_Data          846      0.00%      0.00%
+system.ruby.dir_cntrl0.WB.GETS                      1      0.00%      0.00%
+system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Clean           75      0.00%      0.00%
+system.ruby.dir_cntrl0.WB.Writeback_Exclusive_Dirty          767      0.00%      0.00%
+system.ruby.dir_cntrl0.WB_E_W.GETS                  1      0.00%      0.00%
+system.ruby.dir_cntrl0.WB_E_W.Memory_Ack          767      0.00%      0.00%
+system.ruby.dir_cntrl0.NO_F.PUTF                    5      0.00%      0.00%
+system.ruby.dir_cntrl0.NO_F_W.Memory_Data            4      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------