stats: updates due to changes to ruby

Ruby's controller statistics have been mostly moved to stats.txt now.
Plus stats.txt for solaris/t1000-simple-atomic and arm/20.parser are
also being updated.

2 files changed, 53 insertions, 142 deletions

diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index f73b12883..29f0cd3f5 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Feb/02/2013 08:06:19
+Real time: Jun/08/2013 13:44:09
 
 Profiler Stats
 --------------
@@ -7,20 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.39
-Virtual_time_in_minutes: 0.0065
-Virtual_time_in_hours:   0.000108333
-Virtual_time_in_days:    4.51389e-06
+Virtual_time_in_seconds: 0.45
+Virtual_time_in_minutes: 0.0075
+Virtual_time_in_hours:   0.000125
+Virtual_time_in_days:    5.20833e-06
 
 Ruby_current_time: 221941
 Ruby_start_time: 0
 Ruby_cycles: 221941
 
-mbytes_resident: 49.5742
-mbytes_total: 265.59
-resident_ratio: 0.186701
-
-ruby_cycles_executed: [ 221942 ]
+mbytes_resident: 50.1211
+mbytes_total: 138.504
+resident_ratio: 0.361931
 
 Busy Controller Counts:
 L1Cache-0:0  
@@ -63,7 +61,6 @@ Request vs. RubySystem State Profile
 --------------------------------
 
 
-filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
 
 Message Delayed Cycles
 ----------------------
@@ -84,11 +81,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 9328
+page_reclaims: 9501
 page_faults: 0
 swaps: 0
 block_inputs: 0
-block_outputs: 80
+block_outputs: 88
 
 Network Stats
 -------------
@@ -132,129 +129,3 @@ links_utilized_percent_switch_2: 2.06125
   outgoing_messages_switch_2_link_1_Control: 916 7328 [ 0 0 916 0 0 0 0 0 0 0 ] base_latency: 1
   outgoing_messages_switch_2_link_1_Data: 914 65808 [ 0 0 914 0 0 0 0 0 0 0 ] base_latency: 1
 
- --- L1Cache ---
- - Event Counts -
-Load [42 ] 42
-Ifetch [58 ] 58
-Store [855 ] 855
-Data [916 ] 916
-Fwd_GETX [0 ] 0
-Inv [0 ] 0
-Replacement [914 ] 914
-Writeback_Ack [912 ] 912
-Writeback_Nack [0 ] 0
-
- - Transitions -
-I  Load [42 ] 42
-I  Ifetch [56 ] 56
-I  Store [819 ] 819
-I  Inv [0 ] 0
-I  Replacement [0 ] 0
-
-II  Writeback_Nack [0 ] 0
-
-M  Load [0 ] 0
-M  Ifetch [2 ] 2
-M  Store [36 ] 36
-M  Fwd_GETX [0 ] 0
-M  Inv [0 ] 0
-M  Replacement [914 ] 914
-
-MI  Fwd_GETX [0 ] 0
-MI  Inv [0 ] 0
-MI  Writeback_Ack [912 ] 912
-MI  Writeback_Nack [0 ] 0
-
-MII  Fwd_GETX [0 ] 0
-
-IS  Data [98 ] 98
-
-IM  Data [818 ] 818
-
-Memory controller: system.ruby.dir_cntrl0.memBuffer:
-  memory_total_requests: 1830
-  memory_reads: 916
-  memory_writes: 914
-  memory_refreshes: 1542
-  memory_total_request_delays: 1930
-  memory_delays_per_request: 1.05464
-  memory_delays_in_input_queue: 182
-  memory_delays_behind_head_of_bank_queue: 3
-  memory_delays_stalled_at_head_of_bank_queue: 1745
-  memory_stalls_for_bank_busy: 343
-  memory_stalls_for_random_busy: 0
-  memory_stalls_for_anti_starvation: 0
-  memory_stalls_for_arbitration: 167
-  memory_stalls_for_bus: 617
-  memory_stalls_for_tfaw: 0
-  memory_stalls_for_read_write_turnaround: 556
-  memory_stalls_for_read_read_turnaround: 62
-  accesses_per_bank: 64  60  44  96  107  64  62  38  55  54  54  36  48  34  66  48  56  54  60  70  56  62  44  62  48  58  64  72  46  46  36  66  
-
- --- Directory ---
- - Event Counts -
-GETX [916 ] 916
-GETS [0 ] 0
-PUTX [914 ] 914
-PUTX_NotOwner [0 ] 0
-DMA_READ [0 ] 0
-DMA_WRITE [0 ] 0
-Memory_Data [916 ] 916
-Memory_Ack [914 ] 914
-
- - Transitions -
-I  GETX [916 ] 916
-I  PUTX_NotOwner [0 ] 0
-I  DMA_READ [0 ] 0
-I  DMA_WRITE [0 ] 0
-
-M  GETX [0 ] 0
-M  PUTX [914 ] 914
-M  PUTX_NotOwner [0 ] 0
-M  DMA_READ [0 ] 0
-M  DMA_WRITE [0 ] 0
-
-M_DRD  GETX [0 ] 0
-M_DRD  PUTX [0 ] 0
-
-M_DWR  GETX [0 ] 0
-M_DWR  PUTX [0 ] 0
-
-M_DWRI  GETX [0 ] 0
-M_DWRI  Memory_Ack [0 ] 0
-
-M_DRDI  GETX [0 ] 0
-M_DRDI  Memory_Ack [0 ] 0
-
-IM  GETX [0 ] 0
-IM  GETS [0 ] 0
-IM  PUTX [0 ] 0
-IM  PUTX_NotOwner [0 ] 0
-IM  DMA_READ [0 ] 0
-IM  DMA_WRITE [0 ] 0
-IM  Memory_Data [916 ] 916
-
-MI  GETX [0 ] 0
-MI  GETS [0 ] 0
-MI  PUTX [0 ] 0
-MI  PUTX_NotOwner [0 ] 0
-MI  DMA_READ [0 ] 0
-MI  DMA_WRITE [0 ] 0
-MI  Memory_Ack [914 ] 914
-
-ID  GETX [0 ] 0
-ID  GETS [0 ] 0
-ID  PUTX [0 ] 0
-ID  PUTX_NotOwner [0 ] 0
-ID  DMA_READ [0 ] 0
-ID  DMA_WRITE [0 ] 0
-ID  Memory_Data [0 ] 0
-
-ID_W  GETX [0 ] 0
-ID_W  GETS [0 ] 0
-ID_W  PUTX [0 ] 0
-ID_W  PUTX_NotOwner [0 ] 0
-ID_W  DMA_READ [0 ] 0
-ID_W  DMA_WRITE [0 ] 0
-ID_W  Memory_Ack [0 ] 0
-
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index 967007849..e77006cfe 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,11 +4,51 @@ sim_seconds                                  0.000222                       # Nu
 sim_ticks                                      221941                       # Number of ticks simulated
 final_tick                                     221941                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2117650                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 149428                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                3023855                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 141832                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.cacheMemory.demand_hits           38                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          917                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses          955                       # Number of cache demand accesses
+system.ruby.dir_cntrl0.memBuffer.memReq          1830                       # Total number of memory requests
+system.ruby.dir_cntrl0.memBuffer.memRead          916                       # Number of memory reads
+system.ruby.dir_cntrl0.memBuffer.memWrite          914                       # Number of memory writes
+system.ruby.dir_cntrl0.memBuffer.memRefresh         1542                       # Number of memory refreshes
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles         1745                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memInputQ          182                       # Delay in the input queue
+system.ruby.dir_cntrl0.memBuffer.memBankQ            3                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls         1930                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     1.054645                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy          343                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy          617                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy          556                       # memory stalls due to read write turnaround
+system.ruby.dir_cntrl0.memBuffer.memDataBusBusy           62                       # memory stalls due to read read turnaround
+system.ruby.dir_cntrl0.memBuffer.memArbWait          167                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memBankCount |          64      3.50%      3.50% |          60      3.28%      6.78% |          44      2.40%      9.18% |          96      5.25%     14.43% |         107      5.85%     20.27% |          64      3.50%     23.77% |          62      3.39%     27.16% |          38      2.08%     29.23% |          55      3.01%     32.24% |          54      2.95%     35.19% |          54      2.95%     38.14% |          36      1.97%     40.11% |          48      2.62%     42.73% |          34      1.86%     44.59% |          66      3.61%     48.20% |          48      2.62%     50.82% |          56      3.06%     53.88% |          54      2.95%     56.83% |          60      3.28%     60.11% |          70      3.83%     63.93% |          56      3.06%     66.99% |          62      3.39%     70.38% |          44      2.40%     72.79% |          62      3.39%     76.17% |          48      2.62%     78.80% |          58      3.17%     81.97% |          64      3.50%     85.46% |          72      3.93%     89.40% |          46      2.51%     91.91% |          46      2.51%     94.43% |          36      1.97%     96.39% |          66      3.61%    100.00% # Number of accesses per bank
+system.ruby.dir_cntrl0.memBuffer.memBankCount::total         1830                       # Number of accesses per bank
+
+system.ruby.l1_cntrl0.Load                         42      0.00%      0.00%
+system.ruby.l1_cntrl0.Ifetch                       58      0.00%      0.00%
+system.ruby.l1_cntrl0.Store                       855      0.00%      0.00%
+system.ruby.l1_cntrl0.Data                        916      0.00%      0.00%
+system.ruby.l1_cntrl0.Replacement                 914      0.00%      0.00%
+system.ruby.l1_cntrl0.Writeback_Ack               912      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Load                       42      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Ifetch                     56      0.00%      0.00%
+system.ruby.l1_cntrl0.I.Store                     819      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Ifetch                      2      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Store                      36      0.00%      0.00%
+system.ruby.l1_cntrl0.M.Replacement               914      0.00%      0.00%
+system.ruby.l1_cntrl0.MI.Writeback_Ack            912      0.00%      0.00%
+system.ruby.l1_cntrl0.IS.Data                      98      0.00%      0.00%
+system.ruby.l1_cntrl0.IM.Data                     818      0.00%      0.00%
+system.ruby.dir_cntrl0.GETX                       916      0.00%      0.00%
+system.ruby.dir_cntrl0.PUTX                       914      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Data                916      0.00%      0.00%
+system.ruby.dir_cntrl0.Memory_Ack                 914      0.00%      0.00%
+system.ruby.dir_cntrl0.I.GETX                     916      0.00%      0.00%
+system.ruby.dir_cntrl0.M.PUTX                     914      0.00%      0.00%
+system.ruby.dir_cntrl0.IM.Memory_Data             916      0.00%      0.00%
+system.ruby.dir_cntrl0.MI.Memory_Ack              914      0.00%      0.00%
 
 ---------- End Simulation Statistics   ----------