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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
| commit | 64806c4c13040832dd1e24b8fb0c347cd794398e (patch) | |
| tree | 8fd8715bae92bf048efbd48d62616105638a5b24 /tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout | |
| parent | f800f268dbf638d21987c9bb8a235263ba715a93 (diff) | |
| download | gem5-64806c4c13040832dd1e24b8fb0c347cd794398e.tar.xz | |
tests: Reflect name change in DRAM tests
This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.
--HG--
rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout')
| -rwxr-xr-x | tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout new file mode 100755 index 000000000..cffe93183 --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 22 2014 16:54:17 +gem5 started Jan 22 2014 17:29:00 +gem5 executing on u200540-lin +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 100000000000 because simulate() limit reached |