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author | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-09-04 13:22:57 -0400 |
commit | 0495b7e9e795fafbaeac55b6d84db51a5cf975a8 (patch) | |
tree | f8fb6a614b00c48451e69a497e8d5ca1e3a0bac8 /tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout | |
parent | 19a5b68db7d73542833d94ec8b23cad6daf0a787 (diff) | |
download | gem5-0495b7e9e795fafbaeac55b6d84db51a5cf975a8.tar.xz |
tests: Move ISA-independent tests to the NULL ISA
This patch simply takes a first step to use the NULL ISA build for
tests that do not make use of a CPU. Most of the Ruby tests could go
the same way, but to avoid duplicating a lot of compilation targets
that will have to wait until Ruby is built as a library and linked in
independently.
--HG--
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini => tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr => tests/quick/se/50.memtest/ref/null/none/memtest/simerr
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout => tests/quick/se/50.memtest/ref/null/none/memtest/simout
rename : tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt => tests/quick/se/50.memtest/ref/null/none/memtest/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simerr
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
rename : tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout')
-rwxr-xr-x | tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout new file mode 100755 index 000000000..d1faa751a --- /dev/null +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Aug 6 2012 15:52:45 +gem5 started Aug 6 2012 15:56:03 +gem5 executing on 61f1f4j +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 300940000 because Done |