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| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-11-16 05:08:57 -0600 |
| commit | de489e1997ee6c37aaf6e876e32622f6c648fe95 (patch) | |
| tree | 40d4093453491b007167c971ebbb18c8ae0b77fa /tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem | |
| parent | 08cec03f8ec3bc427700343a7bd7d216433f93fc (diff) | |
| download | gem5-de489e1997ee6c37aaf6e876e32622f6c648fe95.tar.xz | |
stats: updates due to recent chagnesets
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem')
3 files changed, 10 insertions, 7 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini index 0c06c4a1a..0936865ed 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini @@ -24,6 +24,7 @@ mem_mode=timing mem_ranges= memories=system.physmem mmap_using_noreserve=false +multi_thread=false num_work_ids=16 readfile= symbolfile= diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout index 01f1d48fb..bbcc7960c 100755 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout @@ -1,10 +1,12 @@ +Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout +Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 17 2015 08:02:53 -gem5 started Jun 17 2015 09:01:31 -gem5 executing on e104799-lin -command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /work/gem5/outgoing/gem5_2/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem +gem5 compiled Nov 15 2015 14:58:33 +gem5 started Nov 15 2015 14:58:46 +gem5 executing on ribera.cs.wisc.edu, pid 5048 +command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re /scratch/nilay/GEM5/gem5/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt index a95826599..57e0820a3 100644 --- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt +++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 16291006908 # Simulator tick rate (ticks/s) -host_mem_usage 266948 # Number of bytes of host memory used -host_seconds 6.14 # Real time elapsed on the host +host_tick_rate 12448574230 # Simulator tick rate (ticks/s) +host_mem_usage 263544 # Number of bytes of host memory used +host_seconds 8.03 # Real time elapsed on the host system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory |