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authorNilay Vaish <nilay@cs.wisc.edu>2015-03-09 09:39:09 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-03-09 09:39:09 -0500
commit99fb8f81407efa54008ddf443718e492f583b142 (patch)
tree48e79a13dc012864045058f6ca3aadc3b9a767a8 /tests/quick/se/70.tgen/ref/null
parent0c8e025c3bd208e516f1c4247fdf3af7aebb2300 (diff)
downloadgem5-99fb8f81407efa54008ddf443718e492f583b142.tar.xz
stats: changes to due to recent set of patches
Diffstat (limited to 'tests/quick/se/70.tgen/ref/null')
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini9
-rw-r--r--tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini16
2 files changed, 22 insertions, 3 deletions
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index b1d661d27..82326fb62 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -70,7 +71,9 @@ transition_latency=100000000
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
width=16
master=system.physmem.port
@@ -95,6 +98,7 @@ latency_bins=20
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
+stack_dist_calc=Null
system=system
trace_compress=true
trace_enable=false
@@ -131,7 +135,7 @@ IDD62=0.000000
VDD=1.500000
VDD2=0.000000
activation_limit=4
-addr_mapping=RoRaBaChCo
+addr_mapping=RoRaBaCoCh
bank_groups_per_rank=0
banks_per_rank=8
burst_length=8
@@ -140,6 +144,7 @@ clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
+device_size=536870912
devices_per_rank=8
dll=true
eventq_index=0
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index c210da503..91ff0eb51 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -23,6 +23,7 @@ load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
+mmap_using_noreserve=false
num_work_ids=16
readfile=
symbolfile=
@@ -70,7 +71,9 @@ transition_latency=100000000
type=NoncoherentXBar
clk_domain=system.clk_domain
eventq_index=0
-header_cycles=1
+forward_latency=1
+frontend_latency=2
+response_latency=2
use_default_range=false
width=16
master=system.physmem.port
@@ -78,6 +81,7 @@ slave=system.monitor.master system.system_port
[system.monitor]
type=CommMonitor
+children=stack_dist_calc
bandwidth_bins=20
burst_length_bins=20
clk_domain=system.clk_domain
@@ -95,6 +99,7 @@ latency_bins=20
outstanding_bins=20
read_addr_mask=18446744073709551615
sample_period=1000000000
+stack_dist_calc=system.monitor.stack_dist_calc
system=system
trace_compress=true
trace_enable=true
@@ -104,6 +109,15 @@ write_addr_mask=18446744073709551615
master=system.membus.slave[0]
slave=system.cpu.port
+[system.monitor.stack_dist_calc]
+type=StackDistCalc
+disable_linear_hists=false
+disable_log_hists=false
+eventq_index=0
+linear_hist_bins=16
+log_hist_bins=32
+verify=true
+
[system.physmem]
type=SimpleMemory
bandwidth=73.000000