stats: updates due to recent ruby and x86 changes

Also updates many out of date config files.

2 files changed, 48 insertions, 12 deletions

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
index b3c13e1c2..a7dfb0cb5 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
@@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu membus monitor physmem
+children=clk_domain cpu dvfs_handler membus monitor physmem
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -37,7 +39,9 @@ system_port=system.membus.slave[1]
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
@@ -48,12 +52,20 @@ voltage=1.000000
 [system.cpu]
 type=TrafficGen
 clk_domain=system.clk_domain
-config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
+config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
 elastic_req=false
 eventq_index=0
 system=system
 port=system.monitor.slave
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
@@ -83,6 +95,9 @@ latency_bins=20
 outstanding_bins=20
 read_addr_mask=18446744073709551615
 sample_period=1000000000
+system=system
+trace_compress=true
+trace_enable=false
 trace_file=
 transaction_bins=20
 write_addr_mask=18446744073709551615
@@ -90,9 +105,9 @@ master=system.membus.slave[0]
 slave=system.cpu.port
 
 [system.physmem]
-type=SimpleDRAM
+type=DRAMCtrl
 activation_limit=4
-addr_mapping=RaBaChCo
+addr_mapping=RoRaBaChCo
 banks_per_rank=8
 burst_length=8
 channels=1
@@ -103,26 +118,32 @@ device_rowbuffer_size=1024
 devices_per_rank=8
 eventq_index=0
 in_addr_map=true
+max_accesses_per_row=16
 mem_sched_policy=frfcfs
+min_writes_per_switch=16
 null=false
-page_policy=open
+page_policy=open_adaptive
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
 static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
+tCK=1250
 tCL=13750
 tRAS=35000
 tRCD=13750
 tREFI=7800000
-tRFC=300000
+tRFC=260000
 tRP=13750
-tRRD=6250
+tRRD=6000
+tRTP=7500
+tRTW=2500
+tWR=15000
 tWTR=7500
-tXAW=40000
-write_buffer_size=32
-write_high_thresh_perc=70
-write_low_thresh_perc=0
+tXAW=30000
+write_buffer_size=64
+write_high_thresh_perc=85
+write_low_thresh_perc=50
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index 1932695fb..bda575e80 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -10,14 +10,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=clk_domain cpu membus monitor physmem
+children=clk_domain cpu dvfs_handler membus monitor physmem
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 init_param=0
 kernel=
+kernel_addr_check=true
 load_addr_mask=1099511627775
+load_offset=0
 mem_mode=timing
 mem_ranges=
 memories=system.physmem
@@ -37,7 +39,9 @@ system_port=system.membus.slave[1]
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+domain_id=-1
 eventq_index=0
+init_perf_level=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
@@ -54,6 +58,14 @@ eventq_index=0
 system=system
 port=system.monitor.slave
 
+[system.dvfs_handler]
+type=DVFSHandler
+domains=
+enable=false
+eventq_index=0
+sys_clk_domain=system.clk_domain
+transition_latency=100000000
+
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
@@ -83,6 +95,9 @@ latency_bins=20
 outstanding_bins=20
 read_addr_mask=18446744073709551615
 sample_period=1000000000
+system=system
+trace_compress=true
+trace_enable=true
 trace_file=monitor.ptrc.gz
 transaction_bins=20
 write_addr_mask=18446744073709551615