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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
| commit | 64806c4c13040832dd1e24b8fb0c347cd794398e (patch) | |
| tree | 8fd8715bae92bf048efbd48d62616105638a5b24 /tests/quick/se/70.tgen/tgen-simple-mem.cfg | |
| parent | f800f268dbf638d21987c9bb8a235263ba715a93 (diff) | |
| download | gem5-64806c4c13040832dd1e24b8fb0c347cd794398e.tar.xz | |
tests: Reflect name change in DRAM tests
This patch reflects the recent name change in the DRAM TrafficGen
tests and also tidies up the test directory.
--HG--
rename : tests/configs/tgen-simple-dram.py => tests/configs/tgen-dram-ctrl.py
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/config.ini
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simerr
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/simout
rename : tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt => tests/quick/se/70.tgen/ref/null/none/tgen-dram-ctrl/stats.txt
rename : tests/quick/se/70.tgen/tgen-simple-dram.cfg => tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
Diffstat (limited to 'tests/quick/se/70.tgen/tgen-simple-mem.cfg')
| -rw-r--r-- | tests/quick/se/70.tgen/tgen-simple-mem.cfg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/quick/se/70.tgen/tgen-simple-mem.cfg b/tests/quick/se/70.tgen/tgen-simple-mem.cfg index 532f1ef21..6d037f9ea 100644 --- a/tests/quick/se/70.tgen/tgen-simple-mem.cfg +++ b/tests/quick/se/70.tgen/tgen-simple-mem.cfg @@ -8,9 +8,9 @@ # STATE <id> <duration (ticks)> <type> # # State IDLE idles -# -# States LINEAR and RANDOM have additional <percent reads> <start addr> -# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)> +# +# States LINEAR and RANDOM have additional <percent reads> <start addr> +# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)> # <data limit (bytes)> # # State TRACE plays back a pre-recorded trace once |