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author | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-21 11:48:11 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-09-21 11:48:11 -0400 |
commit | efea870fce8c00dbb8d5b9b33fe6fd0cf2e3b960 (patch) | |
tree | 35729f5ff93cde1982eb62306c0a0f403ae96f63 /tests/quick/se/70.tgen/tgen-simple-mem.cfg | |
parent | d75b1b5a7366c162ffca69b29901f4cb5e05895d (diff) | |
download | gem5-efea870fce8c00dbb8d5b9b33fe6fd0cf2e3b960.tar.xz |
TrafficGen: Add a basic traffic generator regression
This patch adds a basic regression for the traffic generator. The
regression also serves as an example of the file formats used. More
complex regressions that make use of a DRAM controller model will
follow shortly.
Diffstat (limited to 'tests/quick/se/70.tgen/tgen-simple-mem.cfg')
-rw-r--r-- | tests/quick/se/70.tgen/tgen-simple-mem.cfg | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/tests/quick/se/70.tgen/tgen-simple-mem.cfg b/tests/quick/se/70.tgen/tgen-simple-mem.cfg new file mode 100644 index 000000000..532f1ef21 --- /dev/null +++ b/tests/quick/se/70.tgen/tgen-simple-mem.cfg @@ -0,0 +1,27 @@ +# This format supports comments using the '#' symbol as the leading +# character of the line +# +# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order, +# where the states are the nodes in the graph, init describes what +# state to start in, and transition describes the edges of the graph. +# +# STATE <id> <duration (ticks)> <type> +# +# State IDLE idles +# +# States LINEAR and RANDOM have additional <percent reads> <start addr> +# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)> +# <data limit (bytes)> +# +# State TRACE plays back a pre-recorded trace once +# +# Addresses are expressed as decimal numbers, both in the +# configuration and the trace file. The period in the linear and +# random state is from a uniform random distribution over the +# interval. If a specific value is desired, then the min and max can +# be set to the same value. +STATE 0 1000000 TRACE tests/quick/se/70.tgen/tgen-simple-mem.trc 100 +STATE 1 1000000000 RANDOM 0 0 134217728 64 30000 30000 0 +INIT 0 +TRANSITION 0 1 1 +TRANSITION 1 1 1 |