stats: update stats for cache occupancy and clock domain changes

6 files changed, 38 insertions, 17 deletions

diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
index 61b6eb32e..b3c13e1c2 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu membus monitor physmem
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -34,10 +37,12 @@ system_port=system.membus.slave[1]
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+eventq_index=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
 [system.cpu]
@@ -45,12 +50,14 @@ type=TrafficGen
 clk_domain=system.clk_domain
 config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
 elastic_req=false
+eventq_index=0
 system=system
 port=system.monitor.slave
 
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=16
@@ -69,6 +76,7 @@ disable_itt_dists=false
 disable_latency_hists=false
 disable_outstanding_hists=false
 disable_transaction_hists=false
+eventq_index=0
 itt_bins=20
 itt_max_bin=100000
 latency_bins=20
@@ -93,6 +101,7 @@ conf_table_reported=true
 device_bus_width=8
 device_rowbuffer_size=1024
 devices_per_rank=8
+eventq_index=0
 in_addr_map=true
 mem_sched_policy=frfcfs
 null=false
@@ -104,13 +113,16 @@ static_backend_latency=10000
 static_frontend_latency=10000
 tBURST=5000
 tCL=13750
+tRAS=35000
 tRCD=13750
 tREFI=7800000
 tRFC=300000
 tRP=13750
+tRRD=6250
 tWTR=7500
 tXAW=40000
 write_buffer_size=32
-write_thresh_perc=70
+write_high_thresh_perc=70
+write_low_thresh_perc=0
 port=system.membus.master[0]
 
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
index 2426a6cee..cffe93183 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:53:51
-gem5 started Sep 22 2013 05:53:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:54:17
+gem5 started Jan 22 2014 17:29:00
+gem5 executing on u200540-lin
 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
index 9c1ab67e5..9a5e1cab0 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/stats.txt
@@ -4,9 +4,11 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                            20181472495                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 192916                       # Number of bytes of host memory used
-host_seconds                                     4.96                       # Real time elapsed on the host
+host_tick_rate                            33856013702                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 195468                       # Number of bytes of host memory used
+host_seconds                                     2.95                       # Real time elapsed on the host
+system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu              213331136                       # Number of bytes read from this memory
 system.physmem.bytes_read::total            213331136                       # Number of bytes read from this memory
 system.physmem.num_reads::cpu                 3333299                       # Number of read requests responded to by this memory
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
index 27a6fb9af..1932695fb 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -1,7 +1,9 @@
 [root]
 type=Root
 children=system
+eventq_index=0
 full_system=false
+sim_quantum=0
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -12,6 +14,7 @@ children=clk_domain cpu membus monitor physmem
 boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
+eventq_index=0
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -34,10 +37,12 @@ system_port=system.membus.slave[1]
 type=SrcClockDomain
 children=voltage_domain
 clock=1000
+eventq_index=0
 voltage_domain=system.clk_domain.voltage_domain
 
 [system.clk_domain.voltage_domain]
 type=VoltageDomain
+eventq_index=0
 voltage=1.000000
 
 [system.cpu]
@@ -45,12 +50,14 @@ type=TrafficGen
 clk_domain=system.clk_domain
 config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
 elastic_req=false
+eventq_index=0
 system=system
 port=system.monitor.slave
 
 [system.membus]
 type=NoncoherentBus
 clk_domain=system.clk_domain
+eventq_index=0
 header_cycles=1
 use_default_range=false
 width=16
@@ -69,6 +76,7 @@ disable_itt_dists=false
 disable_latency_hists=false
 disable_outstanding_hists=false
 disable_transaction_hists=false
+eventq_index=0
 itt_bins=20
 itt_max_bin=100000
 latency_bins=20
@@ -86,6 +94,7 @@ type=SimpleMemory
 bandwidth=73.000000
 clk_domain=system.clk_domain
 conf_table_reported=true
+eventq_index=0
 in_addr_map=true
 latency=30000
 latency_var=0
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
index efa3fa542..ccbd2154c 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
-Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep 22 2013 05:53:51
-gem5 started Sep 22 2013 05:53:54
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 16:54:17
+gem5 started Jan 22 2014 17:29:05
+gem5 executing on u200540-lin
 command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
index 14b3c1d80..ead00396f 100644
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/stats.txt
@@ -4,9 +4,11 @@ sim_seconds                                  0.100000                       # Nu
 sim_ticks                                100000000000                       # Number of ticks simulated
 final_tick                               100000000000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                             8032030639                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 228596                       # Number of bytes of host memory used
-host_seconds                                    12.45                       # Real time elapsed on the host
+host_tick_rate                            14364594493                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 195500                       # Number of bytes of host memory used
+host_seconds                                     6.96                       # Real time elapsed on the host
+system.clk_domain.voltage_domain.voltage            1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu                     64                       # Number of bytes read from this memory
 system.physmem.bytes_read::total                   64                       # Number of bytes read from this memory
 system.physmem.bytes_written::cpu           213329152                       # Number of bytes written to this memory