stats: Update to match classic memory changes

1 files changed, 172 insertions, 168 deletions

diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
index b87761f8a..21be26077 100644
--- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
+++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
@@ -1,19 +1,19 @@
 
 ---------- Begin Simulation Statistics ----------
-sim_seconds                                  0.230198                       # Number of seconds simulated
-sim_ticks                                230197694500                       # Number of ticks simulated
-final_tick                               230197694500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds                                  0.230201                       # Number of seconds simulated
+sim_ticks                                230201146500                       # Number of ticks simulated
+final_tick                               230201146500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 688414                       # Simulator instruction rate (inst/s)
-host_op_rate                                   725763                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              922189750                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 268612                       # Number of bytes of host memory used
-host_seconds                                   249.62                       # Real time elapsed on the host
+host_inst_rate                                 826360                       # Simulator instruction rate (inst/s)
+host_op_rate                                   871192                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1106995865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 273252                       # Number of bytes of host memory used
+host_seconds                                   207.95                       # Real time elapsed on the host
 sim_insts                                   171842484                       # Number of instructions simulated
 sim_ops                                     181165371                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.physmem.bytes_read::cpu.inst            110656                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.data            110336                       # Number of bytes read from this memory
 system.physmem.bytes_read::total               220992                       # Number of bytes read from this memory
@@ -22,17 +22,17 @@ system.physmem.bytes_inst_read::total          110656                       # Nu
 system.physmem.num_reads::cpu.inst               1729                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.data               1724                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                  3453                       # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst               480700                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data               479310                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total                  960010                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst          480700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total             480700                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst              480700                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data              479310                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total                 960010                       # Total bandwidth to/from this memory (bytes/s)
-system.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.physmem.bw_read::cpu.inst               480693                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data               479303                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total                  959995                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst          480693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total             480693                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              480693                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data              479303                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total                 959995                       # Total bandwidth to/from this memory (bytes/s)
+system.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu_clk_domain.clock                       500                       # Clock period in ticks
-system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -62,7 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -92,7 +92,7 @@ system.cpu.dtb.inst_accesses                        0                       # IT
 system.cpu.dtb.hits                                 0                       # DTB hits
 system.cpu.dtb.misses                               0                       # DTB misses
 system.cpu.dtb.accesses                             0                       # DTB accesses
-system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -122,7 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0
 system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
 system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
 system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
-system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.itb.walker.walks                         0                       # Table walker walks requested
 system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -153,8 +153,8 @@ system.cpu.itb.hits                                 0                       # DT
 system.cpu.itb.misses                               0                       # DTB misses
 system.cpu.itb.accesses                             0                       # DTB accesses
 system.cpu.workload.num_syscalls                  400                       # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON    230197694500                       # Cumulative time (in ticks) in various power states
-system.cpu.numCycles                        460395389                       # number of cpu cycles simulated
+system.cpu.pwrStateResidencyTicks::ON    230201146500                       # Cumulative time (in ticks) in various power states
+system.cpu.numCycles                        460402293                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
 system.cpu.committedInsts                   171842484                       # Number of instructions committed
@@ -175,7 +175,7 @@ system.cpu.num_mem_refs                      40540779                       # nu
 system.cpu.num_load_insts                    27896144                       # Number of load instructions
 system.cpu.num_store_insts                   12644635                       # Number of store instructions
 system.cpu.num_idle_cycles                   0.002000                       # Number of idle cycles
-system.cpu.num_busy_cycles               460395388.998000                       # Number of busy cycles
+system.cpu.num_busy_cycles               460402292.998000                       # Number of busy cycles
 system.cpu.not_idle_fraction                 1.000000                       # Percentage of non-idle cycles
 system.cpu.idle_fraction                     0.000000                       # Percentage of idle cycles
 system.cpu.Branches                          40300312                       # Number of branches fetched
@@ -214,16 +214,16 @@ system.cpu.op_class::MemWrite                12644635      6.96%    100.00% # Cl
 system.cpu.op_class::IprAccess                      0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::InstPrefetch                   0      0.00%    100.00% # Class of executed instruction
 system.cpu.op_class::total                  181650743                       # Class of executed instruction
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.tags.replacements                40                       # number of replacements
-system.cpu.dcache.tags.tagsinuse          1363.571253                       # Cycle average of tags in use
+system.cpu.dcache.tags.tagsinuse          1363.564425                       # Cycle average of tags in use
 system.cpu.dcache.tags.total_refs            40162626                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs              1789                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs          22449.762996                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data  1363.571253                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data     0.332903                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total     0.332903                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data  1363.564425                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.332901                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.332901                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024         1749                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0           14                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -233,7 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4         1345
 system.cpu.dcache.tags.occ_task_id_percent::1024     0.427002                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses          80330619                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses         80330619                       # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.dcache.ReadReq_hits::cpu.data     27754163                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        27754163                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
@@ -258,14 +258,14 @@ system.cpu.dcache.demand_misses::cpu.data         1788                       # n
 system.cpu.dcache.demand_misses::total           1788                       # number of demand (read+write) misses
 system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
 system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data     39940000                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total     39940000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data     67838500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total     67838500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data    107778500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total    107778500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data    107778500                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total    107778500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     40571000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     40571000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     68930500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     68930500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    109501500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    109501500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    109501500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    109501500                       # number of overall miss cycles
 system.cpu.dcache.ReadReq_accesses::cpu.data     27754851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     27754851                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
@@ -290,14 +290,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data     0.000045
 system.cpu.dcache.demand_miss_rate::total     0.000045                       # miss rate for demand accesses
 system.cpu.dcache.overall_miss_rate::cpu.data     0.000045                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.000045                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 60278.803132                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 60245.108999                       # average overall miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 61242.449664                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 61208.216881                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -316,16 +316,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data         1788
 system.cpu.dcache.demand_mshr_misses::total         1788                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39252000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total     39252000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     66738500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total     66738500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        61000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        61000                       # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data    105990500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total    105990500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data    106051500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total    106051500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     39883000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     39883000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     67830500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     67830500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data        62000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.SoftPFReq_mshr_miss_latency::total        62000                       # number of SoftPFReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    107713500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    107713500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    107775500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    107775500                       # number of overall MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000025                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
@@ -336,26 +336,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000045
 system.cpu.dcache.demand_mshr_miss_rate::total     0.000045                       # mshr miss rate for demand accesses
 system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.000045                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636                       # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        61000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        61000                       # average SoftPFReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232                       # average overall mshr miss latency
-system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909                       # average WriteReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data        62000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total        62000                       # average SoftPFReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085                       # average overall mshr miss latency
+system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.tags.replacements              1506                       # number of replacements
-system.cpu.icache.tags.tagsinuse          1147.958164                       # Cycle average of tags in use
+system.cpu.icache.tags.tagsinuse          1147.953271                       # Cycle average of tags in use
 system.cpu.icache.tags.total_refs           189857002                       # Total number of references to valid blocks.
 system.cpu.icache.tags.sampled_refs              3051                       # Sample count of references to valid blocks.
 system.cpu.icache.tags.avg_refs          62227.794821                       # Average number of references to valid blocks.
 system.cpu.icache.tags.warmup_cycle                 0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst  1147.958164                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst     0.560526                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total     0.560526                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_blocks::cpu.inst  1147.953271                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.560524                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.560524                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_task_id_blocks::1024         1545                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::0           24                       # Occupied blocks per task id
 system.cpu.icache.tags.age_task_id_blocks_1024::1           21                       # Occupied blocks per task id
@@ -365,7 +365,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4          942
 system.cpu.icache.tags.occ_task_id_percent::1024     0.754395                       # Percentage of cache occupancy per task id
 system.cpu.icache.tags.tag_accesses         379723157                       # Number of tag accesses
 system.cpu.icache.tags.data_accesses        379723157                       # Number of data accesses
-system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.icache.ReadReq_hits::cpu.inst    189857002                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       189857002                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst     189857002                       # number of demand (read+write) hits
@@ -378,12 +378,12 @@ system.cpu.icache.demand_misses::cpu.inst         3051                       # n
 system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
 system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
 system.cpu.icache.overall_misses::total          3051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst    124592000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total    124592000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst    124592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total    124592000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst    124592000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total    124592000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    126321000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    126321000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    126321000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    126321000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    126321000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    126321000                       # number of overall miss cycles
 system.cpu.icache.ReadReq_accesses::cpu.inst    189860053                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    189860053                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.demand_accesses::cpu.inst    189860053                       # number of demand (read+write) accesses
@@ -396,12 +396,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst     0.000016
 system.cpu.icache.demand_miss_rate::total     0.000016                       # miss rate for demand accesses
 system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
 system.cpu.icache.overall_miss_rate::total     0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 40836.447067                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 40836.447067                       # average overall miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509                       # average overall miss latency
+system.cpu.icache.demand_avg_miss_latency::total 41403.146509                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::total 41403.146509                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -416,48 +416,46 @@ system.cpu.icache.demand_mshr_misses::cpu.inst         3051
 system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
 system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    121541000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total    121541000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst    121541000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total    121541000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst    121541000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total    121541000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    123270000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    123270000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    123270000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    123270000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    123270000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    123270000                       # number of overall MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000016                       # mshr miss rate for ReadReq accesses
 system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.demand_mshr_miss_rate::total     0.000016                       # mshr miss rate for demand accesses
 system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
 system.cpu.icache.overall_mshr_miss_rate::total     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067                       # average overall mshr miss latency
-system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509                       # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509                       # average overall mshr miss latency
+system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.tags.replacements                0                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse         1675.610098                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs               2846                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs             2369                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs             1.201351                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.tagsinuse         2511.620011                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs               2869                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs             3453                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             0.830872                       # Average number of references to valid blocks.
 system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks     3.037805                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst  1169.001518                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   503.570775                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  1168.996513                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  1342.623498                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.035675                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total     0.051136                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024         2369                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0           30                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1           18                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2          320                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3          322                       # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1679                       # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024     0.072296                       # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses            54045                       # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses           54045                       # Number of data accesses
-system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.040974                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.076649                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1024         3453                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           29                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1           30                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2          341                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3          536                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4         2517                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.105377                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses            54029                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses           54029                       # Number of data accesses
+system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.l2cache.WritebackDirty_hits::writebacks           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackDirty_hits::total           16                       # number of WritebackDirty hits
 system.cpu.l2cache.WritebackClean_hits::writebacks         1448                       # number of WritebackClean hits
@@ -486,18 +484,18 @@ system.cpu.l2cache.demand_misses::total          3453                       # nu
 system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
 system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     65004500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::total     65004500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    102968000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadCleanReq_miss_latency::total    102968000                       # number of ReadCleanReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     37629500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.ReadSharedReq_miss_latency::total     37629500                       # number of ReadSharedReq miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst    102968000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.data    102634000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::total    205602000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst    102968000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.data    102634000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::total    205602000                       # number of overall miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     66096500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     66096500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    104697000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadCleanReq_miss_latency::total    104697000                       # number of ReadCleanReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data     38261500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.ReadSharedReq_miss_latency::total     38261500                       # number of ReadSharedReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    104697000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    104358000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    209055000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    104697000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    104358000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    209055000                       # number of overall miss cycles
 system.cpu.l2cache.WritebackDirty_accesses::writebacks           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackDirty_accesses::total           16                       # number of WritebackDirty accesses(hits+misses)
 system.cpu.l2cache.WritebackClean_accesses::writebacks         1448                       # number of WritebackClean accesses(hits+misses)
@@ -526,18 +524,18 @@ system.cpu.l2cache.demand_miss_rate::total     0.713430                       #
 system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132                       # average ReadCleanReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101                       # average ReadSharedReq miss latency
-system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101                       # average ReadSharedReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082                       # average overall miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403                       # average ReadExReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132                       # average ReadCleanReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101                       # average ReadSharedReq miss latency
+system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101                       # average ReadSharedReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -556,18 +554,18 @@ system.cpu.l2cache.demand_mshr_misses::total         3453
 system.cpu.l2cache.overall_mshr_misses::cpu.inst         1729                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.data         1724                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total         3453                       # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     54084500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     54084500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     85678000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     85678000                       # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31309500                       # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     85678000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     85394000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total    171072000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     85678000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     85394000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total    171072000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     55176500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     55176500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst     87407000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total     87407000                       # number of ReadCleanReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data     31941500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total     31941500                       # number of ReadSharedReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     87407000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     87118000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    174525000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     87407000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     87118000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    174525000                       # number of overall MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992727                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.992727                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadCleanReq accesses
@@ -580,25 +578,25 @@ system.cpu.l2cache.demand_mshr_miss_rate::total     0.713430
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.713430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132                       # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101                       # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082                       # average overall mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132                       # average ReadCleanReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101                       # average ReadSharedReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082                       # average overall mshr miss latency
 system.cpu.toL2Bus.snoop_filter.tot_requests         6386                       # Total number of requests made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_requests         1644                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_requests           64                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
 system.cpu.toL2Bus.snoop_filter.tot_snoops            0                       # Total number of snoops made to the snoop filter.
 system.cpu.toL2Bus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
 system.cpu.toL2Bus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.cpu.toL2Bus.trans_dist::ReadResp          3740                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackDirty           16                       # Transaction distribution
 system.cpu.toL2Bus.trans_dist::WritebackClean         1506                       # Transaction distribution
@@ -632,7 +630,13 @@ system.cpu.toL2Bus.respLayer0.occupancy       4576500                       # La
 system.cpu.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
 system.cpu.toL2Bus.respLayer1.occupancy       2683500                       # Layer occupancy (ticks)
 system.cpu.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
-system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500                       # Cumulative time (in ticks) in various power states
+system.membus.snoop_filter.tot_requests          3453                       # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests            0                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500                       # Cumulative time (in ticks) in various power states
 system.membus.trans_dist::ReadResp               2361                       # Transaction distribution
 system.membus.trans_dist::ReadExReq              1092                       # Transaction distribution
 system.membus.trans_dist::ReadExResp             1092                       # Transaction distribution