diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-05-31 16:55:47 +0100 |
| commit | dafec4a51542b76a926b390f0cafa6c715a54c49 (patch) | |
| tree | b9088b609725b87ec1ef5f6a5359b3454ed4519c /tests/quick/se/70.twolf/ref/sparc | |
| parent | c661cc75eca97989d72c513550b7a63e995a3982 (diff) | |
| download | gem5-dafec4a51542b76a926b390f0cafa6c715a54c49.tar.xz | |
stats: update and fix e273e86a873d
Diffstat (limited to 'tests/quick/se/70.twolf/ref/sparc')
| -rw-r--r-- | tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt | 124 | ||||
| -rw-r--r-- | tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt | 515 |
2 files changed, 639 insertions, 0 deletions
diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index e69de29bb..4c392ae66 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -0,0 +1,124 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.096723 # Number of seconds simulated +sim_ticks 96722945000 # Number of ticks simulated +final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1393535 # Simulator instruction rate (inst/s) +host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 696772335 # Simulator tick rate (ticks/s) +host_mem_usage 242012 # Number of bytes of host memory used +host_seconds 138.82 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory +system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 773782140 # Number of instructions bytes read from this memory +system.physmem.bytes_written::cpu.data 72065412 # Number of bytes written to this memory +system.physmem.bytes_written::total 72065412 # Number of bytes written to this memory +system.physmem.num_reads::cpu.inst 193445535 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 57735068 # Number of read requests responded to by this memory +system.physmem.num_reads::total 251180603 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu.data 18976439 # Number of write requests responded to by this memory +system.physmem.num_writes::total 18976439 # Number of write requests responded to by this memory +system.physmem.num_other::cpu.data 22406 # Number of other requests responded to by this memory +system.physmem.num_other::total 22406 # Number of other requests responded to by this memory +system.physmem.bw_read::cpu.inst 7999985319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2310345420 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 10310330739 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7999985319 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 745070490 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 193445891 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060124 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 193445890.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction +system.membus.trans_dist::ReadReq 251180603 # Transaction distribution +system.membus.trans_dist::ReadResp 251180603 # Transaction distribution +system.membus.trans_dist::WriteReq 18976439 # Transaction distribution +system.membus.trans_dist::WriteResp 18976439 # Transaction distribution +system.membus.trans_dist::SwapReq 22406 # Transaction distribution +system.membus.trans_dist::SwapResp 22406 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 386891070 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 153467826 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 540358896 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 773782140 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 295708073 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 1069490213 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 270179448 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715989 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.450942 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 76733913 28.40% 28.40% # Request fanout histogram +system.membus.snoop_fanout::1 193445535 71.60% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 270179448 # Request fanout histogram + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index e69de29bb..812685f18 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -0,0 +1,515 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.270600 # Number of seconds simulated +sim_ticks 270599529500 # Number of ticks simulated +final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 833752 # Simulator instruction rate (inst/s) +host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1166291607 # Simulator tick rate (ticks/s) +host_mem_usage 251752 # Number of bytes of host memory used +host_seconds 232.02 # Real time elapsed on the host +sim_insts 193444518 # Number of instructions simulated +sim_ops 193444756 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory +system.physmem.bytes_read::total 331072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 230208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 230208 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 3597 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1576 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5173 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 850733 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 372743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1223476 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 850733 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) +system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.numCycles 541199059 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 193444518 # Number of instructions committed +system.cpu.committedOps 193444756 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 167974806 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses +system.cpu.num_func_calls 1957920 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 8665106 # number of instructions that are conditional controls +system.cpu.num_int_insts 167974806 # number of integer instructions +system.cpu.num_fp_insts 1970372 # number of float instructions +system.cpu.num_int_register_reads 352617941 # number of times the integer registers were read +system.cpu.num_int_register_writes 163060123 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3181089 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2974850 # number of times the floating registers were written +system.cpu.num_mem_refs 76733958 # number of memory refs +system.cpu.num_load_insts 57735091 # Number of load instructions +system.cpu.num_store_insts 18998867 # Number of store instructions +system.cpu.num_idle_cycles 0.002000 # Number of idle cycles +system.cpu.num_busy_cycles 541199058.998000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 15132745 # Number of branches fetched +system.cpu.op_class::No_OpClass 13329871 6.89% 6.89% # Class of executed instruction +system.cpu.op_class::IntAlu 102506896 52.99% 59.88% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 59.88% # Class of executed instruction +system.cpu.op_class::FloatAdd 875036 0.45% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.33% # Class of executed instruction +system.cpu.op_class::MemRead 57735103 29.85% 90.18% # Class of executed instruction +system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.replacements 2 # number of replacements +system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 1576 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 48688.031091 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 1237.159344 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.302041 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 1574 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 39 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::3 271 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18975362 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 22405 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 22405 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 76709932 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 76709932 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 76709932 # number of overall hits +system.cpu.dcache.overall_hits::total 76709932 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 498 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 498 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 1077 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1077 # number of WriteReq misses +system.cpu.dcache.SwapReq_misses::cpu.data 1 # number of SwapReq misses +system.cpu.dcache.SwapReq_misses::total 1 # number of SwapReq misses +system.cpu.dcache.demand_misses::cpu.data 1575 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1575 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1575 # number of overall misses +system.cpu.dcache.overall_misses::total 1575 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 30877500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 30877500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 66775000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 66775000 # number of WriteReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::cpu.data 62000 # number of SwapReq miss cycles +system.cpu.dcache.SwapReq_miss_latency::total 62000 # number of SwapReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 97652500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 97652500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 97652500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 57735068 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18976439 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::cpu.data 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.SwapReq_accesses::total 22406 # number of SwapReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 76711507 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 76711507 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 76711507 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 76711507 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.000009 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.000057 # miss rate for WriteReq accesses +system.cpu.dcache.SwapReq_miss_rate::cpu.data 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.SwapReq_miss_rate::total 0.000045 # miss rate for SwapReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.000021 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.000021 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.000021 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.000021 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62003.012048 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62003.012048 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000.928505 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 62000.928505 # average WriteReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 62000 # average SwapReq miss latency +system.cpu.dcache.SwapReq_avg_miss_latency::total 62000 # average SwapReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 62001.587302 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 62001.587302 # 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average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59507.784265 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59501.269036 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 59505.799343 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 3597 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 498 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 498 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 53362000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 178079500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 24652000 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 178079500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78014000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 256093500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 178079500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78014000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 256093500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.292725 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.373125 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.373125 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500.927644 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49507.784265 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49502.008032 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49507.784265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49501.269036 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49505.799343 # average overall mshr miss latency +system.cpu.toL2Bus.snoop_filter.tot_requests 24228 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 10365 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 1078 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 12288 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 498 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 34938 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3154 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 38092 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1449600 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 100992 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 1550592 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 0 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 13864 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.000072 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.008493 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 13863 99.99% 99.99% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 1 0.01% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 13864 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 22478000 # Layer occupancy (ticks) +system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer0.occupancy 18432000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.trans_dist::ReadResp 4095 # Transaction distribution +system.membus.trans_dist::ReadExReq 1078 # Transaction distribution +system.membus.trans_dist::ReadExResp 1078 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 4095 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 10346 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 331072 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 5173 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 5173 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 5173 # Request fanout histogram +system.membus.reqLayer0.occupancy 5203000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.respLayer1.occupancy 25865000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |