diff options
author | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-14 11:57:41 -0800 |
---|---|---|
committer | Bobby R. Bruce <bbruce@ucdavis.edu> | 2020-01-24 06:02:32 +0000 |
commit | 377898c4034c72b84b2662ed252fa25079a4ea62 (patch) | |
tree | e643331a8a2b31816021e560f2b21860acc5b6c0 /tests/quick/se/70.twolf/ref/x86/linux | |
parent | db8969f1efb9c9b55c4891da101c9025fc8ffaff (diff) | |
download | gem5-377898c4034c72b84b2662ed252fa25079a4ea62.tar.xz |
tests: Removed 70.twolf tests
In an effort to cleanup the old tests, and migrate useful tests to be
executed via `test/main.py`, it has been decided that the
`test/quick/70.twolf` tests should be removed.
Jira: https://gem5.atlassian.net/browse/GEM5-109
Change-Id: I19f2e20298e14a92f49adf0b8369e1fa09e0c1bc
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24383
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'tests/quick/se/70.twolf/ref/x86/linux')
22 files changed, 0 insertions, 2179 deletions
diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini deleted file mode 100644 index f29a800e1..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/config.ini +++ /dev/null @@ -1,263 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kvm_vm=Null -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=atomic -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=AtomicSimpleCPU -children=apic_clk_domain dtb interrupts isa itb tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fastmem=false -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -simulate_data_stalls=false -simulate_inst_stalls=false -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -width=1 -workload=system.cpu.workload -dcache_port=system.membus.slave[2] -icache_port=system.membus.slave[1] - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.membus.slave[4] - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_latency=1000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -power_model=Null -system=system -int_master=system.membus.slave[5] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.membus.slave[3] - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=twolf smred -cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.int_master - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr deleted file mode 100755 index 094173d40..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout deleted file mode 100755 index c05a3785d..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/simout +++ /dev/null @@ -1,27 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 19:05:53 -gem5 started Apr 3 2017 19:06:21 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87172 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-atomic - -Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sav -Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-atomic/smred.sv2 -Global frequency set at 1000000000000 ticks per second - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 131393279000 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out deleted file mode 100644 index 00387ae5c..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt deleted file mode 100644 index 78c52ebfd..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ /dev/null @@ -1,145 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.131393 -sim_ticks 131393279000 -final_tick 131393279000 -sim_freq 1000000000000 -host_inst_rate 712720 -host_op_rate 1194584 -host_tick_rate 709061486 -host_mem_usage 300116 -host_seconds 185.31 -sim_insts 132071193 -sim_ops 221363385 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.physmem.bytes_read::cpu.inst 1387954936 -system.physmem.bytes_read::cpu.data 310423752 -system.physmem.bytes_read::total 1698378688 -system.physmem.bytes_inst_read::cpu.inst 1387954936 -system.physmem.bytes_inst_read::total 1387954936 -system.physmem.bytes_written::cpu.data 99822191 -system.physmem.bytes_written::total 99822191 -system.physmem.num_reads::cpu.inst 173494367 -system.physmem.num_reads::cpu.data 56682005 -system.physmem.num_reads::total 230176372 -system.physmem.num_writes::cpu.data 20515731 -system.physmem.num_writes::total 20515731 -system.physmem.bw_read::cpu.inst 10563363260 -system.physmem.bw_read::cpu.data 2362554267 -system.physmem.bw_read::total 12925917527 -system.physmem.bw_inst_read::cpu.inst 10563363260 -system.physmem.bw_inst_read::total 10563363260 -system.physmem.bw_write::cpu.data 759720678 -system.physmem.bw_write::total 759720678 -system.physmem.bw_total::cpu.inst 10563363260 -system.physmem.bw_total::cpu.data 3122274945 -system.physmem.bw_total::total 13685638205 -system.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.cpu_clk_domain.clock 500 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.cpu.apic_clk_domain.clock 8000 -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.cpu.workload.numSyscalls 400 -system.cpu.pwrStateResidencyTicks::ON 131393279000 -system.cpu.numCycles 262786559 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 132071193 -system.cpu.committedOps 221363385 -system.cpu.num_int_alu_accesses 219019986 -system.cpu.num_fp_alu_accesses 2162459 -system.cpu.num_func_calls 1595632 -system.cpu.num_conditional_control_insts 8268466 -system.cpu.num_int_insts 219019986 -system.cpu.num_fp_insts 2162459 -system.cpu.num_int_register_reads 519996939 -system.cpu.num_int_register_writes 201355989 -system.cpu.num_fp_register_reads 3037165 -system.cpu.num_fp_register_writes 1831403 -system.cpu.num_cc_register_reads 96962463 -system.cpu.num_cc_register_writes 56242058 -system.cpu.num_mem_refs 77165304 -system.cpu.num_load_insts 56649587 -system.cpu.num_store_insts 20515717 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 262786559 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 12326938 -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% -system.cpu.op_class::IntMult 772953 0.35% 61.47% -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% -system.cpu.op_class::FloatCmp 0 0.00% 65.14% -system.cpu.op_class::FloatCvt 0 0.00% 65.14% -system.cpu.op_class::FloatMult 0 0.00% 65.14% -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% -system.cpu.op_class::FloatDiv 0 0.00% 65.14% -system.cpu.op_class::FloatMisc 0 0.00% 65.14% -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% -system.cpu.op_class::SimdAdd 0 0.00% 65.14% -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% -system.cpu.op_class::SimdAlu 0 0.00% 65.14% -system.cpu.op_class::SimdCmp 0 0.00% 65.14% -system.cpu.op_class::SimdCvt 0 0.00% 65.14% -system.cpu.op_class::SimdMisc 0 0.00% 65.14% -system.cpu.op_class::SimdMult 0 0.00% 65.14% -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% -system.cpu.op_class::SimdShift 0 0.00% 65.14% -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% -system.cpu.op_class::MemRead 55945136 25.27% 90.41% -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 221363385 -system.membus.snoop_filter.tot_requests 0 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 -system.membus.trans_dist::ReadReq 230176372 -system.membus.trans_dist::ReadResp 230176372 -system.membus.trans_dist::WriteReq 20515731 -system.membus.trans_dist::WriteResp 20515731 -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 -system.membus.pkt_count_system.cpu.icache_port::total 346988734 -system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 -system.membus.pkt_count_system.cpu.dcache_port::total 154395472 -system.membus.pkt_count::total 501384206 -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 -system.membus.pkt_size_system.cpu.icache_port::total 1387954936 -system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 -system.membus.pkt_size_system.cpu.dcache_port::total 410245943 -system.membus.pkt_size::total 1798200879 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 250692103 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 250692103 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 250692103 - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini deleted file mode 100644 index 66b18ed6d..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/config.ini +++ /dev/null @@ -1,432 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -exit_on_work_items=false -init_param=0 -kernel= -kernel_addr_check=true -kvm_vm=Null -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -mmap_using_noreserve=false -multi_thread=false -num_work_ids=16 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -readfile= -symbolfile= -thermal_components= -thermal_model=Null -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=TimingSimpleCPU -children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -branchPred=Null -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -default_p_state=UNDEFINED -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numThreads=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -switched_out=false -syscallRetryLatency=10000 -system=system -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.apic_clk_domain] -type=DerivedClockDomain -clk_divider=16 -clk_domain=system.cpu_clk_domain -eventq_index=0 - -[system.cpu.dcache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tag_latency=2 -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=262144 -tag_latency=2 - -[system.cpu.dtb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.dtb.walker - -[system.cpu.dtb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[3] - -[system.cpu.icache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=2 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=2 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=true -max_miss_count=0 -mshrs=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tag_latency=2 -tags=system.cpu.icache.tags -tgts_per_mshr=20 -write_buffers=8 -writeback_clean=true -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=2 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=131072 -tag_latency=2 - -[system.cpu.interrupts] -type=X86LocalApic -clk_domain=system.cpu.apic_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -int_latency=1000 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -pio_addr=2305843009213693952 -pio_latency=100000 -power_model=Null -system=system -int_master=system.membus.slave[2] -int_slave=system.membus.master[2] -pio=system.membus.master[1] - -[system.cpu.isa] -type=X86ISA -eventq_index=0 - -[system.cpu.itb] -type=X86TLB -children=walker -eventq_index=0 -size=64 -walker=system.cpu.itb.walker - -[system.cpu.itb.walker] -type=X86PagetableWalker -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -num_squash_per_cycle=4 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -system=system -port=system.cpu.toL2Bus.slave[2] - -[system.cpu.l2cache] -type=Cache -children=tags -addr_ranges=0:18446744073709551615:0:0:0:0 -assoc=8 -clk_domain=system.cpu_clk_domain -clusivity=mostly_incl -data_latency=20 -default_p_state=UNDEFINED -demand_mshr_reserve=1 -eventq_index=0 -is_read_only=false -max_miss_count=0 -mshrs=20 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tag_latency=20 -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -write_buffers=8 -writeback_clean=false -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -data_latency=20 -default_p_state=UNDEFINED -eventq_index=0 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -sequential_access=false -size=2097152 -tag_latency=20 - -[system.cpu.toL2Bus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.cpu_clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=0 -frontend_latency=1 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=false -power_model=Null -response_latency=1 -snoop_filter=system.cpu.toL2Bus.snoop_filter -snoop_response_latency=1 -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - -[system.cpu.toL2Bus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=0 -max_capacity=8388608 -system=system - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=Process -cmd=twolf smred -cwd=build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing -drivers= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/usr/local/google/home/gabeblack/gem5/dist/m5/cpu2000/binaries/x86/linux/twolf -gid=100 -input=cin -kvmInSE=false -maxStackSize=67108864 -output=cout -pgid=100 -pid=100 -ppid=0 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -children=snoop_filter -clk_domain=system.clk_domain -default_p_state=UNDEFINED -eventq_index=0 -forward_latency=4 -frontend_latency=3 -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -point_of_coherency=true -power_model=Null -response_latency=2 -snoop_filter=system.membus.snoop_filter -snoop_response_latency=4 -system=system -use_default_range=false -width=16 -master=system.physmem.port system.cpu.interrupts.pio system.cpu.interrupts.int_slave -slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master - -[system.membus.snoop_filter] -type=SnoopFilter -eventq_index=0 -lookup_latency=1 -max_capacity=8388608 -system=system - -[system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clk_domain=system.clk_domain -conf_table_reported=true -default_p_state=UNDEFINED -eventq_index=0 -in_addr_map=true -kvm_map=true -latency=30000 -latency_var=0 -null=false -p_state_clk_gate_bins=20 -p_state_clk_gate_max=1000000000000 -p_state_clk_gate_min=1000 -power_model=Null -range=0:134217727:0:0:0:0 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr deleted file mode 100755 index 094173d40..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -info: Increasing stack size by one page. diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout deleted file mode 100755 index cd651257e..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/simout +++ /dev/null @@ -1,27 +0,0 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/simerr -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Apr 3 2017 19:05:53 -gem5 started Apr 3 2017 19:06:21 -gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87178 -command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/X86/gem5.opt -d build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/70.twolf/x86/linux/simple-timing - -Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sav -Couldn't unlink build/X86/tests/opt/quick/se/70.twolf/x86/linux/simple-timing/smred.sv2 -Global frequency set at 1000000000000 ticks per second - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 - 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 - 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 - 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 - 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 - 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 -106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 250991873500 because exiting with last active thread context diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out deleted file mode 100644 index 00387ae5c..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.out +++ /dev/null @@ -1,276 +0,0 @@ - -TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988 -Standard Cell Placement and Global Routing Program -Authors: Carl Sechen, Bill Swartz - Yale University - - -NOTE: Restart file .rs2 not used - -TimberWolf will perform a global route step -rowSep: 1.000000 -feedThruWidth: 4 - -****************** -BLOCK DATA -block:1 desire:85 -block:2 desire:85 -Total Desired Length: 170 -total cell length: 168 -total block length: 168 -block x-span:84 block y-span:78 -implicit feed thru range: -84 -Using default value of bin.penalty.control:1.000000 -numBins automatically set to:5 -binWidth = average_cell_width + 0 sigma= 17 -average_cell_width is:16 -standard deviation of cell length is:23.6305 -TimberWolfSC starting from the beginning - - - -THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645 -The number of nets with 1 pin is 4 -The number of nets with 2 pin is 9 -The number of nets with 3 pin is 0 -The number of nets with 4 pin is 2 -The number of nets with 5 pin is 0 -The number of nets with 6 pin is 0 -The number of nets with 7 pin is 0 -The number of nets with 8 pin is 0 -The number of nets with 9 pin is 0 -The number of nets with 10 pin or more is 0 - -New Cost Function: Initial Horizontal Cost:242 -New Cost Function: FEEDS:0 MISSING_ROWS:-46 - -bdxlen:86 bdylen:78 -l:0 t:78 r:86 b:0 - - - -THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645 - - - -THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44 - -The rand generator seed was at utemp() : 1 - - - tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000 - tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000 - tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000 - tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000 - - I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs - 1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40 - 2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46 - 3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.2 0.0 0 46 - 4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48 - 5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46 - 6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52 - 7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50 - 8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48 - 9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48 - 10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48 - 11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50 - 12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44 - 13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50 - 14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50 - 15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46 - 16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52 - 17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50 - 18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48 - 19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48 - 20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52 - 21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52 - 22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50 - 23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48 - 24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42 - 25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52 - 26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52 - 27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50 - 28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48 - 29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50 - 30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46 - 31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48 - 32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48 - 33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52 - 34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48 - 35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48 - 36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50 - 37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52 - 38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52 - 39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48 - 40 251 8 741 104 159 0.0 0.8 0.5 36.2 47.5 0.0 0 48 - 41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50 - 42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50 - 43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48 - 44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52 - 45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50 - 46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52 - 47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52 - 48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48 - 49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52 - 50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52 - 51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52 - 52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46 - 53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44 - 54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50 - 55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52 - 56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48 - 57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52 - 58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50 - 59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50 - 60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52 - 61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48 - 62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48 - 63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52 - 64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52 - 65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50 - 66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52 - 67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52 - 68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52 - 69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52 - 70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52 - 71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52 - 72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52 - 73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52 - 74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52 - 75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52 - 76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52 - 77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52 - 78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50 - 79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52 - 80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52 - 81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52 - 82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50 - 83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50 - 84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52 - 85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52 - 86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52 - 87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52 - 88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52 - 89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52 - 90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52 - 91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52 - 92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52 - 93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52 - 94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52 - 95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52 - 96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52 - 97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52 - 98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52 - 99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52 -100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52 -101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52 -102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52 -103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52 -104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52 -105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52 -106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52 -107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52 -108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52 -109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52 -110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52 -111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52 -112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52 -113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52 -114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52 -115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52 -116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52 -117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52 -118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52 -119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52 -120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52 -121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8 - -Initial Wiring Cost: 645 Final Wiring Cost: 732 -############## Percent Wire Cost Reduction: -13 - - -Initial Wire Length: 645 Final Wire Length: 732 -************** Percent Wire Length Reduction: -13 - - -Initial Horiz. Wire: 216 Final Horiz. Wire: 147 -$$$$$$$$$$$ Percent H-Wire Length Reduction: 32 - - -Initial Vert. Wire: 429 Final Vert. Wire: 585 -@@@@@@@@@@@ Percent V-Wire Length Reduction: -36 - -Before Feeds are Added: -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 82 -20 - 2 86 -16 - -LONGEST Block is:2 Its length is:86 -BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET - 1 86 -16 - 2 86 -16 - -LONGEST Block is:1 Its length is:86 -Added: 1 feed-through cells - -Removed the cell overlaps --- Will do neighbor interchanges only now - -TOTAL INTERCONNECT LENGTH: 994 -OVERLAP PENALTY: 0 - -initialRowControl: 1.650 -finalRowControl: 0.300 -iter T Wire accept - 122 0.001 976 16% - 123 0.001 971 0% - 124 0.001 971 0% -Total Feed-Alignment Movement (Pass 1): 0 -Total Feed-Alignment Movement (Pass 2): 0 -Total Feed-Alignment Movement (Pass 3): 0 -Total Feed-Alignment Movement (Pass 4): 0 -Total Feed-Alignment Movement (Pass 5): 0 -Total Feed-Alignment Movement (Pass 6): 0 -Total Feed-Alignment Movement (Pass 7): 0 -Total Feed-Alignment Movement (Pass 8): 0 - -The rand generator seed was at globroute() : 987654321 - - -Total Number of Net Segments: 9 -Number of Switchable Net Segments: 0 - -Number of channels: 3 - - - -THIS IS THE ORIGINAL NUMBER OF TRACKS: 5 - - -no. of accepted flips: 0 -no. of attempted flips: 0 -THIS IS THE NUMBER OF TRACKS: 5 - - - -FINAL NUMBER OF ROUTING TRACKS: 5 - -MAX OF CHANNEL: 1 is: 0 -MAX OF CHANNEL: 2 is: 4 -MAX OF CHANNEL: 3 is: 1 -FINAL TOTAL INTERCONNECT LENGTH: 978 -FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978 -MAX NUMBER OF ATTEMPTED FLIPS PER T: 55 - - -cost_scale_factor:3.90616 - -Number of Feed Thrus: 0 -Number of Implicit Feed Thrus: 0 - -Statistics: -Number of Standard Cells: 10 -Number of Pads: 0 -Number of Nets: 15 -Number of Pins: 46 -Usage statistics not available diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin deleted file mode 100644 index 62b922e4e..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pin +++ /dev/null @@ -1,17 +0,0 @@ -$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0 -$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0 -B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0 -B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0 -B7 3 ACOUNT_1 01#Z 17 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0 -B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0 -B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0 -$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0 -$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0 -$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0 -$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 deleted file mode 100644 index bdc569e39..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl1 +++ /dev/null @@ -1,11 +0,0 @@ -$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1 -$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1 -$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1 -ACOUNT_1 14 0 18 26 2 1 -twfeed1 18 0 22 26 0 1 -$COUNT_1/$FJK3_1 22 0 86 26 0 1 -$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2 -$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2 -$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2 -$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2 -$COUNT_1/$FJK3_2 22 52 86 78 0 2 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 deleted file mode 100644 index 6e2601e82..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.pl2 +++ /dev/null @@ -1,2 +0,0 @@ -1 0 0 86 26 0 0 -2 0 52 86 78 0 0 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav deleted file mode 100644 index 04c8e9935..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sav +++ /dev/null @@ -1,18 +0,0 @@ -0.009592 -121 -0 -1 -0.000000 -0.500000 -3.906156 -1 -1 1 2 37 13 -2 2 0 34 65 -3 2 2 63 65 -4 1 0 59 13 -5 1 2 32 13 -6 2 0 23 65 -7 1 2 12 13 -8 2 0 6 65 -9 1 0 70 13 -10 2 0 70 65 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 deleted file mode 100644 index 9dd68ecdb..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.sv2 +++ /dev/null @@ -1,19 +0,0 @@ -0.001000 -123 -0 -2 -0.000000 -0.500000 -3.906156 -1 -1 1 2 16 13 -2 2 2 19 65 -3 2 2 14 65 -4 1 0 11 13 -5 1 2 6 13 -6 2 0 3 65 -7 1 0 2 13 -8 2 2 9 65 -9 1 0 50 13 -10 2 0 54 65 -11 1 0 84 13 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf deleted file mode 100644 index a4c2eac35..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/smred.twf +++ /dev/null @@ -1,29 +0,0 @@ -net 1 -segment channel 2 - pin1 1 pin2 7 0 0 -net 2 -segment channel 3 -pin1 41 pin2 42 0 0 -segment channel 2 -pin1 12 pin2 3 0 0 -net 3 -segment channel 2 -pin1 35 pin2 36 0 0 -segment channel 2 -pin1 19 pin2 35 0 0 -net 4 -segment channel 2 - pin1 5 pin2 38 0 0 -net 5 -net 7 -segment channel 2 - pin1 14 pin2 43 0 0 -net 8 -segment channel 2 - pin1 23 pin2 17 0 0 -net 9 -net 11 -segment channel 2 - pin1 25 pin2 31 0 0 -net 14 -net 15 diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt deleted file mode 100644 index 225096fb5..000000000 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ /dev/null @@ -1,531 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.250992 -sim_ticks 250991873500 -final_tick 250991873500 -sim_freq 1000000000000 -host_inst_rate 493841 -host_op_rate 827723 -host_tick_rate 938509817 -host_mem_usage 310112 -host_seconds 267.44 -sim_insts 132071193 -sim_ops 221363385 -system.voltage_domain.voltage 1 -system.clk_domain.clock 1000 -system.physmem.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.physmem.bytes_read::cpu.inst 181760 -system.physmem.bytes_read::cpu.data 121280 -system.physmem.bytes_read::total 303040 -system.physmem.bytes_inst_read::cpu.inst 181760 -system.physmem.bytes_inst_read::total 181760 -system.physmem.num_reads::cpu.inst 2840 -system.physmem.num_reads::cpu.data 1895 -system.physmem.num_reads::total 4735 -system.physmem.bw_read::cpu.inst 724167 -system.physmem.bw_read::cpu.data 483203 -system.physmem.bw_read::total 1207370 -system.physmem.bw_inst_read::cpu.inst 724167 -system.physmem.bw_inst_read::total 724167 -system.physmem.bw_total::cpu.inst 724167 -system.physmem.bw_total::cpu.data 483203 -system.physmem.bw_total::total 1207370 -system.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu_clk_domain.clock 500 -system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.apic_clk_domain.clock 8000 -system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.workload.numSyscalls 400 -system.cpu.pwrStateResidencyTicks::ON 250991873500 -system.cpu.numCycles 501983747 -system.cpu.numWorkItemsStarted 0 -system.cpu.numWorkItemsCompleted 0 -system.cpu.committedInsts 132071193 -system.cpu.committedOps 221363385 -system.cpu.num_int_alu_accesses 219019986 -system.cpu.num_fp_alu_accesses 2162459 -system.cpu.num_func_calls 1595632 -system.cpu.num_conditional_control_insts 8268466 -system.cpu.num_int_insts 219019986 -system.cpu.num_fp_insts 2162459 -system.cpu.num_int_register_reads 519996939 -system.cpu.num_int_register_writes 201355989 -system.cpu.num_fp_register_reads 3037165 -system.cpu.num_fp_register_writes 1831403 -system.cpu.num_cc_register_reads 96962463 -system.cpu.num_cc_register_writes 56242058 -system.cpu.num_mem_refs 77165304 -system.cpu.num_load_insts 56649587 -system.cpu.num_store_insts 20515717 -system.cpu.num_idle_cycles 0 -system.cpu.num_busy_cycles 501983747 -system.cpu.not_idle_fraction 1 -system.cpu.idle_fraction 0 -system.cpu.Branches 12326938 -system.cpu.op_class::No_OpClass 1176721 0.53% 0.53% -system.cpu.op_class::IntAlu 134111833 60.58% 61.12% -system.cpu.op_class::IntMult 772953 0.35% 61.47% -system.cpu.op_class::IntDiv 7031501 3.18% 64.64% -system.cpu.op_class::FloatAdd 1105073 0.50% 65.14% -system.cpu.op_class::FloatCmp 0 0.00% 65.14% -system.cpu.op_class::FloatCvt 0 0.00% 65.14% -system.cpu.op_class::FloatMult 0 0.00% 65.14% -system.cpu.op_class::FloatMultAcc 0 0.00% 65.14% -system.cpu.op_class::FloatDiv 0 0.00% 65.14% -system.cpu.op_class::FloatMisc 0 0.00% 65.14% -system.cpu.op_class::FloatSqrt 0 0.00% 65.14% -system.cpu.op_class::SimdAdd 0 0.00% 65.14% -system.cpu.op_class::SimdAddAcc 0 0.00% 65.14% -system.cpu.op_class::SimdAlu 0 0.00% 65.14% -system.cpu.op_class::SimdCmp 0 0.00% 65.14% -system.cpu.op_class::SimdCvt 0 0.00% 65.14% -system.cpu.op_class::SimdMisc 0 0.00% 65.14% -system.cpu.op_class::SimdMult 0 0.00% 65.14% -system.cpu.op_class::SimdMultAcc 0 0.00% 65.14% -system.cpu.op_class::SimdShift 0 0.00% 65.14% -system.cpu.op_class::SimdShiftAcc 0 0.00% 65.14% -system.cpu.op_class::SimdSqrt 0 0.00% 65.14% -system.cpu.op_class::SimdFloatAdd 0 0.00% 65.14% -system.cpu.op_class::SimdFloatAlu 0 0.00% 65.14% -system.cpu.op_class::SimdFloatCmp 0 0.00% 65.14% -system.cpu.op_class::SimdFloatCvt 0 0.00% 65.14% -system.cpu.op_class::SimdFloatDiv 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMisc 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMult 0 0.00% 65.14% -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.14% -system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.14% -system.cpu.op_class::MemRead 55945136 25.27% 90.41% -system.cpu.op_class::MemWrite 20410230 9.22% 99.63% -system.cpu.op_class::FloatMemRead 704451 0.32% 99.95% -system.cpu.op_class::FloatMemWrite 105487 0.05% 100.00% -system.cpu.op_class::IprAccess 0 0.00% 100.00% -system.cpu.op_class::InstPrefetch 0 0.00% 100.00% -system.cpu.op_class::total 221363385 -system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.dcache.tags.replacements 41 -system.cpu.dcache.tags.tagsinuse 1363.408611 -system.cpu.dcache.tags.total_refs 77195831 -system.cpu.dcache.tags.sampled_refs 1905 -system.cpu.dcache.tags.avg_refs 40522.745932 -system.cpu.dcache.tags.warmup_cycle 0 -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.408611 -system.cpu.dcache.tags.occ_percent::cpu.data 0.332863 -system.cpu.dcache.tags.occ_percent::total 0.332863 -system.cpu.dcache.tags.occ_task_id_blocks::1024 1864 -system.cpu.dcache.tags.age_task_id_blocks_1024::0 7 -system.cpu.dcache.tags.age_task_id_blocks_1024::1 14 -system.cpu.dcache.tags.age_task_id_blocks_1024::2 43 -system.cpu.dcache.tags.age_task_id_blocks_1024::3 472 -system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 -system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 -system.cpu.dcache.tags.tag_accesses 154397377 -system.cpu.dcache.tags.data_accesses 154397377 -system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.dcache.ReadReq_hits::cpu.data 56681678 -system.cpu.dcache.ReadReq_hits::total 56681678 -system.cpu.dcache.WriteReq_hits::cpu.data 20514153 -system.cpu.dcache.WriteReq_hits::total 20514153 -system.cpu.dcache.demand_hits::cpu.data 77195831 -system.cpu.dcache.demand_hits::total 77195831 -system.cpu.dcache.overall_hits::cpu.data 77195831 -system.cpu.dcache.overall_hits::total 77195831 -system.cpu.dcache.ReadReq_misses::cpu.data 327 -system.cpu.dcache.ReadReq_misses::total 327 -system.cpu.dcache.WriteReq_misses::cpu.data 1578 -system.cpu.dcache.WriteReq_misses::total 1578 -system.cpu.dcache.demand_misses::cpu.data 1905 -system.cpu.dcache.demand_misses::total 1905 -system.cpu.dcache.overall_misses::cpu.data 1905 -system.cpu.dcache.overall_misses::total 1905 -system.cpu.dcache.ReadReq_miss_latency::cpu.data 20253500 -system.cpu.dcache.ReadReq_miss_latency::total 20253500 -system.cpu.dcache.WriteReq_miss_latency::cpu.data 99266000 -system.cpu.dcache.WriteReq_miss_latency::total 99266000 -system.cpu.dcache.demand_miss_latency::cpu.data 119519500 -system.cpu.dcache.demand_miss_latency::total 119519500 -system.cpu.dcache.overall_miss_latency::cpu.data 119519500 -system.cpu.dcache.overall_miss_latency::total 119519500 -system.cpu.dcache.ReadReq_accesses::cpu.data 56682005 -system.cpu.dcache.ReadReq_accesses::total 56682005 -system.cpu.dcache.WriteReq_accesses::cpu.data 20515731 -system.cpu.dcache.WriteReq_accesses::total 20515731 -system.cpu.dcache.demand_accesses::cpu.data 77197736 -system.cpu.dcache.demand_accesses::total 77197736 -system.cpu.dcache.overall_accesses::cpu.data 77197736 -system.cpu.dcache.overall_accesses::total 77197736 -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000006 -system.cpu.dcache.ReadReq_miss_rate::total 0.000006 -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000077 -system.cpu.dcache.WriteReq_miss_rate::total 0.000077 -system.cpu.dcache.demand_miss_rate::cpu.data 0.000025 -system.cpu.dcache.demand_miss_rate::total 0.000025 -system.cpu.dcache.overall_miss_rate::cpu.data 0.000025 -system.cpu.dcache.overall_miss_rate::total 0.000025 -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 61937.308869 -system.cpu.dcache.ReadReq_avg_miss_latency::total 61937.308869 -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62906.210393 -system.cpu.dcache.WriteReq_avg_miss_latency::total 62906.210393 -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62739.895013 -system.cpu.dcache.demand_avg_miss_latency::total 62739.895013 -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62739.895013 -system.cpu.dcache.overall_avg_miss_latency::total 62739.895013 -system.cpu.dcache.blocked_cycles::no_mshrs 0 -system.cpu.dcache.blocked_cycles::no_targets 0 -system.cpu.dcache.blocked::no_mshrs 0 -system.cpu.dcache.blocked::no_targets 0 -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan -system.cpu.dcache.avg_blocked_cycles::no_targets nan -system.cpu.dcache.writebacks::writebacks 7 -system.cpu.dcache.writebacks::total 7 -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 327 -system.cpu.dcache.ReadReq_mshr_misses::total 327 -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1578 -system.cpu.dcache.WriteReq_mshr_misses::total 1578 -system.cpu.dcache.demand_mshr_misses::cpu.data 1905 -system.cpu.dcache.demand_mshr_misses::total 1905 -system.cpu.dcache.overall_mshr_misses::cpu.data 1905 -system.cpu.dcache.overall_mshr_misses::total 1905 -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 19926500 -system.cpu.dcache.ReadReq_mshr_miss_latency::total 19926500 -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 97688000 -system.cpu.dcache.WriteReq_mshr_miss_latency::total 97688000 -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 117614500 -system.cpu.dcache.demand_mshr_miss_latency::total 117614500 -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 117614500 -system.cpu.dcache.overall_mshr_miss_latency::total 117614500 -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000006 -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000006 -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000077 -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000077 -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 -system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 -system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60937.308869 -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60937.308869 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61906.210393 -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61906.210393 -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61739.895013 -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61739.895013 -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61739.895013 -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61739.895013 -system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.icache.tags.replacements 2836 -system.cpu.icache.tags.tagsinuse 1455.237724 -system.cpu.icache.tags.total_refs 173489674 -system.cpu.icache.tags.sampled_refs 4694 -system.cpu.icache.tags.avg_refs 36959.879421 -system.cpu.icache.tags.warmup_cycle 0 -system.cpu.icache.tags.occ_blocks::cpu.inst 1455.237724 -system.cpu.icache.tags.occ_percent::cpu.inst 0.710565 -system.cpu.icache.tags.occ_percent::total 0.710565 -system.cpu.icache.tags.occ_task_id_blocks::1024 1858 -system.cpu.icache.tags.age_task_id_blocks_1024::0 37 -system.cpu.icache.tags.age_task_id_blocks_1024::1 60 -system.cpu.icache.tags.age_task_id_blocks_1024::2 470 -system.cpu.icache.tags.age_task_id_blocks_1024::3 422 -system.cpu.icache.tags.age_task_id_blocks_1024::4 869 -system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 -system.cpu.icache.tags.tag_accesses 346993430 -system.cpu.icache.tags.data_accesses 346993430 -system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.icache.ReadReq_hits::cpu.inst 173489674 -system.cpu.icache.ReadReq_hits::total 173489674 -system.cpu.icache.demand_hits::cpu.inst 173489674 -system.cpu.icache.demand_hits::total 173489674 -system.cpu.icache.overall_hits::cpu.inst 173489674 -system.cpu.icache.overall_hits::total 173489674 -system.cpu.icache.ReadReq_misses::cpu.inst 4694 -system.cpu.icache.ReadReq_misses::total 4694 -system.cpu.icache.demand_misses::cpu.inst 4694 -system.cpu.icache.demand_misses::total 4694 -system.cpu.icache.overall_misses::cpu.inst 4694 -system.cpu.icache.overall_misses::total 4694 -system.cpu.icache.ReadReq_miss_latency::cpu.inst 203072500 -system.cpu.icache.ReadReq_miss_latency::total 203072500 -system.cpu.icache.demand_miss_latency::cpu.inst 203072500 -system.cpu.icache.demand_miss_latency::total 203072500 -system.cpu.icache.overall_miss_latency::cpu.inst 203072500 -system.cpu.icache.overall_miss_latency::total 203072500 -system.cpu.icache.ReadReq_accesses::cpu.inst 173494368 -system.cpu.icache.ReadReq_accesses::total 173494368 -system.cpu.icache.demand_accesses::cpu.inst 173494368 -system.cpu.icache.demand_accesses::total 173494368 -system.cpu.icache.overall_accesses::cpu.inst 173494368 -system.cpu.icache.overall_accesses::total 173494368 -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 -system.cpu.icache.ReadReq_miss_rate::total 0.000027 -system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 -system.cpu.icache.demand_miss_rate::total 0.000027 -system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 -system.cpu.icache.overall_miss_rate::total 0.000027 -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 43262.143161 -system.cpu.icache.ReadReq_avg_miss_latency::total 43262.143161 -system.cpu.icache.demand_avg_miss_latency::cpu.inst 43262.143161 -system.cpu.icache.demand_avg_miss_latency::total 43262.143161 -system.cpu.icache.overall_avg_miss_latency::cpu.inst 43262.143161 -system.cpu.icache.overall_avg_miss_latency::total 43262.143161 -system.cpu.icache.blocked_cycles::no_mshrs 0 -system.cpu.icache.blocked_cycles::no_targets 0 -system.cpu.icache.blocked::no_mshrs 0 -system.cpu.icache.blocked::no_targets 0 -system.cpu.icache.avg_blocked_cycles::no_mshrs nan -system.cpu.icache.avg_blocked_cycles::no_targets nan -system.cpu.icache.writebacks::writebacks 2836 -system.cpu.icache.writebacks::total 2836 -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4694 -system.cpu.icache.ReadReq_mshr_misses::total 4694 -system.cpu.icache.demand_mshr_misses::cpu.inst 4694 -system.cpu.icache.demand_mshr_misses::total 4694 -system.cpu.icache.overall_mshr_misses::cpu.inst 4694 -system.cpu.icache.overall_mshr_misses::total 4694 -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 198378500 -system.cpu.icache.ReadReq_mshr_miss_latency::total 198378500 -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 198378500 -system.cpu.icache.demand_mshr_miss_latency::total 198378500 -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 198378500 -system.cpu.icache.overall_mshr_miss_latency::total 198378500 -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000027 -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000027 -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000027 -system.cpu.icache.demand_mshr_miss_rate::total 0.000027 -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000027 -system.cpu.icache.overall_mshr_miss_rate::total 0.000027 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 42262.143161 -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 42262.143161 -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 42262.143161 -system.cpu.icache.demand_avg_mshr_miss_latency::total 42262.143161 -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 42262.143161 -system.cpu.icache.overall_avg_mshr_miss_latency::total 42262.143161 -system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.l2cache.tags.replacements 0 -system.cpu.l2cache.tags.tagsinuse 3195.628328 -system.cpu.l2cache.tags.total_refs 4741 -system.cpu.l2cache.tags.sampled_refs 4735 -system.cpu.l2cache.tags.avg_refs 1.001267 -system.cpu.l2cache.tags.warmup_cycle 0 -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1829.901516 -system.cpu.l2cache.tags.occ_blocks::cpu.data 1365.726812 -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055844 -system.cpu.l2cache.tags.occ_percent::cpu.data 0.041679 -system.cpu.l2cache.tags.occ_percent::total 0.097523 -system.cpu.l2cache.tags.occ_task_id_blocks::1024 4735 -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 37 -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 39 -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 512 -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 947 -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3200 -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.144501 -system.cpu.l2cache.tags.tag_accesses 80543 -system.cpu.l2cache.tags.data_accesses 80543 -system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.l2cache.WritebackDirty_hits::writebacks 7 -system.cpu.l2cache.WritebackDirty_hits::total 7 -system.cpu.l2cache.WritebackClean_hits::writebacks 2836 -system.cpu.l2cache.WritebackClean_hits::total 2836 -system.cpu.l2cache.ReadExReq_hits::cpu.data 3 -system.cpu.l2cache.ReadExReq_hits::total 3 -system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1854 -system.cpu.l2cache.ReadCleanReq_hits::total 1854 -system.cpu.l2cache.ReadSharedReq_hits::cpu.data 7 -system.cpu.l2cache.ReadSharedReq_hits::total 7 -system.cpu.l2cache.demand_hits::cpu.inst 1854 -system.cpu.l2cache.demand_hits::cpu.data 10 -system.cpu.l2cache.demand_hits::total 1864 -system.cpu.l2cache.overall_hits::cpu.inst 1854 -system.cpu.l2cache.overall_hits::cpu.data 10 -system.cpu.l2cache.overall_hits::total 1864 -system.cpu.l2cache.ReadExReq_misses::cpu.data 1575 -system.cpu.l2cache.ReadExReq_misses::total 1575 -system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2840 -system.cpu.l2cache.ReadCleanReq_misses::total 2840 -system.cpu.l2cache.ReadSharedReq_misses::cpu.data 320 -system.cpu.l2cache.ReadSharedReq_misses::total 320 -system.cpu.l2cache.demand_misses::cpu.inst 2840 -system.cpu.l2cache.demand_misses::cpu.data 1895 -system.cpu.l2cache.demand_misses::total 4735 -system.cpu.l2cache.overall_misses::cpu.inst 2840 -system.cpu.l2cache.overall_misses::cpu.data 1895 -system.cpu.l2cache.overall_misses::total 4735 -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95288500 -system.cpu.l2cache.ReadExReq_miss_latency::total 95288500 -system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 171853000 -system.cpu.l2cache.ReadCleanReq_miss_latency::total 171853000 -system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 19362000 -system.cpu.l2cache.ReadSharedReq_miss_latency::total 19362000 -system.cpu.l2cache.demand_miss_latency::cpu.inst 171853000 -system.cpu.l2cache.demand_miss_latency::cpu.data 114650500 -system.cpu.l2cache.demand_miss_latency::total 286503500 -system.cpu.l2cache.overall_miss_latency::cpu.inst 171853000 -system.cpu.l2cache.overall_miss_latency::cpu.data 114650500 -system.cpu.l2cache.overall_miss_latency::total 286503500 -system.cpu.l2cache.WritebackDirty_accesses::writebacks 7 -system.cpu.l2cache.WritebackDirty_accesses::total 7 -system.cpu.l2cache.WritebackClean_accesses::writebacks 2836 -system.cpu.l2cache.WritebackClean_accesses::total 2836 -system.cpu.l2cache.ReadExReq_accesses::cpu.data 1578 -system.cpu.l2cache.ReadExReq_accesses::total 1578 -system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 4694 -system.cpu.l2cache.ReadCleanReq_accesses::total 4694 -system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 327 -system.cpu.l2cache.ReadSharedReq_accesses::total 327 -system.cpu.l2cache.demand_accesses::cpu.inst 4694 -system.cpu.l2cache.demand_accesses::cpu.data 1905 -system.cpu.l2cache.demand_accesses::total 6599 -system.cpu.l2cache.overall_accesses::cpu.inst 4694 -system.cpu.l2cache.overall_accesses::cpu.data 1905 -system.cpu.l2cache.overall_accesses::total 6599 -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 -system.cpu.l2cache.ReadExReq_miss_rate::total 0.998099 -system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.605028 -system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.978593 -system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.978593 -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 -system.cpu.l2cache.demand_miss_rate::total 0.717533 -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 -system.cpu.l2cache.overall_miss_rate::total 0.717533 -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500.634921 -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500.634921 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60511.619718 -system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60511.619718 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60506.250000 -system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60506.250000 -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60511.619718 -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60501.583113 -system.cpu.l2cache.demand_avg_miss_latency::total 60507.602957 -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60511.619718 -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60501.583113 -system.cpu.l2cache.overall_avg_miss_latency::total 60507.602957 -system.cpu.l2cache.blocked_cycles::no_mshrs 0 -system.cpu.l2cache.blocked_cycles::no_targets 0 -system.cpu.l2cache.blocked::no_mshrs 0 -system.cpu.l2cache.blocked::no_targets 0 -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan -system.cpu.l2cache.avg_blocked_cycles::no_targets nan -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 -system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 -system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2840 -system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2840 -system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 320 -system.cpu.l2cache.ReadSharedReq_mshr_misses::total 320 -system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 -system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 -system.cpu.l2cache.demand_mshr_misses::total 4735 -system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 -system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 -system.cpu.l2cache.overall_mshr_misses::total 4735 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 79538500 -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 79538500 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 143453000 -system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 143453000 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16162000 -system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16162000 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143453000 -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 95700500 -system.cpu.l2cache.demand_mshr_miss_latency::total 239153500 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143453000 -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 95700500 -system.cpu.l2cache.overall_mshr_miss_latency::total 239153500 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.998099 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.605028 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.978593 -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.978593 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 -system.cpu.l2cache.demand_mshr_miss_rate::total 0.717533 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 -system.cpu.l2cache.overall_mshr_miss_rate::total 0.717533 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500.634921 -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500.634921 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50511.619718 -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50511.619718 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50506.250000 -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50506.250000 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50511.619718 -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50501.583113 -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50507.602957 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50511.619718 -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50501.583113 -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50507.602957 -system.cpu.toL2Bus.snoop_filter.tot_requests 9476 -system.cpu.toL2Bus.snoop_filter.hit_single_requests 2878 -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 -system.cpu.toL2Bus.snoop_filter.tot_snoops 0 -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 -system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 -system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.cpu.toL2Bus.trans_dist::ReadResp 5021 -system.cpu.toL2Bus.trans_dist::WritebackDirty 7 -system.cpu.toL2Bus.trans_dist::WritebackClean 2836 -system.cpu.toL2Bus.trans_dist::CleanEvict 34 -system.cpu.toL2Bus.trans_dist::ReadExReq 1578 -system.cpu.toL2Bus.trans_dist::ReadExResp 1578 -system.cpu.toL2Bus.trans_dist::ReadCleanReq 4694 -system.cpu.toL2Bus.trans_dist::ReadSharedReq 327 -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 12224 -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3851 -system.cpu.toL2Bus.pkt_count::total 16075 -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 481920 -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 122368 -system.cpu.toL2Bus.pkt_size::total 604288 -system.cpu.toL2Bus.snoops 0 -system.cpu.toL2Bus.snoopTraffic 0 -system.cpu.toL2Bus.snoop_fanout::samples 6599 -system.cpu.toL2Bus.snoop_fanout::mean 0.000152 -system.cpu.toL2Bus.snoop_fanout::stdev 0.012310 -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% -system.cpu.toL2Bus.snoop_fanout::0 6598 99.98% 99.98% -system.cpu.toL2Bus.snoop_fanout::1 1 0.02% 100.00% -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% -system.cpu.toL2Bus.snoop_fanout::min_value 0 -system.cpu.toL2Bus.snoop_fanout::max_value 1 -system.cpu.toL2Bus.snoop_fanout::total 6599 -system.cpu.toL2Bus.reqLayer0.occupancy 7581000 -system.cpu.toL2Bus.reqLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer0.occupancy 7041000 -system.cpu.toL2Bus.respLayer0.utilization 0.0 -system.cpu.toL2Bus.respLayer1.occupancy 2857500 -system.cpu.toL2Bus.respLayer1.utilization 0.0 -system.membus.snoop_filter.tot_requests 4735 -system.membus.snoop_filter.hit_single_requests 0 -system.membus.snoop_filter.hit_multi_requests 0 -system.membus.snoop_filter.tot_snoops 0 -system.membus.snoop_filter.hit_single_snoops 0 -system.membus.snoop_filter.hit_multi_snoops 0 -system.membus.pwrStateResidencyTicks::UNDEFINED 250991873500 -system.membus.trans_dist::ReadResp 3160 -system.membus.trans_dist::ReadExReq 1575 -system.membus.trans_dist::ReadExResp 1575 -system.membus.trans_dist::ReadSharedReq 3160 -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9470 -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 9470 -system.membus.pkt_count::total 9470 -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 303040 -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 303040 -system.membus.pkt_size::total 303040 -system.membus.snoops 0 -system.membus.snoopTraffic 0 -system.membus.snoop_fanout::samples 4735 -system.membus.snoop_fanout::mean 0 -system.membus.snoop_fanout::stdev 0 -system.membus.snoop_fanout::underflows 0 0.00% 0.00% -system.membus.snoop_fanout::0 4735 100.00% 100.00% -system.membus.snoop_fanout::1 0 0.00% 100.00% -system.membus.snoop_fanout::overflows 0 0.00% 100.00% -system.membus.snoop_fanout::min_value 0 -system.membus.snoop_fanout::max_value 0 -system.membus.snoop_fanout::total 4735 -system.membus.reqLayer0.occupancy 4771000 -system.membus.reqLayer0.utilization 0.0 -system.membus.respLayer1.occupancy 23675000 -system.membus.respLayer1.utilization 0.0 - ----------- End Simulation Statistics ---------- |