diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-06 17:16:44 +0100 |
| commit | 85997e66a08b71d701e5b41462d1cfd42660b0c7 (patch) | |
| tree | bc242f1a2bfc3a92b18da04805d9ebd8864b5320 /tests/quick/se/70.twolf | |
| parent | 21b66f45422bc449d4a8b86ab452d6b6ae5838bf (diff) | |
| download | gem5-85997e66a08b71d701e5b41462d1cfd42660b0c7.tar.xz | |
stats: Add power stats to test references
Change-Id: Ic827213134b199446822f128b81d4a480e777fee
Diffstat (limited to 'tests/quick/se/70.twolf')
8 files changed, 114 insertions, 40 deletions
diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt index 185d54bdc..ba862710c 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.045952 # Nu sim_ticks 45951567500 # Number of ticks simulated final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1593313 # Simulator instruction rate (inst/s) -host_op_rate 1593310 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 796655733 # Simulator tick rate (ticks/s) -host_mem_usage 242160 # Number of bytes of host memory used -host_seconds 57.68 # Real time elapsed on the host +host_inst_rate 3168591 # Simulator instruction rate (inst/s) +host_op_rate 3168590 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1584296087 # Simulator tick rate (ticks/s) +host_mem_usage 288936 # Number of bytes of host memory used +host_seconds 29.00 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 367612356 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 108337521 # Number of bytes read from this memory system.physmem.bytes_read::total 475949877 # Number of bytes read from this memory @@ -35,6 +36,7 @@ system.physmem.bw_write::total 672903574 # Wr system.physmem.bw_total::cpu.inst 7999995996 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3030549393 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11030545389 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -69,6 +71,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 45951567500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -127,6 +130,7 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 45951567500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 111899287 # Transaction distribution system.membus.trans_dist::ReadResp 111899287 # Transaction distribution system.membus.trans_dist::WriteReq 6501103 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt index 356207999..12386b790 100644 --- a/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.118763 # Nu sim_ticks 118762761500 # Number of ticks simulated final_tick 118762761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 940295 # Simulator instruction rate (inst/s) -host_op_rate 940295 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1215106876 # Simulator tick rate (ticks/s) -host_mem_usage 251128 # Number of bytes of host memory used -host_seconds 97.74 # Real time elapsed on the host +host_inst_rate 1861883 # Simulator instruction rate (inst/s) +host_op_rate 1861883 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2406038400 # Simulator tick rate (ticks/s) +host_mem_usage 298932 # Number of bytes of host memory used +host_seconds 49.36 # Real time elapsed on the host sim_insts 91903056 # Number of instructions simulated sim_ops 91903056 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 167744 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory system.physmem.bytes_read::total 304960 # Number of bytes read from this memory @@ -29,6 +30,7 @@ system.physmem.bw_inst_read::total 1412429 # In system.physmem.bw_total::cpu.inst 1412429 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1155379 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 2567808 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses @@ -63,6 +65,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 389 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 118762761500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 237525523 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -121,6 +124,7 @@ system.cpu.op_class::MemWrite 6501126 7.07% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 91903089 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 157 # number of replacements system.cpu.dcache.tags.tagsinuse 1441.946319 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26495078 # Total number of references to valid blocks. @@ -139,6 +143,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 19995723 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 19995723 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 6499355 # number of WriteReq hits @@ -227,6 +232,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59260.683761 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59260.683761 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59260.683761 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 6681 # number of replacements system.cpu.icache.tags.tagsinuse 1417.953327 # Cycle average of tags in use system.cpu.icache.tags.total_refs 91894580 # Total number of references to valid blocks. @@ -245,6 +251,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 953 system.cpu.icache.tags.occ_task_id_percent::1024 0.893066 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 183814690 # Number of tag accesses system.cpu.icache.tags.data_accesses 183814690 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits @@ -313,6 +320,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 27101.645123 system.cpu.icache.demand_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 27101.645123 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 27101.645123 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2073.923151 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 12687 # Total number of references to valid blocks. @@ -335,6 +343,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2096 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.094879 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 145425 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 145425 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 107 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 6681 # number of WritebackClean hits @@ -475,6 +484,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 8985 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 107 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 6681 # Transaction distribution @@ -507,6 +517,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 12765000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 3334500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 118762761500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3043 # Transaction distribution system.membus.trans_dist::ReadExReq 1722 # Transaction distribution system.membus.trans_dist::ReadExResp 1722 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index 5f1cdd65c..a504e35f9 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.099596 # Nu sim_ticks 99596491500 # Number of ticks simulated final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2176341 # Simulator instruction rate (inst/s) -host_op_rate 2294214 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1257887009 # Simulator tick rate (ticks/s) -host_mem_usage 304976 # Number of bytes of host memory used -host_seconds 79.18 # Real time elapsed on the host +host_inst_rate 2111044 # Simulator instruction rate (inst/s) +host_op_rate 2225381 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1220146763 # Simulator tick rate (ticks/s) +host_mem_usage 306656 # Number of bytes of host memory used +host_seconds 81.63 # Real time elapsed on the host sim_insts 172317410 # Number of instructions simulated sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory @@ -35,7 +36,9 @@ system.physmem.bw_write::total 454362792 # Wr system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -65,6 +68,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -94,6 +98,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -123,6 +128,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -153,6 +159,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 99596491500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 199192984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -213,6 +220,7 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 99596491500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 217614903 # Transaction distribution system.membus.trans_dist::ReadResp 217637310 # Transaction distribution system.membus.trans_dist::WriteReq 12364287 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 84721fe7c..f6691b610 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.230198 # Nu sim_ticks 230197694500 # Number of ticks simulated final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1495549 # Simulator instruction rate (inst/s) -host_op_rate 1576687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2003415873 # Simulator tick rate (ticks/s) -host_mem_usage 314964 # Number of bytes of host memory used -host_seconds 114.90 # Real time elapsed on the host +host_inst_rate 1499491 # Simulator instruction rate (inst/s) +host_op_rate 1580842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2008696236 # Simulator tick rate (ticks/s) +host_mem_usage 315632 # Number of bytes of host memory used +host_seconds 114.60 # Real time elapsed on the host sim_insts 171842484 # Number of instructions simulated sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory system.physmem.bytes_read::total 220992 # Number of bytes read from this memory @@ -29,7 +30,9 @@ system.physmem.bw_inst_read::total 480700 # In system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -59,6 +62,7 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -88,6 +92,7 @@ system.cpu.dtb.inst_accesses 0 # IT system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -117,6 +122,7 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -147,6 +153,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 460395389 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -207,6 +214,7 @@ system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 181650743 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 40 # number of replacements system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. @@ -225,6 +233,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits @@ -337,6 +346,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 1506 # number of replacements system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. @@ -355,6 +365,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 942 system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits @@ -423,6 +434,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. @@ -445,6 +457,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits @@ -585,6 +598,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution @@ -617,6 +631,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 4576500 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 2361 # Transaction distribution system.membus.trans_dist::ReadExReq 1092 # Transaction distribution system.membus.trans_dist::ReadExResp 1092 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt index 4c392ae66..00d6259ce 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.096723 # Nu sim_ticks 96722945000 # Number of ticks simulated final_tick 96722945000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1393535 # Simulator instruction rate (inst/s) -host_op_rate 1393537 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 696772335 # Simulator tick rate (ticks/s) -host_mem_usage 242012 # Number of bytes of host memory used -host_seconds 138.82 # Real time elapsed on the host +host_inst_rate 2890225 # Simulator instruction rate (inst/s) +host_op_rate 2890229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1445122551 # Simulator tick rate (ticks/s) +host_mem_usage 288744 # Number of bytes of host memory used +host_seconds 66.93 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 773782140 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 223463413 # Number of bytes read from this memory system.physmem.bytes_read::total 997245553 # Number of bytes read from this memory @@ -37,8 +38,10 @@ system.physmem.bw_write::total 745070490 # Wr system.physmem.bw_total::cpu.inst 7999985319 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3055415910 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 11055401229 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 96722945000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 193445891 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -97,6 +100,7 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 96722945000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 251180603 # Transaction distribution system.membus.trans_dist::ReadResp 251180603 # Transaction distribution system.membus.trans_dist::WriteReq 18976439 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt index 812685f18..a32bf8738 100644 --- a/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.270600 # Nu sim_ticks 270599529500 # Number of ticks simulated final_tick 270599529500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 833752 # Simulator instruction rate (inst/s) -host_op_rate 833752 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1166291607 # Simulator tick rate (ticks/s) -host_mem_usage 251752 # Number of bytes of host memory used -host_seconds 232.02 # Real time elapsed on the host +host_inst_rate 1741327 # Simulator instruction rate (inst/s) +host_op_rate 1741329 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2435851420 # Simulator tick rate (ticks/s) +host_mem_usage 298736 # Number of bytes of host memory used +host_seconds 111.09 # Real time elapsed on the host sim_insts 193444518 # Number of instructions simulated sim_ops 193444756 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 230208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 100864 # Number of bytes read from this memory system.physmem.bytes_read::total 331072 # Number of bytes read from this memory @@ -29,8 +30,10 @@ system.physmem.bw_inst_read::total 850733 # In system.physmem.bw_total::cpu.inst 850733 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 372743 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1223476 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.workload.num_syscalls 401 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 270599529500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 541199059 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -89,6 +92,7 @@ system.cpu.op_class::MemWrite 18998867 9.82% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 193445773 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 2 # number of replacements system.cpu.dcache.tags.tagsinuse 1237.159344 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 76732337 # Total number of references to valid blocks. @@ -107,6 +111,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1237 system.cpu.dcache.tags.occ_task_id_percent::1024 0.384277 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 153469402 # Number of tag accesses system.cpu.dcache.tags.data_accesses 153469402 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 57734570 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 57734570 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 18975362 # number of WriteReq hits @@ -215,6 +220,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61001.587302 system.cpu.dcache.demand_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61001.587302 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 61001.587302 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 10362 # number of replacements system.cpu.icache.tags.tagsinuse 1591.528232 # Cycle average of tags in use system.cpu.icache.tags.total_refs 193433248 # Total number of references to valid blocks. @@ -233,6 +239,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 687 system.cpu.icache.tags.occ_task_id_percent::1024 0.940430 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 386903360 # Number of tag accesses system.cpu.icache.tags.data_accesses 386903360 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 193433248 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 193433248 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 193433248 # number of demand (read+write) hits @@ -301,6 +308,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 26362.548828 system.cpu.icache.demand_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 26362.548828 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 26362.548828 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2678.246108 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 19053 # Total number of references to valid blocks. @@ -323,6 +331,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2688 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.125031 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 198999 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 198999 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 2 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 10362 # number of WritebackClean hits @@ -457,6 +466,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 12786 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 2 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 10362 # Transaction distribution @@ -488,6 +498,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 18432000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2364000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 270599529500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 4095 # Transaction distribution system.membus.trans_dist::ReadExReq 1078 # Transaction distribution system.membus.trans_dist::ReadExResp 1078 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt index a92d8585c..044a8cac9 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.131393 # Nu sim_ticks 131393279000 # Number of ticks simulated final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 719836 # Simulator instruction rate (inst/s) -host_op_rate 1206511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 716141111 # Simulator tick rate (ticks/s) -host_mem_usage 284280 # Number of bytes of host memory used -host_seconds 183.47 # Real time elapsed on the host +host_inst_rate 1595970 # Simulator instruction rate (inst/s) +host_op_rate 2674991 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1587777431 # Simulator tick rate (ticks/s) +host_mem_usage 331680 # Number of bytes of host memory used +host_seconds 82.75 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 1387954936 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 310423752 # Number of bytes read from this memory system.physmem.bytes_read::total 1698378688 # Number of bytes read from this memory @@ -35,9 +36,14 @@ system.physmem.bw_write::total 759720678 # Wr system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 131393279000 # Cumulative time (in ticks) in various power states system.cpu.numCycles 262786559 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -98,6 +104,7 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.membus.pwrStateResidencyTicks::UNDEFINED 131393279000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 230176372 # Transaction distribution system.membus.trans_dist::ReadResp 230176372 # Transaction distribution system.membus.trans_dist::WriteReq 20515731 # Transaction distribution diff --git a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt index cbc3cc2d9..42017c57f 100644 --- a/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/x86/linux/simple-timing/stats.txt @@ -4,15 +4,16 @@ sim_seconds 0.250987 # Nu sim_ticks 250987138500 # Number of ticks simulated final_tick 250987138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 489633 # Simulator instruction rate (inst/s) -host_op_rate 820669 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 930494730 # Simulator tick rate (ticks/s) -host_mem_usage 293244 # Number of bytes of host memory used -host_seconds 269.74 # Real time elapsed on the host +host_inst_rate 1028477 # Simulator instruction rate (inst/s) +host_op_rate 1723822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1954510825 # Simulator tick rate (ticks/s) +host_mem_usage 341680 # Number of bytes of host memory used +host_seconds 128.41 # Real time elapsed on the host sim_insts 132071193 # Number of instructions simulated sim_ops 221363385 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks +system.physmem.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.physmem.bytes_read::cpu.inst 181760 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 121280 # Number of bytes read from this memory system.physmem.bytes_read::total 303040 # Number of bytes read from this memory @@ -29,9 +30,14 @@ system.physmem.bw_inst_read::total 724181 # In system.physmem.bw_total::cpu.inst 724181 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 483212 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 1207393 # Total bandwidth to/from this memory (bytes/s) +system.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu.interrupts.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states +system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.workload.num_syscalls 400 # Number of system calls +system.cpu.pwrStateResidencyTicks::ON 250987138500 # Cumulative time (in ticks) in various power states system.cpu.numCycles 501974277 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed @@ -92,6 +98,7 @@ system.cpu.op_class::MemWrite 20515717 9.27% 100.00% # Cl system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 221363385 # Class of executed instruction +system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.replacements 41 # number of replacements system.cpu.dcache.tags.tagsinuse 1363.414730 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 77195831 # Total number of references to valid blocks. @@ -110,6 +117,7 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::4 1328 system.cpu.dcache.tags.occ_task_id_percent::1024 0.455078 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 154397377 # Number of tag accesses system.cpu.dcache.tags.data_accesses 154397377 # Number of data accesses +system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.dcache.ReadReq_hits::cpu.data 56681678 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 56681678 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 20514153 # number of WriteReq hits @@ -198,6 +206,7 @@ system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60745.144357 system.cpu.dcache.demand_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60745.144357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 60745.144357 # average overall mshr miss latency +system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.replacements 2836 # number of replacements system.cpu.icache.tags.tagsinuse 1455.245085 # Cycle average of tags in use system.cpu.icache.tags.total_refs 173489673 # Total number of references to valid blocks. @@ -216,6 +225,7 @@ system.cpu.icache.tags.age_task_id_blocks_1024::4 869 system.cpu.icache.tags.occ_task_id_percent::1024 0.907227 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 346993428 # Number of tag accesses system.cpu.icache.tags.data_accesses 346993428 # Number of data accesses +system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.icache.ReadReq_hits::cpu.inst 173489673 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 173489673 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 173489673 # number of demand (read+write) hits @@ -284,6 +294,7 @@ system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 41657.115467 system.cpu.icache.demand_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 41657.115467 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 41657.115467 # average overall mshr miss latency +system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.tags.replacements 0 # number of replacements system.cpu.l2cache.tags.tagsinuse 2058.105553 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 4732 # Total number of references to valid blocks. @@ -306,6 +317,7 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2064 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.096558 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 80550 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 80550 # Number of data accesses +system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.l2cache.WritebackDirty_hits::writebacks 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackDirty_hits::total 7 # number of WritebackDirty hits system.cpu.l2cache.WritebackClean_hits::writebacks 2836 # number of WritebackClean hits @@ -446,6 +458,7 @@ system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.cpu.toL2Bus.trans_dist::ReadResp 5021 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackDirty 7 # Transaction distribution system.cpu.toL2Bus.trans_dist::WritebackClean 2836 # Transaction distribution @@ -478,6 +491,7 @@ system.cpu.toL2Bus.respLayer0.occupancy 7041000 # La system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 2857500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.membus.pwrStateResidencyTicks::UNDEFINED 250987138500 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 3160 # Transaction distribution system.membus.trans_dist::ReadExReq 1575 # Transaction distribution system.membus.trans_dist::ReadExResp 1575 # Transaction distribution |