diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2012-06-29 11:19:03 -0400 |
| commit | 3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0 (patch) | |
| tree | 63ce098bc690eb5b58b3297b747794d623cface4 /tests/quick/se | |
| parent | af2b14a362281f36347728e13dcd6b2c4d3c4991 (diff) | |
| download | gem5-3965ecc36b3d928cf8f6a66e50eed3c6de1a54c0.tar.xz | |
Stats: Update stats for RAS and LRU fixes.
Diffstat (limited to 'tests/quick/se')
31 files changed, 8170 insertions, 8210 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index bcee17b83..da5dd186c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:03:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:21 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 12450500 because target called exit() +Exiting @ tick 12146500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index e9f17ec08..40a9fef11 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12450500 # Number of ticks simulated -final_tick 12450500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 12146500 # Number of ticks simulated +final_tick 12146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 73568 # Simulator instruction rate (inst/s) -host_op_rate 73552 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 143373020 # Simulator tick rate (ticks/s) -host_mem_usage 215332 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 109785 # Simulator instruction rate (inst/s) +host_op_rate 109750 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 208686624 # Simulator tick rate (ticks/s) +host_mem_usage 218220 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 6386 # Number of instructions simulated sim_ops 6386 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 20096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 11264 # Number of bytes read from this memory -system.physmem.bytes_read::total 31360 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 314 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 31232 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 19968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 19968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 176 # Number of read requests responded to by this memory -system.physmem.num_reads::total 490 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1614071724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 904702622 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2518774346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1614071724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1614071724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 904702622 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2518774346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 488 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1643930350 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 927345326 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2571275676 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1643930350 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1643930350 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 927345326 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2571275676 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1943 # DTB read hits -system.cpu.dtb.read_misses 53 # DTB read misses +system.cpu.dtb.read_hits 1978 # DTB read hits +system.cpu.dtb.read_misses 49 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1996 # DTB read accesses -system.cpu.dtb.write_hits 1071 # DTB write hits -system.cpu.dtb.write_misses 32 # DTB write misses +system.cpu.dtb.read_accesses 2027 # DTB read accesses +system.cpu.dtb.write_hits 1059 # DTB write hits +system.cpu.dtb.write_misses 31 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1103 # DTB write accesses -system.cpu.dtb.data_hits 3014 # DTB hits -system.cpu.dtb.data_misses 85 # DTB misses +system.cpu.dtb.write_accesses 1090 # DTB write accesses +system.cpu.dtb.data_hits 3037 # DTB hits +system.cpu.dtb.data_misses 80 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3099 # DTB accesses -system.cpu.itb.fetch_hits 2367 # ITB hits -system.cpu.itb.fetch_misses 26 # ITB misses +system.cpu.dtb.data_accesses 3117 # DTB accesses +system.cpu.itb.fetch_hits 2279 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2393 # ITB accesses +system.cpu.itb.fetch_accesses 2309 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 24902 # number of cpu cycles simulated +system.cpu.numCycles 24294 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2873 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1642 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 561 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2186 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 748 # Number of BTB hits +system.cpu.BPredUnit.lookups 2808 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1620 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 530 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2127 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 736 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 430 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 100 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7799 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 16643 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2873 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1178 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2979 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1864 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 854 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 590 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2367 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 368 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.232358 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.611762 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 421 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7536 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16063 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2808 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1157 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2867 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1787 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 912 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 23 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 639 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2279 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 349 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.217632 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.600569 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10526 77.94% 77.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 289 2.14% 80.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 251 1.86% 81.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 257 1.90% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 272 2.01% 85.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 206 1.53% 87.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 248 1.84% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 173 1.28% 90.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1283 9.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10325 78.27% 78.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 292 2.21% 80.48% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 224 1.70% 82.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.71% 83.88% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 268 2.03% 85.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 190 1.44% 87.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 268 2.03% 89.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 182 1.38% 90.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1218 9.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13505 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.115372 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.668340 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8546 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 938 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2784 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 62 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1175 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 292 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 96 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15310 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 265 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1175 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8782 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 334 # Number of cycles rename is blocking +system.cpu.fetch.rateDist::total 13192 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.115584 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.661192 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8379 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 934 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2684 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 63 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1132 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 256 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14824 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 236 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1132 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8584 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 335 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 357 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2587 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 270 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14488 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 212 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10864 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18125 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18108 # Number of integer rename lookups +system.cpu.rename.RunCycles 2519 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 265 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14111 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 206 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 17651 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 17634 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4583 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6281 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 777 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1352 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 6007 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 33 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 768 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2619 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1317 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12765 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 26 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10522 # Number of instructions issued +system.cpu.iq.iqInstsAdded 12558 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10419 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 44 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6026 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3602 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13505 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.779119 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.404443 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 5861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13192 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.789797 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.411802 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9165 67.86% 67.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1484 10.99% 78.85% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1164 8.62% 87.47% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 762 5.64% 93.11% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 469 3.47% 96.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 274 2.03% 98.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 142 1.05% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.25% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 11 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8893 67.41% 67.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1482 11.23% 78.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1143 8.66% 87.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 751 5.69% 93.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 453 3.43% 96.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 282 2.14% 98.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.13% 99.70% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 30 0.23% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 9 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13505 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13192 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 10 8.93% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 58.04% 66.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 37 33.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 7.41% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.41% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 64 59.26% 66.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 36 33.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7148 67.93% 67.95% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.96% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2225 21.15% 89.13% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1144 10.87% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7046 67.63% 67.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.67% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2237 21.47% 89.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1131 10.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10522 # Type of FU issued -system.cpu.iq.rate 0.422536 # Inst issue rate -system.cpu.iq.fu_busy_cnt 112 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010644 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34684 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18825 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9477 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10419 # Type of FU issued +system.cpu.iq.rate 0.428871 # Inst issue rate +system.cpu.iq.fu_busy_cnt 108 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010366 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 34161 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 18458 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9433 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10621 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10514 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 63 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1431 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1434 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 487 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 452 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1175 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1132 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 41 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12870 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 183 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2616 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1352 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 177 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2619 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1317 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 166 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 401 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 567 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9878 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 644 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 137 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 530 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 9845 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2040 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 574 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 79 # number of nop insts executed -system.cpu.iew.exec_refs 3117 # number of memory reference insts executed -system.cpu.iew.exec_branches 1605 # Number of branches executed -system.cpu.iew.exec_stores 1108 # Number of stores executed -system.cpu.iew.exec_rate 0.396675 # Inst execution rate -system.cpu.iew.wb_sent 9634 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9487 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4957 # num instructions producing a value -system.cpu.iew.wb_consumers 6732 # num instructions consuming a value +system.cpu.iew.exec_nop 83 # number of nop insts executed +system.cpu.iew.exec_refs 3133 # number of memory reference insts executed +system.cpu.iew.exec_branches 1595 # Number of branches executed +system.cpu.iew.exec_stores 1093 # Number of stores executed +system.cpu.iew.exec_rate 0.405244 # Inst execution rate +system.cpu.iew.wb_sent 9591 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9443 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4951 # num instructions producing a value +system.cpu.iew.wb_consumers 6720 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.380973 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.736334 # average fanout of values written-back +system.cpu.iew.wb_rate 0.388697 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.736756 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6436 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6261 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 475 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12330 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519303 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.354208 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 447 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12060 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.530929 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.361741 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9591 77.79% 77.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1448 11.74% 89.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 489 3.97% 93.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 259 2.10% 95.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 152 1.23% 96.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 96 0.78% 97.61% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 104 0.84% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 40 0.32% 98.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 151 1.22% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9314 77.23% 77.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1447 12.00% 89.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 498 4.13% 93.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 2.09% 95.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 164 1.36% 96.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.77% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 106 0.88% 98.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 41 0.34% 98.80% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 145 1.20% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12330 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12060 # Number of insts commited each cycle system.cpu.commit.committedInsts 6403 # Number of instructions committed system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,70 +310,70 @@ system.cpu.commit.branches 1051 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6321 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 151 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24667 # The number of ROB reads -system.cpu.rob.rob_writes 26868 # The number of ROB writes -system.cpu.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11397 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 24228 # The number of ROB reads +system.cpu.rob.rob_writes 26471 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11102 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6386 # Number of Instructions Simulated system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6386 # Number of Instructions Simulated -system.cpu.cpi 3.899468 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.899468 # CPI: Total CPI of All Threads -system.cpu.ipc 0.256445 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.256445 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12526 # number of integer regfile reads -system.cpu.int_regfile_writes 7116 # number of integer regfile writes +system.cpu.cpi 3.804259 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.804259 # CPI: Total CPI of All Threads +system.cpu.ipc 0.262863 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.262863 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12506 # number of integer regfile reads +system.cpu.int_regfile_writes 7104 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 162.256588 # Cycle average of tags in use -system.cpu.icache.total_refs 1909 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 315 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.060317 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 161.646618 # Cycle average of tags in use +system.cpu.icache.total_refs 1829 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.843450 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.256588 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079227 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079227 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits -system.cpu.icache.overall_hits::total 1909 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses -system.cpu.icache.overall_misses::total 458 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16026500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16026500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16026500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16026500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16026500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2367 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2367 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2367 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2367 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2367 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.193494 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.193494 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.193494 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.193494 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.193494 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34992.358079 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34992.358079 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34992.358079 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34992.358079 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 161.646618 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078929 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078929 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1829 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1829 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1829 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1829 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1829 # number of overall hits +system.cpu.icache.overall_hits::total 1829 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 450 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 450 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 450 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 450 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 450 # number of overall misses +system.cpu.icache.overall_misses::total 450 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15742000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15742000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15742000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15742000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15742000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2279 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2279 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2279 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2279 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2279 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.197455 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.197455 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.197455 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.197455 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.197455 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34982.222222 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34982.222222 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34982.222222 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34982.222222 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -382,94 +382,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 143 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 143 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 143 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 143 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 143 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 143 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 315 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11133500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11133500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11133500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11133500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133080 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.133080 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.133080 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35344.444444 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35344.444444 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35344.444444 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 137 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 137 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 137 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 137 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 137 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 137 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 313 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11060000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11060000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11060000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11060000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.137341 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.137341 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.137341 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35335.463259 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35335.463259 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35335.463259 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 109.847039 # Cycle average of tags in use -system.cpu.dcache.total_refs 2244 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 175 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.822857 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 109.846299 # Cycle average of tags in use +system.cpu.dcache.total_refs 2275 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 176 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.926136 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 109.847039 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 109.846299 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.026818 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.026818 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1735 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1735 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 1766 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1766 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 509 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 509 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2244 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2244 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2244 # number of overall hits -system.cpu.dcache.overall_hits::total 2244 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 144 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 144 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2275 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2275 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2275 # number of overall hits +system.cpu.dcache.overall_hits::total 2275 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 146 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 146 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 356 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 356 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses -system.cpu.dcache.overall_misses::total 500 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5240000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5240000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 12485500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 12485500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17725500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17725500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17725500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1879 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1879 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5337000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5337000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 12518000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 12518000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17855000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17855000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17855000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1912 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1912 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2744 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2744 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2744 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2744 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076637 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076637 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2777 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2777 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2777 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2777 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076360 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076360 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.182216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.182216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.182216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.182216 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36388.888889 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36388.888889 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35071.629213 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35071.629213 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35451 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35451 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.180771 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.180771 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.180771 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.180771 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36554.794521 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36554.794521 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35162.921348 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35162.921348 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35567.729084 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35567.729084 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -478,14 +478,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 40 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 40 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 284 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 284 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 324 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 324 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 324 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 326 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses @@ -494,103 +494,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 176 system.cpu.dcache.demand_mshr_misses::total 176 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 176 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3722000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6297500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6297500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055349 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055349 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3764000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2575000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6339000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6339000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054393 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054393 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064140 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064140 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064140 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35788.461538 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35788.461538 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35770.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35781.250000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35781.250000 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063378 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063378 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36192.307692 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36192.307692 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35763.888889 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35763.888889 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36017.045455 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36017.045455 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.787735 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.380125 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 418 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002392 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002404 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 162.229240 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 62.558495 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004951 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001909 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006860 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 161.620273 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 62.759852 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004932 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001915 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006848 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 314 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 312 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 104 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 418 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 416 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 314 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 312 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 176 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 490 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 314 # number of overall misses +system.cpu.l2cache.demand_misses::total 488 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 176 # number of overall misses -system.cpu.l2cache.overall_misses::total 490 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10779500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3600000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14379500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2488500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2488500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10779500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6088500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16868000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10779500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6088500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16868000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 488 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10703000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3603500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14306500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2489000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2489000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 10703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6092500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16795500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 10703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6092500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16795500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 419 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 417 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 313 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 176 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 491 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 489 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 313 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 176 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 491 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996825 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 489 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997613 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997602 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996825 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996825 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997955 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34329.617834 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34615.384615 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34400.717703 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34562.500000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34562.500000 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34424.489796 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34329.617834 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34593.750000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34424.489796 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997955 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34304.487179 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34649.038462 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34390.625000 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34569.444444 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34417.008197 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34304.487179 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34616.477273 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34417.008197 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -599,50 +599,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 418 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 416 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 176 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 490 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 488 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 176 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 490 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9770500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3273500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13044000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9770500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5537500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15308000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9770500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5537500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15308000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 488 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9702500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3275000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12977500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2264500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9702500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5539500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15242000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9702500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5539500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15242000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997613 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997602 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996825 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997955 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31116.242038 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31475.961538 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31205.741627 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31444.444444 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31116.242038 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31463.068182 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31240.816327 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997955 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31097.756410 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31490.384615 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31195.913462 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31451.388889 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31097.756410 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31474.431818 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31233.606557 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index 157d28a7a..2586fc610 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 13:45:03 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:32 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 7015000 because target called exit() +Exiting @ tick 6934000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 119328db2..729742f8d 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000007 # Number of seconds simulated -sim_ticks 7015000 # Number of ticks simulated -final_tick 7015000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 6934000 # Number of ticks simulated +final_tick 6934000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 16156 # Simulator instruction rate (inst/s) -host_op_rate 16154 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 47467285 # Simulator tick rate (ticks/s) -host_mem_usage 214556 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 29510 # Simulator instruction rate (inst/s) +host_op_rate 29504 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85688409 # Simulator tick rate (ticks/s) +host_mem_usage 217944 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 12096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 5504 # Number of bytes read from this memory -system.physmem.bytes_read::total 17600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 12096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 12096 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 189 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 86 # Number of read requests responded to by this memory -system.physmem.num_reads::total 275 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1724305061 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 784604419 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2508909480 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1724305061 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1724305061 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 784604419 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2508909480 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory +system.physmem.bytes_read::total 17472 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory +system.physmem.num_reads::total 273 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1735217768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 784539948 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2519757716 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1735217768 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1735217768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 784539948 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2519757716 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 711 # DTB read hits -system.cpu.dtb.read_misses 43 # DTB read misses +system.cpu.dtb.read_hits 704 # DTB read hits +system.cpu.dtb.read_misses 36 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 380 # DTB write hits -system.cpu.dtb.write_misses 23 # DTB write misses +system.cpu.dtb.read_accesses 740 # DTB read accesses +system.cpu.dtb.write_hits 367 # DTB write hits +system.cpu.dtb.write_misses 22 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 403 # DTB write accesses -system.cpu.dtb.data_hits 1091 # DTB hits -system.cpu.dtb.data_misses 66 # DTB misses +system.cpu.dtb.write_accesses 389 # DTB write accesses +system.cpu.dtb.data_hits 1071 # DTB hits +system.cpu.dtb.data_misses 58 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1157 # DTB accesses -system.cpu.itb.fetch_hits 1067 # ITB hits -system.cpu.itb.fetch_misses 33 # ITB misses +system.cpu.dtb.data_accesses 1129 # DTB accesses +system.cpu.itb.fetch_hits 999 # ITB hits +system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1100 # ITB accesses +system.cpu.itb.fetch_accesses 1029 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -60,246 +60,246 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 14031 # number of cpu cycles simulated +system.cpu.numCycles 13869 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1201 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 569 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 276 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 824 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 230 # Number of BTB hits +system.cpu.BPredUnit.lookups 1119 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 563 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 252 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 783 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 216 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 243 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 3890 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7412 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1201 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 473 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 922 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 250 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 210 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 34 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 3820 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 6858 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1119 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 426 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1175 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 850 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 242 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 780 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1067 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 174 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.086804 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.510240 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 783 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 999 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 170 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.037362 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.461313 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5560 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 47 0.69% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 133 1.95% 84.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 103 1.51% 85.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 148 2.17% 87.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 78 1.14% 88.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 68 1.00% 89.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.94% 90.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 619 9.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 5436 82.23% 82.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 51 0.77% 83.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 129 1.95% 84.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 97 1.47% 86.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 136 2.06% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 62 0.94% 89.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 66 1.00% 90.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 64 0.97% 91.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 570 8.62% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 6820 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.085596 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.528259 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 4790 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 271 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1197 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 17 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 545 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 185 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 6611 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.080684 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.494484 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 4718 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 256 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1133 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 10 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 494 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 166 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 83 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6535 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 298 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 545 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 4889 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 77 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 6102 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 494 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 4814 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 67 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 147 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1115 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 47 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6259 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 17 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 24 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4535 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 7053 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 7041 # Number of integer rename lookups +system.cpu.rename.RunCycles 1046 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 43 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 5849 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 16 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 16 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4252 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6619 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6607 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2767 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2484 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 996 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 505 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5232 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 7 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4206 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2612 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1532 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 6820 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616716 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.331431 # Number of insts issued each cycle +system.cpu.rename.skidInsts 137 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 945 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 472 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 4975 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 4026 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 68 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2372 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1428 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 6611 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.608985 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.321430 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5134 75.28% 75.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 613 8.99% 84.27% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 383 5.62% 89.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 269 3.94% 93.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 207 3.04% 96.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 134 1.96% 98.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 52 0.76% 99.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 14 0.21% 99.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 4990 75.48% 75.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 583 8.82% 84.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 382 5.78% 90.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 267 4.04% 94.12% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 192 2.90% 97.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 114 1.72% 98.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 53 0.80% 99.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 18 0.27% 99.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 12 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 6820 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 6611 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 11.63% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 11.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 15 34.88% 46.51% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 53.49% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 9.09% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 17 38.64% 47.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 23 52.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2987 71.02% 71.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 71.04% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 805 19.14% 90.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 413 9.82% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2853 70.86% 70.86% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.89% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 775 19.25% 90.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 397 9.86% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4206 # Type of FU issued -system.cpu.iq.rate 0.299765 # Inst issue rate -system.cpu.iq.fu_busy_cnt 43 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010223 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15313 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7848 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3807 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 4026 # Type of FU issued +system.cpu.iq.rate 0.290288 # Inst issue rate +system.cpu.iq.fu_busy_cnt 44 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010929 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 14762 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7351 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3682 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4242 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4063 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 33 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 581 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 530 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 211 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 178 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 545 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 494 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 53 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5607 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 106 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 996 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 505 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 7 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5319 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 96 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 945 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 472 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 80 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 161 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 241 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4005 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 757 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 201 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 54 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 207 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 3873 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 741 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 153 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 368 # number of nop insts executed -system.cpu.iew.exec_refs 1160 # number of memory reference insts executed -system.cpu.iew.exec_branches 681 # Number of branches executed -system.cpu.iew.exec_stores 403 # Number of stores executed -system.cpu.iew.exec_rate 0.285439 # Inst execution rate -system.cpu.iew.wb_sent 3920 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3813 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1793 # num instructions producing a value -system.cpu.iew.wb_consumers 2339 # num instructions consuming a value +system.cpu.iew.exec_nop 338 # number of nop insts executed +system.cpu.iew.exec_refs 1130 # number of memory reference insts executed +system.cpu.iew.exec_branches 650 # Number of branches executed +system.cpu.iew.exec_stores 389 # Number of stores executed +system.cpu.iew.exec_rate 0.279256 # Inst execution rate +system.cpu.iew.wb_sent 3778 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3688 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1732 # num instructions producing a value +system.cpu.iew.wb_consumers 2249 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.271755 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.766567 # average fanout of values written-back +system.cpu.iew.wb_rate 0.265917 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.770120 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 3022 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2738 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 198 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6275 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.410518 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.252508 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 172 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 6117 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.421121 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.275697 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5374 85.64% 85.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 226 3.60% 89.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 318 5.07% 94.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.91% 96.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 75 1.20% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 53 0.84% 98.26% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 33 0.53% 98.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 17 0.27% 99.06% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 59 0.94% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5226 85.43% 85.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 218 3.56% 89.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 319 5.21% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 117 1.91% 96.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 69 1.13% 97.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.92% 98.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 32 0.52% 98.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 19 0.31% 99.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61 1.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6275 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6117 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -310,69 +310,69 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 59 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11567 # The number of ROB reads -system.cpu.rob.rob_writes 11753 # The number of ROB writes +system.cpu.rob.rob_reads 11123 # The number of ROB reads +system.cpu.rob.rob_writes 11131 # The number of ROB writes system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7211 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 7258 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.878090 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.878090 # CPI: Total CPI of All Threads -system.cpu.ipc 0.170123 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.170123 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4832 # number of integer regfile reads -system.cpu.int_regfile_writes 2958 # number of integer regfile writes +system.cpu.cpi 5.810222 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.810222 # CPI: Total CPI of All Threads +system.cpu.ipc 0.172110 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.172110 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4695 # number of integer regfile reads +system.cpu.int_regfile_writes 2856 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 93.540284 # Cycle average of tags in use -system.cpu.icache.total_refs 817 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 189 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.322751 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 93.248355 # Cycle average of tags in use +system.cpu.icache.total_refs 752 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 93.540284 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.045674 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.045674 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 817 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 817 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 817 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 817 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 817 # number of overall hits -system.cpu.icache.overall_hits::total 817 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 250 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 250 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 250 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 250 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 250 # number of overall misses -system.cpu.icache.overall_misses::total 250 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 8957500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 8957500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 8957500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 8957500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 8957500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1067 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1067 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1067 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1067 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1067 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.234302 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.234302 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.234302 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.234302 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.234302 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35830 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35830 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35830 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35830 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 93.248355 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045531 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045531 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 752 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 752 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 752 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 752 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 752 # number of overall hits +system.cpu.icache.overall_hits::total 752 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 247 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 247 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 247 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 247 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 247 # number of overall misses +system.cpu.icache.overall_misses::total 247 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 8946000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 8946000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 8946000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 8946000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 8946000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 999 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 999 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 999 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 999 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 999 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.247247 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.247247 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.247247 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.247247 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.247247 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36218.623482 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36218.623482 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36218.623482 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36218.623482 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -381,94 +381,94 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 189 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 6695500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 6695500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6695500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 6695500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.177132 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.177132 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.177132 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35425.925926 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35425.925926 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35425.925926 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 59 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 59 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 59 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 59 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 6660500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 6660500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6660500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 6660500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188188 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188188 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188188 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35428.191489 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35428.191489 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35428.191489 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 46.152964 # Cycle average of tags in use -system.cpu.dcache.total_refs 793 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 86 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.220930 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.780075 # Cycle average of tags in use +system.cpu.dcache.total_refs 785 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 9.235294 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 46.152964 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.011268 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 571 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 571 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.780075 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011177 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 563 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 563 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 222 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 222 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 793 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 793 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 793 # number of overall hits -system.cpu.dcache.overall_hits::total 793 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 107 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 107 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 785 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 785 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 785 # number of overall hits +system.cpu.dcache.overall_hits::total 785 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 110 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 110 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 72 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 72 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 179 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 179 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 179 # number of overall misses -system.cpu.dcache.overall_misses::total 179 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3676500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3676500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2816000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2816000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 182 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses +system.cpu.dcache.overall_misses::total 182 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3679000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3679000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 2813500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 2813500 # number of WriteReq miss cycles system.cpu.dcache.demand_miss_latency::cpu.data 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 6492500 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 6492500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 6492500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 678 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 678 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 673 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 673 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 972 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 972 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 972 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 972 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.157817 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.157817 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 967 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 967 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 967 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 967 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.163447 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.163447 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.244898 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.244898 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.184156 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.184156 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.184156 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.184156 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34359.813084 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34359.813084 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39111.111111 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39111.111111 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 36270.949721 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 36270.949721 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.188211 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188211 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188211 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188211 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33445.454545 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 33445.454545 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39076.388889 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 39076.388889 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35673.076923 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35673.076923 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -477,91 +477,91 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 48 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 48 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 93 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 93 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 93 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 62 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 97 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 97 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 97 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 24 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 86 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 86 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2205000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 873500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3078500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3078500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.091445 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.091445 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2166000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 871000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3037000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3037000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.090639 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.090639 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.088477 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.088477 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35564.516129 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36395.833333 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35796.511628 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35796.511628 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.087901 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.087901 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35508.196721 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36291.666667 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35729.411765 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35729.411765 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 122.732805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 122.119430 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 251 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 93.626172 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 29.106633 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002857 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000888 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003746 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 189 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 62 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 251 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 93.334885 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.784545 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002848 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000878 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003727 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 189 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 86 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 275 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 189 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 86 # number of overall misses -system.cpu.l2cache.overall_misses::total 275 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6484000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2135500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8619500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 832000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 832000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 6484000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 2967500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9451500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 6484000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 2967500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9451500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 62 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 251 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses +system.cpu.l2cache.overall_misses::total 273 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 6449000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2098500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 8547500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 830000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 830000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 6449000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 2928500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 9377500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 6449000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 2928500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 9377500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 189 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 86 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 275 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 189 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 86 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 275 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -573,17 +573,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34306.878307 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34443.548387 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34340.637450 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34369.090909 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34306.878307 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34505.813953 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34369.090909 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34303.191489 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34401.639344 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34327.309237 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34583.333333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34349.816850 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34303.191489 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34452.941176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34349.816850 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -592,28 +592,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 189 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 62 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 251 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 189 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 86 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 275 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 189 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 86 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 275 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5881500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1936500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7818000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 757500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5881500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2694000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8575500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5881500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2694000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8575500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5849000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1904500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7753500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 755000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5849000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2659500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 8508500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5849000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2659500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 8508500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -625,17 +625,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31119.047619 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31233.870968 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31147.410359 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31562.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31119.047619 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31325.581395 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31183.636364 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31111.702128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31221.311475 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31138.554217 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31458.333333 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31111.702128 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31288.235294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31166.666667 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index 9fb63a7a7..c374c028c 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:41 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:53 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ea50665b2..9b64fc302 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 43907 # Simulator instruction rate (inst/s) -host_op_rate 54769 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 98312554 # Simulator tick rate (ticks/s) -host_mem_usage 230064 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 40668 # Simulator instruction rate (inst/s) +host_op_rate 50741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91257316 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -70,7 +70,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5752 # number of cpu cycles simulated +system.cpu.checker.numCycles 5742 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -115,319 +115,318 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -436,110 +435,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -548,16 +547,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -566,73 +565,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -645,27 +644,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -681,49 +680,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index fc15b65e3..8b9162b5e 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:30 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:34:42 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 10303500 because target called exit() +Exiting @ tick 10305000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 85d0d7401..e182dd250 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10303500 # Number of ticks simulated -final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 10305000 # Number of ticks simulated +final_tick 10305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 49511 # Simulator instruction rate (inst/s) -host_op_rate 61757 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 110854808 # Simulator tick rate (ticks/s) -host_mem_usage 229756 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated +host_inst_rate 29768 # Simulator instruction rate (inst/s) +host_op_rate 37142 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 66801597 # Simulator tick rate (ticks/s) +host_mem_usage 232684 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory -system.physmem.bytes_read::total 25664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7872 # Number of bytes read from this memory +system.physmem.bytes_read::total 25536 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory -system.physmem.num_reads::total 401 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 123 # Number of read requests responded to by this memory +system.physmem.num_reads::total 399 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1714119360 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 763901019 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2478020378 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1714119360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1714119360 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 763901019 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2478020378 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,319 +70,318 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20608 # number of cpu cycles simulated +system.cpu.numCycles 20611 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2552 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1875 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 474 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2008 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 693 # Number of BTB hits +system.cpu.BPredUnit.lookups 2522 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1857 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 445 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1967 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 669 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 237 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 53 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6263 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13044 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2552 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 930 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2846 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1780 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1715 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 37 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2031 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 304 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.376812 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.767860 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 255 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6205 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12809 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2522 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 924 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2802 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1712 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 1810 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 1996 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 298 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.366631 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.761460 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9229 76.43% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 246 2.04% 78.47% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 197 1.63% 80.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 227 1.88% 81.98% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 225 1.86% 83.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 278 2.30% 86.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 120 0.99% 87.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 130 1.08% 88.22% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1423 11.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9191 76.64% 76.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 251 2.09% 78.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 179 1.49% 80.22% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.85% 82.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 215 1.79% 83.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 290 2.42% 86.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 118 0.98% 87.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 119 0.99% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1408 11.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12075 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.123835 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.632958 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6461 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1883 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2624 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 61 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1046 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 174 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14512 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 583 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1046 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6744 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1422 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2398 # Number of cycles rename is running +system.cpu.fetch.rateDist::total 11993 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.122362 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.621464 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6357 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1977 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2573 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 70 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1016 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 444 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 14344 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 551 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 1016 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6632 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 279 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 1507 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2368 # Number of cycles rename is running system.cpu.rename.UnblockCycles 191 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 13646 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 155 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 13298 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 62745 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 61353 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 7614 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 44 # count of serializing insts renamed +system.cpu.rename.RenamedInsts 13444 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 160 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 13077 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 61779 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 60371 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 1408 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 7404 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 45 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 42 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 614 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2865 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1803 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 22 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 17 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11802 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 52 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9165 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5733 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 16704 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12075 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.759006 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.446143 # Number of insts issued each cycle +system.cpu.rename.skidInsts 627 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2891 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1788 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11732 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9186 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5655 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 16152 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11993 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.765947 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.466891 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8430 69.81% 69.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1334 11.05% 80.86% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 801 6.63% 87.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 552 4.57% 92.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 480 3.98% 96.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 289 2.39% 98.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 130 1.08% 99.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 44 0.36% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8390 69.96% 69.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1302 10.86% 80.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.58% 87.39% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 542 4.52% 91.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 463 3.86% 95.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 295 2.46% 98.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 149 1.24% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.38% 99.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 18 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12075 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11993 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.38% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 150 69.12% 70.51% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 29.49% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5502 60.03% 60.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.11% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.14% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2395 26.13% 86.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1258 13.73% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5505 59.93% 59.93% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.04% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2406 26.19% 86.23% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1265 13.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9165 # Type of FU issued -system.cpu.iq.rate 0.444730 # Inst issue rate -system.cpu.iq.fu_busy_cnt 215 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.023459 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30696 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 17588 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8151 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9186 # Type of FU issued +system.cpu.iq.rate 0.445684 # Inst issue rate +system.cpu.iq.fu_busy_cnt 217 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.023623 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30663 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 17408 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8220 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 46 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9360 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9383 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 64 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1664 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1691 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 865 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 850 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1046 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 1016 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 175 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11855 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 180 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2865 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1803 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 11783 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 140 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2891 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1788 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 104 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 425 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8667 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2152 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 498 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 88 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 407 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8719 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2169 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 467 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1 # number of nop insts executed -system.cpu.iew.exec_refs 3351 # number of memory reference insts executed -system.cpu.iew.exec_branches 1406 # Number of branches executed -system.cpu.iew.exec_stores 1199 # Number of stores executed -system.cpu.iew.exec_rate 0.420565 # Inst execution rate -system.cpu.iew.wb_sent 8349 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8167 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3874 # num instructions producing a value -system.cpu.iew.wb_consumers 7832 # num instructions consuming a value +system.cpu.iew.exec_nop 0 # number of nop insts executed +system.cpu.iew.exec_refs 3377 # number of memory reference insts executed +system.cpu.iew.exec_branches 1400 # Number of branches executed +system.cpu.iew.exec_stores 1208 # Number of stores executed +system.cpu.iew.exec_rate 0.423027 # Inst execution rate +system.cpu.iew.wb_sent 8403 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8236 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3901 # num instructions producing a value +system.cpu.iew.wb_consumers 7899 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.396302 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.494637 # average fanout of values written-back +system.cpu.iew.wb_rate 0.399592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.493860 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions -system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 6115 # The number of squashed insts skipped by commit +system.cpu.commit.commitCommittedInsts 4591 # The number of committed instructions +system.cpu.commit.commitCommittedOps 5729 # The number of committed instructions +system.cpu.commit.commitSquashedInsts 6053 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 378 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11030 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.520308 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.336045 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 355 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10978 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521862 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.331986 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8688 78.77% 78.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1103 10.00% 88.77% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 433 3.93% 92.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 253 2.29% 94.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 182 1.65% 96.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 178 1.61% 98.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.51% 98.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 39 0.35% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 98 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8629 78.60% 78.60% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1108 10.09% 88.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 430 3.92% 92.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 264 2.40% 95.02% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 184 1.68% 96.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 173 1.58% 98.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 56 0.51% 98.78% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 40 0.36% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 94 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11030 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4600 # Number of instructions committed -system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 10978 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4591 # Number of instructions committed +system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 2139 # Number of memory references committed -system.cpu.commit.loads 1201 # Number of loads committed +system.cpu.commit.refs 2138 # Number of memory references committed +system.cpu.commit.loads 1200 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 945 # Number of branches committed +system.cpu.commit.branches 944 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. -system.cpu.commit.int_insts 4985 # Number of committed integer instructions. +system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 94 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22629 # The number of ROB reads -system.cpu.rob.rob_writes 24771 # The number of ROB writes -system.cpu.timesIdled 177 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8533 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4600 # Number of Instructions Simulated -system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 4600 # Number of Instructions Simulated -system.cpu.cpi 4.480000 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.480000 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223214 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223214 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39716 # number of integer regfile reads -system.cpu.int_regfile_writes 8038 # number of integer regfile writes +system.cpu.rob.rob_reads 22509 # The number of ROB reads +system.cpu.rob.rob_writes 24591 # The number of ROB writes +system.cpu.timesIdled 178 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8618 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4591 # Number of Instructions Simulated +system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 4591 # Number of Instructions Simulated +system.cpu.cpi 4.489436 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.489436 # CPI: Total CPI of All Threads +system.cpu.ipc 0.222745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.222745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 40006 # number of integer regfile reads +system.cpu.int_regfile_writes 8113 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 16043 # number of misc regfile reads +system.cpu.misc_regfile_reads 15846 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes -system.cpu.icache.replacements 2 # number of replacements -system.cpu.icache.tagsinuse 151.737773 # Cycle average of tags in use -system.cpu.icache.total_refs 1665 # Total number of references to valid blocks. +system.cpu.icache.replacements 5 # number of replacements +system.cpu.icache.tagsinuse 150.103653 # Cycle average of tags in use +system.cpu.icache.total_refs 1637 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.625000 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.530405 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 151.737773 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074091 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074091 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1665 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1665 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1665 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1665 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1665 # number of overall hits -system.cpu.icache.overall_hits::total 1665 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12617500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12617500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12617500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12617500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12617500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2031 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2031 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2031 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2031 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2031 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.180207 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 150.103653 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073293 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073293 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1637 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1637 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1637 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1637 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1637 # number of overall hits +system.cpu.icache.overall_hits::total 1637 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses +system.cpu.icache.overall_misses::total 359 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12452500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12452500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12452500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12452500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12452500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1996 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1996 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1996 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1996 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1996 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.179860 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.179860 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.179860 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.179860 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.179860 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34686.629526 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34686.629526 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34686.629526 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34686.629526 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,110 +390,110 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9833500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9833500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9833500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9833500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33221.283784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9831500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9831500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9831500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148297 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148297 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148297 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33214.527027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33214.527027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 33214.527027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.257006 # Cycle average of tags in use -system.cpu.dcache.total_refs 2425 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 87.680549 # Cycle average of tags in use +system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.275168 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.409396 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.257006 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021303 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1796 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1796 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 87.680549 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021406 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1816 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1816 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2405 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2405 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2405 # number of overall hits -system.cpu.dcache.overall_hits::total 2405 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2425 # number of overall hits +system.cpu.dcache.overall_hits::total 2425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 173 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 173 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5541500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5541500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 477 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 477 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 477 # number of overall misses +system.cpu.dcache.overall_misses::total 477 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5540500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5540500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10913500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10913500 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16385500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16385500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1966 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1966 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16454000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16454000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16454000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1989 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2879 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2879 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2879 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2879 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086470 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2902 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2902 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2902 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2902 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086978 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.086978 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.164641 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.164641 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32597.058824 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.164369 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.164369 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.164369 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.164369 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32026.011561 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 32026.011561 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35899.671053 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35899.671053 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34494.758910 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34494.758910 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -503,16 +502,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 328 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 328 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 328 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -521,73 +520,73 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 149 system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3192000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4693500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4693500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054425 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3133500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053796 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053796 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31500 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051344 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051344 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29285.046729 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35845.238095 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31134.228188 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 31134.228188 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 188.789311 # Cycle average of tags in use -system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.111421 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 188.762510 # Cycle average of tags in use +system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 357 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.117647 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.150350 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.638961 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001423 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.243584 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.518926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001420 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005761 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 22 # number of overall hits +system.cpu.l2cache.overall_hits::total 42 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 361 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 129 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 129 # number of overall misses -system.cpu.l2cache.overall_misses::total 405 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9475500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2999000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12474500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9475500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4445500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13921000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9475500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4445500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13921000 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 403 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9473000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2933000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12406000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1449000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9473000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4382000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13855000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9473000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4382000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13855000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -600,27 +599,27 @@ system.cpu.l2cache.overall_accesses::cpu.inst 296 system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813084 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.794393 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.895782 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.865772 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.852349 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.905618 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.865772 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34331.521739 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34471.264368 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::cpu.data 0.852349 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.905618 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34322.463768 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34505.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.650970 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34500 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34500 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34379.652605 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34322.463768 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34503.937008 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34379.652605 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -636,49 +635,49 @@ system.cpu.l2cache.demand_mshr_hits::total 4 # system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 399 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11202500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12517500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12517500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 399 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2552500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11142500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1317000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3869500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12459500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3869500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12459500 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.775701 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.757009 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.885856 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.896629 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.838926 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31416 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.825503 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.896629 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31123.188406 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31512.345679 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31211.484594 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31357.142857 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31123.188406 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31459.349593 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31226.817043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout index a8cf8ab9b..a902d2024 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:03 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:15 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic-dummychecker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index a4d8f3fa5..2fe5ceaba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 760705 # Simulator instruction rate (inst/s) -host_op_rate 946184 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 472746039 # Simulator tick rate (ticks/s) -host_mem_usage 219832 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 136961 # Simulator instruction rate (inst/s) +host_op_rate 170823 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 85547635 # Simulator tick rate (ticks/s) +host_mem_usage 223208 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -121,26 +121,26 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout index f818842dc..d40bbcb86 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:23:52 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:04 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 2875500 because target called exit() +Exiting @ tick 2870500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index 44b5714ac..ef6865dff 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2875500 # Number of ticks simulated -final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2870500 # Number of ticks simulated +final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 577592 # Simulator instruction rate (inst/s) -host_op_rate 718947 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 359450620 # Simulator tick rate (ticks/s) -host_mem_usage 219740 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4600 # Number of instructions simulated -sim_ops 5739 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 18452 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 4492 # Number of bytes read from this memory -system.physmem.bytes_read::total 22944 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18452 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18452 # Number of instructions bytes read from this memory +host_inst_rate 62314 # Simulator instruction rate (inst/s) +host_op_rate 77743 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 38944247 # Simulator tick rate (ticks/s) +host_mem_usage 223212 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 4591 # Number of instructions simulated +sim_ops 5729 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory +system.physmem.bytes_read::total 22907 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4613 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 1158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5771 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6416970962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1562163102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 7979134064 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6416970962 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1268648931 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6416970962 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2830812033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9247782994 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -76,26 +76,26 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 5752 # number of cpu cycles simulated +system.cpu.numCycles 5742 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4600 # Number of instructions committed -system.cpu.committedOps 5739 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4591 # Number of instructions committed +system.cpu.committedOps 5729 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 25237 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 25195 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 5752 # Number of busy cycles +system.cpu.num_busy_cycles 5742 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout index a6d6adcc2..d4a066c4f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:14:06 -gem5 started Jun 4 2012 17:24:13 +gem5 compiled Jun 28 2012 22:10:14 +gem5 started Jun 29 2012 00:35:26 gem5 executing on zizzer -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing +command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 26361000 because target called exit() +Exiting @ tick 26351000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 0449db647..bac15b503 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 26361000 # Number of ticks simulated -final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 26351000 # Number of ticks simulated +final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 366471 # Simulator instruction rate (inst/s) -host_op_rate 454532 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2105652624 # Simulator tick rate (ticks/s) -host_mem_usage 228652 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4574 # Number of instructions simulated -sim_ops 5682 # Number of ops (including micro ops) simulated +host_inst_rate 50718 # Simulator instruction rate (inst/s) +host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292657577 # Simulator tick rate (ticks/s) +host_mem_usage 231660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 4565 # Number of instructions simulated +sim_ops 5672 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory system.physmem.bytes_read::total 22400 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 546261523 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 303478624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 849740146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 546261523 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 546261523 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 303478624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 849740146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -70,43 +70,43 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 52722 # number of cpu cycles simulated +system.cpu.numCycles 52702 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4574 # Number of instructions committed -system.cpu.committedOps 5682 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses +system.cpu.committedInsts 4565 # Number of instructions committed +system.cpu.committedOps 5672 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses -system.cpu.num_func_calls 185 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls -system.cpu.num_int_insts 4985 # number of integer instructions +system.cpu.num_func_calls 203 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls +system.cpu.num_int_insts 4976 # number of integer instructions system.cpu.num_fp_insts 16 # number of float instructions -system.cpu.num_int_register_reads 28701 # number of times the integer registers were read -system.cpu.num_int_register_writes 5345 # number of times the integer registers were written +system.cpu.num_int_register_reads 28656 # number of times the integer registers were read +system.cpu.num_int_register_writes 5334 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_mem_refs 2139 # number of memory refs -system.cpu.num_load_insts 1201 # Number of load instructions +system.cpu.num_mem_refs 2138 # number of memory refs +system.cpu.num_load_insts 1200 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0 # Number of idle cycles -system.cpu.num_busy_cycles 52722 # Number of busy cycles +system.cpu.num_busy_cycles 52702 # Number of busy cycles system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.idle_fraction 0 # Percentage of idle cycles system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.tagsinuse 114.525744 # Cycle average of tags in use -system.cpu.icache.total_refs 4373 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use +system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4373 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4373 # number of overall hits -system.cpu.icache.overall_hits::total 4373 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits +system.cpu.icache.overall_hits::total 4364 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses @@ -119,18 +119,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12824000 system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4614 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4614 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4614 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4614 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052232 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052232 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052232 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052232 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 53211.618257 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency @@ -157,12 +157,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12101000 system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12101000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052232 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052232 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052232 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052232 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency @@ -171,26 +171,26 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use -system.cpu.dcache.total_refs 1941 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use +system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 82.937979 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020249 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1919 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1919 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1919 # number of overall hits -system.cpu.dcache.overall_hits::total 1919 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1918 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1918 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1918 # number of overall hits +system.cpu.dcache.overall_hits::total 1918 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses @@ -207,26 +207,26 @@ system.cpu.dcache.demand_miss_latency::cpu.data 7224000 system.cpu.dcache.demand_miss_latency::total 7224000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 7224000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 7224000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1147 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1146 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1146 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2060 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2060 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2060 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085440 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085440 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2059 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2059 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2059 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2059 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085515 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.085515 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.068447 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.068447 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.068447 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.068447 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.068480 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.068480 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.068480 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.068480 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 49142.857143 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency @@ -259,14 +259,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085440 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085515 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.085515 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.068447 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.068447 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.068480 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068480 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.068480 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency @@ -277,16 +277,16 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index c92fa97a1..d99f33506 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:58:11 -gem5 started Jun 4 2012 14:43:27 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:52:53 gem5 executing on zizzer -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing +command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 12671500 because target called exit() +Exiting @ tick 12478500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 69e82fc15..7981b4fdb 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 12671500 # Number of ticks simulated -final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000012 # Number of seconds simulated +sim_ticks 12478500 # Number of ticks simulated +final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63611 # Simulator instruction rate (inst/s) -host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 155871053 # Simulator tick rate (ticks/s) -host_mem_usage 216124 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 84509 # Simulator instruction rate (inst/s) +host_op_rate 84485 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 203899861 # Simulator tick rate (ticks/s) +host_mem_usage 220092 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5169 # Number of instructions simulated sim_ops 5169 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory +system.physmem.bytes_read::total 30784 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory +system.physmem.num_reads::total 481 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,101 +46,101 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 25344 # number of cpu cycles simulated +system.cpu.numCycles 24958 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2242 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1547 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1757 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 473 # Number of BTB hits +system.cpu.BPredUnit.lookups 2172 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 271 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 92 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8296 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13683 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2242 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 744 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3324 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1376 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 663 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2039 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.031667 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.344238 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9939 74.94% 74.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 10.16% 85.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 128 0.97% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 139 1.05% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 303 2.28% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 122 0.92% 90.32% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 146 1.10% 91.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 140 1.06% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 998 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13263 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.088463 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.539891 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8460 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 795 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3128 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 40 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 840 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 144 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 52 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12579 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 215 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 840 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8664 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 204 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 498 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2966 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 91 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11935 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 82 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7222 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 14215 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 14211 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3014 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2873 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3812 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 17 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 229 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2496 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1209 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 18 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9121 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8177 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 38 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3469 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2115 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13263 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.616527 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.283212 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9760 73.59% 73.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1384 10.44% 84.02% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 845 6.37% 90.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 558 4.21% 94.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 351 2.65% 97.25% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 227 1.71% 98.96% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 90 0.68% 99.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 34 0.26% 99.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13263 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -171,120 +171,120 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 97 63.82% 66.45% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 51 33.55% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4822 58.97% 58.97% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.04% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2258 27.61% 86.68% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1089 13.32% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8177 # Type of FU issued -system.cpu.iq.rate 0.322640 # Inst issue rate +system.cpu.iq.FU_type_0::total 8121 # Type of FU issued +system.cpu.iq.rate 0.325387 # Inst issue rate system.cpu.iq.fu_busy_cnt 152 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018589 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29803 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12607 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7305 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8327 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1332 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 284 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 840 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10598 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 139 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2496 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1209 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 371 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 503 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7763 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2105 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1464 # number of nop insts executed -system.cpu.iew.exec_refs 3166 # number of memory reference insts executed -system.cpu.iew.exec_branches 1317 # Number of branches executed -system.cpu.iew.exec_stores 1061 # Number of stores executed -system.cpu.iew.exec_rate 0.306305 # Inst execution rate -system.cpu.iew.wb_sent 7406 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7307 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2841 # num instructions producing a value -system.cpu.iew.wb_consumers 4060 # num instructions consuming a value +system.cpu.iew.exec_nop 1469 # number of nop insts executed +system.cpu.iew.exec_refs 3191 # number of memory reference insts executed +system.cpu.iew.exec_branches 1304 # Number of branches executed +system.cpu.iew.exec_stores 1065 # Number of stores executed +system.cpu.iew.exec_rate 0.311163 # Inst execution rate +system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7294 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2836 # num instructions producing a value +system.cpu.iew.wb_consumers 4075 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.288313 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699754 # average fanout of values written-back +system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 4764 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 425 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12423 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.468969 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.246143 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9990 80.42% 80.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1014 8.16% 88.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 641 5.16% 93.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 335 2.70% 96.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 140 1.13% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 89 0.72% 98.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 74 0.60% 98.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 44 0.35% 99.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 96 0.77% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12423 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle system.cpu.commit.committedInsts 5826 # Number of instructions committed system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,69 +295,69 @@ system.cpu.commit.branches 916 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5124 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 96 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22904 # The number of ROB reads -system.cpu.rob.rob_writes 22029 # The number of ROB writes -system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 12081 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 22599 # The number of ROB reads +system.cpu.rob.rob_writes 21853 # The number of ROB writes +system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5169 # Number of Instructions Simulated system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5169 # Number of Instructions Simulated -system.cpu.cpi 4.903076 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.903076 # CPI: Total CPI of All Threads -system.cpu.ipc 0.203954 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.203954 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10565 # number of integer regfile reads -system.cpu.int_regfile_writes 5131 # number of integer regfile writes +system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads +system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10560 # number of integer regfile reads +system.cpu.int_regfile_writes 5130 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 151 # number of misc regfile reads -system.cpu.icache.replacements 19 # number of replacements -system.cpu.icache.tagsinuse 165.584947 # Cycle average of tags in use -system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 344 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.627907 # Average number of references to valid blocks. +system.cpu.misc_regfile_reads 150 # number of misc regfile reads +system.cpu.icache.replacements 17 # number of replacements +system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use +system.cpu.icache.total_refs 1503 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 165.584947 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.080852 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.080852 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits -system.cpu.icache.overall_hits::total 1592 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses -system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15909500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15909500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15909500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15909500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits +system.cpu.icache.overall_hits::total 1503 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses +system.cpu.icache.overall_misses::total 435 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -366,54 +366,54 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 344 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 344 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use -system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use +system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022540 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1886 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1886 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2472 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2472 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2472 # number of overall hits -system.cpu.dcache.overall_hits::total 2472 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits +system.cpu.dcache.overall_hits::total 2489 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses @@ -422,38 +422,38 @@ system.cpu.dcache.demand_misses::cpu.data 472 # n system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses system.cpu.dcache.overall_misses::total 472 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4826500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4826500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11393500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11393500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16220000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16220000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16220000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2019 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -462,119 +462,119 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 330 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 330 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.134201 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005134 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006908 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 341 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 341 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 341 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses -system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11691000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3142000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14833000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1769000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11691000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4911000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16602000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11691000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4911000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16602000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 344 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 435 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses +system.cpu.l2cache.overall_misses::total 481 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1768500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4947000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 16540500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4947000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16540500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 341 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 433 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 341 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.993072 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991202 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.993802 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991202 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,50 +583,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10590500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2858000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13448500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10498500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2890500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13389000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1604000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10498500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4494500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14993000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10498500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4494500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14993000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993072 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.993802 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991202 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.993802 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.650888 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31418.478261 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31137.209302 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.650888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31430.069930 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31170.478170 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index b797dcfe3..584102e9c 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:59:33 -gem5 started Jun 4 2012 14:44:10 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:53:15 gem5 executing on zizzer -command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing +command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 11243500 because target called exit() +Exiting @ tick 11179000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 975867801..f8f7991bd 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,32 +1,32 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000011 # Number of seconds simulated -sim_ticks 11243500 # Number of ticks simulated -final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 11179000 # Number of ticks simulated +final_tick 11179000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 72271 # Simulator instruction rate (inst/s) -host_op_rate 72256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 140039967 # Simulator tick rate (ticks/s) -host_mem_usage 211876 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 61972 # Simulator instruction rate (inst/s) +host_op_rate 61960 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119400246 # Simulator tick rate (ticks/s) +host_mem_usage 216052 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5800 # Number of instructions simulated sim_ops 5800 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 6336 # Number of bytes read from this memory -system.physmem.bytes_read::total 28736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory +system.physmem.bytes_read::total 28864 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 22400 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22400 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 350 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 99 # Number of read requests responded to by this memory -system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1992262196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 563525593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2555787789 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1992262196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1992262196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 563525593 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2555787789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory +system.physmem.num_reads::total 451 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2003757044 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 578227033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2581984077 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2003757044 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2003757044 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 578227033 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2581984077 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -46,245 +46,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 22488 # number of cpu cycles simulated +system.cpu.numCycles 22359 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2514 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2062 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 468 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2079 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 622 # Number of BTB hits +system.cpu.BPredUnit.lookups 2487 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2038 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 457 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2063 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 631 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 36 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6888 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14589 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2514 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2426 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1431 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 816 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 157 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 28 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 6834 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14542 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2487 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 788 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2415 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1412 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 813 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1899 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 313 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.315628 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.735108 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.320439 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.737355 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8663 78.12% 78.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.59% 79.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 171 1.54% 81.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 143 1.29% 82.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 201 1.81% 84.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 144 1.30% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.27% 87.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 106 0.96% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1233 11.12% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8598 78.07% 78.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 170 1.54% 79.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 167 1.52% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 144 1.31% 82.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 198 1.80% 84.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 151 1.37% 85.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 257 2.33% 87.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 107 0.97% 88.91% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1221 11.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11089 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.111793 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.648746 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7080 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 888 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2252 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 11013 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.111230 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.650387 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7023 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 884 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2239 # Number of cycles decode is running system.cpu.decode.UnblockCycles 74 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 795 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 365 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12905 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 444 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 795 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7301 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 305 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 349 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2095 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 244 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12210 # Number of instructions processed by rename +system.cpu.decode.SquashCycles 793 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 359 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12898 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 445 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 793 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7240 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 304 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2086 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12206 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 200 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10547 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19978 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19923 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 201 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10543 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19911 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19856 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5007 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5540 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 5536 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 25 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 515 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2074 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1892 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 518 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2072 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1895 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 60 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 30 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10875 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 62 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9284 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 151 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4827 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4112 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11089 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.837226 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.572881 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 10882 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 61 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 9264 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 154 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4859 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4160 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 11013 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.841188 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.574613 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7692 69.37% 69.37% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1077 9.71% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 744 6.71% 85.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 533 4.81% 90.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 478 4.31% 94.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 322 2.90% 97.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 147 1.33% 99.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 52 0.47% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 44 0.40% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 7627 69.25% 69.25% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1067 9.69% 78.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 747 6.78% 85.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 527 4.79% 90.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 479 4.35% 94.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 323 2.93% 97.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 151 1.37% 99.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 51 0.46% 99.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 41 0.37% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11089 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11013 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.47% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.47% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 76 43.93% 47.40% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 91 52.60% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 6 3.35% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.35% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 80 44.69% 48.04% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 93 51.96% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5734 61.76% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1852 19.95% 81.73% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1696 18.27% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5707 61.60% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.60% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1853 20.00% 81.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1702 18.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9284 # Type of FU issued -system.cpu.iq.rate 0.412842 # Inst issue rate -system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018634 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29919 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15735 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8360 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9264 # Type of FU issued +system.cpu.iq.rate 0.414330 # Inst issue rate +system.cpu.iq.fu_busy_cnt 179 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019322 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29812 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15773 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8347 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9423 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9409 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 65 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1112 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1110 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 846 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 849 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 795 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 113 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10937 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 113 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2074 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1892 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 52 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 793 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 112 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10943 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 107 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2072 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1895 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 89 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 309 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 398 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8754 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1704 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 530 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 311 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 389 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8757 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1710 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3258 # number of memory reference insts executed -system.cpu.iew.exec_branches 1391 # Number of branches executed -system.cpu.iew.exec_stores 1554 # Number of stores executed -system.cpu.iew.exec_rate 0.389274 # Inst execution rate -system.cpu.iew.wb_sent 8553 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8387 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4351 # num instructions producing a value -system.cpu.iew.wb_consumers 7020 # num instructions consuming a value +system.cpu.iew.exec_refs 3276 # number of memory reference insts executed +system.cpu.iew.exec_branches 1382 # Number of branches executed +system.cpu.iew.exec_stores 1566 # Number of stores executed +system.cpu.iew.exec_rate 0.391654 # Inst execution rate +system.cpu.iew.wb_sent 8550 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8374 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4334 # num instructions producing a value +system.cpu.iew.wb_consumers 6981 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.372954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.619801 # average fanout of values written-back +system.cpu.iew.wb_rate 0.374525 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.620828 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 5146 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5152 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 305 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10294 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.563435 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.344775 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 300 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 10220 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.567515 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.347907 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 7857 76.33% 76.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1043 10.13% 86.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 648 6.29% 92.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 255 2.48% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 186 1.81% 97.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 110 1.07% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 58 0.56% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 42 0.41% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 95 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 7783 76.15% 76.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1041 10.19% 86.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 649 6.35% 92.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.50% 95.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 188 1.84% 97.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 108 1.06% 98.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 57 0.56% 98.65% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 45 0.44% 99.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 93 0.91% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10294 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10220 # Number of insts commited each cycle system.cpu.commit.committedInsts 5800 # Number of instructions committed system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -295,68 +295,68 @@ system.cpu.commit.branches 1038 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5706 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 95 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21145 # The number of ROB reads -system.cpu.rob.rob_writes 22688 # The number of ROB writes -system.cpu.timesIdled 217 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11399 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21079 # The number of ROB reads +system.cpu.rob.rob_writes 22698 # The number of ROB writes +system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11346 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5800 # Number of Instructions Simulated system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5800 # Number of Instructions Simulated -system.cpu.cpi 3.877241 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.877241 # CPI: Total CPI of All Threads -system.cpu.ipc 0.257915 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.257915 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13921 # number of integer regfile reads -system.cpu.int_regfile_writes 7265 # number of integer regfile writes +system.cpu.cpi 3.855000 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.855000 # CPI: Total CPI of All Threads +system.cpu.ipc 0.259403 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.259403 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13891 # number of integer regfile reads +system.cpu.int_regfile_writes 7248 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.379391 # Cycle average of tags in use -system.cpu.icache.total_refs 1462 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 172.424294 # Cycle average of tags in use +system.cpu.icache.total_refs 1455 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.118310 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.098592 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.379391 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084170 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084170 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1462 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1462 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1462 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1462 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1462 # number of overall hits -system.cpu.icache.overall_hits::total 1462 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 15734000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 15734000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 15734000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 15734000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.230121 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.230121 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.230121 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 36004.576659 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 36004.576659 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 172.424294 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.084192 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.084192 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1455 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1455 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1455 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1455 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1455 # number of overall hits +system.cpu.icache.overall_hits::total 1455 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses +system.cpu.icache.overall_misses::total 432 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 15599000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 15599000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 15599000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 15599000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.228935 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.228935 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.228935 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.228935 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.228935 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36108.796296 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 36108.796296 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 36108.796296 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 36108.796296 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -365,12 +365,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 82 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 82 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 82 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 82 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 82 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 82 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 77 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 77 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 77 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 77 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 355 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 355 # number of demand (read+write) MSHR misses @@ -383,12 +383,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.186940 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.186940 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.186940 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.188129 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.188129 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.188129 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.188129 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34978.873239 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency @@ -397,14 +397,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 system.cpu.icache.overall_avg_mshr_miss_latency::total 34978.873239 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 63.023619 # Cycle average of tags in use system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks. +system.cpu.dcache.sampled_refs 101 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 21.940594 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015262 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015262 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 63.023619 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015387 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015387 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1486 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1486 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 730 # number of WriteReq hits @@ -413,46 +413,46 @@ system.cpu.dcache.demand_hits::cpu.data 2216 # nu system.cpu.dcache.demand_hits::total 2216 # number of demand (read+write) hits system.cpu.dcache.overall_hits::cpu.data 2216 # number of overall hits system.cpu.dcache.overall_hits::total 2216 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 83 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 83 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 86 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 316 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 316 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 399 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 399 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 399 # number of overall misses -system.cpu.dcache.overall_misses::total 399 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 2993000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 2993000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10587500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10587500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13580500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13580500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13580500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1569 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 402 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 402 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 402 # number of overall misses +system.cpu.dcache.overall_misses::total 402 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3106000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3106000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 10571500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 10571500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13677500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13677500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13677500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1572 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1572 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.052900 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2618 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2618 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2618 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2618 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.054707 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.054707 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.302103 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.152581 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.152581 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36060.240964 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 33504.746835 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 34036.340852 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.153552 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.153552 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.153552 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.153552 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36116.279070 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36116.279070 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33454.113924 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 33454.113924 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 34023.631841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 34023.631841 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -461,58 +461,58 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 32 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 33 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 33 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 268 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 268 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 51 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 301 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 301 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 301 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 48 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 48 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 99 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 99 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032505 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 101 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 101 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 1890500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1748500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 3639000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 3639000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.033715 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.033715 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037859 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037859 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35676.470588 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36468.750000 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36060.606061 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038579 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038579 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35669.811321 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36427.083333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36029.702970 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36029.702970 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.260551 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 403 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012407 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 30.269313 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000924 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006157 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 171.544564 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 30.715987 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005235 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000937 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006173 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits @@ -520,60 +520,60 @@ system.cpu.l2cache.demand_hits::total 5 # nu system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 51 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 401 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 403 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 48 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 48 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 99 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 449 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 451 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 99 # number of overall misses -system.cpu.l2cache.overall_misses::total 449 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12030500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1761000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13791500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1675000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 12030500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3436000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 15466500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 12030500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3436000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 15466500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses +system.cpu.l2cache.overall_misses::total 451 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12033000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1829000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13862000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1674500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 12033000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 3503500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 15536500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 12033000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 3503500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 15536500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 355 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 51 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 48 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 101 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 456 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 101 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 456 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987685 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987745 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.988987 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.989035 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.988987 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34392.768080 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34895.833333 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34446.547884 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34446.547884 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989035 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34380 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34509.433962 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34397.022333 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34885.416667 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34449.002217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34380 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34688.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34449.002217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -583,49 +583,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 51 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 401 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 403 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 99 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 449 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 451 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 99 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 449 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10905000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1600500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12505500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10908500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12570500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1521500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10908500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3183500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 14092000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10908500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3183500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 14092000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987685 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987745 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.988987 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989035 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.988987 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31185.785536 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31687.500000 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31239.420935 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989035 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31167.142857 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31358.490566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31192.307692 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31697.916667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31167.142857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31519.801980 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31246.119734 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index 0e67a0bd3..8da405b24 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:39:51 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:52 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 13973500 because target called exit() +Exiting @ tick 13801000 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 972719e56..3bebb79ad 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,52 +1,52 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13973500 # Number of ticks simulated -final_tick 13973500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13801000 # Number of ticks simulated +final_tick 13801000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 68487 # Simulator instruction rate (inst/s) -host_op_rate 68480 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 74908448 # Simulator tick rate (ticks/s) -host_mem_usage 215960 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 32086 # Simulator instruction rate (inst/s) +host_op_rate 32085 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 34665771 # Simulator tick rate (ticks/s) +host_mem_usage 218816 # Number of bytes of host memory used +host_seconds 0.40 # Real time elapsed on the host sim_insts 12773 # Number of instructions simulated sim_ops 12773 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22592 # Number of bytes read from this memory -system.physmem.bytes_read::total 62784 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40192 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 628 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 353 # Number of read requests responded to by this memory -system.physmem.num_reads::total 981 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2876301571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1616774609 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4493076180 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2876301571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2876301571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1616774609 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 4493076180 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22720 # Number of bytes read from this memory +system.physmem.bytes_read::total 62720 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 355 # Number of read requests responded to by this memory +system.physmem.num_reads::total 980 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 2898340700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1646257518 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4544598218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 2898340700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 2898340700 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 2898340700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1646257518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 4544598218 # Total bandwidth to/from this memory (bytes/s) system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4112 # DTB read hits -system.cpu.dtb.read_misses 99 # DTB read misses +system.cpu.dtb.read_hits 4109 # DTB read hits +system.cpu.dtb.read_misses 91 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4211 # DTB read accesses -system.cpu.dtb.write_hits 2113 # DTB write hits -system.cpu.dtb.write_misses 55 # DTB write misses +system.cpu.dtb.read_accesses 4200 # DTB read accesses +system.cpu.dtb.write_hits 2070 # DTB write hits +system.cpu.dtb.write_misses 61 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2168 # DTB write accesses -system.cpu.dtb.data_hits 6225 # DTB hits -system.cpu.dtb.data_misses 154 # DTB misses +system.cpu.dtb.write_accesses 2131 # DTB write accesses +system.cpu.dtb.data_hits 6179 # DTB hits +system.cpu.dtb.data_misses 152 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6379 # DTB accesses -system.cpu.itb.fetch_hits 5262 # ITB hits -system.cpu.itb.fetch_misses 46 # ITB misses +system.cpu.dtb.data_accesses 6331 # DTB accesses +system.cpu.itb.fetch_hits 5033 # ITB hits +system.cpu.itb.fetch_misses 52 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5308 # ITB accesses +system.cpu.itb.fetch_accesses 5085 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -61,361 +61,360 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 27948 # number of cpu cycles simulated +system.cpu.numCycles 27603 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6404 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3641 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1747 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4779 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 777 # Number of BTB hits +system.cpu.BPredUnit.lookups 6273 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3546 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1676 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 4641 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 749 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 907 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 237 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1564 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 36319 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6404 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1684 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 6095 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1819 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 42 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5262 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 778 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 22184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.637171 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.955550 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 905 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 178 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1498 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 35104 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6273 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1654 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5870 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1752 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5033 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 742 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 21582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.626541 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.950246 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 16089 72.53% 72.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 484 2.18% 74.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 383 1.73% 76.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 489 2.20% 78.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 412 1.86% 80.49% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 381 1.72% 82.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 471 2.12% 84.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 577 2.60% 86.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2898 13.06% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15712 72.80% 72.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 465 2.15% 74.96% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 353 1.64% 76.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 445 2.06% 78.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 412 1.91% 80.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 367 1.70% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 466 2.16% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 577 2.67% 87.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2785 12.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 22184 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.229140 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.299521 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 30972 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4872 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5207 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 530 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2493 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 640 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 419 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 31709 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 698 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2493 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 31718 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 2312 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4929 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1950 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 29261 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1965 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 22098 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36589 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 36555 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 21582 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.227258 # Number of branch fetches per cycle +system.cpu.fetch.rate 1.271746 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 29958 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 5047 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5024 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 472 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2407 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 618 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 398 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 30693 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 650 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2407 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 30628 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2400 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 805 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 4751 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1917 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28414 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 8 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 1949 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21384 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 35492 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 35458 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9166 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12932 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 50 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5419 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2664 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1324 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. +system.cpu.rename.UndoneMaps 12218 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 55 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 5512 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 3 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2650 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1324 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 24 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2635 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1309 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25756 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 47 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21797 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11896 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6581 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 22184 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.982555 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.521995 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 25261 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21461 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11327 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6314 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 21582 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.994393 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.507504 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13300 59.95% 59.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3017 13.60% 73.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2291 10.33% 83.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1563 7.05% 90.93% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1046 4.72% 95.64% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 585 2.64% 98.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 293 1.32% 99.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 70 0.32% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 19 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 12693 58.81% 58.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3009 13.94% 72.76% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2444 11.32% 84.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1529 7.08% 91.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1011 4.68% 95.85% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 561 2.60% 98.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 239 1.11% 99.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 74 0.34% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 22 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 22184 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 21582 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 16 8.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 115 57.50% 65.50% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 69 34.50% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7 3.76% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 115 61.83% 65.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 64 34.41% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7481 68.23% 68.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.25% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2338 21.32% 89.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1141 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7347 68.12% 68.13% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2315 21.46% 89.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1119 10.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10965 # Type of FU issued +system.cpu.iq.FU_type_0::total 10786 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7346 67.82% 67.84% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.86% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2331 21.52% 89.38% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1150 10.62% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7235 67.78% 67.79% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.80% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.82% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2307 21.61% 89.43% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1128 10.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10832 # Type of FU issued +system.cpu.iq.FU_type_1::total 10675 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14827 68.02% 68.04% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 68.05% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 68.05% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.07% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4669 21.42% 89.49% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2291 10.51% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14582 67.95% 67.97% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 67.97% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 67.97% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 67.99% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4622 21.54% 89.53% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2247 10.47% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21797 # Type of FU issued -system.cpu.iq.rate 0.779913 # Inst issue rate +system.cpu.iq.FU_type::total 21461 # Type of FU issued +system.cpu.iq.rate 0.777488 # Inst issue rate system.cpu.iq.fu_busy_cnt::0 93 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 107 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 200 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004267 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004909 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.009176 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 66052 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37703 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19403 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_cnt::1 93 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 186 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004333 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004333 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008667 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 64765 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36642 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19216 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21971 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21621 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 55 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1479 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 459 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1462 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 419 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread1.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1465 # Number of loads squashed -system.cpu.iew.lsq.thread1.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 459 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedLoads 1450 # Number of loads squashed +system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 444 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2493 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 461 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25944 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 945 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5314 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2648 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 47 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 29 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 2407 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 503 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25446 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 693 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5282 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2593 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 33 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 326 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 259 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 1247 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1573 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20270 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2100 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2134 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4234 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1527 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 1506 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20047 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2108 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2105 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4213 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 72 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed -system.cpu.iew.exec_nop::total 141 # number of nop insts executed -system.cpu.iew.exec_refs::0 3199 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3222 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6421 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1640 # Number of branches executed -system.cpu.iew.exec_branches::1 1645 # Number of branches executed -system.cpu.iew.exec_branches::total 3285 # Number of branches executed -system.cpu.iew.exec_stores::0 1099 # Number of stores executed -system.cpu.iew.exec_stores::1 1088 # Number of stores executed -system.cpu.iew.exec_stores::total 2187 # Number of stores executed -system.cpu.iew.exec_rate 0.725276 # Inst execution rate -system.cpu.iew.wb_sent::0 9893 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9800 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19693 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9771 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9652 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19423 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5068 # num instructions producing a value -system.cpu.iew.wb_producers::1 5042 # num instructions producing a value -system.cpu.iew.wb_producers::total 10110 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6625 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6584 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13209 # num instructions consuming a value +system.cpu.iew.exec_nop::0 69 # number of nop insts executed +system.cpu.iew.exec_nop::1 66 # number of nop insts executed +system.cpu.iew.exec_nop::total 135 # number of nop insts executed +system.cpu.iew.exec_refs::0 3190 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3171 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6361 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1643 # Number of branches executed +system.cpu.iew.exec_branches::1 1639 # Number of branches executed +system.cpu.iew.exec_branches::total 3282 # Number of branches executed +system.cpu.iew.exec_stores::0 1082 # Number of stores executed +system.cpu.iew.exec_stores::1 1066 # Number of stores executed +system.cpu.iew.exec_stores::total 2148 # Number of stores executed +system.cpu.iew.exec_rate 0.726262 # Inst execution rate +system.cpu.iew.wb_sent::0 9814 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9693 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19507 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9690 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9546 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19236 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5036 # num instructions producing a value +system.cpu.iew.wb_producers::1 4985 # num instructions producing a value +system.cpu.iew.wb_producers::total 10021 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6558 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6494 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 13052 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.349614 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.345356 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.694969 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.764981 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.765796 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.765387 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.351049 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.345832 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.696881 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.767917 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.767632 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.767775 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 13040 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12581 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1358 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 22111 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.579214 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.379258 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1295 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 21524 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.595010 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.388263 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 16588 75.02% 75.02% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2733 12.36% 87.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1194 5.40% 92.78% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 519 2.35% 95.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 313 1.42% 96.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 257 1.16% 97.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 189 0.85% 98.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 86 0.39% 98.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 232 1.05% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 15949 74.10% 74.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2814 13.07% 87.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1173 5.45% 92.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 493 2.29% 94.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 336 1.56% 96.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 260 1.21% 97.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 183 0.85% 98.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 102 0.47% 99.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 214 0.99% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 22111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 21524 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6403 # Number of instructions committed system.cpu.commit.committedInsts::1 6404 # Number of instructions committed system.cpu.commit.committedInsts::total 12807 # Number of instructions committed @@ -446,78 +445,78 @@ system.cpu.commit.int_insts::total 12642 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 232 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 114163 # The number of ROB reads -system.cpu.rob.rob_writes 54209 # The number of ROB writes -system.cpu.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5764 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 111695 # The number of ROB reads +system.cpu.rob.rob_writes 53212 # The number of ROB writes +system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6021 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6386 # Number of Instructions Simulated system.cpu.committedInsts::1 6387 # Number of Instructions Simulated system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12773 # Number of Instructions Simulated -system.cpu.cpi::0 4.376448 # CPI: Cycles Per Instruction -system.cpu.cpi::1 4.375763 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.188053 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.228496 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.228532 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.457027 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25651 # number of integer regfile reads -system.cpu.int_regfile_writes 14680 # number of integer regfile writes +system.cpu.cpi::0 4.322424 # CPI: Cycles Per Instruction +system.cpu.cpi::1 4.321747 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.161043 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.231352 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.231388 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.462740 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 25345 # number of integer regfile reads +system.cpu.int_regfile_writes 14554 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads system.cpu.misc_regfile_writes 2 # number of misc regfile writes -system.cpu.icache.replacements::0 7 # number of replacements +system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements -system.cpu.icache.replacements::total 7 # number of replacements -system.cpu.icache.tagsinuse 324.653687 # Cycle average of tags in use -system.cpu.icache.total_refs 4369 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 631 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.923930 # Average number of references to valid blocks. +system.cpu.icache.replacements::total 6 # number of replacements +system.cpu.icache.tagsinuse 321.631643 # Cycle average of tags in use +system.cpu.icache.total_refs 4144 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 6.609250 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 324.653687 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.158522 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.158522 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4369 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4369 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4369 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4369 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4369 # number of overall hits -system.cpu.icache.overall_hits::total 4369 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 893 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 893 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 893 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 893 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 893 # number of overall misses -system.cpu.icache.overall_misses::total 893 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 31736000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 31736000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 31736000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 31736000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 31736000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 31736000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5262 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5262 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5262 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5262 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5262 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5262 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.169707 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.169707 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.169707 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.169707 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.169707 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.169707 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35538.633819 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 35538.633819 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 35538.633819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 35538.633819 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 35538.633819 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 321.631643 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.157047 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.157047 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4144 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4144 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4144 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4144 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4144 # number of overall hits +system.cpu.icache.overall_hits::total 4144 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 889 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 889 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 889 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 889 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 889 # number of overall misses +system.cpu.icache.overall_misses::total 889 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 31471500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 31471500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 31471500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 31471500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 31471500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 31471500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5033 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5033 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5033 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5033 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5033 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5033 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.176634 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.176634 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.176634 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.176634 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.176634 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.176634 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35401.012373 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 35401.012373 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 35401.012373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 35401.012373 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 35401.012373 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -532,90 +531,90 @@ system.cpu.icache.demand_mshr_hits::cpu.inst 262 system.cpu.icache.demand_mshr_hits::total 262 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::cpu.inst 262 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 262 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 631 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 631 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 631 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 631 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 631 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 631 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22442500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22442500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22442500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22442500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22442500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22442500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.119916 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.119916 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.119916 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.119916 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35566.561014 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35566.561014 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35566.561014 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 35566.561014 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22341500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22341500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22341500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22341500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.124578 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.124578 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.124578 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.124578 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35632.376396 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35632.376396 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35632.376396 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 35632.376396 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 221.504894 # Cycle average of tags in use -system.cpu.dcache.total_refs 4696 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 353 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.303116 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 221.639601 # Cycle average of tags in use +system.cpu.dcache.total_refs 4700 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 355 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.239437 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 221.504894 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.054078 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.054078 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3676 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3676 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4696 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4696 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4696 # number of overall hits -system.cpu.dcache.overall_hits::total 4696 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 311 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 311 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 710 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 710 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 221.639601 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.054111 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.054111 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3679 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3679 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1021 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1021 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 4700 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4700 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4700 # number of overall hits +system.cpu.dcache.overall_hits::total 4700 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 312 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 312 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 709 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 709 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 1021 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 1021 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 1021 # number of overall misses system.cpu.dcache.overall_misses::total 1021 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11221000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11221000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22533500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22533500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33754500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33754500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33754500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33754500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3987 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3987 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11353000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11353000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22399000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22399000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 33752000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33752000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33752000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33752000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3991 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3991 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5717 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5717 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5717 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5717 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078004 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078004 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.410405 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.178590 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.178590 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.178590 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.178590 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36080.385852 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 36080.385852 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31737.323944 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 31737.323944 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33060.235064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 33060.235064 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 33060.235064 # average overall miss latency +system.cpu.dcache.demand_accesses::cpu.data 5721 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5721 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5721 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5721 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078176 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078176 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409827 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.409827 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.178465 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.178465 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.178465 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.178465 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36387.820513 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 36387.820513 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31592.383639 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 31592.383639 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 33057.786484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 33057.786484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 33057.786484 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -624,121 +623,121 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 102 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 102 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 564 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 564 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 668 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 668 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 668 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 207 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 353 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 353 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7607500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7607500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5291500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 5291500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12899000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12899000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12899000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12899000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051919 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061746 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061746 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061746 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36751.207729 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36751.207729 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36243.150685 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36243.150685 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36541.076487 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 36541.076487 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_hits::cpu.data 666 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 666 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 666 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 666 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7724000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7724000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5248500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5248500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12972500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12972500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12972500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12972500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.052618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.052618 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062052 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062052 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062052 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36780.952381 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 36780.952381 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36196.551724 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36196.551724 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36542.253521 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 36542.253521 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 449.601344 # Cycle average of tags in use -system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 447.061292 # Cycle average of tags in use +system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 835 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.003593 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002395 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 324.972112 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 124.629233 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009917 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003803 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013721 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 628 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 207 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 321.947671 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 125.113621 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009825 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003818 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013643 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.cpu.l2cache.overall_hits::total 2 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 210 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 835 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 628 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 353 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 981 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 628 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 353 # number of overall misses -system.cpu.l2cache.overall_misses::total 981 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21636000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28852000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5063500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5063500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 21636000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12279500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 33915500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 21636000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12279500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 33915500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 631 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 207 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 838 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 631 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 353 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 984 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 631 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 353 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 984 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.995246 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 355 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 980 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 355 # number of overall misses +system.cpu.l2cache.overall_misses::total 980 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 21523000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7330000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28853000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5026500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 5026500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 21523000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12356500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 33879500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21523000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12356500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 33879500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 627 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 837 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 355 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 982 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 355 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 982 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996810 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.996420 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997611 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995246 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.996951 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995246 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997963 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.996951 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34452.229299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34859.903382 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34553.293413 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34681.506849 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34681.506849 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34572.375127 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34452.229299 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34786.118980 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34572.375127 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997963 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34436.800000 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34904.761905 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34554.491018 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34665.517241 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34665.517241 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34570.918367 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34436.800000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34807.042254 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34570.918367 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -747,50 +746,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5250 system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 207 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 835 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 353 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 981 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 353 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 981 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19659500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6570000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26229500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4611000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4611000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19659500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11181000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 30840500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19659500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11181000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 30840500 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 355 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 980 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 355 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 980 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19555500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6675000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26230500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4577500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4577500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19555500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11252500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 30808000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19555500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11252500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 30808000 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.996420 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997611 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.996951 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995246 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997963 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.996951 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31304.936306 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31739.130435 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31412.574850 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.191781 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.191781 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31304.936306 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31674.220963 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31437.818552 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997963 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31288.800000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31785.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31413.772455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31568.965517 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31568.965517 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31288.800000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31697.183099 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31436.734694 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index f0f4b69ef..c81e9ca95 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:02 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:53:48 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Begining test of difficult SPARC instructions... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 19744500 because target called exit() +Exiting @ tick 19806500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index a887522dd..52156950f 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19744500 # Number of ticks simulated -final_tick 19744500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 19806500 # Number of ticks simulated +final_tick 19806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 74885 # Simulator instruction rate (inst/s) -host_op_rate 74878 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 102311932 # Simulator tick rate (ticks/s) -host_mem_usage 222004 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 96556 # Simulator instruction rate (inst/s) +host_op_rate 96545 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 132327745 # Simulator tick rate (ticks/s) +host_mem_usage 221008 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 14449 # Number of instructions simulated sim_ops 14449 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory @@ -19,251 +19,251 @@ system.physmem.bytes_inst_read::total 21632 # Nu system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 484 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1095596242 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 473245714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1568841956 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1095596242 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1095596242 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 473245714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1568841956 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092166713 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 471764320 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1563931033 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092166713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092166713 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092166713 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 471764320 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1563931033 # Total bandwidth to/from this memory (bytes/s) system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 39490 # number of cpu cycles simulated +system.cpu.numCycles 39614 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6899 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4560 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1119 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5346 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2573 # Number of BTB hits +system.cpu.BPredUnit.lookups 6890 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4576 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5201 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2595 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 464 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 172 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11886 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32156 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6899 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3037 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9512 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3178 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 6896 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 459 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 11869 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32300 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6890 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3054 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9560 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3188 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 6935 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 726 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5506 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 480 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 30987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.037725 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.210162 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 5516 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 469 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 31065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.039755 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.210803 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 21475 69.30% 69.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4729 15.26% 84.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 477 1.54% 86.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 446 1.44% 87.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 688 2.22% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 747 2.41% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 238 0.77% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 276 0.89% 93.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1911 6.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 21505 69.23% 69.23% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4746 15.28% 84.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 494 1.59% 86.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 444 1.43% 87.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 682 2.20% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 763 2.46% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 240 0.77% 92.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 277 0.89% 93.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1914 6.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 30987 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.174702 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.814282 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12512 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 7643 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8680 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 189 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1963 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29984 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13183 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 245 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 6907 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8245 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 444 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27285 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 121 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24368 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 50732 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 50732 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 31065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.173928 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.815368 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 12513 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 7669 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8722 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 190 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1971 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30088 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1971 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13189 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 248 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 6922 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8283 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 452 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27408 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 125 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24445 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50953 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50953 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13832 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10536 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10613 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 705 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 708 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2853 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3628 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2841 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3647 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2469 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23083 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 663 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21701 # Number of instructions issued +system.cpu.iq.iqInstsAdded 23180 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 670 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21761 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8350 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5831 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 188 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 30987 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.700326 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.316293 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 8457 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5919 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 195 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 31065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.700499 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.316624 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 21563 69.59% 69.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3594 11.60% 81.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2382 7.69% 88.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1729 5.58% 94.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 896 2.89% 97.34% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 479 1.55% 98.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 250 0.81% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 75 0.24% 99.94% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 21619 69.59% 69.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3603 11.60% 81.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2384 7.67% 88.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1730 5.57% 94.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 898 2.89% 97.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 488 1.57% 98.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 252 0.81% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 72 0.23% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 30987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 31065 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 54 30.17% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 30.17% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.53% 44.69% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 99 55.31% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 54 29.19% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.19% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.05% 43.24% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 105 56.76% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16032 73.88% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.88% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3432 15.81% 89.69% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2237 10.31% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16056 73.78% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.78% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3441 15.81% 89.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2264 10.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21701 # Type of FU issued -system.cpu.iq.rate 0.549532 # Inst issue rate -system.cpu.iq.fu_busy_cnt 179 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008248 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 74673 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32122 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19916 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21761 # Type of FU issued +system.cpu.iq.rate 0.549326 # Inst issue rate +system.cpu.iq.fu_busy_cnt 185 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008501 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 74877 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32333 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19979 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21880 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21946 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1402 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1421 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 1021 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1971 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 144 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24909 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3628 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 663 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 25018 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 406 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3647 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2469 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 670 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 956 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20511 # Number of executed instructions +system.cpu.iew.predictedTakenIncorrect 291 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 962 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1253 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20571 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 3278 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 1190 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1163 # number of nop insts executed -system.cpu.iew.exec_refs 5392 # number of memory reference insts executed -system.cpu.iew.exec_branches 4300 # Number of branches executed -system.cpu.iew.exec_stores 2114 # Number of stores executed -system.cpu.iew.exec_rate 0.519397 # Inst execution rate -system.cpu.iew.wb_sent 20186 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19916 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9270 # num instructions producing a value -system.cpu.iew.wb_consumers 11399 # num instructions consuming a value +system.cpu.iew.exec_nop 1168 # number of nop insts executed +system.cpu.iew.exec_refs 5421 # number of memory reference insts executed +system.cpu.iew.exec_branches 4301 # Number of branches executed +system.cpu.iew.exec_stores 2143 # Number of stores executed +system.cpu.iew.exec_rate 0.519286 # Inst execution rate +system.cpu.iew.wb_sent 20246 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19979 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9281 # num instructions producing a value +system.cpu.iew.wb_consumers 11411 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504330 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.813229 # average fanout of values written-back +system.cpu.iew.wb_rate 0.504342 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.813338 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions -system.cpu.commit.commitSquashedInsts 9652 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9761 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1119 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29041 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.522537 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.206609 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 29111 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521281 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.203804 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 21661 74.59% 74.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 4067 14.00% 88.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1430 4.92% 93.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 794 2.73% 96.25% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 339 1.17% 97.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 260 0.90% 98.31% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 321 1.11% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 68 0.23% 99.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 101 0.35% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21721 74.61% 74.61% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4069 13.98% 88.59% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1444 4.96% 93.55% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 793 2.72% 96.28% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 337 1.16% 97.43% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 258 0.89% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 320 1.10% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 71 0.24% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 98 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29041 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 29111 # Number of insts commited each cycle system.cpu.commit.committedInsts 15175 # Number of instructions committed system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -274,68 +274,68 @@ system.cpu.commit.branches 3359 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12186 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 52944 # The number of ROB reads -system.cpu.rob.rob_writes 51625 # The number of ROB writes -system.cpu.timesIdled 185 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8503 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 53126 # The number of ROB reads +system.cpu.rob.rob_writes 51851 # The number of ROB writes +system.cpu.timesIdled 186 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 8549 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14449 # Number of Instructions Simulated system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14449 # Number of Instructions Simulated -system.cpu.cpi 2.733061 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.733061 # CPI: Total CPI of All Threads -system.cpu.ipc 0.365890 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.365890 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32680 # number of integer regfile reads -system.cpu.int_regfile_writes 18187 # number of integer regfile writes -system.cpu.misc_regfile_reads 7045 # number of misc regfile reads +system.cpu.cpi 2.741643 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.741643 # CPI: Total CPI of All Threads +system.cpu.ipc 0.364745 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.364745 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32757 # number of integer regfile reads +system.cpu.int_regfile_writes 18209 # number of integer regfile writes +system.cpu.misc_regfile_reads 7073 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 200.774248 # Cycle average of tags in use -system.cpu.icache.total_refs 5020 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 201.055469 # Cycle average of tags in use +system.cpu.icache.total_refs 5034 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 340 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.764706 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 14.805882 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 200.774248 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.098034 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.098034 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5020 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5020 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5020 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5020 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5020 # number of overall hits -system.cpu.icache.overall_hits::total 5020 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 486 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 486 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 486 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 486 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 486 # number of overall misses -system.cpu.icache.overall_misses::total 486 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 16725500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 16725500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 16725500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 16725500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 16725500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 16725500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5506 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5506 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5506 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5506 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5506 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.088267 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.088267 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.088267 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.088267 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.088267 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.088267 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34414.609053 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 34414.609053 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 34414.609053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 34414.609053 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 34414.609053 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 201.055469 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.098172 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.098172 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5034 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5034 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5034 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5034 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5034 # number of overall hits +system.cpu.icache.overall_hits::total 5034 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 482 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 482 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 482 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 482 # number of overall misses +system.cpu.icache.overall_misses::total 482 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 16634500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 16634500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 16634500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 16634500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 16634500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 16634500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5516 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5516 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5516 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5516 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5516 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.087382 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.087382 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.087382 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.087382 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.087382 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.087382 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34511.410788 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 34511.410788 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 34511.410788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 34511.410788 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 34511.410788 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,12 +344,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 142 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 142 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 142 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 142 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 142 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 142 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses @@ -362,12 +362,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11937500 system.cpu.icache.demand_mshr_miss_latency::total 11937500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11937500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 11937500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061751 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.061751 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061751 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.061751 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.061639 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.061639 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.061639 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.061639 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35110.294118 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35110.294118 # average overall mshr miss latency @@ -376,66 +376,66 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35110.294118 system.cpu.icache.overall_avg_mshr_miss_latency::total 35110.294118 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 103.476464 # Cycle average of tags in use -system.cpu.dcache.total_refs 4083 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 103.574586 # Cycle average of tags in use +system.cpu.dcache.total_refs 4084 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.965753 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 27.972603 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 103.476464 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025263 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025263 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3043 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3043 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 103.574586 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025287 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025287 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3044 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3044 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1034 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1034 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4077 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4077 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4077 # number of overall hits -system.cpu.dcache.overall_hits::total 4077 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 118 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 118 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4078 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4078 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4078 # number of overall hits +system.cpu.dcache.overall_hits::total 4078 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 116 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 116 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 408 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 408 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 526 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 526 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 526 # number of overall misses -system.cpu.dcache.overall_misses::total 526 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4092500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4092500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14593500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14593500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 18686000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 18686000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 18686000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 18686000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3161 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3161 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 524 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 524 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 524 # number of overall misses +system.cpu.dcache.overall_misses::total 524 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4022000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4022000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14592500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14592500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18614500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18614500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18614500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18614500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3160 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3160 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4603 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4603 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4603 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4603 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.037330 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.037330 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 4602 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4602 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4602 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4602 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.036709 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.036709 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282940 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.282940 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.114273 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.114273 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.114273 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.114273 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34682.203390 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 34682.203390 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35768.382353 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35768.382353 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 35524.714829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35524.714829 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35524.714829 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.113864 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.113864 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.113864 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.113864 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34672.413793 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 34672.413793 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35765.931373 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35765.931373 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 35523.854962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35523.854962 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35523.854962 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -444,14 +444,14 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 53 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 325 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 325 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 380 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 380 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 380 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 380 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 378 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 378 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 378 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 378 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -462,40 +462,40 @@ system.cpu.dcache.overall_mshr_misses::cpu.data 146 system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2979500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2979500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5223000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5223000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5223000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019930 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019930 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2978500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2978500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5222000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5222000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5222000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5222000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.019937 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.019937 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031718 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031718 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031718 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031725 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031725 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031725 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35611.111111 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35611.111111 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35897.590361 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35897.590361 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35773.972603 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35773.972603 # average overall mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35885.542169 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35885.542169 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35767.123288 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 35767.123288 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 236.259194 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 236.586962 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004988 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 200.029408 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 36.229787 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006104 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001106 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 200.308921 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 36.278041 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.006113 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001107 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.007220 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -513,17 +513,17 @@ system.cpu.l2cache.demand_misses::total 484 # nu system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses system.cpu.l2cache.overall_misses::total 484 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11582500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11581500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2169000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13751500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13750500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2869000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2869000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11582500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 11581500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 5038000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16620500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11582500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 16619500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 11581500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 5038000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16620500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 16619500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) @@ -546,17 +546,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995885 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994118 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995885 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34267.751479 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34264.792899 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34428.571429 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34293.017456 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 34290.523691 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34566.265060 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34566.265060 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34339.876033 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34267.751479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 34337.809917 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34264.792899 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34506.849315 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34339.876033 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 34337.809917 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -576,17 +576,17 @@ system.cpu.l2cache.demand_mshr_misses::total 484 system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10497000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1968500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12465500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10495000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1969500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12464500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2607500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2607500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10497000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4576000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15073000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10497000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4576000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15073000 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10495000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15072000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10495000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15072000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995037 # mshr miss rate for ReadReq accesses @@ -598,17 +598,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995885 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994118 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995885 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31056.213018 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31086.034913 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050.295858 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31261.904762 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31083.541147 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31415.662651 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31415.662651 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31056.213018 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31342.465753 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31142.561983 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050.295858 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31140.495868 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 51784eba5..b2cdd54e1 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,82 +1,82 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:14 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done -[Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 Iteration 1 completed -[Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 3, Thread 2] Got lock [Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 Iteration 3 completed +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3 Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 -[Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 Iteration 5 completed -[Iteration 6, Thread 3] Got lock -[Iteration 6, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 6, Thread 1] Got lock -[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 6, Thread 2] Got lock -[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 Iteration 6 completed [Iteration 7, Thread 1] Got lock [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock -[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 [Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 3] Got lock -[Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock [Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 111402500 because target called exit() +Exiting @ tick 111594500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 1590e3eee..ea1876230 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,191 +1,191 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000111 # Number of seconds simulated -sim_ticks 111402500 # Number of ticks simulated -final_tick 111402500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000112 # Number of seconds simulated +sim_ticks 111594500 # Number of ticks simulated +final_tick 111594500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 133234 # Simulator instruction rate (inst/s) -host_op_rate 133234 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 13628365 # Simulator tick rate (ticks/s) -host_mem_usage 236536 # Number of bytes of host memory used -host_seconds 8.17 # Real time elapsed on the host -sim_insts 1089093 # Number of instructions simulated -sim_ops 1089093 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 23232 # Number of bytes read from this memory +host_inst_rate 200629 # Simulator instruction rate (inst/s) +host_op_rate 200629 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20568067 # Simulator tick rate (ticks/s) +host_mem_usage 235024 # Number of bytes of host memory used +host_seconds 5.43 # Real time elapsed on the host +sim_insts 1088531 # Number of instructions simulated +sim_ops 1088531 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::cpu0.inst 23104 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10816 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 5120 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 5632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 43072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 23232 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 29312 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 363 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 42880 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 23104 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 5632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 29120 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu0.inst 361 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 169 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 80 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 88 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 673 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 208541101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 97089383 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 8042907 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 45959471 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 11489868 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 574493 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7468414 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 386634052 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208541101 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 8042907 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 45959471 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 574493 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 263117973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208541101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 97089383 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 8042907 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 45959471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 11489868 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 574493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7468414 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 386634052 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_reads::total 670 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu0.inst 207035293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 96922339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 50468437 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 11470099 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1147010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2294020 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7455565 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 384248328 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 207035293 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 50468437 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1147010 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2294020 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 260944760 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 207035293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 96922339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 50468437 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 11470099 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1147010 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2294020 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7455565 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 384248328 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 222806 # number of cpu cycles simulated +system.cpu0.numCycles 223190 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 87253 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 84917 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 1303 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 84794 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 82358 # Number of BTB hits +system.cpu0.BPredUnit.lookups 87370 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 85036 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1313 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 84895 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 82517 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 518 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 136 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 17579 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 517995 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 87253 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 82876 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 170053 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3992 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13261 # Number of cycles fetch has spent blocked +system.cpu0.BPredUnit.usedRAS 514 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 17415 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 518858 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 87370 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 83031 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 170328 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 4037 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13330 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1318 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 6218 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 521 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.529816 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.210666 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1404 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 6152 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 508 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.530311 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.210840 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 34703 16.95% 16.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 84234 41.14% 58.09% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 594 0.29% 58.38% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 959 0.47% 58.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 591 0.29% 59.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 80169 39.15% 98.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 594 0.29% 98.58% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 373 0.18% 98.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2539 1.24% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34729 16.94% 16.94% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 84380 41.15% 58.09% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 595 0.29% 58.38% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 973 0.47% 58.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 523 0.26% 59.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 80298 39.16% 98.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 656 0.32% 98.58% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 373 0.18% 98.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2530 1.23% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 204756 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391610 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.324870 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18003 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14874 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 169024 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 315 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2540 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 515001 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2540 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18709 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 1371 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12822 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 168665 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 649 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 511590 # Number of instructions processed by rename +system.cpu0.fetch.rateDist::total 205057 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391460 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.324737 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 18107 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14779 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 169274 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 322 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2575 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 515764 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2575 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18814 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 1415 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12654 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 168925 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 674 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 512400 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 235 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 349678 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 1020456 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 1020456 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 335896 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13782 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 911 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 939 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 4054 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 163918 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 82754 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 79985 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 79744 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 427655 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 948 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 424795 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 156 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11264 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 10234 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 389 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 204756 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.074640 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.085274 # Number of insts issued each cycle +system.cpu0.rename.LSQFullEvents 252 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 350257 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 1022076 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 1022076 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 336320 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13937 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 921 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 951 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4116 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 164196 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 82879 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 80125 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 79869 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 428350 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 958 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 425359 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11411 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10569 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 399 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205057 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.074345 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.084750 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33869 16.54% 16.54% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5212 2.55% 19.09% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 81806 39.95% 59.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 81161 39.64% 98.68% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1586 0.77% 99.45% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 710 0.35% 99.80% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 306 0.15% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33897 16.53% 16.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5266 2.57% 19.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 81920 39.95% 59.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 81274 39.63% 98.68% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1599 0.78% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 693 0.34% 99.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 302 0.15% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 90 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 16 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 204756 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205057 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 53 21.81% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 21.81% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 78 32.10% 53.91% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 46.09% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 54 22.69% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 72 30.25% 52.94% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 112 47.06% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 179222 42.19% 42.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 179447 42.19% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.19% # Type of FU issued @@ -214,159 +214,159 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.19% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.19% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 163383 38.46% 80.65% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 82190 19.35% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 163633 38.47% 80.66% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 82279 19.34% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 424795 # Type of FU issued -system.cpu0.iq.rate 1.906569 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 243 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000572 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 1054745 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 439928 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 422836 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.FU_type_0::total 425359 # Type of FU issued +system.cpu0.iq.rate 1.905816 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 238 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000560 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 1056189 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 440777 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 423418 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 425038 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 425597 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 79492 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 79599 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2386 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2452 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 61 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1482 # Number of stores squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 58 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1501 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2540 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 996 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 509141 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 346 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 163918 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 82754 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 837 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 38 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 2575 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1020 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 41 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 509980 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 329 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 164196 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 82879 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 846 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 43 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 61 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 382 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 1141 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 1523 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 423658 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 163081 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1137 # Number of squashed instructions skipped in execute +system.cpu0.iew.memOrderViolationEvents 58 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 368 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1157 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1525 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 424238 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 163317 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1121 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 80538 # number of nop insts executed -system.cpu0.iew.exec_refs 245123 # number of memory reference insts executed -system.cpu0.iew.exec_branches 84187 # Number of branches executed -system.cpu0.iew.exec_stores 82042 # Number of stores executed -system.cpu0.iew.exec_rate 1.901466 # Inst execution rate -system.cpu0.iew.wb_sent 423189 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 422836 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 250585 # num instructions producing a value -system.cpu0.iew.wb_consumers 253105 # num instructions consuming a value +system.cpu0.iew.exec_nop 80672 # number of nop insts executed +system.cpu0.iew.exec_refs 245449 # number of memory reference insts executed +system.cpu0.iew.exec_branches 84313 # Number of branches executed +system.cpu0.iew.exec_stores 82132 # Number of stores executed +system.cpu0.iew.exec_rate 1.900793 # Inst execution rate +system.cpu0.iew.wb_sent 423777 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 423418 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 250898 # num instructions producing a value +system.cpu0.iew.wb_consumers 253433 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.897777 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.990044 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.897119 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989997 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitCommittedInsts 496189 # The number of committed instructions -system.cpu0.commit.commitCommittedOps 496189 # The number of committed instructions -system.cpu0.commit.commitSquashedInsts 12929 # The number of squashed insts skipped by commit +system.cpu0.commit.commitCommittedInsts 496825 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 496825 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 13135 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 1303 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202233 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.453551 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.134267 # Number of insts commited each cycle +system.cpu0.commit.branchMispredicts 1313 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202499 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.453469 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.133222 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 34442 17.03% 17.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 83893 41.48% 58.51% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2396 1.18% 59.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 690 0.34% 60.04% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 548 0.27% 60.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 79225 39.18% 99.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 480 0.24% 99.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 324 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 34446 17.01% 17.01% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 84010 41.49% 58.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2422 1.20% 59.69% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 711 0.35% 60.04% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 562 0.28% 60.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 79343 39.18% 99.50% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 465 0.23% 99.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 235 0.12% 99.85% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 305 0.15% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202233 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 496189 # Number of instructions committed -system.cpu0.commit.committedOps 496189 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202499 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 496825 # Number of instructions committed +system.cpu0.commit.committedOps 496825 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 242804 # Number of memory references committed -system.cpu0.commit.loads 161532 # Number of loads committed +system.cpu0.commit.refs 243122 # Number of memory references committed +system.cpu0.commit.loads 161744 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 83160 # Number of branches committed +system.cpu0.commit.branches 83266 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 334226 # Number of committed integer instructions. +system.cpu0.commit.int_insts 334650 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 324 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 305 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 709866 # The number of ROB reads -system.cpu0.rob.rob_writes 1020791 # The number of ROB writes -system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 18050 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 416214 # Number of Instructions Simulated -system.cpu0.committedOps 416214 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 416214 # Number of Instructions Simulated -system.cpu0.cpi 0.535316 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535316 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.868056 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.868056 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 757980 # number of integer regfile reads -system.cpu0.int_regfile_writes 341432 # number of integer regfile writes +system.cpu0.rob.rob_reads 710993 # The number of ROB reads +system.cpu0.rob.rob_writes 1022511 # The number of ROB writes +system.cpu0.timesIdled 324 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 18133 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 416744 # Number of Instructions Simulated +system.cpu0.committedOps 416744 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 416744 # Number of Instructions Simulated +system.cpu0.cpi 0.535557 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535557 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.867216 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.867216 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 758967 # number of integer regfile reads +system.cpu0.int_regfile_writes 341941 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 246952 # number of misc regfile reads +system.cpu0.misc_regfile_reads 247293 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes -system.cpu0.icache.replacements 300 # number of replacements -system.cpu0.icache.tagsinuse 248.673809 # Cycle average of tags in use -system.cpu0.icache.total_refs 5459 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 593 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.205734 # Average number of references to valid blocks. +system.cpu0.icache.replacements 307 # number of replacements +system.cpu0.icache.tagsinuse 248.147409 # Cycle average of tags in use +system.cpu0.icache.total_refs 5393 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 598 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.018395 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 248.673809 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.485691 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5459 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5459 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5459 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5459 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5459 # number of overall hits -system.cpu0.icache.overall_hits::total 5459 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 248.147409 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.484663 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5393 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5393 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5393 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5393 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5393 # number of overall hits +system.cpu0.icache.overall_hits::total 5393 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 759 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 759 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 759 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 759 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 759 # number of overall misses system.cpu0.icache.overall_misses::total 759 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 29159500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 29159500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 29159500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 29159500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 29159500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 6218 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6218 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 6218 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6218 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 6218 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.122065 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.122065 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.122065 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.122065 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.122065 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38418.313570 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38418.313570 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38418.313570 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38418.313570 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 28913000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 28913000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 28913000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 28913000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 28913000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 6152 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6152 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 6152 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6152 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 6152 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.123375 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.123375 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.123375 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.123375 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.123375 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38093.544137 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38093.544137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38093.544137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38093.544137 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -375,106 +375,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 165 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 165 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 165 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 594 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 594 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 594 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 594 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 594 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21891000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21891000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21891000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.095529 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.095529 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.095529 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36853.535354 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36853.535354 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36853.535354 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 160 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 160 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 160 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 160 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 160 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 599 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 599 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 599 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 21855500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 21855500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21855500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.097367 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.097367 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.097367 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36486.644407 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36486.644407 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36486.644407 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 8 # number of replacements -system.cpu0.dcache.tagsinuse 141.285775 # Cycle average of tags in use -system.cpu0.dcache.total_refs 100453 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 577.316092 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 144.541703 # Cycle average of tags in use +system.cpu0.dcache.total_refs 163878 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 171 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 958.350877 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.285775 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275949 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 83026 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 83026 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 80684 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 80684 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 163710 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 163710 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 163710 # number of overall hits -system.cpu0.dcache.overall_hits::total 163710 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 495 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 495 # number of ReadReq misses +system.cpu0.dcache.occ_blocks::cpu0.data 144.541703 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.282308 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 83150 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 83150 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 80790 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 80790 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 163940 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 163940 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 163940 # number of overall hits +system.cpu0.dcache.overall_hits::total 163940 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 500 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 500 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 546 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 546 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 20 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 20 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1041 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1041 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1041 # number of overall misses -system.cpu0.dcache.overall_misses::total 1041 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 13976000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24361986 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 380500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 380500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38337986 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38337986 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38337986 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 83521 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 81230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 81230 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1046 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1046 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1046 # number of overall misses +system.cpu0.dcache.overall_misses::total 1046 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 13780500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24368986 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 390500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38149486 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38149486 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38149486 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 83650 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 81336 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 81336 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 164751 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 164751 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 164751 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 164751 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.005927 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006722 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.476190 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006319 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.006319 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006319 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006319 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28234.343434 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44619.021978 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19025 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 19025 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36828.036503 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 36828.036503 # average overall miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 164986 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 164986 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 164986 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 164986 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.005977 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.006713 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006340 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006340 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006340 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006340 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27561 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27561 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 44631.842491 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 18595.238095 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 36471.783939 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 36471.783939 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 194000 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked @@ -483,476 +483,476 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs 10210.526316 system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 313 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 313 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 370 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 370 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 683 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 182 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 182 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 176 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 176 # number of WriteReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 20 # number of SwapReq MSHR misses -system.cpu0.dcache.SwapReq_mshr_misses::total 20 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4954500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6250000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 320500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11204500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11204500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002179 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002167 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.476190 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002173 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002173 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27222.527473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35511.363636 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 16025 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31297.486034 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31297.486034 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 320 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 320 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 371 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 371 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 691 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 180 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 180 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 175 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 175 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4933000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6275500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 327500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11208500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11208500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002152 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002152 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002152 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002152 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 27405.555556 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35860 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 15595.238095 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31573.239437 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31573.239437 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 187393 # number of cpu cycles simulated +system.cpu1.numCycles 187839 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 57495 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 54509 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 1432 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 50945 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 49902 # Number of BTB hits +system.cpu1.BPredUnit.lookups 50940 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 47890 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 1510 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 44289 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 43310 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 759 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.usedRAS 829 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 28506 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 323137 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 57495 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 50661 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4204 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 33253 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 31688 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 280910 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 50940 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 44139 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 100869 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4392 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 39081 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6513 # Number of stall cycles due to no active thread to fetch from -system.cpu1.fetch.PendingTrapStallCycles 1058 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 19809 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.750206 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.168540 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.NoActiveThreadStallCycles 6575 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 1045 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 22757 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.542894 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.098462 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 72029 39.01% 39.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 57027 30.89% 69.90% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 6026 3.26% 73.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3313 1.79% 74.96% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 681 0.37% 75.33% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 39928 21.63% 96.95% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1176 0.64% 97.59% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 885 0.48% 98.07% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3563 1.93% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 81198 44.60% 44.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 51887 28.50% 73.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7438 4.09% 77.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3280 1.80% 78.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 684 0.38% 79.36% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 31924 17.53% 96.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1209 0.66% 97.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 879 0.48% 98.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3568 1.96% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 184628 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.306815 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.724381 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 34082 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 29678 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 106549 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 5112 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2694 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 318863 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2694 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 34823 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 15756 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 13064 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 101771 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 10007 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 316589 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 26 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 63 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 221379 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 610170 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 610170 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 206274 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15105 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1171 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1292 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 12551 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 90746 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 43396 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 43483 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 38230 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 262560 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 6300 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 264126 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 64 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 12570 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 11522 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 184628 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.430585 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.313833 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 182067 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.271190 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.495483 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 38413 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 34373 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 93637 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 6265 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2804 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 276803 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2804 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 39183 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 19194 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14318 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 87661 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 12332 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 274424 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 52 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 191179 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 520245 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 520245 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 175779 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15400 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1221 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1348 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 15085 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 76182 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 35431 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 36807 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 30214 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 225638 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 7711 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 228522 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 12774 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 11561 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 762 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 182067 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.255153 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.306407 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 69552 37.67% 37.67% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 22561 12.22% 49.89% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 43412 23.51% 73.40% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 44019 23.84% 97.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3358 1.82% 99.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1272 0.69% 99.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 343 0.19% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 54 0.03% 99.97% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 78861 43.31% 43.31% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 26436 14.52% 57.83% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 35607 19.56% 77.39% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 36159 19.86% 97.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3279 1.80% 99.05% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1252 0.69% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 353 0.19% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 59 0.03% 99.97% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 184628 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 182067 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 21 6.65% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.65% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 85 26.90% 33.54% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 66.46% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 20 6.62% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 6.62% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 72 23.84% 30.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 69.54% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 126488 47.89% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 94921 35.94% 83.83% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 42717 16.17% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 112122 49.06% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.06% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 81642 35.73% 84.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 34758 15.21% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 264126 # Type of FU issued -system.cpu1.iq.rate 1.409476 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 316 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001196 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 713260 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 281477 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 262161 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 228522 # Type of FU issued +system.cpu1.iq.rate 1.216584 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 302 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001322 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 639493 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 246163 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 226488 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 264442 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 228824 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 37998 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 30049 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2692 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 47 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1591 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2733 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 40 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1566 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2694 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1681 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 49 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 313238 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 90746 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 43396 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1094 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 45 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2804 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1582 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 271136 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 377 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 76182 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 35431 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1144 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 47 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 484 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 1109 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1593 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 262830 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 89694 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1296 # Number of squashed instructions skipped in execute +system.cpu1.iew.memOrderViolationEvents 40 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 494 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 1182 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1676 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 227186 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 75112 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1336 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 44378 # number of nop insts executed -system.cpu1.iew.exec_refs 132319 # number of memory reference insts executed -system.cpu1.iew.exec_branches 53738 # Number of branches executed -system.cpu1.iew.exec_stores 42625 # Number of stores executed -system.cpu1.iew.exec_rate 1.402560 # Inst execution rate -system.cpu1.iew.wb_sent 262446 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 262161 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 149144 # num instructions producing a value -system.cpu1.iew.wb_consumers 154061 # num instructions consuming a value +system.cpu1.iew.exec_nop 37787 # number of nop insts executed +system.cpu1.iew.exec_refs 109780 # number of memory reference insts executed +system.cpu1.iew.exec_branches 47145 # Number of branches executed +system.cpu1.iew.exec_stores 34668 # Number of stores executed +system.cpu1.iew.exec_rate 1.209472 # Inst execution rate +system.cpu1.iew.wb_sent 226789 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 226488 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 126631 # num instructions producing a value +system.cpu1.iew.wb_consumers 131515 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.398990 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.968084 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.205756 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.962864 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitCommittedInsts 298843 # The number of committed instructions -system.cpu1.commit.commitCommittedOps 298843 # The number of committed instructions -system.cpu1.commit.commitSquashedInsts 14389 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 5646 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1432 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 175422 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.703566 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.044466 # Number of insts commited each cycle +system.cpu1.commit.commitCommittedInsts 256347 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 256347 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 14788 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 6949 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1510 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 172689 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.484443 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.966336 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 68710 39.17% 39.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 51651 29.44% 68.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6180 3.52% 72.14% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6549 3.73% 75.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1541 0.88% 76.75% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 38344 21.86% 98.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 640 0.36% 98.97% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 995 0.57% 99.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 79222 45.88% 45.88% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 45065 26.10% 71.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6173 3.57% 75.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 7849 4.55% 80.09% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1517 0.88% 80.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 30495 17.66% 98.63% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 550 0.32% 98.95% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 998 0.58% 99.53% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 820 0.47% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 175422 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 298843 # Number of instructions committed -system.cpu1.commit.committedOps 298843 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 172689 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 256347 # Number of instructions committed +system.cpu1.commit.committedOps 256347 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 129859 # Number of memory references committed -system.cpu1.commit.loads 88054 # Number of loads committed -system.cpu1.commit.membars 4938 # Number of memory barriers committed -system.cpu1.commit.branches 52708 # Number of branches committed +system.cpu1.commit.refs 107314 # Number of memory references committed +system.cpu1.commit.loads 73449 # Number of loads committed +system.cpu1.commit.membars 6235 # Number of memory barriers committed +system.cpu1.commit.branches 46061 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 204694 # Number of committed integer instructions. +system.cpu1.commit.int_insts 175498 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 820 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 487255 # The number of ROB reads -system.cpu1.rob.rob_writes 629168 # The number of ROB writes +system.cpu1.rob.rob_reads 442417 # The number of ROB reads +system.cpu1.rob.rob_writes 545088 # The number of ROB writes system.cpu1.timesIdled 232 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 2765 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35411 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 250401 # Number of Instructions Simulated -system.cpu1.committedOps 250401 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 250401 # Number of Instructions Simulated -system.cpu1.cpi 0.748372 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748372 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.336235 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.336235 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 456552 # number of integer regfile reads -system.cpu1.int_regfile_writes 212248 # number of integer regfile writes +system.cpu1.idleCycles 5772 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35349 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 213261 # Number of Instructions Simulated +system.cpu1.committedOps 213261 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 213261 # Number of Instructions Simulated +system.cpu1.cpi 0.880794 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.880794 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.135339 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.135339 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 389025 # number of integer regfile reads +system.cpu1.int_regfile_writes 181950 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 133945 # number of misc regfile reads +system.cpu1.misc_regfile_reads 111436 # number of misc regfile reads system.cpu1.misc_regfile_writes 646 # number of misc regfile writes -system.cpu1.icache.replacements 322 # number of replacements -system.cpu1.icache.tagsinuse 82.769076 # Cycle average of tags in use -system.cpu1.icache.total_refs 19304 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 435 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.377011 # Average number of references to valid blocks. +system.cpu1.icache.replacements 321 # number of replacements +system.cpu1.icache.tagsinuse 92.166456 # Cycle average of tags in use +system.cpu1.icache.total_refs 22247 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 51.025229 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 82.769076 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.161658 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 19304 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 19304 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 19304 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 19304 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 19304 # number of overall hits -system.cpu1.icache.overall_hits::total 19304 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 505 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 505 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 505 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 505 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 505 # number of overall misses -system.cpu1.icache.overall_misses::total 505 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7500500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7500500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7500500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7500500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7500500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 19809 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 19809 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 19809 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 19809 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 19809 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.025493 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025493 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.025493 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025493 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.025493 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14852.475248 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14852.475248 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14852.475248 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14852.475248 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 92.166456 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.180013 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 22247 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22247 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22247 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22247 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22247 # number of overall hits +system.cpu1.icache.overall_hits::total 22247 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 510 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 510 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 510 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 510 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 510 # number of overall misses +system.cpu1.icache.overall_misses::total 510 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 11347500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 11347500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 11347500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 11347500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 11347500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 22757 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 22757 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 22757 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 22757 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 22757 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022411 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022411 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022411 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022411 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022411 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 22250 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 22250 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 22250 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 22250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 22250 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 22250 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 70 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 70 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 70 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 70 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 435 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 435 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 435 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 435 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 435 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5474500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5474500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5474500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5474500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5474500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.021960 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.021960 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.021960 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.021960 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12585.057471 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.057471 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12585.057471 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 74 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 74 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 74 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 74 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 436 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 436 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 436 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8591500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8591500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8591500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8591500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8591500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8591500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.019159 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.019159 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.019159 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.019159 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19705.275229 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19705.275229 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19705.275229 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 24.070551 # Cycle average of tags in use -system.cpu1.dcache.total_refs 48111 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1603.700000 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 27.650583 # Cycle average of tags in use +system.cpu1.dcache.total_refs 40148 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1384.413793 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 24.070551 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.047013 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.047013 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 51204 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 51204 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 41589 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 41589 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 92793 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 92793 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 92793 # number of overall hits -system.cpu1.dcache.overall_hits::total 92793 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 475 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 475 # number of ReadReq misses +system.cpu1.dcache.occ_blocks::cpu1.data 27.650583 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054005 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054005 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 44622 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 44622 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 33643 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 33643 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 78265 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 78265 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 78265 # number of overall hits +system.cpu1.dcache.overall_hits::total 78265 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 425 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 425 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 154 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 154 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 629 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 629 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 629 # number of overall misses -system.cpu1.dcache.overall_misses::total 629 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9635500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 9635500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2967500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2967500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1038500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 1038500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 12603000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 12603000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 12603000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 12603000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 51679 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 51679 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 41743 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 41743 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 93422 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 93422 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 93422 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 93422 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009191 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.009191 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003689 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.003689 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006733 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.006733 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006733 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.006733 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20285.263158 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20285.263158 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19269.480519 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19269.480519 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 20770 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 20770 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20036.565978 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20036.565978 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20036.565978 # average overall miss latency +system.cpu1.dcache.SwapReq_misses::cpu1.data 52 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 52 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 579 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 579 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 579 # number of overall misses +system.cpu1.dcache.overall_misses::total 579 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 9294500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 9294500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3142500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3142500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 1219000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 1219000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 12437000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 12437000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 12437000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 12437000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 45047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 45047 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 33797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 33797 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 78844 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 78844 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 78844 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 78844 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009435 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.009435 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004557 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.004557 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.764706 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.764706 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007344 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.007344 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007344 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.007344 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21869.411765 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 21869.411765 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 20405.844156 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 20405.844156 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 23442.307692 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 23442.307692 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21480.138169 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21480.138169 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21480.138169 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -961,476 +961,474 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 319 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 319 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 45 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 364 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 156 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 109 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 265 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2052000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1523500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 888500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3575500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3575500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003019 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002611 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002837 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002837 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13153.846154 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13977.064220 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 17770 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13492.452830 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13492.452830 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 266 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 266 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 47 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 313 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 313 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 313 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 159 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 159 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 52 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 52 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 266 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2405000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1693500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 1063000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4098500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4098500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003530 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.003166 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.764706 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.003374 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.003374 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15125.786164 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15827.102804 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 20442.307692 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15407.894737 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15407.894737 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 187102 # number of cpu cycles simulated +system.cpu2.numCycles 187552 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.BPredUnit.lookups 52366 # Number of BP lookups -system.cpu2.BPredUnit.condPredicted 49346 # Number of conditional branches predicted -system.cpu2.BPredUnit.condIncorrect 1501 # Number of conditional branches incorrect -system.cpu2.BPredUnit.BTBLookups 45884 # Number of BTB lookups -system.cpu2.BPredUnit.BTBHits 44697 # Number of BTB hits +system.cpu2.BPredUnit.lookups 49236 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 46105 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 1532 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 42466 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 41429 # Number of BTB hits system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.BPredUnit.usedRAS 764 # Number of times the RAS was used to get a target. -system.cpu2.BPredUnit.RASInCorrect 230 # Number of incorrect RAS predictions. -system.cpu2.fetch.icacheStallCycles 30829 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 289891 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 52366 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 45461 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 103159 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 4491 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 37226 # Number of cycles fetch has spent blocked +system.cpu2.BPredUnit.usedRAS 825 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 33274 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 268508 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 49236 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42254 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 98143 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 4464 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 42536 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6501 # Number of stall cycles due to no active thread to fetch from -system.cpu2.fetch.PendingTrapStallCycles 1096 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 21870 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 331 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.595192 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.120038 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.NoActiveThreadStallCycles 6571 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 1082 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 24716 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 294 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.455596 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.059567 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 78569 43.23% 43.23% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 52779 29.04% 72.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 6971 3.84% 76.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3518 1.94% 78.05% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 702 0.39% 78.44% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 33444 18.40% 96.84% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1229 0.68% 97.51% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 914 0.50% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3602 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 86323 46.80% 46.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 50944 27.62% 74.41% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 8337 4.52% 78.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3301 1.79% 80.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 755 0.41% 81.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 29086 15.77% 96.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1170 0.63% 97.53% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 883 0.48% 98.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3667 1.99% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 181728 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.279879 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.549374 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 37176 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 32970 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 96308 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 5861 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2912 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 285362 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2912 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 37970 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 18336 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 13742 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 90714 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 11553 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 283108 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 56 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 197373 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 538438 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 538438 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 181356 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 16017 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1193 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1308 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 14181 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 79045 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 36977 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 38155 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 31746 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 233020 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 7475 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 234915 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 13691 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 12875 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 913 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 181728 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.292674 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.310296 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 184466 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.262519 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.431646 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 41063 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 36807 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89946 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 7224 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2855 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 264281 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2855 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 41843 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 22202 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 13743 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 82992 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 14260 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 261668 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 57 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 181221 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 490993 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 490993 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 165322 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 15899 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1233 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1350 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 17036 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 71489 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 32632 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 34884 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 27362 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 213682 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 8649 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 217360 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 13263 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11908 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 765 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 184466 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.178320 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.292872 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 76657 42.18% 42.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 25237 13.89% 56.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 37132 20.43% 76.50% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 37732 20.76% 97.27% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3274 1.80% 99.07% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1229 0.68% 99.74% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 84063 45.57% 45.57% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 29277 15.87% 61.44% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 32764 17.76% 79.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 33297 18.05% 97.25% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3312 1.80% 99.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1277 0.69% 99.74% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 362 0.20% 99.94% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 181728 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 184466 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 21 6.69% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.69% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 83 26.43% 33.12% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 66.88% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 20 6.64% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 6.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 71 23.59% 30.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 114779 48.86% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.86% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 83862 35.70% 84.56% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 36274 15.44% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107542 49.48% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.48% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77871 35.83% 85.30% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 31947 14.70% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 234915 # Type of FU issued -system.cpu2.iq.rate 1.255545 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 314 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001337 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 651945 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 254231 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 232815 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 217360 # Type of FU issued +system.cpu2.iq.rate 1.158932 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001385 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 619541 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 235636 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 215243 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 235229 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 217661 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 31545 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 27206 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 3013 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2801 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1611 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 42 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1615 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2912 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 1924 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 279572 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 369 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 79045 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 36977 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1114 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2855 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 1726 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 258195 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 386 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 71489 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 32632 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1140 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 517 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 1138 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1655 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 233532 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 77718 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1383 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 42 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 1199 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1712 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 215982 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 70400 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1378 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 39077 # number of nop insts executed -system.cpu2.iew.exec_refs 113896 # number of memory reference insts executed -system.cpu2.iew.exec_branches 48223 # Number of branches executed -system.cpu2.iew.exec_stores 36178 # Number of stores executed -system.cpu2.iew.exec_rate 1.248153 # Inst execution rate -system.cpu2.iew.wb_sent 233124 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 232815 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 130712 # num instructions producing a value -system.cpu2.iew.wb_consumers 135609 # num instructions consuming a value +system.cpu2.iew.exec_nop 35864 # number of nop insts executed +system.cpu2.iew.exec_refs 102255 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45260 # Number of branches executed +system.cpu2.iew.exec_stores 31855 # Number of stores executed +system.cpu2.iew.exec_rate 1.151585 # Inst execution rate +system.cpu2.iew.wb_sent 215555 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 215243 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 119078 # num instructions producing a value +system.cpu2.iew.wb_consumers 124002 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.244321 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.963889 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.147644 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.960291 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitCommittedInsts 263733 # The number of committed instructions -system.cpu2.commit.commitCommittedOps 263733 # The number of committed instructions -system.cpu2.commit.commitSquashedInsts 15844 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 6562 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1501 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 172316 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.530520 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.983884 # Number of insts commited each cycle +system.cpu2.commit.commitCommittedInsts 242999 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 242999 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 15188 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7884 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1532 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 175041 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.388240 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.921152 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 76563 44.43% 44.43% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 46194 26.81% 71.24% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6230 3.62% 74.85% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 7466 4.33% 79.19% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1536 0.89% 80.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 32043 18.60% 98.67% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 480 0.28% 98.95% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 990 0.57% 99.53% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 814 0.47% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 85384 48.78% 48.78% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43145 24.65% 73.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6226 3.56% 76.98% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 8763 5.01% 81.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1523 0.87% 82.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 27601 15.77% 98.63% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 589 0.34% 98.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 998 0.57% 99.54% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 812 0.46% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 172316 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 263733 # Number of instructions committed -system.cpu2.commit.committedOps 263733 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 175041 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 242999 # Number of instructions committed +system.cpu2.commit.committedOps 242999 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 111398 # Number of memory references committed -system.cpu2.commit.loads 76032 # Number of loads committed -system.cpu2.commit.membars 5840 # Number of memory barriers committed -system.cpu2.commit.branches 47167 # Number of branches committed +system.cpu2.commit.refs 99705 # Number of memory references committed +system.cpu2.commit.loads 68688 # Number of loads committed +system.cpu2.commit.membars 7170 # Number of memory barriers committed +system.cpu2.commit.branches 44148 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 180680 # Number of committed integer instructions. +system.cpu2.commit.int_insts 165976 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 814 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 450492 # The number of ROB reads -system.cpu2.rob.rob_writes 562082 # The number of ROB writes -system.cpu2.timesIdled 233 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 5374 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35702 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 219944 # Number of Instructions Simulated -system.cpu2.committedOps 219944 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 219944 # Number of Instructions Simulated -system.cpu2.cpi 0.850680 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.850680 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.175530 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.175530 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 401453 # number of integer regfile reads -system.cpu2.int_regfile_writes 187612 # number of integer regfile writes +system.cpu2.rob.rob_reads 431829 # The number of ROB reads +system.cpu2.rob.rob_writes 519243 # The number of ROB writes +system.cpu2.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 3086 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 200891 # Number of Instructions Simulated +system.cpu2.committedOps 200891 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 200891 # Number of Instructions Simulated +system.cpu2.cpi 0.933601 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.933601 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.071122 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.071122 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 366578 # number of integer regfile reads +system.cpu2.int_regfile_writes 171642 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 115545 # number of misc regfile reads +system.cpu2.misc_regfile_reads 103931 # number of misc regfile reads system.cpu2.misc_regfile_writes 646 # number of misc regfile writes -system.cpu2.icache.replacements 325 # number of replacements -system.cpu2.icache.tagsinuse 91.851117 # Cycle average of tags in use -system.cpu2.icache.total_refs 21358 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 440 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 48.540909 # Average number of references to valid blocks. +system.cpu2.icache.replacements 324 # number of replacements +system.cpu2.icache.tagsinuse 83.306019 # Cycle average of tags in use +system.cpu2.icache.total_refs 24210 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 438 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 55.273973 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 91.851117 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.179397 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 21358 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 21358 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 21358 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 21358 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 21358 # number of overall hits -system.cpu2.icache.overall_hits::total 21358 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 512 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 512 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 512 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 512 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 512 # number of overall misses -system.cpu2.icache.overall_misses::total 512 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 11141500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 11141500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 11141500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 11141500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 11141500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 21870 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 21870 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 21870 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 21870 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 21870 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.023411 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.023411 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.023411 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.023411 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.023411 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21760.742188 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 21760.742188 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 21760.742188 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21760.742188 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 21760.742188 # average overall miss latency -system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked +system.cpu2.icache.occ_blocks::cpu2.inst 83.306019 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.162707 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.162707 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 24210 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 24210 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 24210 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 24210 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 24210 # number of overall hits +system.cpu2.icache.overall_hits::total 24210 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 506 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 506 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 506 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 506 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 506 # number of overall misses +system.cpu2.icache.overall_misses::total 506 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 7060500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 7060500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 7060500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 7060500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 7060500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 7060500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 24716 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 24716 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 24716 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 24716 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 24716 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 24716 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.020473 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.020473 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.020473 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.020473 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.020473 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.020473 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13953.557312 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13953.557312 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13953.557312 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13953.557312 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs 33000 # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 72 # number of ReadReq MSHR hits -system.cpu2.icache.ReadReq_mshr_hits::total 72 # number of ReadReq MSHR hits -system.cpu2.icache.demand_mshr_hits::cpu2.inst 72 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits -system.cpu2.icache.overall_mshr_hits::cpu2.inst 72 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_hits::total 72 # number of overall MSHR hits -system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 440 # number of ReadReq MSHR misses -system.cpu2.icache.ReadReq_mshr_misses::total 440 # number of ReadReq MSHR misses -system.cpu2.icache.demand_mshr_misses::cpu2.inst 440 # number of demand (read+write) MSHR misses -system.cpu2.icache.demand_mshr_misses::total 440 # number of demand (read+write) MSHR misses -system.cpu2.icache.overall_mshr_misses::cpu2.inst 440 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_misses::total 440 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 8467000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 8467000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 8467000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 8467000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8467000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 8467000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.020119 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.020119 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.020119 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.020119 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 19243.181818 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 19243.181818 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 19243.181818 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 68 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 68 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 438 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 438 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 438 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 438 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 438 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5136000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5136000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5136000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5136000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5136000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5136000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017721 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.017721 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017721 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.017721 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11726.027397 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11726.027397 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11726.027397 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 26.720433 # Cycle average of tags in use -system.cpu2.dcache.total_refs 41712 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1345.548387 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 24.973314 # Cycle average of tags in use +system.cpu2.dcache.total_refs 37203 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1328.678571 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 26.720433 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.052188 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.052188 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 45716 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 45716 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 35144 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 35144 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 24.973314 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.048776 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.048776 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42731 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42731 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 30798 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 30798 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 14 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 80860 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 80860 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 80860 # number of overall hits -system.cpu2.dcache.overall_hits::total 80860 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 438 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 438 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 146 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 146 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 62 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 62 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 584 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 584 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 584 # number of overall misses -system.cpu2.dcache.overall_misses::total 584 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 10255000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 10255000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2937000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2937000 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1181000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 1181000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 13192000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 13192000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 46154 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 46154 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 35290 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 35290 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 76 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 76 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 81444 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 81444 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 81444 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 81444 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009490 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.009490 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004137 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004137 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.815789 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.815789 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007171 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.007171 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007171 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.007171 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23413.242009 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 23413.242009 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20116.438356 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 20116.438356 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 19048.387097 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 19048.387097 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 22589.041096 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 22589.041096 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 22589.041096 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 73529 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 73529 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 73529 # number of overall hits +system.cpu2.dcache.overall_hits::total 73529 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 443 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 443 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 151 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 151 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 54 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 54 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 594 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 594 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 594 # number of overall misses +system.cpu2.dcache.overall_misses::total 594 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 9862000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 9862000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2806000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2806000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 1173500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 1173500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 12668000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 12668000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 12668000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 12668000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43174 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43174 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 30949 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74123 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74123 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74123 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74123 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.010261 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004879 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794118 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008014 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.008014 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008014 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.008014 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 22261.851016 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18582.781457 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 21731.481481 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 21326.599327 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 21326.599327 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1439,368 +1437,366 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 267 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 45 # number of WriteReq MSHR hits -system.cpu2.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 312 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 312 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 312 # number of overall MSHR hits -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 171 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 62 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 272 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2480000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1516500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 995000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3996500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3996500 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003705 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.002862 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.815789 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003340 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003340 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14502.923977 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15014.851485 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 16048.387097 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14693.014706 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14693.014706 # average overall mshr miss latency +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 279 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 279 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 47 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 47 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 326 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 326 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 326 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 164 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 104 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 54 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 268 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 268 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 268 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2336000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1419000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 1011500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3755000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3755000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003799 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003360 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794118 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003616 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003616 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 14243.902439 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13644.230769 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 18731.481481 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14011.194030 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14011.194030 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 186832 # number of cpu cycles simulated +system.cpu3.numCycles 187286 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 49447 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 46344 # Number of conditional branches predicted -system.cpu3.BPredUnit.condIncorrect 1525 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 42752 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 41712 # Number of BTB hits +system.cpu3.BPredUnit.lookups 59110 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 55955 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 1573 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 52456 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 51388 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.BPredUnit.usedRAS 813 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.usedRAS 831 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.fetch.icacheStallCycles 32933 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 270157 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 49447 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 42525 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 98584 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 4439 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 41922 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 27555 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 332776 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 59110 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 52219 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 115081 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 4575 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 31846 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6509 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 1070 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 24454 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 317 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.469347 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.064581 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6567 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 1060 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 19062 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 312 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.798352 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.183167 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 85278 46.38% 46.38% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 51117 27.80% 74.18% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 8231 4.48% 78.66% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3382 1.84% 80.50% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 704 0.38% 80.88% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 29457 16.02% 96.90% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1168 0.64% 97.54% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 877 0.48% 98.02% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3648 1.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 69964 37.81% 37.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 58012 31.35% 69.16% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 5498 2.97% 72.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3553 1.92% 74.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 717 0.39% 74.44% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 41629 22.50% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1211 0.65% 97.59% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 858 0.46% 98.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3603 1.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 183862 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.264660 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.445989 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 40520 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 36424 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 90525 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 7045 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2839 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 265643 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2839 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 41308 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 21637 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 13915 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 83785 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13869 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 263122 # Number of instructions processed by rename -system.cpu3.rename.IQFullEvents 18 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 51 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 182223 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 494224 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 494224 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 166723 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 15500 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1230 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1367 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 16602 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 72088 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 32971 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 35168 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 27743 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 215022 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 8560 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 218529 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 12998 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 11805 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 824 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 183862 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.188549 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.293380 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 185045 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.315614 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.776833 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 32638 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 28853 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 109537 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 4519 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2931 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 328437 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2931 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 33475 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 14026 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 13970 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 105232 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 8844 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 325744 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 59 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 228226 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 629601 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 629601 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 212325 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 15901 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1261 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1383 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 11670 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 93735 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 45116 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 44692 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 39822 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 270564 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 6038 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 271349 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 117 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 13410 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 12382 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 838 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 185045 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.466395 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.313251 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 83207 45.26% 45.26% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 28783 15.65% 60.91% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 33187 18.05% 78.96% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 33716 18.34% 97.30% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3245 1.76% 99.06% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1264 0.69% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 353 0.19% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 50 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 67828 36.65% 36.65% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 21223 11.47% 48.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 45218 24.44% 72.56% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 45760 24.73% 97.29% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3300 1.78% 99.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1261 0.68% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 341 0.18% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 61 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 183862 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 185045 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 21 7.02% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 7.02% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 68 22.74% 29.77% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 21 6.80% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 6.80% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 78 25.24% 32.04% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 67.96% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 107929 49.39% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.39% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 78286 35.82% 85.21% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 32314 14.79% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 129621 47.77% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.77% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 97351 35.88% 83.65% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 44377 16.35% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 218529 # Type of FU issued -system.cpu3.iq.rate 1.169655 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001368 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 621265 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 236621 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 216530 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 271349 # Type of FU issued +system.cpu3.iq.rate 1.448848 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 309 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001139 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 728169 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 290051 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 269261 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 218828 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 271658 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 27592 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 39639 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2778 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2895 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 6 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 41 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1562 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 39 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1672 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2839 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 1746 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 259780 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 389 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 72088 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 32971 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1143 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 55 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewSquashCycles 2931 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 1690 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 60 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 322365 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 383 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 93735 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 45116 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1181 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 62 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 41 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 513 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 1186 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1699 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 217228 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 70964 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1301 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 39 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 528 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 1218 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1746 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 269989 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 92559 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1360 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 36198 # number of nop insts executed -system.cpu3.iew.exec_refs 103196 # number of memory reference insts executed -system.cpu3.iew.exec_branches 45494 # Number of branches executed -system.cpu3.iew.exec_stores 32232 # Number of stores executed -system.cpu3.iew.exec_rate 1.162692 # Inst execution rate -system.cpu3.iew.wb_sent 216841 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 216530 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 119982 # num instructions producing a value -system.cpu3.iew.wb_consumers 124874 # num instructions consuming a value +system.cpu3.iew.exec_nop 45763 # number of nop insts executed +system.cpu3.iew.exec_refs 136843 # number of memory reference insts executed +system.cpu3.iew.exec_branches 55022 # Number of branches executed +system.cpu3.iew.exec_stores 44284 # Number of stores executed +system.cpu3.iew.exec_rate 1.441587 # Inst execution rate +system.cpu3.iew.wb_sent 269584 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 269261 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 153664 # num instructions producing a value +system.cpu3.iew.wb_consumers 158539 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.158956 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.960825 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.437700 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.969250 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitCommittedInsts 244729 # The number of committed instructions -system.cpu3.commit.commitCommittedOps 244729 # The number of committed instructions -system.cpu3.commit.commitSquashedInsts 15046 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7736 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1525 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 174515 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.402338 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.927125 # Number of insts commited each cycle +system.cpu3.commit.commitCommittedInsts 306791 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 306791 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 15574 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 5200 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1573 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 175548 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.747619 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.056560 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 84328 48.32% 48.32% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 43439 24.89% 73.21% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6199 3.55% 76.76% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8632 4.95% 81.71% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1540 0.88% 82.59% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 28042 16.07% 98.66% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 531 0.30% 98.97% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 992 0.57% 99.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 812 0.47% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 66312 37.77% 37.77% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 53003 30.19% 67.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6220 3.54% 71.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 6065 3.45% 74.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1526 0.87% 75.83% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 40098 22.84% 98.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 522 0.30% 98.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 989 0.56% 99.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 813 0.46% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 174515 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 244729 # Number of instructions committed -system.cpu3.commit.committedOps 244729 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 175548 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 306791 # Number of instructions committed +system.cpu3.commit.committedOps 306791 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 100719 # Number of memory references committed -system.cpu3.commit.loads 69310 # Number of loads committed -system.cpu3.commit.membars 7019 # Number of memory barriers committed -system.cpu3.commit.branches 44389 # Number of branches committed +system.cpu3.commit.refs 134284 # Number of memory references committed +system.cpu3.commit.loads 90840 # Number of loads committed +system.cpu3.commit.membars 4481 # Number of memory barriers committed +system.cpu3.commit.branches 53890 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 167227 # Number of committed integer instructions. +system.cpu3.commit.int_insts 210289 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 813 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 432891 # The number of ROB reads -system.cpu3.rob.rob_writes 522404 # The number of ROB writes -system.cpu3.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 2970 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 35972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 202534 # Number of Instructions Simulated -system.cpu3.committedOps 202534 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 202534 # Number of Instructions Simulated -system.cpu3.cpi 0.922472 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.922472 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.084043 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.084043 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 369217 # number of integer regfile reads -system.cpu3.int_regfile_writes 172842 # number of integer regfile writes +system.cpu3.rob.rob_reads 496513 # The number of ROB reads +system.cpu3.rob.rob_writes 647676 # The number of ROB writes +system.cpu3.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 2241 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 35902 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 257635 # Number of Instructions Simulated +system.cpu3.committedOps 257635 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 257635 # Number of Instructions Simulated +system.cpu3.cpi 0.726943 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.726943 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.375623 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.375623 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 470214 # number of integer regfile reads +system.cpu3.int_regfile_writes 218594 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 104868 # number of misc regfile reads +system.cpu3.misc_regfile_reads 138505 # number of misc regfile reads system.cpu3.misc_regfile_writes 646 # number of misc regfile writes -system.cpu3.icache.replacements 320 # number of replacements -system.cpu3.icache.tagsinuse 85.923076 # Cycle average of tags in use -system.cpu3.icache.total_refs 23951 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 432 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 55.442130 # Average number of references to valid blocks. +system.cpu3.icache.replacements 322 # number of replacements +system.cpu3.icache.tagsinuse 87.207959 # Cycle average of tags in use +system.cpu3.icache.total_refs 18566 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 436 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 42.582569 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 85.923076 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.167819 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 23951 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 23951 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 23951 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 23951 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 23951 # number of overall hits -system.cpu3.icache.overall_hits::total 23951 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 503 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 503 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 503 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 503 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 503 # number of overall misses -system.cpu3.icache.overall_misses::total 503 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6843000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6843000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6843000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6843000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6843000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 24454 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 24454 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 24454 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 24454 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 24454 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020569 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020569 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020569 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020569 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020569 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13604.373757 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13604.373757 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13604.373757 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13604.373757 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 87.207959 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.170328 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.170328 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 18566 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 18566 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 18566 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 18566 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 18566 # number of overall hits +system.cpu3.icache.overall_hits::total 18566 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 496 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 496 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 496 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 496 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 496 # number of overall misses +system.cpu3.icache.overall_misses::total 496 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6966500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6966500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6966500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6966500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6966500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 19062 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 19062 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 19062 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 19062 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 19062 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.026020 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.026020 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.026020 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.026020 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.026020 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.026020 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14045.362903 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14045.362903 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14045.362903 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14045.362903 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14045.362903 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1809,106 +1805,106 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 71 # number of ReadReq MSHR hits -system.cpu3.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits -system.cpu3.icache.demand_mshr_hits::cpu3.inst 71 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits -system.cpu3.icache.overall_mshr_hits::cpu3.inst 71 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_hits::total 71 # number of overall MSHR hits -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 432 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 432 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 432 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 432 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 432 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4912000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4912000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4912000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4912000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017666 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.017666 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017666 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.017666 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11370.370370 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11370.370370 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11370.370370 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 60 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 60 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 60 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 60 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 60 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 436 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 436 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 436 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 436 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 436 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 5084500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 5084500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 5084500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 5084500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 5084500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 5084500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022873 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.022873 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022873 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.022873 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11661.697248 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11661.697248 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11661.697248 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 25.290478 # Cycle average of tags in use -system.cpu3.dcache.total_refs 37716 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1257.200000 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 26.205436 # Cycle average of tags in use +system.cpu3.dcache.total_refs 49620 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1772.142857 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.290478 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.049395 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.049395 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 42933 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 42933 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 31189 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 31189 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 74122 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 74122 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 74122 # number of overall hits -system.cpu3.dcache.overall_hits::total 74122 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 420 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 420 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 149 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 149 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 57 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 569 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 569 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 569 # number of overall misses -system.cpu3.dcache.overall_misses::total 569 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8616000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 8616000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 3007500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 3007500 # number of WriteReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1198000 # number of SwapReq miss cycles -system.cpu3.dcache.SwapReq_miss_latency::total 1198000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 11623500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 11623500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 11623500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 11623500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 43353 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 43353 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 31338 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 31338 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 74691 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 74691 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 74691 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 74691 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.009688 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.009688 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004755 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.004755 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.007618 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.007618 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.007618 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.007618 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20514.285714 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 20514.285714 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20184.563758 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 20184.563758 # average WriteReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 21017.543860 # average SwapReq miss latency -system.cpu3.dcache.SwapReq_avg_miss_latency::total 21017.543860 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 20427.943761 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 20427.943761 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 20427.943761 # average overall miss latency +system.cpu3.dcache.occ_blocks::cpu3.data 26.205436 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.051182 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.051182 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 52477 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 52477 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 43221 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 43221 # number of WriteReq hits +system.cpu3.dcache.SwapReq_hits::cpu3.data 12 # number of SwapReq hits +system.cpu3.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu3.dcache.demand_hits::cpu3.data 95698 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 95698 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 95698 # number of overall hits +system.cpu3.dcache.overall_hits::total 95698 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 424 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 424 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 150 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 150 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 61 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 61 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 574 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 574 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 574 # number of overall misses +system.cpu3.dcache.overall_misses::total 574 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 8617000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 8617000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2850000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2850000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 1161500 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 1161500 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 11467000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 11467000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 11467000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 11467000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 52901 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 52901 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 43371 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 43371 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 73 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 96272 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 96272 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 96272 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 96272 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008015 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.008015 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003459 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.003459 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.835616 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.835616 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005962 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005962 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005962 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005962 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20323.113208 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 20323.113208 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19000 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 19000 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 19040.983607 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 19040.983607 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 19977.351916 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 19977.351916 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 19977.351916 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1917,298 +1913,288 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 257 # number of ReadReq MSHR hits -system.cpu3.dcache.ReadReq_mshr_hits::total 257 # number of ReadReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 45 # number of WriteReq MSHR hits -system.cpu3.dcache.WriteReq_mshr_hits::total 45 # number of WriteReq MSHR hits -system.cpu3.dcache.demand_mshr_hits::cpu3.data 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_hits::total 302 # number of demand (read+write) MSHR hits -system.cpu3.dcache.overall_mshr_hits::cpu3.data 302 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_hits::total 302 # number of overall MSHR hits -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 264 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 46 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 46 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 310 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 310 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 310 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 310 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 160 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 160 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 57 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 57 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 267 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 267 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 267 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2151000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2151000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1621000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1621000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 1027000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 1027000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3772000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3772000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3772000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3772000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003760 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003760 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003319 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.802817 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.003575 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.003575 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13196.319018 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13196.319018 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15586.538462 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15586.538462 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 18017.543860 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 18017.543860 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14127.340824 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14127.340824 # average overall mshr miss latency +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 61 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 61 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 264 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 264 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 264 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1797000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1797000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1508500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1508500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 978500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.SwapReq_mshr_miss_latency::total 978500 # number of SwapReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3305500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3305500 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3305500 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3305500 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003025 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003025 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002398 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002398 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.835616 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.835616 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.002742 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002742 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.002742 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 11231.250000 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 11231.250000 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 14504.807692 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 14504.807692 # average WriteReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 16040.983607 # average SwapReq mshr miss latency +system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 16040.983607 # average SwapReq mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 12520.833333 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 12520.833333 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 441.136869 # Cycle average of tags in use -system.l2c.total_refs 1471 # Total number of references to valid blocks. -system.l2c.sampled_refs 544 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.704044 # Average number of references to valid blocks. +system.l2c.tagsinuse 436.530480 # Cycle average of tags in use +system.l2c.total_refs 1479 # Total number of references to valid blocks. +system.l2c.sampled_refs 536 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.759328 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 4.878414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 294.783080 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.595754 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 9.493651 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 0.732946 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 64.319288 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 5.723296 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.834559 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.775880 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000074 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.004498 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000909 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000145 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000011 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000981 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000087 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000013 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 0.840422 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 294.533073 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.606311 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 70.480803 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.728880 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.673039 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.734409 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.156423 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.777117 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004494 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000910 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.001075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000087 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000026 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.inst 0.000033 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006731 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 231 # number of ReadReq hits +system.l2c.occ_percent::total 0.006661 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 238 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 420 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 13 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 355 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 7 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 430 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1474 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.ReadReq_hits::cpu1.inst 347 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 431 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1479 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 238 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 420 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 355 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 7 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 430 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits -system.l2c.demand_hits::total 1474 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 231 # number of overall hits +system.l2c.demand_hits::cpu1.inst 347 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 431 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 431 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::total 1479 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 238 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 420 # number of overall hits -system.l2c.overall_hits::cpu1.data 13 # number of overall hits -system.l2c.overall_hits::cpu2.inst 355 # number of overall hits -system.l2c.overall_hits::cpu2.data 7 # number of overall hits -system.l2c.overall_hits::cpu3.inst 430 # number of overall hits -system.l2c.overall_hits::cpu3.data 13 # number of overall hits -system.l2c.overall_hits::total 1474 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 363 # number of ReadReq misses +system.l2c.overall_hits::cpu1.inst 347 # number of overall hits +system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu2.inst 431 # number of overall hits +system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu3.inst 431 # number of overall hits +system.l2c.overall_hits::cpu3.data 11 # number of overall hits +system.l2c.overall_hits::total 1479 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 361 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 75 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 85 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 89 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 7 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.inst 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 549 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 22 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 21 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 80 # number of UpgradeReq misses +system.l2c.ReadReq_misses::total 546 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 23 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 81 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 363 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 361 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.data 169 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 85 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 89 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 680 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 363 # number of overall misses +system.l2c.demand_misses::total 677 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.inst 361 # number of overall misses system.l2c.overall_misses::cpu0.data 169 # number of overall misses -system.l2c.overall_misses::cpu1.inst 15 # number of overall misses -system.l2c.overall_misses::cpu1.data 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 85 # number of overall misses -system.l2c.overall_misses::cpu2.data 20 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 89 # number of overall misses +system.l2c.overall_misses::cpu1.data 20 # number of overall misses +system.l2c.overall_misses::cpu2.inst 7 # number of overall misses +system.l2c.overall_misses::cpu2.data 13 # number of overall misses +system.l2c.overall_misses::cpu3.inst 5 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 680 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 18919500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 3929500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 744500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 4376000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 366000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 99500 # number of ReadReq miss cycles +system.l2c.overall_misses::total 677 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.inst 18817000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 3930500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4612000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 366000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 304000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 52500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 254000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 52500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 28540000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 52500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 52500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3.data 52500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 157500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 4939500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 680500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3.data 627500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6875000 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.inst 18919500 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::total 28388500 # number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 4938500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 681500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 629500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 628000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6877500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18817000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8869000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 744500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 4376000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1046500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 99500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 680000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 35415000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.inst 18919500 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4612000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1047500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 304000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 682000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 254000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 680500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 35266000 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 18817000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8869000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 744500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 4376000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1046500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 99500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 680000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 35415000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.inst 594 # number of ReadReq accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 4612000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1047500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 304000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 682000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 254000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 680500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 35266000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.inst 599 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 80 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 435 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 14 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 440 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 432 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2023 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 25 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 83 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 438 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 436 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2025 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 26 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 84 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 594 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 599 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 174 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 435 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 440 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 432 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 26 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2154 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 594 # number of overall (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 438 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.inst 436 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2156 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 599 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 174 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 435 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 440 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 432 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2154 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.611111 # miss rate for ReadReq accesses +system.l2c.overall_accesses::cpu1.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 438 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 436 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2156 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.602671 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.937500 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.034483 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.071429 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.193182 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.500000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.004630 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.271379 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.880000 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.204128 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.015982 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.011468 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269630 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.884615 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.963855 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.964286 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.611111 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.602671 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971264 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.034483 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.500000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.193182 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.740741 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.004630 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.315692 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.611111 # miss rate for overall accesses +system.l2c.demand_miss_rate::cpu1.inst 0.204128 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.015982 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.011468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314007 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.602671 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971264 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.034483 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.500000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.193182 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.740741 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.004630 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.315692 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52119.834711 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52393.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49633.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51482.352941 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 52285.714286 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49750 # average ReadReq miss latency +system.l2c.overall_miss_rate::cpu1.inst 0.204128 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.015982 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.011468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314007 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52124.653740 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52406.666667 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51820.224719 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52285.714286 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 43428.571429 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 52500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 50800 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 52500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51985.428051 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 2500 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3088.235294 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 2625 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1968.750000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52547.872340 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52346.153846 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52480.916031 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 51993.589744 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52537.234043 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52423.076923 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52458.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52333.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 52325 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 49750 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52080.882353 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 52119.834711 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52375 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 50800 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52091.580502 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 52124.653740 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52479.289941 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 49633.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 51482.352941 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 52325 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 49750 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52080.882353 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51820.224719 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52375 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 43428.571429 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 52461.538462 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 50800 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 52346.153846 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52091.580502 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2229,154 +2215,154 @@ system.l2c.overall_mshr_hits::cpu1.inst 1 # nu system.l2c.overall_mshr_hits::cpu2.inst 5 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 7 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.inst 363 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 361 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.data 75 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 14 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 80 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 7 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 88 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3.inst 4 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 542 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 22 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 21 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 20 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 80 # number of UpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 539 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 23 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 81 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 12 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 363 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 361 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.data 169 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 14 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 80 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3.inst 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 88 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3.inst 4 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 673 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 363 # number of overall MSHR misses +system.l2c.demand_mshr_misses::total 670 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 361 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.data 169 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 14 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 80 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3.inst 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 88 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 673 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14492500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3016500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 560000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 3200000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 280000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::total 670 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 14412000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3017000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3521000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 280000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 80000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 40000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 160000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21669000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 880000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 840000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 680000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 800000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 3200000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3793000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 481500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 522500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21550000 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 920000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 800000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 760000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 760500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 3240500 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3791500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 522500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 483500 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 481500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5278500 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 14492500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 6809500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 560000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 3200000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 802500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5279000 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 14412000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 6808500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 802500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 80000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 523500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 160000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 521500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 26947500 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 14492500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 6809500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 560000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 3200000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 802500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 26829000 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 14412000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6808500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3521000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 802500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 80000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 523500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 160000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 521500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 26947500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for ReadReq accesses +system.l2c.overall_mshr_miss_latency::total 26829000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.937500 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.071429 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.500000 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.071429 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.267919 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.880000 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.266173 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.884615 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.963855 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.964286 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.312442 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.611111 # mshr miss rate for overall accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.310761 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.602671 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032184 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.500000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.181818 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002315 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.312442 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40220 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.201835 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.004566 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.310761 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40226.666667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39979.704797 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39981.447124 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40351.063830 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40026.315789 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40006.172840 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40335.106383 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40192.307692 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40291.666667 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40293.893130 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40297.709924 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39924.242424 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40292.899408 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40115.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39922.437673 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40286.982249 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40011.363636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40125 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40269.230769 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40040.861813 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40043.283582 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout index 7edc0f615..4b3a2eb90 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:23 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:10 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index a670e1cab..382c1c71b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87713500 # Number of ticks simulated final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1597903 # Simulator instruction rate (inst/s) -host_op_rate 1597833 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 206906108 # Simulator tick rate (ticks/s) -host_mem_usage 1149840 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host +host_inst_rate 1588944 # Simulator instruction rate (inst/s) +host_op_rate 1588869 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 205745598 # Simulator tick rate (ticks/s) +host_mem_usage 1148436 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host sim_insts 677340 # Number of instructions simulated sim_ops 677340 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory @@ -122,15 +122,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets nan system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use -system.cpu0.dcache.total_refs 61599 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 150.735434 # Cycle average of tags in use +system.cpu0.dcache.total_refs 81884 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 490.323353 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.712770 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284595 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284595 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 150.735434 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.294405 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.294405 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 54431 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 54431 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits @@ -179,8 +179,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.numCycles 173308 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started @@ -246,35 +246,35 @@ system.cpu1.icache.avg_blocked_cycles::no_targets nan system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 29.073016 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26889 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 960.321429 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 30.314752 # Cycle average of tags in use +system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 29.073016 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.056783 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40468 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40468 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 30.314752 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.059208 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53031 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53031 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53031 # number of overall hits -system.cpu1.dcache.overall_hits::total 53031 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 176 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 176 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits +system.cpu1.dcache.overall_hits::total 53033 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses -system.cpu1.dcache.overall_misses::total 282 # number of overall misses +system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses +system.cpu1.dcache.overall_misses::total 280 # number of overall misses system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) @@ -285,16 +285,16 @@ system.cpu1.dcache.demand_accesses::cpu1.data 53313 system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004330 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005290 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005290 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005290 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005290 # miss rate for overall accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -303,8 +303,6 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.numCycles 173308 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started @@ -370,35 +368,35 @@ system.cpu2.icache.avg_blocked_cycles::no_targets nan system.cpu2.icache.fast_writes 0 # number of fast writes performed system.cpu2.icache.cache_copies 0 # number of cache copies performed system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 28.420699 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33771 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1206.107143 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 29.603311 # Cycle average of tags in use +system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 28.420699 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.055509 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42192 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42192 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 29.603311 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.057819 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58190 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58190 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58190 # number of overall hits -system.cpu2.dcache.overall_hits::total 58190 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 162 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 162 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits +system.cpu2.dcache.overall_hits::total 58192 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 271 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 271 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 271 # number of overall misses -system.cpu2.dcache.overall_misses::total 271 # number of overall misses +system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses +system.cpu2.dcache.overall_misses::total 269 # number of overall misses system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) @@ -409,16 +407,16 @@ system.cpu2.dcache.demand_accesses::cpu2.data 58461 system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003825 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003825 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004636 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004636 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004636 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004636 # miss rate for overall accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -427,8 +425,6 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.numCycles 173307 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started @@ -494,35 +490,35 @@ system.cpu3.icache.avg_blocked_cycles::no_targets nan system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 27.588376 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30309 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1045.137931 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 28.793270 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 27.588376 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.053884 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41299 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41299 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 28.793270 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.056237 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55559 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55559 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55559 # number of overall hits -system.cpu3.dcache.overall_hits::total 55559 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 159 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 159 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits +system.cpu3.dcache.overall_hits::total 55561 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 261 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 261 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 261 # number of overall misses -system.cpu3.dcache.overall_misses::total 261 # number of overall misses +system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses +system.cpu3.dcache.overall_misses::total 259 # number of overall misses system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) @@ -533,16 +529,16 @@ system.cpu3.dcache.demand_accesses::cpu3.data 55820 system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003835 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003835 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004676 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004676 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004676 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004676 # miss rate for overall accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,16 +547,14 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 371.980910 # Cycle average of tags in use -system.l2c.total_refs 1223 # Total number of references to valid blocks. -system.l2c.sampled_refs 426 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.870892 # Average number of references to valid blocks. +system.l2c.tagsinuse 366.557230 # Cycle average of tags in use +system.l2c.total_refs 1220 # Total number of references to valid blocks. +system.l2c.sampled_refs 421 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 6.390048 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.966368 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 239.409595 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 55.204245 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 59.507442 # Average occupied blocks per requestor @@ -569,7 +563,7 @@ system.l2c.occ_blocks::cpu2.inst 1.930518 # Av system.l2c.occ_blocks::cpu2.data 0.935341 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.977501 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.905573 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000098 # Average percentage of cache occupancy +system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy @@ -578,38 +572,38 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005676 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005593 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 185 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1226 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses @@ -620,10 +614,10 @@ system.l2c.ReadReq_misses::cpu3.inst 2 # nu system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses system.l2c.ReadReq_misses::total 423 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 20 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 87 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses @@ -650,19 +644,19 @@ system.l2c.overall_misses::total 559 # nu system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1649 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 20 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 89 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -671,35 +665,35 @@ system.l2c.ReadExReq_accesses::total 136 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1785 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1785 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.256519 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.977528 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -708,21 +702,21 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.313165 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.313165 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index 3d54c9924..145ab230c 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 12:01:47 -gem5 started Jun 4 2012 14:45:33 +gem5 compiled Jun 28 2012 22:06:58 +gem5 started Jun 28 2012 22:54:12 gem5 executing on zizzer -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp +command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done @@ -79,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 Iteration 10 completed PASSED :-) -Exiting @ tick 262298000 because target called exit() +Exiting @ tick 262299000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 36b8c656f..c654a221f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 262298000 # Number of ticks simulated -final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 262299000 # Number of ticks simulated +final_tick 262299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1070900 # Simulator instruction rate (inst/s) -host_op_rate 1070867 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 424091073 # Simulator tick rate (ticks/s) -host_mem_usage 232420 # Number of bytes of host memory used -host_seconds 0.62 # Real time elapsed on the host -sim_insts 662307 # Number of instructions simulated -sim_ops 662307 # Number of ops (including micro ops) simulated +host_inst_rate 1271827 # Simulator instruction rate (inst/s) +host_op_rate 1271784 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 503510999 # Simulator tick rate (ticks/s) +host_mem_usage 230932 # Number of bytes of host memory used +host_seconds 0.52 # Real time elapsed on the host +sim_insts 662502 # Number of instructions simulated +sim_ops 662502 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 3776 # Number of bytes read from this memory @@ -34,31 +34,31 @@ system.physmem.num_reads::cpu2.data 16 # Nu system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69539226 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40259552 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 14395840 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 5367940 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2195976 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3903957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 243997 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 3659959 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139566447 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69539226 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 14395840 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2195976 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 243997 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86375039 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69539226 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40259552 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 14395840 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 5367940 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2195976 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3903957 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 243997 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 3659959 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139566447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69538961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40259399 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 14395785 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5367920 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 2195967 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3903942 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243996 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3659945 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139565915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69538961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 14395785 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 2195967 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243996 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86374710 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69538961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40259399 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 14395785 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5367920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 2195967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3903942 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243996 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3659945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139565915 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 524596 # number of cpu cycles simulated +system.cpu0.numCycles 524598 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.committedInsts 158353 # Number of instructions committed @@ -77,18 +77,18 @@ system.cpu0.num_mem_refs 73905 # nu system.cpu0.num_load_insts 48930 # Number of load instructions system.cpu0.num_store_insts 24975 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 524596 # Number of busy cycles +system.cpu0.num_busy_cycles 524598 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.479188 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 212.479251 # Cycle average of tags in use system.cpu0.icache.total_refs 157949 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 212.479251 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414999 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414999 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits @@ -158,15 +158,15 @@ system.cpu0.icache.demand_avg_mshr_miss_latency::total 36665.952891 system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_miss_latency::total 36665.952891 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 9 # number of replacements -system.cpu0.dcache.tagsinuse 141.233342 # Cycle average of tags in use -system.cpu0.dcache.total_refs 56009 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 329.464706 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 145.603716 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73381 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 439.407186 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 141.233342 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.275846 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.275846 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 145.603716 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284382 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284382 # Average percentage of cache occupancy system.cpu0.dcache.ReadReq_hits::cpu0.data 48758 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 48758 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 24741 # number of WriteReq hits @@ -187,16 +187,16 @@ system.cpu0.dcache.demand_misses::cpu0.data 345 # system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4749000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7175000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 387000 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 387000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11924000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11924000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11924000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4747000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7176000 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 389000 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 389000 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11923000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11923000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11923000 # number of overall miss cycles system.cpu0.dcache.ReadReq_accesses::cpu0.data 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 48920 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 24924 # number of WriteReq accesses(hits+misses) @@ -217,16 +217,16 @@ system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_miss_rate::total 0.004672 # miss rate for demand accesses system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004672 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.004672 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 29314.814815 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 39207.650273 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 14884.615385 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 34562.318841 # average overall miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 29302.469136 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 39213.114754 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14961.538462 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34559.420290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34559.420290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -235,8 +235,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 6 # number of writebacks -system.cpu0.dcache.writebacks::total 6 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks +system.cpu0.dcache.writebacks::total 1 # number of writebacks system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses @@ -247,16 +247,16 @@ system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4263000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6626000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 309000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10889000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10889000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10889000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4261000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6627000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311000 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10888000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10888000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10888000 # number of overall MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003312 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007342 # mshr miss rate for WriteReq accesses @@ -267,84 +267,84 @@ system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004672 system.cpu0.dcache.demand_mshr_miss_rate::total 0.004672 # mshr miss rate for demand accesses system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004672 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.004672 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26314.814815 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36207.650273 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11884.615385 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31562.318841 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26302.469136 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36213.114754 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11961.538462 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31559.420290 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31559.420290 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 524596 # number of cpu cycles simulated +system.cpu1.numCycles 524598 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 172325 # Number of instructions committed -system.cpu1.committedOps 172325 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 107932 # Number of integer alu accesses +system.cpu1.committedInsts 172389 # Number of instructions committed +system.cpu1.committedOps 172389 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 107964 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36203 # number of instructions that are conditional controls -system.cpu1.num_int_insts 107932 # number of integer instructions +system.cpu1.num_conditional_control_insts 36219 # number of instructions that are conditional controls +system.cpu1.num_int_insts 107964 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 249091 # number of times the integer registers were read -system.cpu1.num_int_register_writes 92744 # number of times the integer registers were written +system.cpu1.num_int_register_reads 249169 # number of times the integer registers were read +system.cpu1.num_int_register_writes 92792 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 47898 # number of memory refs -system.cpu1.num_load_insts 39616 # Number of load instructions +system.cpu1.num_mem_refs 47914 # number of memory refs +system.cpu1.num_load_insts 39632 # Number of load instructions system.cpu1.num_store_insts 8282 # Number of store instructions -system.cpu1.num_idle_cycles 68578.001739 # Number of idle cycles -system.cpu1.num_busy_cycles 456017.998261 # Number of busy cycles -system.cpu1.not_idle_fraction 0.869275 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.130725 # Percentage of idle cycles +system.cpu1.num_idle_cycles 68732.001738 # Number of idle cycles +system.cpu1.num_busy_cycles 455865.998262 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868982 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131018 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 70.076133 # Cycle average of tags in use -system.cpu1.icache.total_refs 171992 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.077944 # Cycle average of tags in use +system.cpu1.icache.total_refs 172056 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 469.923497 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 470.098361 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 70.076133 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.136867 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 171992 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 171992 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 171992 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 171992 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 171992 # number of overall hits -system.cpu1.icache.overall_hits::total 171992 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.077944 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136871 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 172056 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 172056 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 172056 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 172056 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 172056 # number of overall hits +system.cpu1.icache.overall_hits::total 172056 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7920500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7920500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7920500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7920500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7920500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 172358 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 172358 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 172358 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 172358 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 172358 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7921500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7921500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7921500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7921500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7921500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 172422 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 172422 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 172422 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 172422 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 172422 # number of overall (read+write) accesses system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.ReadReq_miss_rate::total 0.002123 # miss rate for ReadReq accesses system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002123 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total 0.002123 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002123 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.002123 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21640.710383 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21640.710383 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21643.442623 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21643.442623 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21643.442623 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21643.442623 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6822000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6822000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6822000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6822000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6823000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6823000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6823000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6823000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002123 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.002123 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002123 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.002123 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18639.344262 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18639.344262 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18642.076503 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18642.076503 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18642.076503 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 2 # number of replacements -system.cpu1.dcache.tagsinuse 26.693562 # Cycle average of tags in use -system.cpu1.dcache.total_refs 18908 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 609.935484 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 27.731444 # Cycle average of tags in use +system.cpu1.dcache.total_refs 18765 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 647.068966 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 26.693562 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.052136 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39428 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39428 # number of ReadReq hits +system.cpu1.dcache.occ_blocks::cpu1.data 27.731444 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.054163 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 39445 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 39445 # number of ReadReq hits system.cpu1.dcache.WriteReq_hits::cpu1.data 8099 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 8099 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 18 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 18 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 47527 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 47527 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 47527 # number of overall hits -system.cpu1.dcache.overall_hits::total 47527 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 181 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 181 # number of ReadReq misses +system.cpu1.dcache.demand_hits::cpu1.data 47544 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 47544 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 47544 # number of overall hits +system.cpu1.dcache.overall_hits::total 47544 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 179 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 179 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 98 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 98 # number of WriteReq misses system.cpu1.dcache.SwapReq_misses::cpu1.data 65 # number of SwapReq misses system.cpu1.dcache.SwapReq_misses::total 65 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 279 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 279 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 279 # number of overall misses -system.cpu1.dcache.overall_misses::total 279 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3713000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1889000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1889000 # number of WriteReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 277 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 277 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 277 # number of overall misses +system.cpu1.dcache.overall_misses::total 277 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3683000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1838000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1838000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 415000 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 415000 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5602000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5602000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5602000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 39609 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 39609 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5521000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5521000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5521000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 39624 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 39624 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 8197 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 83 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 83 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 47806 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 47806 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 47806 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 47806 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004570 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004570 # miss rate for ReadReq accesses +system.cpu1.dcache.demand_accesses::cpu1.data 47821 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 47821 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 47821 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 47821 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004517 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.004517 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.011956 # miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.783133 # miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_miss_rate::total 0.783133 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005836 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005836 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005836 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005836 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 20513.812155 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19275.510204 # average WriteReq miss latency +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005792 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005792 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005792 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005792 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 20575.418994 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18755.102041 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18755.102041 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6384.615385 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 6384.615385 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20078.853047 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19931.407942 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19931.407942 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,86 +455,84 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu1.dcache.writebacks::total 1 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 181 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 181 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 179 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 179 # number of ReadReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 98 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 98 # number of WriteReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 65 # number of SwapReq MSHR misses system.cpu1.dcache.SwapReq_mshr_misses::total 65 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 279 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 279 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 279 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3170000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1595000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1595000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 277 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3146000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1544000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1544000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 220000 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 220000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4765000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4765000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004570 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004570 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4690000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4690000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004517 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004517 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.011956 # mshr miss rate for WriteReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.783133 # mshr miss rate for SwapReq accesses system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.783133 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005836 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005836 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17513.812155 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16275.510204 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.005792 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.005792 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17575.418994 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15755.102041 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15755.102041 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3384.615385 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3384.615385 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17078.853047 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16931.407942 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16931.407942 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 524596 # number of cpu cycles simulated +system.cpu2.numCycles 524598 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 165499 # Number of instructions committed -system.cpu2.committedOps 165499 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 112355 # Number of integer alu accesses +system.cpu2.committedInsts 165564 # Number of instructions committed +system.cpu2.committedOps 165564 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 112387 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 30582 # number of instructions that are conditional controls -system.cpu2.num_int_insts 112355 # number of integer instructions +system.cpu2.num_conditional_control_insts 30599 # number of instructions that are conditional controls +system.cpu2.num_int_insts 112387 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 289268 # number of times the integer registers were read -system.cpu2.num_int_register_writes 110631 # number of times the integer registers were written +system.cpu2.num_int_register_reads 289349 # number of times the integer registers were read +system.cpu2.num_int_register_writes 110679 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 57941 # number of memory refs -system.cpu2.num_load_insts 41852 # Number of load instructions +system.cpu2.num_mem_refs 57957 # number of memory refs +system.cpu2.num_load_insts 41868 # Number of load instructions system.cpu2.num_store_insts 16089 # Number of store instructions -system.cpu2.num_idle_cycles 68840.001738 # Number of idle cycles -system.cpu2.num_busy_cycles 455755.998262 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868775 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131225 # Percentage of idle cycles +system.cpu2.num_idle_cycles 68998.001737 # Number of idle cycles +system.cpu2.num_busy_cycles 455599.998263 # Number of busy cycles +system.cpu2.not_idle_fraction 0.868475 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.131525 # Percentage of idle cycles system.cpu2.icache.replacements 280 # number of replacements -system.cpu2.icache.tagsinuse 65.601019 # Cycle average of tags in use -system.cpu2.icache.total_refs 165166 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 65.602896 # Cycle average of tags in use +system.cpu2.icache.total_refs 165231 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 451.273224 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 451.450820 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 65.601019 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.128127 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 165166 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 165166 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 165166 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 165166 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 165166 # number of overall hits -system.cpu2.icache.overall_hits::total 165166 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 65.602896 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.128131 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 165231 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 165231 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 165231 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 165231 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 165231 # number of overall hits +system.cpu2.icache.overall_hits::total 165231 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses @@ -547,18 +545,18 @@ system.cpu2.icache.demand_miss_latency::cpu2.inst 5648500 system.cpu2.icache.demand_miss_latency::total 5648500 # number of demand (read+write) miss cycles system.cpu2.icache.overall_miss_latency::cpu2.inst 5648500 # number of overall miss cycles system.cpu2.icache.overall_miss_latency::total 5648500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 165532 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 165532 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 165532 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 165532 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 165532 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002211 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002211 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002211 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002211 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002211 # miss rate for overall accesses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 165597 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 165597 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 165597 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 165597 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 165597 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002210 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002210 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002210 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002210 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002210 # miss rate for overall accesses system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109 # average ReadReq miss latency system.cpu2.icache.ReadReq_avg_miss_latency::total 15433.060109 # average ReadReq miss latency system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109 # average overall miss latency @@ -585,12 +583,12 @@ system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 4550500 system.cpu2.icache.demand_mshr_miss_latency::total 4550500 # number of demand (read+write) MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 4550500 # number of overall MSHR miss cycles system.cpu2.icache.overall_mshr_miss_latency::total 4550500 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002211 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.002211 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002211 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.002211 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.002210 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.002210 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.002210 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.002210 # mshr miss rate for overall accesses system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12433.060109 # average ReadReq mshr miss latency system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency @@ -598,75 +596,75 @@ system.cpu2.icache.demand_avg_mshr_miss_latency::total 12433.060109 system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109 # average overall mshr miss latency system.cpu2.icache.overall_avg_mshr_miss_latency::total 12433.060109 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 2 # number of replacements -system.cpu2.dcache.tagsinuse 24.943438 # Cycle average of tags in use -system.cpu2.dcache.total_refs 34578 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1115.419355 # Average number of references to valid blocks. +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 25.974144 # Cycle average of tags in use +system.cpu2.dcache.total_refs 34436 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1187.448276 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.943438 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.048718 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 41688 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 41688 # number of ReadReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.974144 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050731 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 41706 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 41706 # number of ReadReq hits system.cpu2.dcache.WriteReq_hits::cpu2.data 15916 # number of WriteReq hits system.cpu2.dcache.WriteReq_hits::total 15916 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 57604 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 57604 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 57604 # number of overall hits -system.cpu2.dcache.overall_hits::total 57604 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 156 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 156 # number of ReadReq misses +system.cpu2.dcache.demand_hits::cpu2.data 57622 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 57622 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 57622 # number of overall hits +system.cpu2.dcache.overall_hits::total 57622 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 154 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 154 # number of ReadReq misses system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses system.cpu2.dcache.SwapReq_misses::cpu2.data 51 # number of SwapReq misses system.cpu2.dcache.SwapReq_misses::total 51 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 265 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 265 # number of overall misses -system.cpu2.dcache.overall_misses::total 265 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 2527000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2084000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2084000 # number of WriteReq miss cycles +system.cpu2.dcache.demand_misses::cpu2.data 263 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 263 # number of overall misses +system.cpu2.dcache.overall_misses::total 263 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 2498000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2031000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2031000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 305000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 305000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 4611000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 4611000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 4611000 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 41844 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 41844 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.demand_miss_latency::cpu2.data 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 4529000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 4529000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 4529000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 41860 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 41860 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::total 16025 # number of WriteReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::cpu2.data 62 # number of SwapReq accesses(hits+misses) system.cpu2.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 57869 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 57869 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 57869 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 57869 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003728 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003728 # miss rate for ReadReq accesses +system.cpu2.dcache.demand_accesses::cpu2.data 57885 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 57885 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 57885 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 57885 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003679 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.003679 # miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_miss_rate::total 0.006802 # miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.822581 # miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_miss_rate::total 0.822581 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004579 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004579 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004579 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004579 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 16198.717949 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19119.266055 # average WriteReq miss latency +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004543 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.004543 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004543 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.004543 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 16220.779221 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 18633.027523 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 18633.027523 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5980.392157 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 5980.392157 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17400 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 17400 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 17220.532319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 17220.532319 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -675,116 +673,114 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu2.dcache.writebacks::total 1 # number of writebacks -system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 156 # number of ReadReq MSHR misses -system.cpu2.dcache.ReadReq_mshr_misses::total 156 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 154 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 154 # number of ReadReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 109 # number of WriteReq MSHR misses system.cpu2.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 51 # number of SwapReq MSHR misses system.cpu2.dcache.SwapReq_mshr_misses::total 51 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 265 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2059000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1757000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1757000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_misses::cpu2.data 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 263 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 2036000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1704000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1704000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 152000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 152000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 3816000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 3816000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003728 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003728 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3740000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3740000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003679 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003679 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.006802 # mshr miss rate for WriteReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.822581 # mshr miss rate for SwapReq accesses system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.822581 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.004579 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.004579 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13198.717949 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16119.266055 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004543 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004543 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 13220.779221 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15633.027523 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15633.027523 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2980.392157 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 2980.392157 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14400 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14400 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 14220.532319 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 14220.532319 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 524596 # number of cpu cycles simulated +system.cpu3.numCycles 524598 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 166130 # Number of instructions committed -system.cpu3.committedOps 166130 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 112098 # Number of integer alu accesses +system.cpu3.committedInsts 166196 # Number of instructions committed +system.cpu3.committedOps 166196 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 112131 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31024 # number of instructions that are conditional controls -system.cpu3.num_int_insts 112098 # number of integer instructions +system.cpu3.num_conditional_control_insts 31040 # number of instructions that are conditional controls +system.cpu3.num_int_insts 112131 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 286475 # number of times the integer registers were read -system.cpu3.num_int_register_writes 109360 # number of times the integer registers were written +system.cpu3.num_int_register_reads 286557 # number of times the integer registers were read +system.cpu3.num_int_register_writes 109409 # number of times the integer registers were written system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 57243 # number of memory refs -system.cpu3.num_load_insts 41720 # Number of load instructions +system.cpu3.num_mem_refs 57260 # number of memory refs +system.cpu3.num_load_insts 41737 # Number of load instructions system.cpu3.num_store_insts 15523 # Number of store instructions -system.cpu3.num_idle_cycles 69090.001737 # Number of idle cycles -system.cpu3.num_busy_cycles 455505.998263 # Number of busy cycles -system.cpu3.not_idle_fraction 0.868299 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.131701 # Percentage of idle cycles +system.cpu3.num_idle_cycles 69252.001736 # Number of idle cycles +system.cpu3.num_busy_cycles 455345.998264 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867990 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132010 # Percentage of idle cycles system.cpu3.icache.replacements 281 # number of replacements -system.cpu3.icache.tagsinuse 67.737646 # Cycle average of tags in use -system.cpu3.icache.total_refs 165796 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 67.739564 # Cycle average of tags in use +system.cpu3.icache.total_refs 165862 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 451.760218 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 451.940054 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 67.737646 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.132300 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 165796 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 165796 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 165796 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 165796 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 165796 # number of overall hits -system.cpu3.icache.overall_hits::total 165796 # number of overall hits +system.cpu3.icache.occ_blocks::cpu3.inst 67.739564 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132304 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 165862 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 165862 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 165862 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 165862 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 165862 # number of overall hits +system.cpu3.icache.overall_hits::total 165862 # number of overall hits system.cpu3.icache.ReadReq_misses::cpu3.inst 367 # number of ReadReq misses system.cpu3.icache.ReadReq_misses::total 367 # number of ReadReq misses system.cpu3.icache.demand_misses::cpu3.inst 367 # number of demand (read+write) misses system.cpu3.icache.demand_misses::total 367 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 367 # number of overall misses system.cpu3.icache.overall_misses::total 367 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5531500 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 5531500 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 5531500 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 5531500 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 5531500 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 166163 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 166163 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 166163 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 166163 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 166163 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002209 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002209 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002209 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002209 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002209 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 15072.207084 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 15072.207084 # average overall miss latency +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 5533500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 5533500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5533500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5533500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5533500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 166229 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 166229 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 166229 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 166229 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 166229 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002208 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002208 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002208 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002208 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002208 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15077.656676 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 15077.656676 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15077.656676 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 15077.656676 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -799,94 +795,94 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4430500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4430500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4430500 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002209 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002209 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002209 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12072.207084 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 12072.207084 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4432500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4432500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4432500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002208 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002208 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002208 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12077.656676 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12077.656676 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12077.656676 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 2 # number of replacements -system.cpu3.dcache.tagsinuse 25.684916 # Cycle average of tags in use -system.cpu3.dcache.total_refs 33474 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 32 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1046.062500 # Average number of references to valid blocks. +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 26.774212 # Cycle average of tags in use +system.cpu3.dcache.total_refs 33417 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 30 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 1113.900000 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.684916 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.050166 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41555 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41555 # number of ReadReq hits +system.cpu3.dcache.occ_blocks::cpu3.data 26.774212 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.052293 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 41574 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 41574 # number of ReadReq hits system.cpu3.dcache.WriteReq_hits::cpu3.data 15348 # number of WriteReq hits system.cpu3.dcache.WriteReq_hits::total 15348 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 56903 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 56903 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 56903 # number of overall hits -system.cpu3.dcache.overall_hits::total 56903 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses +system.cpu3.dcache.demand_hits::cpu3.data 56922 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 56922 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 56922 # number of overall hits +system.cpu3.dcache.overall_hits::total 56922 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 155 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 155 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 108 # number of WriteReq misses system.cpu3.dcache.WriteReq_misses::total 108 # number of WriteReq misses system.cpu3.dcache.SwapReq_misses::cpu3.data 54 # number of SwapReq misses system.cpu3.dcache.SwapReq_misses::total 54 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 265 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 265 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 265 # number of overall misses -system.cpu3.dcache.overall_misses::total 265 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 2569000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2080000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2080000 # number of WriteReq miss cycles +system.cpu3.dcache.demand_misses::cpu3.data 263 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 263 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 263 # number of overall misses +system.cpu3.dcache.overall_misses::total 263 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2537000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2537000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2026000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2026000 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 326000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 326000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 4649000 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 4649000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 4649000 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41712 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41712 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.demand_miss_latency::cpu3.data 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4563000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4563000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4563000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 41729 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 41729 # number of ReadReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::cpu3.data 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.WriteReq_accesses::total 15456 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 65 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 57168 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 57168 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 57168 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 57168 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003764 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003764 # miss rate for ReadReq accesses +system.cpu3.dcache.demand_accesses::cpu3.data 57185 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 57185 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 57185 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 57185 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003714 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.003714 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_miss_rate::total 0.006988 # miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.830769 # miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_miss_rate::total 0.830769 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004635 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004635 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004635 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004635 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 16363.057325 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 19259.259259 # average WriteReq miss latency +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004599 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.004599 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004599 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.004599 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16367.741935 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18759.259259 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 18759.259259 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6037.037037 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 6037.037037 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 17543.396226 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17349.809886 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 17349.809886 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -895,65 +891,63 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu3.dcache.writebacks::total 1 # number of writebacks -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 157 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 157 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 155 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 155 # number of ReadReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 108 # number of WriteReq MSHR misses system.cpu3.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 54 # number of SwapReq MSHR misses system.cpu3.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 265 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 265 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 265 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2098000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1756000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1756000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.demand_mshr_misses::cpu3.data 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 263 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 263 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 263 # number of overall MSHR misses +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 2072000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 2072000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1702000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1702000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 164000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 164000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 3854000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 3854000 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003764 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003764 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 3774000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 3774000 # number of overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003714 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003714 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.006988 # mshr miss rate for WriteReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.830769 # mshr miss rate for SwapReq accesses system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.004635 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.004635 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13363.057325 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16259.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.004599 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.004599 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.004599 # mshr miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13367.741935 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 13367.741935 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15759.259259 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 15759.259259 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 3037.037037 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 3037.037037 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14543.396226 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency +system.cpu3.dcache.demand_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14349.809886 # average overall mshr miss latency +system.cpu3.dcache.overall_avg_mshr_miss_latency::total 14349.809886 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 353.886259 # Cycle average of tags in use -system.l2c.total_refs 1223 # Total number of references to valid blocks. -system.l2c.sampled_refs 434 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.817972 # Average number of references to valid blocks. +system.l2c.tagsinuse 349.180649 # Cycle average of tags in use +system.l2c.total_refs 1220 # Total number of references to valid blocks. +system.l2c.sampled_refs 429 # Sample count of references to valid blocks. +system.l2c.avg_refs 2.843823 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 5.597896 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 231.859183 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 54.220360 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 51.601293 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.129067 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.914986 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.831600 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.889759 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 231.859241 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 54.220371 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 51.601321 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 6.129070 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.917102 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.831909 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 0.887228 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.844646 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000085 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu3.data 0.844647 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.003538 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000827 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.000787 # Average percentage of cache occupancy @@ -962,38 +956,38 @@ system.l2c.occ_percent::cpu2.inst 0.000029 # Av system.l2c.occ_percent::cpu2.data 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000014 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005400 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005328 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 182 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 300 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits system.l2c.ReadReq_hits::cpu2.inst 354 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits system.l2c.ReadReq_hits::cpu3.inst 358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1226 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 9 # number of Writeback hits -system.l2c.Writeback_hits::total 9 # number of Writeback hits +system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits +system.l2c.Writeback_hits::total 1 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits system.l2c.demand_hits::cpu0.inst 182 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 300 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits system.l2c.demand_hits::cpu2.inst 354 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits system.l2c.demand_hits::cpu3.inst 358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits -system.l2c.demand_hits::total 1226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits +system.l2c.demand_hits::total 1220 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 182 # number of overall hits system.l2c.overall_hits::cpu0.data 5 # number of overall hits system.l2c.overall_hits::cpu1.inst 300 # number of overall hits -system.l2c.overall_hits::cpu1.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.data 3 # number of overall hits system.l2c.overall_hits::cpu2.inst 354 # number of overall hits -system.l2c.overall_hits::cpu2.data 11 # number of overall hits +system.l2c.overall_hits::cpu2.data 9 # number of overall hits system.l2c.overall_hits::cpu3.inst 358 # number of overall hits -system.l2c.overall_hits::cpu3.data 11 # number of overall hits -system.l2c.overall_hits::total 1226 # number of overall hits +system.l2c.overall_hits::cpu3.data 9 # number of overall hits +system.l2c.overall_hits::total 1220 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 285 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 66 # number of ReadReq misses @@ -1004,10 +998,10 @@ system.l2c.ReadReq_misses::cpu3.inst 9 # nu system.l2c.ReadReq_misses::cpu3.data 2 # number of ReadReq misses system.l2c.ReadReq_misses::total 450 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 28 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 12 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 16 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 72 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 11 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3.data 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 69 # number of UpgradeReq misses system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 15 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu2.data 14 # number of ReadExReq misses @@ -1033,56 +1027,52 @@ system.l2c.overall_misses::cpu3.data 16 # nu system.l2c.overall_misses::total 592 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.inst 14822000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 3432000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 3416000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 413000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 3402000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 411000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.inst 615000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 104000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 429000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.data 99000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 23330000 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 52000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 52000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3.data 52000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 156000 # number of UpgradeReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 446000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.data 101000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 23333000 # number of ReadReq miss cycles system.l2c.ReadExReq_miss_latency::cpu0.data 5148000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 781000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 780000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu2.data 728000 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::cpu3.data 728000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7385000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7384000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.inst 14822000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.data 8580000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 3416000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 1194000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 3402000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1191000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.inst 615000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu2.data 832000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.inst 429000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3.data 827000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 30715000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 446000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 829000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 30717000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.inst 14822000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.data 8580000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 3416000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 1194000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 3402000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1191000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.inst 615000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu2.data 832000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.inst 429000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3.data 827000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 30715000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 446000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 829000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 30717000 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu2.inst 366 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 13 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 11 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu3.inst 367 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 13 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1676 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 9 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 9 # number of Writeback accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 11 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1670 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 30 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 12 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 11 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 15 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 71 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 15 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 14 # number of ReadExReq accesses(hits+misses) @@ -1091,35 +1081,35 @@ system.l2c.ReadExReq_accesses::total 142 # nu system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 28 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 26 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu2.inst 366 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 27 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 25 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu3.inst 367 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 27 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1818 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3.data 25 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1812 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 28 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu2.inst 366 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 27 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 25 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu3.inst 367 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 27 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1818 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 25 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1812 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610278 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.180328 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.615385 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.727273 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.inst 0.032787 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.153846 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.181818 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.inst 0.024523 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.153846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.268496 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.181818 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.269461 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.933333 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.972973 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.971831 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -1128,57 +1118,53 @@ system.l2c.ReadExReq_miss_rate::total 1 # mi system.l2c.demand_miss_rate::cpu0.inst 0.610278 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.180328 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.821429 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.884615 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.inst 0.032787 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.592593 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.640000 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.inst 0.024523 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.592593 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.325633 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.640000 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.326711 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610278 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.180328 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.821429 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.884615 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.inst 0.032787 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.592593 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.640000 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.inst 0.024523 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.592593 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.325633 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.640000 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.326711 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 51625 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51545.454545 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 51375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51250 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 52000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.data 49500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 51844.444444 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 4333.333333 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 3250 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2166.666667 # average UpgradeReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 49555.555556 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.data 50500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 51851.111111 # average ReadReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52000 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52000 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52007.042254 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51545.454545 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 51782.608696 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.inst 51250 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu2.data 52000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 51883.445946 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 49555.555556 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 51812.500000 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51886.824324 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1215,10 +1201,10 @@ system.l2c.ReadReq_mshr_misses::cpu3.inst 1 # n system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses system.l2c.UpgradeReq_mshr_misses::cpu0.data 28 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 12 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3.data 16 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 11 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3.data 15 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 69 # number of UpgradeReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu0.data 99 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu1.data 15 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::cpu2.data 14 # number of ReadExReq MSHR misses @@ -1252,47 +1238,47 @@ system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 40000 system.l2c.ReadReq_mshr_miss_latency::cpu3.data 40000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 17203000 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 1120000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 480000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 640000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 440000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 600000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 2760000 # number of UpgradeReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3960000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 601000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 600000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 560000 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 560000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5681000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5680000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.inst 11402000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.data 6600000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.inst 2360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 881000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 880000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.inst 361000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu2.data 640000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.inst 40000 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu3.data 600000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 22884000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 22883000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.inst 11402000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.data 6600000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.inst 2360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 881000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 880000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.inst 361000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu2.data 640000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu3.data 600000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22883000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.538462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.636364 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.256563 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.972973 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.971831 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1301,21 +1287,21 @@ system.l2c.ReadExReq_mshr_miss_rate::total 1 # system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.314631 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.161202 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.846154 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024590 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.314631 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency @@ -1331,28 +1317,28 @@ system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40000 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40007.042254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40006.993007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40005.244755 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index afb940009..a874a3f37 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read, 5261 write accesses @25602084 -system.cpu0: completed 10000 read, 5478 write accesses @26185688 -system.cpu4: completed 10000 read, 5410 write accesses @26212882 -system.cpu3: completed 10000 read, 5338 write accesses @26366308 -system.cpu1: completed 10000 read, 5460 write accesses @26447108 -system.cpu7: completed 10000 read, 5362 write accesses @26537664 -system.cpu2: completed 10000 read, 5282 write accesses @26676832 -system.cpu6: completed 10000 read, 5370 write accesses @26707781 -system.cpu3: completed 20000 read, 10741 write accesses @51951998 -system.cpu5: completed 20000 read, 10677 write accesses @52231737 -system.cpu0: completed 20000 read, 11006 write accesses @52523512 -system.cpu4: completed 20000 read, 10704 write accesses @52614186 -system.cpu7: completed 20000 read, 10588 write accesses @52674871 -system.cpu1: completed 20000 read, 10959 write accesses @52986792 -system.cpu2: completed 20000 read, 10676 write accesses @53365626 -system.cpu6: completed 20000 read, 10788 write accesses @53537042 -system.cpu5: completed 30000 read, 16233 write accesses @78528098 -system.cpu3: completed 30000 read, 16192 write accesses @78636475 -system.cpu7: completed 30000 read, 15958 write accesses @79069859 -system.cpu0: completed 30000 read, 16488 write accesses @79082669 -system.cpu4: completed 30000 read, 16215 write accesses @79163244 -system.cpu6: completed 30000 read, 16191 write accesses @79592442 -system.cpu2: completed 30000 read, 16073 write accesses @79845712 -system.cpu1: completed 30000 read, 16466 write accesses @80286691 -system.cpu5: completed 40000 read, 21620 write accesses @103783596 -system.cpu0: completed 40000 read, 21781 write accesses @103983848 -system.cpu7: completed 40000 read, 21333 write accesses @104306510 -system.cpu3: completed 40000 read, 21577 write accesses @104792070 -system.cpu6: completed 40000 read, 21636 write accesses @104882247 -system.cpu4: completed 40000 read, 21525 write accesses @104921736 -system.cpu1: completed 40000 read, 21768 write accesses @105789168 -system.cpu2: completed 40000 read, 21470 write accesses @106255146 -system.cpu5: completed 50000 read, 26996 write accesses @130119835 -system.cpu0: completed 50000 read, 27148 write accesses @130621851 -system.cpu4: completed 50000 read, 26714 write accesses @131102250 -system.cpu7: completed 50000 read, 26744 write accesses @131131435 -system.cpu3: completed 50000 read, 26919 write accesses @131315326 -system.cpu6: completed 50000 read, 27071 write accesses @131463045 -system.cpu2: completed 50000 read, 26691 write accesses @132748289 -system.cpu1: completed 50000 read, 27351 write accesses @133533726 -system.cpu0: completed 60000 read, 32524 write accesses @157291050 -system.cpu5: completed 60000 read, 32351 write accesses @157331674 -system.cpu3: completed 60000 read, 32133 write accesses @157609229 -system.cpu4: completed 60000 read, 32278 write accesses @158092666 -system.cpu7: completed 60000 read, 32237 write accesses @158094050 -system.cpu6: completed 60000 read, 32492 write accesses @158284016 -system.cpu2: completed 60000 read, 32099 write accesses @159310066 -system.cpu1: completed 60000 read, 32786 write accesses @160315811 -system.cpu5: completed 70000 read, 37785 write accesses @184174146 -system.cpu0: completed 70000 read, 37907 write accesses @184194427 -system.cpu3: completed 70000 read, 37695 write accesses @184756116 -system.cpu7: completed 70000 read, 37537 write accesses @185107500 -system.cpu6: completed 70000 read, 37865 write accesses @185115722 -system.cpu4: completed 70000 read, 37642 write accesses @185437602 -system.cpu2: completed 70000 read, 37459 write accesses @186101472 -system.cpu1: completed 70000 read, 38271 write accesses @187053767 -system.cpu0: completed 80000 read, 43182 write accesses @210453706 -system.cpu7: completed 80000 read, 43001 write accesses @210994557 -system.cpu5: completed 80000 read, 43199 write accesses @211075215 -system.cpu3: completed 80000 read, 43061 write accesses @211165517 -system.cpu4: completed 80000 read, 43118 write accesses @211798954 -system.cpu6: completed 80000 read, 43219 write accesses @211876903 -system.cpu2: completed 80000 read, 43025 write accesses @212410812 -system.cpu1: completed 80000 read, 43805 write accesses @214554639 -system.cpu0: completed 90000 read, 48653 write accesses @236986702 -system.cpu5: completed 90000 read, 48401 write accesses @237258796 -system.cpu7: completed 90000 read, 48251 write accesses @237456793 -system.cpu4: completed 90000 read, 48341 write accesses @237741580 -system.cpu3: completed 90000 read, 48504 write accesses @237892702 -system.cpu6: completed 90000 read, 48675 write accesses @238620248 -system.cpu2: completed 90000 read, 48457 write accesses @239205755 -system.cpu1: completed 90000 read, 49067 write accesses @239913307 -system.cpu5: completed 100000 read, 53710 write accesses @263488655 +system.cpu4: completed 10000 read, 5380 write accesses @22344646 +system.cpu6: completed 10000 read, 5214 write accesses @22747629 +system.cpu7: completed 10000 read, 5415 write accesses @22929508 +system.cpu2: completed 10000 read, 5407 write accesses @23019836 +system.cpu5: completed 10000 read, 5331 write accesses @23061044 +system.cpu0: completed 10000 read, 5432 write accesses @23140146 +system.cpu3: completed 10000 read, 5376 write accesses @23188049 +system.cpu1: completed 10000 read, 5387 write accesses @23350185 +system.cpu4: completed 20000 read, 10814 write accesses @44761691 +system.cpu7: completed 20000 read, 10827 write accesses @45213444 +system.cpu1: completed 20000 read, 10711 write accesses @45275122 +system.cpu6: completed 20000 read, 10548 write accesses @45324102 +system.cpu3: completed 20000 read, 10701 write accesses @45506880 +system.cpu2: completed 20000 read, 10922 write accesses @45734056 +system.cpu5: completed 20000 read, 10686 write accesses @45942373 +system.cpu0: completed 20000 read, 10937 write accesses @46044746 +system.cpu7: completed 30000 read, 16167 write accesses @66979485 +system.cpu4: completed 30000 read, 16361 write accesses @67223162 +system.cpu6: completed 30000 read, 15931 write accesses @67873351 +system.cpu3: completed 30000 read, 16353 write accesses @68348826 +system.cpu5: completed 30000 read, 16080 write accesses @68377482 +system.cpu1: completed 30000 read, 16196 write accesses @68419268 +system.cpu0: completed 30000 read, 16219 write accesses @68619325 +system.cpu2: completed 30000 read, 16526 write accesses @68648506 +system.cpu4: completed 40000 read, 21581 write accesses @88592659 +system.cpu7: completed 40000 read, 21651 write accesses @88863809 +system.cpu6: completed 40000 read, 21187 write accesses @89230569 +system.cpu1: completed 40000 read, 21556 write accesses @89813083 +system.cpu2: completed 40000 read, 21771 write accesses @90046604 +system.cpu3: completed 40000 read, 21725 write accesses @90210729 +system.cpu5: completed 40000 read, 21435 write accesses @90283858 +system.cpu0: completed 40000 read, 21836 write accesses @90947960 +system.cpu4: completed 50000 read, 27034 write accesses @111338978 +system.cpu6: completed 50000 read, 26346 write accesses @111492478 +system.cpu1: completed 50000 read, 26820 write accesses @112199634 +system.cpu7: completed 50000 read, 27390 write accesses @112358430 +system.cpu5: completed 50000 read, 26711 write accesses @112747804 +system.cpu3: completed 50000 read, 27030 write accesses @113062631 +system.cpu2: completed 50000 read, 27246 write accesses @113387493 +system.cpu0: completed 50000 read, 27088 write accesses @113621350 +system.cpu4: completed 60000 read, 32322 write accesses @134108306 +system.cpu6: completed 60000 read, 31811 write accesses @134700049 +system.cpu2: completed 60000 read, 32452 write accesses @135470855 +system.cpu1: completed 60000 read, 32239 write accesses @135474213 +system.cpu7: completed 60000 read, 32783 write accesses @135487924 +system.cpu5: completed 60000 read, 32297 write accesses @135551091 +system.cpu3: completed 60000 read, 32475 write accesses @135953364 +system.cpu0: completed 60000 read, 32594 write accesses @136506452 +system.cpu4: completed 70000 read, 37624 write accesses @156509147 +system.cpu6: completed 70000 read, 37191 write accesses @157507230 +system.cpu2: completed 70000 read, 37791 write accesses @158024045 +system.cpu7: completed 70000 read, 38252 write accesses @158415918 +system.cpu1: completed 70000 read, 37644 write accesses @158423190 +system.cpu5: completed 70000 read, 37691 write accesses @158678523 +system.cpu3: completed 70000 read, 38021 write accesses @158813067 +system.cpu0: completed 70000 read, 37965 write accesses @159679646 +system.cpu4: completed 80000 read, 42948 write accesses @178855235 +system.cpu6: completed 80000 read, 42510 write accesses @180069540 +system.cpu2: completed 80000 read, 43201 write accesses @180702038 +system.cpu1: completed 80000 read, 43267 write accesses @181114200 +system.cpu7: completed 80000 read, 43705 write accesses @181378010 +system.cpu3: completed 80000 read, 43552 write accesses @181443642 +system.cpu5: completed 80000 read, 43080 write accesses @181574154 +system.cpu0: completed 80000 read, 43418 write accesses @182451715 +system.cpu4: completed 90000 read, 48279 write accesses @201435873 +system.cpu6: completed 90000 read, 47918 write accesses @202390012 +system.cpu2: completed 90000 read, 48513 write accesses @203087400 +system.cpu1: completed 90000 read, 48611 write accesses @203141768 +system.cpu7: completed 90000 read, 48973 write accesses @204050544 +system.cpu5: completed 90000 read, 48423 write accesses @204299514 +system.cpu0: completed 90000 read, 48663 write accesses @204396348 +system.cpu3: completed 90000 read, 48999 write accesses @204475748 +system.cpu4: completed 100000 read, 53697 write accesses @224044586 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 4cc5a9b4f..2045d5848 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:15:53 +gem5 compiled Jun 28 2012 22:05:18 +gem5 started Jun 28 2012 22:09:54 gem5 executing on zizzer -command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest +command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 263488655 because maximum number of loads reached +Exiting @ tick 224044586 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9aa493322..9c1b7f7cc 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,378 +1,378 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000263 # Number of seconds simulated -sim_ticks 263488655 # Number of ticks simulated -final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000224 # Number of seconds simulated +sim_ticks 224044586 # Number of ticks simulated +final_tick 224044586 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 1558675 # Simulator tick rate (ticks/s) -host_mem_usage 343952 # Number of bytes of host memory used -host_seconds 169.05 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 504730 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 513456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 503221 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 509883 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 511138 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 501110 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 514161 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 499881 # Number of bytes read from this memory -system.physmem.bytes_read::total 4057580 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 2601216 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5392 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5426 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5325 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5406 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5472 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5362 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5419 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5298 # Number of bytes written to this memory -system.physmem.bytes_written::total 2644316 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 17740 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 17646 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 17743 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 17727 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 17848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 17774 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 17658 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 17742 # Number of read requests responded to by this memory -system.physmem.num_reads::total 141878 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 40644 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5392 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5325 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5406 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5472 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5362 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5419 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5298 # Number of write requests responded to by this memory -system.physmem.num_writes::total 83744 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 1915566346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 1948683521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 1909839344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 1935123165 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 1939886178 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 1901827614 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 1951359158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 1897163276 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 15399448602 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 9872212525 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 20463879 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 20592917 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 20209599 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 20517012 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 20767498 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 20350022 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 20566350 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 20107128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 10035786930 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 9872212525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 1936030225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 1969276438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 1930048943 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 1955640177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 1960653676 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 1922177636 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 1971925509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 1917270404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 25435235532 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 76856 # number of replacements -system.l2c.tagsinuse 657.714518 # Cycle average of tags in use -system.l2c.total_refs 139150 # Total number of references to valid blocks. -system.l2c.sampled_refs 77525 # Sample count of references to valid blocks. -system.l2c.avg_refs 1.794905 # Average number of references to valid blocks. +host_tick_rate 1786168 # Simulator tick rate (ticks/s) +host_mem_usage 347548 # Number of bytes of host memory used +host_seconds 125.43 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 89715 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 89291 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 88175 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 85667 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 87042 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 87583 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 89679 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 83220 # Number of bytes read from this memory +system.physmem.bytes_read::total 700372 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 455360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5322 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5377 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5241 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5325 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5339 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5367 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5417 # Number of bytes written to this memory +system.physmem.bytes_written::total 498192 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11091 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11171 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11126 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11075 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11127 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11244 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11085 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88957 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7115 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5322 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5241 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5325 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5339 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5367 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5417 # Number of write requests responded to by this memory +system.physmem.num_writes::total 49947 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 400433689 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 398541208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 393560057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 382365856 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 388503028 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 390917726 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 400273006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 371443923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3126038493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2032452594 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 23754200 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 23999687 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 23392665 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 23767591 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 23830078 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 23955053 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 24298735 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 24178223 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2223628827 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2032452594 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 424187889 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 422540895 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 416952722 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 406133447 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 412333106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 414872779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 424571741 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 395622146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 5349667320 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 14607 # number of replacements +system.l2c.tagsinuse 798.832185 # Cycle average of tags in use +system.l2c.total_refs 150557 # Total number of references to valid blocks. +system.l2c.sampled_refs 15432 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.756156 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 468.019905 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 24.077198 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 23.899612 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 23.566419 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 24.461210 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 24.025606 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 23.167376 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 23.494200 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 23.002994 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.457051 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.023513 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.023339 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.023014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.023888 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.023463 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.022624 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.022944 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.022464 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.642299 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10466 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10370 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10579 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10469 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10384 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10590 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10463 # number of ReadReq hits -system.l2c.ReadReq_hits::total 83711 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 94038 # number of Writeback hits -system.l2c.Writeback_hits::total 94038 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 457 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 419 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 446 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 463 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 463 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 415 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 411 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3504 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2829 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2819 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2901 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2765 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2827 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2929 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2882 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2913 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 22865 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 13295 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 13189 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 13480 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 13234 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 13217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 13313 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13472 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13376 # number of demand (read+write) hits -system.l2c.demand_hits::total 106576 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 13295 # number of overall hits -system.l2c.overall_hits::cpu1 13189 # number of overall hits -system.l2c.overall_hits::cpu2 13480 # number of overall hits -system.l2c.overall_hits::cpu3 13234 # number of overall hits -system.l2c.overall_hits::cpu4 13217 # number of overall hits -system.l2c.overall_hits::cpu5 13313 # number of overall hits -system.l2c.overall_hits::cpu6 13472 # number of overall hits -system.l2c.overall_hits::cpu7 13376 # number of overall hits -system.l2c.overall_hits::total 106576 # number of overall hits -system.l2c.ReadReq_misses::cpu0 5163 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 5186 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 5173 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 5223 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 5193 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 5114 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 5145 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 4996 # number of ReadReq misses -system.l2c.ReadReq_misses::total 41193 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1644 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1598 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1617 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1610 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1586 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1626 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1624 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1582 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12887 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 5539 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 5808 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 5466 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 5538 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 5599 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 5507 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 5800 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 5643 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 44900 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 10702 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 10994 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 10639 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 10761 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 10792 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 10621 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 10945 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 10639 # number of demand (read+write) misses -system.l2c.demand_misses::total 86093 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 10702 # number of overall misses -system.l2c.overall_misses::cpu1 10994 # number of overall misses -system.l2c.overall_misses::cpu2 10639 # number of overall misses -system.l2c.overall_misses::cpu3 10761 # number of overall misses -system.l2c.overall_misses::cpu4 10792 # number of overall misses -system.l2c.overall_misses::cpu5 10621 # number of overall misses -system.l2c.overall_misses::cpu6 10945 # number of overall misses -system.l2c.overall_misses::cpu7 10639 # number of overall misses -system.l2c.overall_misses::total 86093 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 256196985 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 257287128 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 256567876 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 259144977 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 257572428 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 253877351 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 255352806 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 247792064 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 2043791615 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 32636387 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 33737386 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 32855972 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 32255171 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 31405634 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 33663875 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 32311068 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 32543105 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 261408598 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 275716926 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 289198618 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 271873258 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 276122659 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 279168031 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 274243794 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 289241297 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 281223785 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 2236788368 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 531913911 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 546485746 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 528441134 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 535267636 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 536740459 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 528121145 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 544594103 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 529015849 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 4280579983 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 531913911 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 546485746 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 528441134 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 535267636 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 536740459 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 528121145 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 544594103 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 529015849 # number of overall miss cycles -system.l2c.overall_miss_latency::total 4280579983 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 15629 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 15556 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 15752 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 15692 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 15583 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 15498 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 15735 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 15459 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 124904 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 94038 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 94038 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2101 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2017 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2063 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2073 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2016 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2089 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2039 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 1993 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 16391 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 8368 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 8627 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 8367 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 8303 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 8426 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 8436 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 8682 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 8556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 67765 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 23997 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 24183 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 24119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 23995 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 24009 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 23934 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 24417 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 24015 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 192669 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 23997 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 24183 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 24119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 23995 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 24009 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 23934 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 24417 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 24015 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 192669 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.330347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.333376 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.328403 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.332845 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.333248 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.329978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.326978 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.323177 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.329797 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.776652 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.778363 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.796469 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.786224 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.661926 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.673235 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.653281 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.666988 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.664491 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.652798 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.668049 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.659537 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.662584 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.445972 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.454617 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.441105 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.448468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.449498 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.443762 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.448253 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.443015 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.446844 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.445972 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.454617 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.441105 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.448468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.449498 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.443762 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.448253 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.443015 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.446844 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 49616.116600 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 49615.022334 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 20284.674323 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 49859.635067 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 49817.112873 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 49702.290320 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 49707.635619 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 49670.188364 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 49741.440015 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 49735.031412 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 49724.239243 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 49757.341526 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 49724.208008 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 49720.418420 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 49702.290320 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 49707.635619 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 49670.188364 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 49741.440015 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 49735.031412 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 49724.239243 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 49757.341526 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 49724.208008 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 49720.418420 # average overall miss latency +system.l2c.occ_blocks::writebacks 740.812109 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.661361 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.247095 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.177515 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 6.855610 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 7.321397 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 7.120032 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 7.753138 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 6.883928 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.723449 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007482 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007077 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007009 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.006695 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007150 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.006953 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.007571 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.006723 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.780110 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10638 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10673 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10613 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10754 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10954 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10851 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10889 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86243 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 75632 # number of Writeback hits +system.l2c.Writeback_hits::total 75632 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 349 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 360 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 332 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 339 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 326 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 357 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2743 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 1883 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1924 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2003 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1977 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 1920 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1982 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 1896 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 15565 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12618 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12556 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12795 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12731 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12874 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12833 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12785 # number of demand (read+write) hits +system.l2c.demand_hits::total 101808 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12618 # number of overall hits +system.l2c.overall_hits::cpu1 12556 # number of overall hits +system.l2c.overall_hits::cpu2 12795 # number of overall hits +system.l2c.overall_hits::cpu3 12616 # number of overall hits +system.l2c.overall_hits::cpu4 12731 # number of overall hits +system.l2c.overall_hits::cpu5 12874 # number of overall hits +system.l2c.overall_hits::cpu6 12833 # number of overall hits +system.l2c.overall_hits::cpu7 12785 # number of overall hits +system.l2c.overall_hits::total 101808 # number of overall hits +system.l2c.ReadReq_misses::cpu0 834 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 832 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 822 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 780 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 790 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 794 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 838 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 736 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6426 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1913 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1876 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1922 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 2012 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1999 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1918 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1887 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15459 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4394 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4308 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4316 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4354 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4292 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4292 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4233 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4328 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34517 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5228 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5140 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5138 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5134 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5082 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5086 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5071 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5064 # number of demand (read+write) misses +system.l2c.demand_misses::total 40943 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5228 # number of overall misses +system.l2c.overall_misses::cpu1 5140 # number of overall misses +system.l2c.overall_misses::cpu2 5138 # number of overall misses +system.l2c.overall_misses::cpu3 5134 # number of overall misses +system.l2c.overall_misses::cpu4 5082 # number of overall misses +system.l2c.overall_misses::cpu5 5086 # number of overall misses +system.l2c.overall_misses::cpu6 5071 # number of overall misses +system.l2c.overall_misses::cpu7 5064 # number of overall misses +system.l2c.overall_misses::total 40943 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 41350032 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 41129977 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 40786420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 38596362 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 39278271 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 39541044 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 41568753 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 36525760 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 318776619 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 49804280 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 51885731 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 53676097 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 52486307 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 52437029 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 51272005 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 52254582 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 52654576 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 416470607 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 219461654 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 215283667 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 215604529 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 217440085 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 214512687 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 214479862 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 211622352 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 216182446 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1724587282 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 260811686 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 256413644 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 256390949 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 256036447 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 253790958 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 254020906 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 253191105 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 252708206 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2043363901 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 260811686 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 256413644 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 256390949 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 256036447 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 253790958 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 254020906 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 253191105 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 252708206 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2043363901 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11472 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11505 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11693 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11393 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11544 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11748 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11689 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11625 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 92669 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 75632 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 75632 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2243 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2225 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2282 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2362 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2331 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2257 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2213 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2289 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18202 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6374 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6191 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6240 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6357 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6269 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6212 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6215 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6224 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50082 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17846 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 17696 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17933 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17750 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 17813 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 17960 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17904 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17849 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 142751 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17846 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 17696 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17933 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17750 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 17813 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 17960 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17904 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17849 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 142751 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.072699 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.072316 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.070298 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.068463 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.068434 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.067586 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.071691 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.063312 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.069344 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.852876 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.843146 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.842244 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.851820 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.857572 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.849801 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.852689 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.844037 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.849302 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.689363 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.695849 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.691667 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.684914 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.684639 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.690921 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.681094 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.695373 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.689210 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.292951 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.290461 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.286511 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.289239 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.285297 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.283185 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.283233 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.283713 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.286814 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.292951 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.290461 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.286511 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.289239 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.285297 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.283185 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.283233 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.283713 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.286814 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 49580.374101 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 49435.068510 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 49618.515815 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 49482.515385 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 49719.330380 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 49799.803526 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 49604.717184 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 49627.391304 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 49607.316993 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 26034.647151 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27657.639126 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27927.209677 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 26086.633698 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 26231.630315 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 26732.015120 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 27691.882353 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 27253.921325 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 26940.332945 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 49945.756486 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 49972.996054 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 49954.710148 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 49940.304318 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 49979.656803 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 49972.008854 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 49993.468462 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 49949.733364 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 49963.417504 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 49887.468630 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 49885.922957 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 49900.924290 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 49870.753214 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 49939.188902 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 49945.125049 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 49929.225991 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 49902.884281 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 49907.527563 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 49887.468630 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 49885.922957 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 49900.924290 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 49870.753214 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 49939.188902 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 49945.125049 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 49929.225991 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 49902.884281 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 49907.527563 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked @@ -381,260 +381,257 @@ system.l2c.avg_blocked_cycles::no_mshrs 6964.928571 # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 40644 # number of writebacks -system.l2c.writebacks::total 40644 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 118 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 121 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 142 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 119 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 123 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 114 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 110 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 114 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 961 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 7 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 8 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu2 5 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu3 7 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu4 6 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu5 5 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu6 5 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu7 6 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::total 49 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 68 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 72 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu2 73 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 47 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 55 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 72 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 58 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 62 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 507 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 186 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 193 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 215 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 166 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 178 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 186 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 168 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 176 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1468 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 186 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 193 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 215 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 166 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 178 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 186 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 168 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 176 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1468 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 5045 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 5065 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 5031 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 5104 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 5070 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 5000 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 5035 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 4882 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 40232 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1637 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1590 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1612 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1603 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1580 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1621 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1619 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1576 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12838 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 5471 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 5736 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 5393 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 5491 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 5544 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 5435 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 5742 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 5581 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 44393 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 10516 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 10801 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 10424 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 10595 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 10614 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 10435 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 10777 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 10463 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 84625 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 10516 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 10801 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 10424 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 10595 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 10614 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 10435 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 10777 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 10463 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 84625 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 201814482 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 202614244 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 201254484 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 204173248 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 202773617 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 200011523 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 201333402 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 195252416 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1609227416 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 65483665 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 63563227 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 64483276 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 64122909 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 63203179 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 64843827 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 64763487 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 63043487 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 513507057 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 218853383 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 229413457 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 215692606 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 219654421 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 221773547 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 217413717 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 229694076 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 223253131 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1775748338 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 420667865 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 432027701 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 416947090 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 423827669 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 424547164 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 417425240 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 431027478 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 418505547 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 3384975754 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 420667865 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 432027701 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 416947090 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 423827669 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 424547164 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 417425240 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 431027478 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 418505547 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 3384975754 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 400422345 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 391061487 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 401502890 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 396621827 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 400743471 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 404102628 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 391101960 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 403583386 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3189139994 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 215688086 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 217048117 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 213007261 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 216128145 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 218848364 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214487951 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 216767566 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 211927994 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1723903484 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 616110431 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 608109604 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 614510151 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 612749972 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 619591835 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 618590579 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 607869526 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 615511380 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 4913043478 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.322797 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.325598 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.319388 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.325261 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.325355 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.322622 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.319987 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.315803 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.322103 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.779153 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.781386 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.773275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.783730 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.775969 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.794017 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.790768 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.783235 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.653800 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.664889 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.644556 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.661327 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.657963 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.644263 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.661368 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.652291 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.655102 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.439225 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.438221 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.446636 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.432190 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.441550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.442084 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.435991 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.441373 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.435686 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.439225 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40002.595611 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 39998.692981 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40001.814722 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39998.991821 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40002.626298 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40000.638344 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.611515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39999.713489 # average overall mshr miss latency +system.l2c.writebacks::writebacks 7115 # number of writebacks +system.l2c.writebacks::total 7115 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 23 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 22 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 24 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 13 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 19 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 17 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu1 4 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu4 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu5 2 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::total 9 # number of UpgradeReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 8 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 13 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 15 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 9 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 12 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 89 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 31 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 35 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 39 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 28 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 24 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 23 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 29 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 244 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 31 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 35 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 39 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 28 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 24 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 23 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 29 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 244 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 812 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 809 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 800 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 756 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 777 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 779 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 819 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 719 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6271 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1913 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1872 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 2011 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1998 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1916 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1887 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1932 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15450 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4381 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4300 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4303 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4339 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4277 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4283 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4229 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4316 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34428 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5193 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5109 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5103 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5095 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5054 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5062 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5048 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5035 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40699 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5193 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5109 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5103 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5095 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5054 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5062 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5048 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5035 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40699 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 32483716 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 32363556 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 32004501 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 30243000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 31083178 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 31162243 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 32763319 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 28723011 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 250826524 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76520708 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 74880632 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 76840756 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 80440711 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79880909 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 76600687 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75440727 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 77280682 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 617885812 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 175203645 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 171923291 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 172082750 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 173484044 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 171083248 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 171323717 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 169163499 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 172603062 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1376867256 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 207687361 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 204286847 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 204087251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 203727044 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 202166426 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 202485960 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 201926818 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 201326073 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1627693780 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 207687361 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 204286847 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 204087251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 203727044 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 202166426 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 202485960 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 201926818 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 201326073 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1627693780 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 393605068 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397164440 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 396084825 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 395564887 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 396845191 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 392884701 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 399924937 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 397605829 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3169679878 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 212842079 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 215082041 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 209602015 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 213002165 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 213521784 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 214681989 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 217761849 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 216562185 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1713056107 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 606447147 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 612246481 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 605686840 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 608567052 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 610366975 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 607566690 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 617686786 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 614168014 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 4882735985 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070781 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070317 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068417 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.066357 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067308 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.066309 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.070066 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061849 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.067671 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852876 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.841348 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.841805 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.851397 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.857143 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.848914 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.852689 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.844037 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.848808 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.687324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.694557 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.689583 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.682555 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.682246 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.689472 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680451 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.693445 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.687433 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285105 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.290990 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.288709 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.284559 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.287042 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.283725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281849 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.281948 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.282089 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285105 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40004.576355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40004.395550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40005.626250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40003.968254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 40004.090090 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.879332 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 40004.052503 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39948.554937 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 39997.851060 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40000.370099 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40000.337607 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40000.393545 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40000.353555 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 39980.434935 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 39979.481733 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 39979.187599 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40000.353002 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 39992.609191 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 39991.701666 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39982.160698 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39991.343249 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 39982.494584 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40000.759411 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40000.867850 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40000.827382 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 39991.441613 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39992.658766 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 39993.714808 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 39985.681542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 39993.582403 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 39985.680864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 40001.271468 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 40001.177400 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 40001.350634 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 39985.317378 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39993.458807 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -663,114 +660,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 99815 # number of read accesses completed -system.cpu0.num_writes 53929 # number of write accesses completed +system.cpu0.num_reads 98637 # number of read accesses completed +system.cpu0.num_writes 53345 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 27826 # number of replacements -system.cpu0.l1c.tagsinuse 347.331950 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11604 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 28187 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.411679 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22018 # number of replacements +system.cpu0.l1c.tagsinuse 396.710521 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13223 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22420 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.589786 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 347.331950 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.678383 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.678383 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 7530 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 7530 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1059 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1059 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 8589 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 8589 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 8589 # number of overall hits -system.cpu0.l1c.overall_hits::total 8589 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 37279 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 37279 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23202 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23202 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 60481 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 60481 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 60481 # number of overall misses -system.cpu0.l1c.overall_misses::total 60481 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1299667421 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1299667421 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1001508092 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1001508092 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2301175513 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2301175513 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2301175513 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2301175513 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44809 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44809 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24261 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 69070 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 69070 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 69070 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 69070 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.831953 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.831953 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956350 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956350 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.875648 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.875648 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.875648 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.875648 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 34863.258698 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 43164.731144 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 38047.907822 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 38047.907822 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.710521 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.774825 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.774825 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8580 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8580 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1119 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1119 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9699 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9699 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9699 # number of overall hits +system.cpu0.l1c.overall_hits::total 9699 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35932 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35932 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23215 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23215 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59147 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59147 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59147 # number of overall misses +system.cpu0.l1c.overall_misses::total 59147 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 928213854 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 928213854 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 888665457 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 888665457 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 1816879311 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 1816879311 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 1816879311 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 1816879311 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44512 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44512 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24334 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24334 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 68846 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 68846 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 68846 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 68846 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.807243 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.807243 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954015 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954015 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.859120 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.859120 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.859120 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.859120 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 25832.512913 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 25832.512913 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 38279.795692 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 38279.795692 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 30718.029841 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 30718.029841 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 30718.029841 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 30718.029841 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 213519076 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67191 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3673.059398 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3177.792800 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 11972 # number of writebacks -system.cpu0.l1c.writebacks::total 11972 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 37279 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 37279 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23202 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23202 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 60481 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 60481 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 60481 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 60481 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262244251 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262244251 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 978215253 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 978215253 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2240459504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2240459504 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2240459504 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2240459504 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 894578632 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 894578632 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 569723237 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 569723237 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1464301869 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1464301869 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.831953 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.831953 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956350 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956350 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.875648 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.875648 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.875648 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 33859.391373 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 42160.816007 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 37044.022156 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9668 # number of writebacks +system.cpu0.l1c.writebacks::total 9668 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35932 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35932 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23215 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23215 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59147 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59147 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59147 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59147 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 892144080 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 892144080 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 865359572 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 865359572 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 1757503652 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 1757503652 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 1757503652 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 1757503652 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 897451639 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 897451639 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 561857596 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 561857596 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1459309235 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1459309235 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.807243 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.807243 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954015 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954015 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.859120 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859120 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.859120 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 24828.678615 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 24828.678615 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 37275.880767 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 37275.880767 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 29714.163897 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 29714.163897 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -778,114 +775,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98493 # number of read accesses completed -system.cpu1.num_writes 53671 # number of write accesses completed +system.cpu1.num_reads 99346 # number of read accesses completed +system.cpu1.num_writes 53405 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 27684 # number of replacements -system.cpu1.l1c.tagsinuse 345.656340 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11419 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 28039 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.407254 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21836 # number of replacements +system.cpu1.l1c.tagsinuse 395.252412 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13010 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22258 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.584509 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 345.656340 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.675110 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.675110 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 7429 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 7429 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1066 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1066 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 8495 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 8495 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 8495 # number of overall hits -system.cpu1.l1c.overall_hits::total 8495 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 37110 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 37110 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 23275 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 23275 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 60385 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 60385 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 60385 # number of overall misses -system.cpu1.l1c.overall_misses::total 60385 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 1301760811 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 1301760811 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 1014297005 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1014297005 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2316057816 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2316057816 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2316057816 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2316057816 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44539 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44539 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24341 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24341 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68880 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68880 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68880 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68880 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.833202 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.833202 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956206 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.956206 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.876670 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.876670 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.876670 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.876670 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 35078.437375 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 43578.818690 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 38354.853291 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 38354.853291 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 395.252412 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.771977 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.771977 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8468 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8468 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1045 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1045 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9513 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9513 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9513 # number of overall hits +system.cpu1.l1c.overall_hits::total 9513 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 36170 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 36170 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22843 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22843 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 59013 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 59013 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 59013 # number of overall misses +system.cpu1.l1c.overall_misses::total 59013 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 930956991 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 930956991 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 873445374 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 873445374 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 1804402365 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 1804402365 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 1804402365 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 1804402365 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44638 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44638 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23888 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23888 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68526 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68526 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68526 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68526 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.810296 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.810296 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.956254 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.956254 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.861177 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.861177 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.861177 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.861177 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 25738.374095 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 25738.374095 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 38236.894191 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 38236.894191 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 30576.353770 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 30576.353770 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 30576.353770 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 30576.353770 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 212850460 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 67062 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3680.878237 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3173.935463 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 11809 # number of writebacks -system.cpu1.l1c.writebacks::total 11809 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 37110 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 37110 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23275 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23275 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 60385 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 60385 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 60385 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 60385 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1264508347 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1264508347 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 990933889 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 990933889 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2255442236 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2255442236 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2255442236 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2255442236 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 877119159 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 877119159 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 578327433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 578327433 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1455446592 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.833202 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956206 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956206 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.876670 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.876670 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 34074.598410 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 42575.032825 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 37351.034793 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9414 # number of writebacks +system.cpu1.l1c.writebacks::total 9414 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 36170 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22843 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22843 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 59013 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 59013 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 59013 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 59013 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 894646237 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 894646237 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 850514976 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 850514976 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 1745161213 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 1745161213 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 1745161213 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 1745161213 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 906808922 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 906808922 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 573615954 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 573615954 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1480424876 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1480424876 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.810296 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.810296 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.956254 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.956254 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.861177 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.861177 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.861177 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 24734.482638 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 24734.482638 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 37233.068161 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 37233.068161 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 29572.487638 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 29572.487638 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -893,114 +890,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 99149 # number of read accesses completed -system.cpu2.num_writes 53185 # number of write accesses completed +system.cpu2.num_reads 99179 # number of read accesses completed +system.cpu2.num_writes 53408 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 27627 # number of replacements -system.cpu2.l1c.tagsinuse 345.430231 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11519 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 27982 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.411657 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21970 # number of replacements +system.cpu2.l1c.tagsinuse 396.422513 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13458 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22394 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.600965 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 345.430231 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.674668 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.674668 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 7576 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 7576 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1069 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1069 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 8645 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 8645 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 8645 # number of overall hits -system.cpu2.l1c.overall_hits::total 8645 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 37144 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 37144 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22885 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22885 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 60029 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 60029 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 60029 # number of overall misses -system.cpu2.l1c.overall_misses::total 60029 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 1302790562 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 1302790562 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 991654869 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 991654869 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2294445431 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2294445431 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2294445431 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2294445431 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44720 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44720 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23954 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23954 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68674 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68674 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68674 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68674 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.830590 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.830590 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955373 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955373 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.874115 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.874115 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.874115 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.874115 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 35074.051314 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 43332.089535 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 38222.283080 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 38222.283080 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 254303447 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 396.422513 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.774263 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.774263 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8875 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8875 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1083 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9958 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9958 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9958 # number of overall hits +system.cpu2.l1c.overall_hits::total 9958 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35921 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35921 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23014 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23014 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58935 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58935 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58935 # number of overall misses +system.cpu2.l1c.overall_misses::total 58935 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 936514854 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 936514854 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 882688372 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 882688372 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 1819203226 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 1819203226 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 1819203226 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 1819203226 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44796 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44796 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24097 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24097 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68893 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68893 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68893 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68893 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.801880 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.801880 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955057 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.955057 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.855457 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.855457 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.855457 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.855457 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 26071.513989 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 26071.513989 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 38354.409142 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 38354.409142 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 30867.960058 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 30867.960058 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 30867.960058 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 30867.960058 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 215347558 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 68698 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 67274 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3701.759105 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3201.051788 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 11784 # number of writebacks -system.cpu2.l1c.writebacks::total 11784 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 37144 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 37144 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22885 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22885 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 60029 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 60029 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 60029 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 60029 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1265501937 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1265501937 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 968684322 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 968684322 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2234186259 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2234186259 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2234186259 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2234186259 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 900513056 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 900513056 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 566349170 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 566349170 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1466862226 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1466862226 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.830590 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.830590 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955373 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955373 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.874115 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.874115 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.874115 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 34070.157684 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 42328.351409 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 37218.448733 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9572 # number of writebacks +system.cpu2.l1c.writebacks::total 9572 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35921 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35921 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23014 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23014 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58935 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58935 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58935 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58935 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 900454097 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 900454097 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 859588304 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 859588304 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 1760042401 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 1760042401 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 1760042401 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 1760042401 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 903394412 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 903394412 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 551786925 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 551786925 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1455181337 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1455181337 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.801880 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.801880 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955057 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955057 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.855457 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855457 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.855457 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 25067.623312 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 25067.623312 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 37350.669332 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 37350.669332 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 29864.128294 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 29864.128294 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1008,114 +1005,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 99588 # number of read accesses completed -system.cpu3.num_writes 53645 # number of write accesses completed +system.cpu3.num_reads 98310 # number of read accesses completed +system.cpu3.num_writes 53451 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 27837 # number of replacements -system.cpu3.l1c.tagsinuse 347.574885 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11563 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 28190 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.410181 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21775 # number of replacements +system.cpu3.l1c.tagsinuse 395.971374 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13179 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22179 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.594211 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 347.574885 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.678857 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.678857 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 7552 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 7552 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1078 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1078 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 8630 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 8630 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 8630 # number of overall hits -system.cpu3.l1c.overall_hits::total 8630 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 37191 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 37191 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 23219 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 23219 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 60410 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 60410 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 60410 # number of overall misses -system.cpu3.l1c.overall_misses::total 60410 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1312024933 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1312024933 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 995527685 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 995527685 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2307552618 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2307552618 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2307552618 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2307552618 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44743 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44743 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24297 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24297 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 69040 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 69040 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 69040 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 69040 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.831214 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.831214 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.955632 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.955632 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.875000 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.875000 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.875000 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.875000 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 35278.022452 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 42875.562470 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 38198.189340 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 38198.189340 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 254462667 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.971374 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.773382 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.773382 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8374 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8374 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1100 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1100 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9474 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9474 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9474 # number of overall hits +system.cpu3.l1c.overall_hits::total 9474 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35667 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35667 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23305 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23305 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58972 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58972 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58972 # number of overall misses +system.cpu3.l1c.overall_misses::total 58972 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 919630073 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 919630073 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 893117472 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 893117472 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 1812747545 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 1812747545 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 1812747545 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 1812747545 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44041 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44041 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24405 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24405 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68446 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68446 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68446 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68446 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.809859 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.809859 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954927 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954927 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.861584 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.861584 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.861584 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.861584 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 25783.779768 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 25783.779768 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 38322.998155 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 38322.998155 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 30739.122719 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 30739.122719 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 30739.122719 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 30739.122719 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 213693223 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 68939 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67039 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3691.127910 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3187.595623 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 11956 # number of writebacks -system.cpu3.l1c.writebacks::total 11956 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 37191 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 37191 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23219 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 23219 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 60410 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 60410 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 60410 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 60410 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1274692143 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1274692143 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 972218785 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 972218785 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2246910928 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2246910928 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2246910928 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2246910928 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 889431937 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 889431937 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 569772276 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 569772276 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1459204213 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1459204213 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.831214 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.831214 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.955632 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.955632 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.875000 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.875000 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.875000 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34274.209970 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 41871.690641 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 37194.354047 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9546 # number of writebacks +system.cpu3.l1c.writebacks::total 9546 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35667 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35667 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23305 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23305 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58972 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58972 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58972 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58972 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 883822339 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 883822339 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 869724232 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 869724232 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 1753546571 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 1753546571 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 1753546571 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 1753546571 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 901886993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 901886993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 561139437 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 561139437 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1463026430 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1463026430 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.809859 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.809859 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954927 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954927 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.861584 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.861584 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.861584 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 24779.833992 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 24779.833992 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 37319.211843 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 37319.211843 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 29735.239961 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 29735.239961 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1123,114 +1120,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99725 # number of read accesses completed -system.cpu4.num_writes 53533 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 53697 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 27683 # number of replacements -system.cpu4.l1c.tagsinuse 347.631602 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11724 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 28041 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.418102 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22069 # number of replacements +system.cpu4.l1c.tagsinuse 396.565187 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13244 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22489 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.588910 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 347.631602 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.678968 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.678968 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 7686 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 7686 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1123 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1123 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 8809 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 8809 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 8809 # number of overall hits -system.cpu4.l1c.overall_hits::total 8809 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 37251 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 37251 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22937 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22937 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 60188 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 60188 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 60188 # number of overall misses -system.cpu4.l1c.overall_misses::total 60188 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1303112178 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1303112178 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 994450363 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 994450363 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2297562541 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2297562541 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2297562541 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2297562541 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44937 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44937 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24060 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24060 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68997 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68997 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68997 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68997 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.828961 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.828961 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.953325 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.953325 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.872328 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.872328 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.872328 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.872328 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 34981.938149 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 43355.729302 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 38173.099970 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 38173.099970 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 396.565187 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.774541 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.774541 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8614 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8614 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1053 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1053 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9667 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9667 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9667 # number of overall hits +system.cpu4.l1c.overall_hits::total 9667 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36078 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36078 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23045 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23045 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59123 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59123 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59123 # number of overall misses +system.cpu4.l1c.overall_misses::total 59123 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 933502205 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 933502205 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 883607398 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 883607398 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 1817109603 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 1817109603 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 1817109603 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 1817109603 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44692 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44692 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24098 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24098 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68790 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68790 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68790 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68790 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.807259 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.807259 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956303 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956303 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.859471 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.859471 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.859471 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.859471 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 25874.555269 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 25874.555269 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 38342.694641 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 38342.694641 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 30734.394449 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 30734.394449 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 30734.394449 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 30734.394449 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 213249503 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67264 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3690.197653 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3170.336331 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 11763 # number of writebacks -system.cpu4.l1c.writebacks::total 11763 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 37251 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 37251 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22937 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22937 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 60188 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 60188 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 60188 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 60188 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1265717116 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1265717116 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 971425596 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 971425596 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2237142712 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2237142712 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2237142712 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2237142712 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 898461911 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 898461911 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 576408625 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 576408625 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1474870536 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1474870536 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.828961 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.828961 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.953325 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.953325 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.872328 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.872328 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.872328 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 33978.070817 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 42351.902864 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 37169.248222 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9627 # number of writebacks +system.cpu4.l1c.writebacks::total 9627 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36078 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36078 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23045 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23045 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59123 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59123 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59123 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59123 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 897285830 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 897285830 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 860474190 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 860474190 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 1757760020 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 1757760020 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 1757760020 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 1757760020 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 897898466 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 897898466 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 564390024 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 564390024 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1462288490 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1462288490 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.807259 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.807259 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956303 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956303 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.859471 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.859471 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.859471 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 24870.719829 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 24870.719829 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 37338.866999 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 37338.866999 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 29730.562049 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 29730.562049 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1238,114 +1235,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 100000 # number of read accesses completed -system.cpu5.num_writes 53710 # number of write accesses completed +system.cpu5.num_reads 98755 # number of read accesses completed +system.cpu5.num_writes 53000 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 27832 # number of replacements -system.cpu5.l1c.tagsinuse 346.806811 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11748 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 28191 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.416729 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21964 # number of replacements +system.cpu5.l1c.tagsinuse 395.335157 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13162 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22364 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.588535 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 346.806811 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.677357 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.677357 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 7592 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 7592 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1126 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1126 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 8718 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 8718 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 8718 # number of overall hits -system.cpu5.l1c.overall_hits::total 8718 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 37349 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 37349 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 23013 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 23013 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 60362 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 60362 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 60362 # number of overall misses -system.cpu5.l1c.overall_misses::total 60362 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1291933371 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1291933371 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 998304045 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 998304045 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2290237416 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2290237416 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2290237416 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2290237416 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44941 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24139 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24139 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 69080 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 69080 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 69080 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.831067 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.953353 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.953353 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.873798 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.873798 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.873798 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.873798 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 34590.842352 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 43380.004563 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 37941.708625 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 37941.708625 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 395.335157 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.772139 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.772139 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8580 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8580 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1063 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1063 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9643 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9643 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9643 # number of overall hits +system.cpu5.l1c.overall_hits::total 9643 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 36060 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 36060 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22989 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22989 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 59049 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 59049 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 59049 # number of overall misses +system.cpu5.l1c.overall_misses::total 59049 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 944228607 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 944228607 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 875107262 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 875107262 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 1819335869 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 1819335869 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 1819335869 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 1819335869 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44640 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44640 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24052 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24052 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68692 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68692 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68692 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68692 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.807796 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.807796 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.955804 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.955804 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859620 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859620 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859620 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859620 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 26184.930865 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 26184.930865 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 38066.347471 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 38066.347471 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 30810.612695 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 30810.612695 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 30810.612695 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 30810.612695 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 213071792 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 67023 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3673.840624 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3179.084672 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 11908 # number of writebacks -system.cpu5.l1c.writebacks::total 11908 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 37349 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 37349 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 23013 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 23013 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 60362 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 60362 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 60362 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 60362 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1254436910 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1254436910 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 975203983 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 975203983 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2229640893 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2229640893 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2229640893 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2229640893 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 902856034 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 902856034 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567587171 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567587171 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1470443205 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1470443205 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.831067 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.831067 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.953353 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.953353 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.873798 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.873798 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.873798 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 33586.894160 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 42376.221397 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 36937.823349 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9605 # number of writebacks +system.cpu5.l1c.writebacks::total 9605 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 36060 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 36060 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22989 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22989 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 59049 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 59049 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 59049 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 59049 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 908030320 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 908030320 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 852027269 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 852027269 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 1760057589 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 1760057589 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 1760057589 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 1760057589 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 893562759 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 893562759 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 567489251 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 567489251 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1461052010 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1461052010 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.807796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.807796 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.955804 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.955804 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859620 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859620 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859620 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 25181.095951 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 25181.095951 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 37062.389360 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 37062.389360 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 29806.729818 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 29806.729818 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1353,114 +1350,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 99389 # number of read accesses completed -system.cpu6.num_writes 53686 # number of write accesses completed +system.cpu6.num_reads 99515 # number of read accesses completed +system.cpu6.num_writes 53091 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 27861 # number of replacements -system.cpu6.l1c.tagsinuse 347.289326 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11520 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 28198 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.408540 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21875 # number of replacements +system.cpu6.l1c.tagsinuse 395.073790 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13163 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22301 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.590243 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 347.289326 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.678299 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.678299 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 7543 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 7543 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1119 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1119 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 8662 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 8662 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 8662 # number of overall hits -system.cpu6.l1c.overall_hits::total 8662 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 37109 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 37109 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23142 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23142 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 60251 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 60251 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 60251 # number of overall misses -system.cpu6.l1c.overall_misses::total 60251 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1299799162 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1299799162 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1015775810 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1015775810 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2315574972 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2315574972 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2315574972 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2315574972 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44652 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24261 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68913 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68913 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68913 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68913 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.831071 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.831071 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.953877 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.953877 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.874305 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.874305 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.874305 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.874305 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 35026.520844 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 43893.173019 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 38432.141740 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 38432.141740 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 395.073790 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.771628 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.771628 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8660 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8660 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1070 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1070 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9730 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9730 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9730 # number of overall hits +system.cpu6.l1c.overall_hits::total 9730 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36079 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36079 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22730 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22730 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58809 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58809 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58809 # number of overall misses +system.cpu6.l1c.overall_misses::total 58809 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 942403765 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 942403765 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 866225957 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 866225957 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 1808629722 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 1808629722 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 1808629722 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 1808629722 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44739 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44739 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23800 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23800 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68539 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68539 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68539 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68539 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806433 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.806433 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.955042 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.955042 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858037 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858037 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858037 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858037 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 26120.562238 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 26120.562238 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 38109.368984 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 38109.368984 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 30754.301586 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 30754.301586 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 30754.301586 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 30754.301586 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 212806358 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66914 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3698.984332 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3180.296470 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 11849 # number of writebacks -system.cpu6.l1c.writebacks::total 11849 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 37109 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 37109 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23142 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23142 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 60251 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 60251 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 60251 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 60251 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262548698 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262548698 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 992541214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 992541214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2255089912 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2255089912 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2255089912 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2255089912 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 877981455 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 877981455 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 574689009 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1452670464 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.831071 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.953877 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.953877 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.874305 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.874305 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 34022.708723 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 42889.171809 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 37428.256992 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9438 # number of writebacks +system.cpu6.l1c.writebacks::total 9438 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36079 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36079 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22730 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22730 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58809 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58809 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58809 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58809 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 906189412 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 906189412 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 843405989 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 843405989 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 1749595401 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 1749595401 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 1749595401 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 1749595401 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 905213986 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 905213986 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 576398345 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 576398345 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1481612331 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1481612331 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806433 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806433 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.955042 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.955042 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858037 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858037 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858037 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 25116.810665 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 25116.810665 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 37105.410867 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 37105.410867 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 29750.470183 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 29750.470183 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1468,114 +1465,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 99694 # number of read accesses completed -system.cpu7.num_writes 53501 # number of write accesses completed +system.cpu7.num_reads 98608 # number of read accesses completed +system.cpu7.num_writes 53688 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 27727 # number of replacements -system.cpu7.l1c.tagsinuse 346.094259 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11534 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 28062 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.411018 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 21767 # number of replacements +system.cpu7.l1c.tagsinuse 394.473547 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13199 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22171 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.595327 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 346.094259 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.675965 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.675965 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 7593 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 7593 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1111 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1111 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 8704 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 8704 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 8704 # number of overall hits -system.cpu7.l1c.overall_hits::total 8704 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 37155 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 37155 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 23121 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 23121 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 60276 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 60276 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 60276 # number of overall misses -system.cpu7.l1c.overall_misses::total 60276 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1287127315 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1287127315 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1006139538 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1006139538 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2293266853 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2293266853 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2293266853 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2293266853 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44748 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44748 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24232 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24232 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68980 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68980 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.830316 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.954152 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.873818 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.873818 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 34642.102409 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 43516.263916 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 38046.102147 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 38046.102147 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 394.473547 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.770456 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.770456 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8649 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8649 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 995 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 995 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9644 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9644 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9644 # number of overall hits +system.cpu7.l1c.overall_hits::total 9644 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35884 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35884 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23099 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23099 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58983 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58983 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58983 # number of overall misses +system.cpu7.l1c.overall_misses::total 58983 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 932010776 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 932010776 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 877703149 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 877703149 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 1809713925 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 1809713925 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 1809713925 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 1809713925 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44533 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44533 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24094 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24094 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68627 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68627 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68627 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68627 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805784 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.805784 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.958703 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.958703 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.859472 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.859472 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.859472 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.859472 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 25972.878609 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 25972.878609 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 37997.452227 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 37997.452227 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 30681.957937 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 30681.957937 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 30681.957937 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 30681.957937 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 213241981 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67091 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3679.369981 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3178.399204 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 11797 # number of writebacks -system.cpu7.l1c.writebacks::total 11797 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 37155 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 37155 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23121 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 23121 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 60276 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 60276 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 60276 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 60276 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1249829653 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1249829653 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 982928032 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 982928032 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2232757685 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2232757685 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2232757685 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2232757685 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 901961636 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 901961636 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 558194703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.830316 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954152 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.873818 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.873818 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 33638.262764 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 42512.349466 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 37042.233808 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9457 # number of writebacks +system.cpu7.l1c.writebacks::total 9457 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35884 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35884 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23099 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23099 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58983 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58983 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58983 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58983 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 895990178 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 895990178 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 854514720 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 854514720 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 1750504898 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 1750504898 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 1750504898 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 1750504898 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 906836045 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 906836045 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 572746318 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 572746318 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1479582363 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1479582363 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805784 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805784 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.958703 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.958703 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.859472 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.859472 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.859472 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 24969.071954 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 24969.071954 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 36993.580674 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 36993.580674 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 29678.125867 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 29678.125867 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |