diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/quick/se | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/quick/se')
38 files changed, 6508 insertions, 6482 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout index acb604328..800d8e238 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 14:07:24 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:12 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 15802500 because target called exit() +Exiting @ tick 16032500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index 8b0cd4f27..1a9d50ed7 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16039500 # Number of ticks simulated -final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16032500 # Number of ticks simulated +final_tick 16032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1336 # Simulator instruction rate (inst/s) -host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3362323 # Simulator tick rate (ticks/s) -host_mem_usage 225744 # Number of bytes of host memory used -host_seconds 4.77 # Real time elapsed on the host +host_inst_rate 34765 # Simulator instruction rate (inst/s) +host_op_rate 34761 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87452252 # Simulator tick rate (ticks/s) +host_mem_usage 269696 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1245470139 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694589116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1940059255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1245470139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1245470139 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1245470139 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694589116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1940059255 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15803000 # Total gap between requests +system.physmem.totGap 15819000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -149,27 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2921750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests +system.physmem.totQLat 2907500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13642500 # Sum of mem lat for all requests system.physmem.totBusLat 2430000 # Total cycles spent in databus access system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 6011.83 # Average queueing delay per request +system.physmem.avgQLat 5982.51 # Average queueing delay per request system.physmem.avgBankLat 17088.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28100.31 # Average memory access latency -system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28070.99 # Average memory access latency +system.physmem.avgRdBW 1940.06 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1940.06 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.15 # Data bus utilization in percentage +system.physmem.busUtil 15.16 # Data bus utilization in percentage system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32516.46 # Average gap between requests +system.physmem.avgGap 32549.38 # Average gap between requests system.cpu.branchPred.lookups 2896 # Number of BP lookups system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect @@ -212,10 +212,10 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32080 # number of cpu cycles simulated +system.cpu.numCycles 32066 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8354 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 16527 # Number of instructions fetch has processed system.cpu.fetch.Branches 2896 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1162 # Number of branches that fetch has predicted taken @@ -226,49 +226,49 @@ system.cpu.fetch.MiscStallCycles 24 # Nu system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 2349 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 363 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.139086 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.536110 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 14511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.138929 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.535970 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 11558 79.66% 79.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11560 79.66% 79.66% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 317 2.18% 81.85% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 230 1.59% 83.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 219 1.51% 84.94% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 255 1.76% 86.70% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 218 1.50% 88.20% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 264 1.82% 90.02% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 185 1.28% 91.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 185 1.27% 91.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1263 8.70% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 14511 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090314 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515406 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9311 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2753 # Number of cycles decode is running +system.cpu.decode.RunCycles 2752 # Number of cycles decode is running system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1212 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 15363 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 15357 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 231 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 1212 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9517 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 9520 # Number of cycles rename is idle system.cpu.rename.BlockCycles 459 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 372 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2631 # Number of cycles rename is running +system.cpu.rename.RunCycles 2630 # Number of cycles rename is running system.cpu.rename.UnblockCycles 318 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14679 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 14673 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 286 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 11023 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 18314 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 18297 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 11018 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18307 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18290 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6453 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6448 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 24 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 757 # count of insts added to the skid buffer @@ -283,15 +283,15 @@ system.cpu.iq.iqSquashedInstsIssued 50 # Nu system.cpu.iq.iqSquashedInstsExamined 6314 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3579 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 11 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14509 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.744779 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.389331 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14511 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.744676 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.388965 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10032 69.14% 69.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1598 11.01% 80.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.13% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 759 5.23% 93.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 472 3.25% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10031 69.13% 69.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1602 11.04% 80.17% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1157 7.97% 88.14% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.23% 93.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 471 3.25% 96.62% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 281 1.94% 98.55% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 159 1.10% 99.65% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 38 0.26% 99.91% # Number of insts issued each cycle @@ -299,7 +299,7 @@ system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14509 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14511 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 16 13.56% 13.56% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 13.56% # attempts to use FU when none available @@ -369,12 +369,12 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.336845 # Inst issue rate +system.cpu.iq.rate 0.336992 # Inst issue rate system.cpu.iq.fu_busy_cnt 118 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 36270 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 19365 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9700 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 9699 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses @@ -395,7 +395,7 @@ system.cpu.iew.iewSquashCycles 1212 # Nu system.cpu.iew.iewBlockCycles 151 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 6 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 13132 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 147 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2761 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1357 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions @@ -405,33 +405,33 @@ system.cpu.iew.memOrderViolationEvents 17 # Nu system.cpu.iew.predictedTakenIncorrect 126 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 393 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 10154 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 10153 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2132 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 652 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 653 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 86 # number of nop insts executed system.cpu.iew.exec_refs 3233 # number of memory reference insts executed system.cpu.iew.exec_branches 1613 # Number of branches executed system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316521 # Inst execution rate -system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9710 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5134 # num instructions producing a value -system.cpu.iew.wb_consumers 6919 # num instructions consuming a value +system.cpu.iew.exec_rate 0.316628 # Inst execution rate +system.cpu.iew.wb_sent 9856 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9709 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5133 # num instructions producing a value +system.cpu.iew.wb_consumers 6918 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back +system.cpu.iew.wb_rate 0.302782 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.741977 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 431 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13297 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.480484 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.303494 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13299 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.480412 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.303409 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10548 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10550 79.33% 79.33% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1447 10.88% 90.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 514 3.87% 94.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 514 3.86% 94.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 246 1.85% 95.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 153 1.15% 97.07% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 103 0.77% 97.85% # Number of insts commited each cycle @@ -441,7 +441,7 @@ system.cpu.commit.committed_per_cycle::8 148 1.11% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13297 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13299 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -454,32 +454,32 @@ system.cpu.commit.int_insts 6307 # Nu system.cpu.commit.function_calls 127 # Number of function calls committed. system.cpu.commit.bw_lim_events 148 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 25928 # The number of ROB reads +system.cpu.rob.rob_reads 25930 # The number of ROB reads system.cpu.rob.rob_writes 27481 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17555 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12888 # number of integer regfile reads -system.cpu.int_regfile_writes 7343 # number of integer regfile writes +system.cpu.cpi 5.032329 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.032329 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198715 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198715 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12887 # number of integer regfile reads +system.cpu.int_regfile_writes 7342 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use +system.cpu.icache.tagsinuse 159.192462 # Cycle average of tags in use system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 159.192462 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits @@ -492,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22201500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22201500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22201500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22201500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22201500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22201500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses @@ -510,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.125000 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46253.125000 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46253.125000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.125000 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46253.125000 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -536,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16101000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16101000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16101000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16101000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51440.894569 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51440.894569 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51440.894569 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51440.894569 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.327579 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.315874 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -583,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15776000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21856500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15776000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 25544000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15776000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25544000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) @@ -616,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50564.102564 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52921.307506 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52559.670782 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50564.102564 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52559.670782 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11906745 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16755536 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11906745 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19551317 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11906745 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19551317 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses @@ -668,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.644231 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40570.305085 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.644231 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40229.047325 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 107.714584 # Cycle average of tags in use system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 107.714584 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026298 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026298 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits @@ -705,14 +705,14 @@ system.cpu.dcache.demand_misses::cpu.data 528 # n system.cpu.dcache.demand_misses::total 528 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 528 # number of overall misses system.cpu.dcache.overall_misses::total 528 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9127000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9127000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9128000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15893487 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15893487 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25020487 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25020487 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25020487 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25020487 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25021487 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25021487 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25021487 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25021487 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1925 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -729,14 +729,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.189247 system.cpu.dcache.demand_miss_rate::total 0.189247 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.189247 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.189247 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54005.917160 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54005.917160 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54011.834320 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54011.834320 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44271.551532 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 44271.551532 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47387.285985 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47387.285985 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47387.285985 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47389.179924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47389.179924 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47389.179924 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 862 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 23 # number of cycles access was blocked diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout index cb5c70de3..4ea05c228 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:48:19 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 9059000 because target called exit() +Exiting @ tick 9350000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index c84a7ed5c..d97241466 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu sim_ticks 9350000 # Number of ticks simulated final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 55287 # Simulator instruction rate (inst/s) -host_op_rate 55271 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 216439769 # Simulator tick rate (ticks/s) -host_mem_usage 224436 # Number of bytes of host memory used -host_seconds 0.04 # Real time elapsed on the host +host_inst_rate 14656 # Simulator instruction rate (inst/s) +host_op_rate 14654 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57391857 # Simulator tick rate (ticks/s) +host_mem_usage 269408 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 1328750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests +system.physmem.totQLat 1327750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7871500 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4885.11 # Average queueing delay per request +system.physmem.avgQLat 4881.43 # Average queueing delay per request system.physmem.avgBankLat 19057.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28943.01 # Average memory access latency +system.physmem.avgMemAccLat 28939.34 # Average memory access latency system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s @@ -215,7 +215,7 @@ system.cpu.workload.num_syscalls 4 # Nu system.cpu.numCycles 18701 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 4189 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 4191 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 6947 # Number of instructions fetch has processed system.cpu.fetch.Branches 1154 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 450 # Number of branches that fetch has predicted taken @@ -227,26 +227,26 @@ system.cpu.fetch.PendingTrapStallCycles 1024 # Nu system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR system.cpu.fetch.CacheLines 1043 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 182 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7320 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.949044 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.362722 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 7322 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.948784 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.362451 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 6126 83.69% 83.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6128 83.69% 83.69% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 54 0.74% 84.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 114 1.56% 85.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 114 1.56% 85.99% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 92 1.26% 87.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 168 2.30% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 73 1.00% 90.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 168 2.29% 89.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 73 1.00% 90.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 64 0.87% 91.41% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 64 0.87% 92.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 565 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7320 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 7322 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.061708 # Number of branch fetches per cycle system.cpu.fetch.rate 0.371477 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5332 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 5334 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 332 # Number of cycles decode is blocked system.cpu.decode.RunCycles 1148 # Number of cycles decode is running system.cpu.decode.UnblockCycles 8 # Number of cycles decode is unblocking @@ -256,7 +256,7 @@ system.cpu.decode.BranchMispred 81 # Nu system.cpu.decode.DecodedInsts 6173 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 500 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5432 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 5434 # Number of cycles rename is idle system.cpu.rename.BlockCycles 109 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 186 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1056 # Number of cycles rename is running @@ -284,14 +284,14 @@ system.cpu.iq.iqSquashedInstsIssued 53 # Nu system.cpu.iq.iqSquashedInstsExamined 2458 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 1421 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7320 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.555328 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.267026 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7322 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.555176 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.266886 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5695 77.80% 77.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 561 7.66% 85.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5697 77.81% 77.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 561 7.66% 85.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 397 5.42% 90.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 261 3.57% 94.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.56% 94.46% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 207 2.83% 97.28% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 126 1.72% 99.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 50 0.68% 99.69% # Number of insts issued each cycle @@ -300,7 +300,7 @@ system.cpu.iq.issued_per_cycle::8 8 0.11% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7320 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7322 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2 4.35% 4.35% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.35% # attempts to use FU when none available @@ -373,7 +373,7 @@ system.cpu.iq.FU_type_0::total 4065 # Ty system.cpu.iq.rate 0.217368 # Inst issue rate system.cpu.iq.fu_busy_cnt 46 # FU busy when requested system.cpu.iq.fu_busy_rate 0.011316 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15536 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 15538 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 7472 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 3658 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads @@ -417,23 +417,23 @@ system.cpu.iew.exec_stores 377 # Nu system.cpu.iew.exec_rate 0.205978 # Inst execution rate system.cpu.iew.wb_sent 3743 # cumulative count of insts sent to commit system.cpu.iew.wb_count 3664 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1730 # num instructions producing a value -system.cpu.iew.wb_consumers 2229 # num instructions consuming a value +system.cpu.iew.wb_producers 1729 # num instructions producing a value +system.cpu.iew.wb_consumers 2228 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_rate 0.195925 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.776133 # average fanout of values written-back +system.cpu.iew.wb_fanout 0.776032 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 2758 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 180 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6820 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.377713 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.238824 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 6822 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.377602 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.238659 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5956 87.33% 87.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 5958 87.34% 87.34% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 201 2.95% 90.28% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 310 4.55% 94.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 116 1.70% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 310 4.54% 94.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 116 1.70% 96.53% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 63 0.92% 97.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 50 0.73% 98.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 32 0.47% 98.65% # Number of insts commited each cycle @@ -442,7 +442,7 @@ system.cpu.commit.committed_per_cycle::8 69 1.01% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6820 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 6822 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -455,10 +455,10 @@ system.cpu.commit.int_insts 2367 # Nu system.cpu.commit.function_calls 71 # Number of function calls committed. system.cpu.commit.bw_lim_events 69 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11838 # The number of ROB reads +system.cpu.rob.rob_reads 11840 # The number of ROB reads system.cpu.rob.rob_writes 11181 # The number of ROB writes system.cpu.timesIdled 163 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 11381 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 11379 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated @@ -492,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 249 # n system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses system.cpu.icache.overall_misses::total 249 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12422499 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12422499 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12422499 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12422499 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12422499 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12422499 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12418499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12418499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12418499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12418499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12418499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12418499 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1043 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1043 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1043 # number of demand (read+write) accesses @@ -510,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.238734 system.cpu.icache.demand_miss_rate::total 0.238734 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.238734 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.238734 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49889.554217 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49889.554217 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49889.554217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49889.554217 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49889.554217 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49873.489960 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49873.489960 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49873.489960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49873.489960 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49873.489960 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 160 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -536,24 +536,24 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 187 system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9626999 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9626999 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9626999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9626999 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9626999 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9626999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9624999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9624999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9624999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9624999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9624999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9624999 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.179291 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.179291 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.179291 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.179291 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51481.278075 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51481.278075 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51470.582888 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51470.582888 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51470.582888 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51470.582888 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use @@ -577,17 +577,17 @@ system.cpu.l2cache.demand_misses::total 272 # nu system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses system.cpu.l2cache.overall_misses::total 272 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9439000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9437000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3587500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13026500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 13024500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1408000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 1408000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 9439000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 9437000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 4995500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14434500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 9439000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 14432500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 9437000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 4995500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14434500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14432500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) @@ -610,17 +610,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50475.935829 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50465.240642 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58811.475410 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52526.209677 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52518.145161 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58666.666667 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53068.014706 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50475.935829 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53060.661765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50465.240642 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58770.588235 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53068.014706 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53060.661765 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -640,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7116144 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9954927 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7116144 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11068939 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7116144 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11068939 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38054.245989 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40140.834677 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38054.245989 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40694.628676 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 875543733..99487a7ba 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -588,6 +588,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -620,6 +621,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -630,6 +632,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index df6ac8e30..d6f213d3f 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:45 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13354000 because target called exit() +Exiting @ tick 13706000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index ed4523776..8dbb84df8 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13709000 # Number of ticks simulated -final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13706000 # Number of ticks simulated +final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31817 # Simulator instruction rate (inst/s) -host_op_rate 39697 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 94976589 # Simulator tick rate (ticks/s) -host_mem_usage 239960 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 599 # Simulator instruction rate (inst/s) +host_op_rate 748 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1788642 # Simulator tick rate (ticks/s) +host_mem_usage 284080 # Number of bytes of host memory used +host_seconds 7.66 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13651500 # Total gap between requests +system.physmem.totGap 13648500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 6364.85 # Av system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.37 # Data bus utilization in percentage @@ -169,14 +169,14 @@ system.physmem.readRowHits 294 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34648.48 # Average gap between requests -system.cpu.branchPred.lookups 2501 # Number of BP lookups -system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect +system.physmem.avgGap 34640.86 # Average gap between requests +system.cpu.branchPred.lookups 2491 # Number of BP lookups +system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 702 # Number of BTB hits +system.cpu.branchPred.BTBHits 700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.checker.dtb.inst_hits 0 # ITB inst hits @@ -267,176 +267,176 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 27419 # number of cpu cycles simulated +system.cpu.numCycles 27413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2445 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2438 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.RunCycles 2238 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8986 # Type of FU issued -system.cpu.iq.rate 0.327729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8967 # Type of FU issued +system.cpu.iq.rate 0.327108 # Inst issue rate +system.cpu.iq.fu_busy_cnt 230 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed @@ -445,57 +445,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1444 # Number of branches executed +system.cpu.iew.exec_refs 3301 # number of memory reference insts executed +system.cpu.iew.exec_branches 1438 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.312302 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8106 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3904 # num instructions producing a value -system.cpu.iew.wb_consumers 7842 # num instructions consuming a value +system.cpu.iew.exec_rate 0.311713 # Inst execution rate +system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3894 # num instructions producing a value +system.cpu.iew.wb_consumers 7825 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -506,74 +506,74 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23072 # The number of ROB reads -system.cpu.rob.rob_writes 23605 # The number of ROB writes -system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23047 # The number of ROB reads +system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39366 # number of integer regfile reads -system.cpu.int_regfile_writes 8019 # number of integer regfile writes +system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39296 # number of integer regfile reads +system.cpu.int_regfile_writes 8001 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2982 # number of misc regfile reads +system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use -system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use +system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits -system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits +system.cpu.icache.overall_hits::total 1590 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -589,36 +589,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -639,17 +639,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -672,17 +672,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -708,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -730,39 +730,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use -system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits -system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -783,28 +783,28 @@ system.cpu.dcache.demand_miss_latency::cpu.data 23550000 system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency @@ -849,14 +849,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 24bdf3e80..a72da393a 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -511,6 +511,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -543,6 +544,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -553,6 +555,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index e90c24cf4..ed98a8f73 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 19:43:34 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 26 2013 15:15:53 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13354000 because target called exit() +Exiting @ tick 13706000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index ef2f22c88..f41a24ed6 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000014 # Number of seconds simulated -sim_ticks 13709000 # Number of ticks simulated -final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13706000 # Number of ticks simulated +final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36221 # Simulator instruction rate (inst/s) -host_op_rate 45190 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108117571 # Simulator tick rate (ticks/s) -host_mem_usage 238932 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host +host_inst_rate 7143 # Simulator instruction rate (inst/s) +host_op_rate 8913 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 21323596 # Simulator tick rate (ticks/s) +host_mem_usage 284080 # Number of bytes of host memory used +host_seconds 0.64 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1269822744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 569552848 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1839375593 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1269822744 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1269822744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 569552848 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1839375593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13651500 # Total gap between requests +system.physmem.totGap 13648500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 6364.85 # Av system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29826.14 # Average memory access latency -system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.37 # Data bus utilization in percentage @@ -169,14 +169,14 @@ system.physmem.readRowHits 294 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34648.48 # Average gap between requests -system.cpu.branchPred.lookups 2501 # Number of BP lookups -system.cpu.branchPred.condPredicted 1795 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 485 # Number of conditional branches incorrect +system.physmem.avgGap 34640.86 # Average gap between requests +system.cpu.branchPred.lookups 2491 # Number of BP lookups +system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups -system.cpu.branchPred.BTBHits 702 # Number of BTB hits +system.cpu.branchPred.BTBHits 700 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 35.526316 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits @@ -222,176 +222,176 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 27419 # number of cpu cycles simulated +system.cpu.numCycles 27413 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12010 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2501 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 994 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2651 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1627 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2253 # Number of cycles fetch has spent blocked -system.cpu.fetch.CacheLines 1956 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.172963 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.585283 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10346 79.60% 79.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.73% 81.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 203 1.56% 82.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 224 1.72% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 223 1.72% 86.34% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 273 2.10% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 95 0.73% 89.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 149 1.15% 90.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1259 9.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12997 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.091214 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.438017 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6958 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2562 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2445 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2438 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 389 # Number of times decode resolved a branch +system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13349 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7224 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking +system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.RunCycles 2238 # Number of cycles rename is running system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12580 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full +system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12581 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57143 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56783 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6908 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 41 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2802 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11260 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8986 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14437 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12997 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.691390 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.397883 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9412 72.42% 72.42% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1312 10.09% 82.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 811 6.24% 88.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 535 4.12% 92.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 465 3.58% 96.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 270 2.08% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 122 0.94% 99.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 55 0.42% 99.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12997 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 63.16% 65.79% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 78 34.21% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5406 60.16% 60.16% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.27% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2347 26.12% 86.39% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1223 13.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8986 # Type of FU issued -system.cpu.iq.rate 0.327729 # Inst issue rate -system.cpu.iq.fu_busy_cnt 228 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025373 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31277 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16519 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8090 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8967 # Type of FU issued +system.cpu.iq.rate 0.327108 # Inst issue rate +system.cpu.iq.fu_busy_cnt 230 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9194 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1602 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed @@ -400,57 +400,57 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11309 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2802 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 109 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 275 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8563 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2135 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 423 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3302 # number of memory reference insts executed -system.cpu.iew.exec_branches 1444 # Number of branches executed +system.cpu.iew.exec_refs 3301 # number of memory reference insts executed +system.cpu.iew.exec_branches 1438 # Number of branches executed system.cpu.iew.exec_stores 1167 # Number of stores executed -system.cpu.iew.exec_rate 0.312302 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8106 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3904 # num instructions producing a value -system.cpu.iew.wb_consumers 7842 # num instructions consuming a value +system.cpu.iew.exec_rate 0.311713 # Inst execution rate +system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8089 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3894 # num instructions producing a value +system.cpu.iew.wb_consumers 7825 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.295634 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.497832 # average fanout of values written-back +system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5585 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 330 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12034 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.476068 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.308850 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9748 81.00% 81.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1072 8.91% 89.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 397 3.30% 93.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 258 2.14% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 183 1.52% 96.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.42% 98.72% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 35 0.29% 99.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 119 0.99% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12034 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle system.cpu.commit.committedInsts 4591 # Number of instructions committed system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -461,74 +461,74 @@ system.cpu.commit.branches 1007 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4976 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23072 # The number of ROB reads -system.cpu.rob.rob_writes 23605 # The number of ROB writes -system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 14422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23047 # The number of ROB reads +system.cpu.rob.rob_writes 23560 # The number of ROB writes +system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4591 # Number of Instructions Simulated system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4591 # Number of Instructions Simulated -system.cpu.cpi 5.972337 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.972337 # CPI: Total CPI of All Threads -system.cpu.ipc 0.167439 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.167439 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39366 # number of integer regfile reads -system.cpu.int_regfile_writes 8019 # number of integer regfile writes +system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads +system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39296 # number of integer regfile reads +system.cpu.int_regfile_writes 8001 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 2982 # number of misc regfile reads +system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.icache.replacements 3 # number of replacements -system.cpu.icache.tagsinuse 146.913425 # Cycle average of tags in use -system.cpu.icache.total_refs 1596 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use +system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.484536 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 146.913425 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.071735 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.071735 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1596 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1596 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1596 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1596 # number of overall hits -system.cpu.icache.overall_hits::total 1596 # number of overall hits +system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits +system.cpu.icache.overall_hits::total 1590 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses system.cpu.icache.overall_misses::total 360 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17745500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17745500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17745500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17745500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17745500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1956 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1956 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1956 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1956 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.184049 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.184049 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.184049 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.184049 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.184049 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49293.055556 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49293.055556 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49293.055556 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49293.055556 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 62 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed @@ -544,36 +544,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14592500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14592500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14592500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14592500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148773 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148773 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148773 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50146.048110 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits @@ -594,17 +594,17 @@ system.cpu.l2cache.demand_misses::total 399 # nu system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses system.cpu.l2cache.overall_misses::total 399 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19078500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14110500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21481000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14110500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21481000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -627,17 +627,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.910959 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51876.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53291.899441 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 53837.092732 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51876.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 53837.092732 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -663,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -685,39 +685,39 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use -system.cpu.dcache.total_refs 2392 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use +system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.383562 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.502557 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021119 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1764 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1764 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2370 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2370 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2370 # number of overall hits -system.cpu.dcache.overall_hits::total 2370 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits +system.cpu.dcache.overall_hits::total 2369 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses @@ -738,28 +738,28 @@ system.cpu.dcache.demand_miss_latency::cpu.data 23550000 system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1957 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1957 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2870 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2870 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2870 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2870 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098620 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098620 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.174216 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.174216 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.174216 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.174216 # miss rate for overall accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency @@ -804,14 +804,14 @@ system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054165 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054165 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051220 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051220 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051220 # mshr miss rate for overall accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout index 25f28ceed..146a5ec3a 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:16:55 +gem5 compiled Mar 26 2013 14:56:08 +gem5 started Mar 26 2013 14:56:29 gem5 executing on ribera.cs.wisc.edu command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 18578000 because target called exit() +Exiting @ tick 19339000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index d65cf38dc..54d30dc78 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19339000 # Number of ticks simulated final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54855 # Simulator instruction rate (inst/s) -host_op_rate 54842 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 182382541 # Simulator tick rate (ticks/s) -host_mem_usage 224336 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 26477 # Simulator instruction rate (inst/s) +host_op_rate 26474 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 88053451 # Simulator tick rate (ticks/s) +host_mem_usage 270344 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -260,19 +260,19 @@ system.cpu.stage4.runCycles 2902 # Nu system.cpu.stage4.utilization 7.502779 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements system.cpu.icache.tagsinuse 149.398891 # Cycle average of tags in use -system.cpu.icache.total_refs 428 # Total number of references to valid blocks. +system.cpu.icache.total_refs 429 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.341693 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.344828 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.occ_blocks::cpu.inst 149.398891 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.072949 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.072949 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 428 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 428 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 428 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 428 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 428 # number of overall hits -system.cpu.icache.overall_hits::total 428 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 429 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 429 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 429 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 429 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 429 # number of overall hits +system.cpu.icache.overall_hits::total 429 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses @@ -285,18 +285,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 18937500 system.cpu.icache.demand_miss_latency::total 18937500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 18937500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 18937500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 774 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 774 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 774 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.447028 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.447028 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.447028 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.447028 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.447028 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.447028 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 775 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 775 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 775 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.446452 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.446452 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.446452 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.446452 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.446452 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.446452 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54732.658960 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54732.658960 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 54732.658960 # average overall miss latency @@ -329,12 +329,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17329000 system.cpu.icache.demand_mshr_miss_latency::total 17329000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17329000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 17329000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.412145 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.412145 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.412145 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.412145 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.411613 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.411613 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.411613 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.411613 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54322.884013 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54322.884013 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54322.884013 # average overall mshr miss latency diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 9962046c6..97699de37 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -481,6 +481,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -513,6 +514,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -520,25 +522,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 3edf11a35..33a7977e7 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:16:48 -gem5 started Jan 23 2013 15:17:06 +gem5 compiled Mar 26 2013 14:56:08 +gem5 started Mar 26 2013 14:56:29 gem5 executing on ribera.cs.wisc.edu command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 16532500 because target called exit() +Exiting @ tick 17026500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 13fbe689c..c79016c7b 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17026500 # Number of ticks simulated final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44899 # Simulator instruction rate (inst/s) -host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 148205995 # Simulator tick rate (ticks/s) -host_mem_usage 226388 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 19281 # Simulator instruction rate (inst/s) +host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 63663526 # Simulator tick rate (ticks/s) +host_mem_usage 270344 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2863000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests +system.physmem.totQLat 2843000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5989.54 # Average queueing delay per request +system.physmem.avgQLat 5947.70 # Average queueing delay per request system.physmem.avgBankLat 19589.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30578.97 # Average memory access latency +system.physmem.avgMemAccLat 30537.13 # Average memory access latency system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s @@ -170,13 +170,13 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap 35495.82 # Average gap between requests -system.cpu.branchPred.lookups 2222 # Number of BP lookups -system.cpu.branchPred.condPredicted 1502 # Number of conditional branches predicted +system.cpu.branchPred.lookups 2218 # Number of BP lookups +system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1693 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups system.cpu.branchPred.BTBHits 508 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 30.005907 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.dtb.read_hits 0 # DTB read hits @@ -202,47 +202,47 @@ system.cpu.numCycles 34054 # nu system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13389 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2222 # Number of branches that fetch encountered +system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3272 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1401 # Number of cycles fetch has spent squashing +system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2013 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 280 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 14126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.947827 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.258648 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10854 76.84% 76.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1348 9.54% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 105 0.74% 87.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 135 0.96% 88.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 305 2.16% 90.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 118 0.84% 91.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 156 1.10% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 1.13% 93.31% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 945 6.69% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 14126 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065249 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.393170 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8860 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 1239 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3094 # Number of cycles decode is running +system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3093 # Number of cycles decode is running system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 889 # Number of cycles decode is squashing +system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12497 # Number of instructions handled by decode +system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 889 # Number of cycles rename is squashing +system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 804 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2958 # Number of cycles rename is running system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename @@ -258,34 +258,34 @@ system.cpu.rename.UndoneMaps 3839 # Nu system.cpu.rename.serializingInsts 18 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2483 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1201 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9303 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8325 # Number of instructions issued +system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3645 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 2172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 14126 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.589339 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.255776 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10546 74.66% 74.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1398 9.90% 84.55% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 898 6.36% 90.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 564 3.99% 94.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 360 2.55% 97.45% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 226 1.60% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 14126 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available @@ -321,8 +321,8 @@ system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4947 59.42% 59.42% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.48% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued @@ -350,72 +350,72 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2263 27.18% 86.71% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1106 13.29% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8325 # Type of FU issued -system.cpu.iq.rate 0.244465 # Inst issue rate +system.cpu.iq.FU_type_0::total 8318 # Type of FU issued +system.cpu.iq.rate 0.244259 # Inst issue rate system.cpu.iq.fu_busy_cnt 159 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019099 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30977 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12971 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7469 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8482 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1320 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 276 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 889 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10864 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 83 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2483 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1201 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 389 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1547 # number of nop insts executed -system.cpu.iew.exec_refs 3203 # number of memory reference insts executed +system.cpu.iew.exec_nop 1546 # number of nop insts executed +system.cpu.iew.exec_refs 3202 # number of memory reference insts executed system.cpu.iew.exec_branches 1355 # Number of branches executed -system.cpu.iew.exec_stores 1078 # Number of stores executed -system.cpu.iew.exec_rate 0.233042 # Inst execution rate -system.cpu.iew.wb_sent 7560 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7471 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2950 # num instructions producing a value -system.cpu.iew.wb_consumers 4259 # num instructions consuming a value +system.cpu.iew.exec_stores 1077 # Number of stores executed +system.cpu.iew.exec_rate 0.232924 # Inst execution rate +system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7467 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2949 # num instructions producing a value +system.cpu.iew.wb_consumers 4258 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219387 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.692651 # average fanout of values written-back +system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5043 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 13237 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.439148 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.223024 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10853 81.99% 81.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle @@ -427,7 +427,7 @@ system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 13237 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -440,10 +440,10 @@ system.cpu.commit.int_insts 5111 # Nu system.cpu.commit.function_calls 87 # Number of function calls committed. system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23973 # The number of ROB reads -system.cpu.rob.rob_writes 22610 # The number of ROB writes -system.cpu.timesIdled 288 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 19928 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23961 # The number of ROB reads +system.cpu.rob.rob_writes 22589 # The number of ROB writes +system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated @@ -451,56 +451,56 @@ system.cpu.cpi 6.604732 # CP system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10756 # number of integer regfile reads -system.cpu.int_regfile_writes 5239 # number of integer regfile writes +system.cpu.int_regfile_reads 10750 # number of integer regfile reads +system.cpu.int_regfile_writes 5236 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 150 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.249914 # Cycle average of tags in use +system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.249914 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079224 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079224 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits system.cpu.icache.overall_hits::total 1566 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses -system.cpu.icache.overall_misses::total 447 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22381500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22381500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22381500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22381500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22381500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22381500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2013 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2013 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2013 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2013 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2013 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.222057 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.222057 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.222057 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.222057 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.222057 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.222057 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50070.469799 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 50070.469799 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 50070.469799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 50070.469799 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 50070.469799 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses +system.cpu.icache.overall_misses::total 446 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.221670 # 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number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -509,48 +509,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # 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Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 164.584950 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.776656 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005023 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006786 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -568,17 +568,17 @@ system.cpu.l2cache.demand_misses::total 478 # nu system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses system.cpu.l2cache.overall_misses::total 478 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17452500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5919000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23371500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17438500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5913000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23351500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2657000 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8570000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26008500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) @@ -601,17 +601,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993763 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51941.964286 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 65043.956044 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 54734.192037 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51900.297619 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64978.021978 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 54687.353630 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 54452.928870 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51941.964286 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60394.366197 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 54452.928870 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 54411.087866 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 54411.087866 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # 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number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13259027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6830321 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20089348 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13259027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6830321 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20089348 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -653,27 +653,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022374 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022374 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -690,14 +690,14 @@ system.cpu.dcache.demand_misses::cpu.data 501 # n system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses system.cpu.dcache.overall_misses::total 501 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9019500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9019500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24118499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24118499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24118499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24118499 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -714,14 +714,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60942.567568 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60942.567568 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48140.716567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48140.716567 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48140.716567 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -746,14 +746,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 142 system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6013500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8722499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8722499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8722499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8722499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -762,14 +762,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66082.417582 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66082.417582 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61426.049296 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 61426.049296 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 073ffb5b4..1aa882d35 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -480,6 +480,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -512,6 +513,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -519,25 +521,28 @@ slave=system.system_port system.cpu.l2cache.mem_side [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 09e115be1..b6781a5c9 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:33:02 -gem5 started Jan 23 2013 15:33:08 +gem5 compiled Mar 26 2013 14:59:37 +gem5 started Mar 26 2013 14:59:57 gem5 executing on ribera.cs.wisc.edu command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 14065500 because target called exit() +Exiting @ tick 14724500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 69396a815..30ea78059 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14724500 # Number of ticks simulated final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62176 # Simulator instruction rate (inst/s) -host_op_rate 62167 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 158021685 # Simulator tick rate (ticks/s) -host_mem_usage 222660 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 11850 # Simulator instruction rate (inst/s) +host_op_rate 11850 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30123505 # Simulator tick rate (ticks/s) +host_mem_usage 266600 # Number of bytes of host memory used +host_seconds 0.49 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -85,8 +85,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -201,7 +201,7 @@ system.cpu.workload.num_syscalls 9 # Nu system.cpu.numCycles 29450 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7445 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7448 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13075 # Number of instructions fetch has processed system.cpu.fetch.Branches 2226 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 797 # Number of branches that fetch has predicted taken @@ -210,26 +210,26 @@ system.cpu.fetch.SquashCycles 1279 # Nu system.cpu.fetch.BlockedCycles 1007 # Number of cycles fetch has spent blocked system.cpu.fetch.CacheLines 1802 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 309 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11548 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.132231 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.547600 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 11551 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.131937 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.547334 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9302 80.55% 80.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9305 80.56% 80.56% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 175 1.52% 82.07% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 174 1.51% 83.57% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 174 1.51% 83.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 140 1.21% 84.79% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 227 1.97% 86.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 132 1.14% 87.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 132 1.14% 87.90% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 256 2.22% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 108 0.94% 91.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 108 0.93% 91.05% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1034 8.95% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11548 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 11551 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.075586 # Number of branch fetches per cycle system.cpu.fetch.rate 0.443973 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7511 # Number of cycles decode is idle +system.cpu.decode.IdleCycles 7514 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1178 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2083 # Number of cycles decode is running system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking @@ -239,7 +239,7 @@ system.cpu.decode.BranchMispred 154 # Nu system.cpu.decode.DecodedInsts 11641 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 431 # Number of squashed instructions handled by decode system.cpu.rename.SquashCycles 697 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7696 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 7699 # Number of cycles rename is idle system.cpu.rename.BlockCycles 476 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 449 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 1969 # Number of cycles rename is running @@ -267,23 +267,23 @@ system.cpu.iq.iqSquashedInstsIssued 171 # Nu system.cpu.iq.iqSquashedInstsExamined 4167 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 3342 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11548 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.771302 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.502142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11551 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.771102 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.501710 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8209 71.09% 71.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1071 9.27% 80.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.85% 87.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 496 4.30% 91.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 4.04% 95.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 302 2.62% 98.16% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8211 71.08% 71.08% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1072 9.28% 80.37% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 790 6.84% 87.20% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 498 4.31% 91.52% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 466 4.03% 95.55% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 301 2.61% 98.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 134 1.16% 99.32% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 44 0.38% 99.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 35 0.30% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11548 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11551 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 8 4.68% 4.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.68% # attempts to use FU when none available @@ -356,9 +356,9 @@ system.cpu.iq.FU_type_0::total 8907 # Ty system.cpu.iq.rate 0.302445 # Inst issue rate system.cpu.iq.fu_busy_cnt 171 # FU busy when requested system.cpu.iq.fu_busy_rate 0.019198 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 29642 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 29645 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 14405 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8122 # Number of integer instruction queue wakeup accesses +system.cpu.iq.int_inst_queue_wakeup_accesses 8123 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses @@ -389,32 +389,32 @@ system.cpu.iew.memOrderViolationEvents 6 # Nu system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 263 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 329 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8492 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 8493 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1673 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 415 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_refs 3204 # number of memory reference insts executed system.cpu.iew.exec_branches 1349 # Number of branches executed system.cpu.iew.exec_stores 1531 # Number of stores executed -system.cpu.iew.exec_rate 0.288353 # Inst execution rate -system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8149 # cumulative count of insts written-back +system.cpu.iew.exec_rate 0.288387 # Inst execution rate +system.cpu.iew.wb_sent 8266 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8150 # cumulative count of insts written-back system.cpu.iew.wb_producers 4198 # num instructions producing a value system.cpu.iew.wb_consumers 6619 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.276706 # insts written-back per cycle +system.cpu.iew.wb_rate 0.276740 # insts written-back per cycle system.cpu.iew.wb_fanout 0.634235 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 4482 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 266 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10851 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.533776 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.333108 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10854 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.533628 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.332953 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8471 78.07% 78.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 999 9.21% 87.27% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8474 78.07% 78.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 999 9.20% 87.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 620 5.71% 92.99% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 267 2.46% 95.45% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 174 1.60% 97.05% # Number of insts commited each cycle @@ -425,7 +425,7 @@ system.cpu.commit.committed_per_cycle::8 101 0.93% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10851 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10854 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -438,10 +438,10 @@ system.cpu.commit.int_insts 5698 # Nu system.cpu.commit.function_calls 103 # Number of function calls committed. system.cpu.commit.bw_lim_events 101 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21024 # The number of ROB reads +system.cpu.rob.rob_reads 21027 # The number of ROB reads system.cpu.rob.rob_writes 21246 # The number of ROB writes system.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17902 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17899 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated @@ -449,8 +449,8 @@ system.cpu.cpi 5.084599 # CP system.cpu.cpi_total 5.084599 # CPI: Total CPI of All Threads system.cpu.ipc 0.196672 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.196672 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13466 # number of integer regfile reads -system.cpu.int_regfile_writes 7036 # number of integer regfile writes +system.cpu.int_regfile_reads 13468 # number of integer regfile reads +system.cpu.int_regfile_writes 7037 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements @@ -474,12 +474,12 @@ system.cpu.icache.demand_misses::cpu.inst 441 # n system.cpu.icache.demand_misses::total 441 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 441 # number of overall misses system.cpu.icache.overall_misses::total 441 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21881500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21881500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21881500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21881500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21881500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21881500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21880000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21880000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21880000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21880000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21880000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21880000 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 1802 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 1802 # number of demand (read+write) accesses @@ -492,12 +492,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.244728 system.cpu.icache.demand_miss_rate::total 0.244728 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.244728 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.244728 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49617.913832 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49617.913832 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49617.913832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49617.913832 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49617.913832 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49614.512472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49614.512472 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49614.512472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49614.512472 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49614.512472 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 210 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -538,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145720 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359554 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy @@ -569,16 +569,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 345 # system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17370000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3170500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 20540500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3171000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20541000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2908000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2908000 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 17370000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6078500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23448500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6079000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23449000 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 17370000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6078500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23448500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6079000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23449000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -602,16 +602,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50347.826087 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58712.962963 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51479.949875 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58722.222222 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51481.203008 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 61872.340426 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 61872.340426 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52576.233184 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50347.826087 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60183.168317 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52575.112108 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60188.118812 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52576.233184 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -666,12 +666,12 @@ system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 63.324326 # Cycle average of tags in use system.cpu.dcache.total_refs 2181 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 21.382353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.324462 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 63.324326 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.015460 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.015460 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1472 # number of ReadReq hits @@ -690,14 +690,14 @@ system.cpu.dcache.demand_misses::cpu.data 438 # n system.cpu.dcache.demand_misses::total 438 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 438 # number of overall misses system.cpu.dcache.overall_misses::total 438 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5160500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5160500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5163000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5163000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 14813997 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 14813997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19974497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19974497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19974497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19974497 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19976997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19976997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19976997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19976997 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1573 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -714,14 +714,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.167239 system.cpu.dcache.demand_miss_rate::total 0.167239 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.167239 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.167239 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51094.059406 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 51094.059406 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51118.811881 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51118.811881 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43958.448071 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 43958.448071 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 45603.874429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 45603.874429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 45603.874429 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45609.582192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45609.582192 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45609.582192 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 419 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -746,14 +746,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3236500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3236500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2957499 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2957499 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6193499 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193499 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6193499 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6193999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 6193999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6193999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 6193999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034965 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -762,14 +762,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038946 system.cpu.dcache.demand_mshr_miss_rate::total 0.038946 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038946 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038946 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58836.363636 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58836.363636 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58845.454545 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58845.454545 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62925.510638 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62925.510638 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60720.578431 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60720.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60725.480392 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60725.480392 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini index 254e6c7c6..08313d557 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini @@ -179,6 +179,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -211,6 +212,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -221,6 +223,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout index 7978eda39..06a0491cb 100755 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorde gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:01:02 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 16286500 because target called exit() +Hello World!Exiting @ tick 16783500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index d53327dbb..91942b523 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48421 # Simulator instruction rate (inst/s) -host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 152524495 # Simulator tick rate (ticks/s) -host_mem_usage 230316 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 18770 # Simulator instruction rate (inst/s) +host_op_rate 18768 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 59128079 # Simulator tick rate (ticks/s) +host_mem_usage 276316 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -149,14 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 2672750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests +system.physmem.totQLat 2671750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12995500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6318.56 # Average queueing delay per request +system.physmem.avgQLat 6316.19 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30724.59 # Average memory access latency +system.physmem.avgMemAccLat 30722.22 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -202,7 +202,7 @@ system.cpu.execution_unit.executions 3957 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9657 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.timesIdled 481 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 27323 # Number of cycles cpu's stages were not processed @@ -225,12 +225,12 @@ system.cpu.cpi_total 6.301483 # CP system.cpu.ipc 0.158693 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC system.cpu.ipc_total 0.158693 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 28929 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4639 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 13.819709 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 30371 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3197 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.523951 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage0.idleCycles 28928 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.822688 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 30373 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.517993 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage2.idleCycles 30535 # Number of cycles 0 instructions are processed. system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. system.cpu.stage2.utilization 9.035391 # Percentage of cycles stage was utilized (processing insts). @@ -241,50 +241,50 @@ system.cpu.stage4.idleCycles 30411 # Nu system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. system.cpu.stage4.utilization 9.404790 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 141.185042 # Cycle average of tags in use -system.cpu.icache.total_refs 895 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 141.184744 # Cycle average of tags in use +system.cpu.icache.total_refs 896 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 3.075601 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 3.079038 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 141.185042 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 141.184744 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.068938 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.068938 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 895 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 895 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 895 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 895 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 895 # number of overall hits -system.cpu.icache.overall_hits::total 895 # number of overall hits +system.cpu.icache.ReadReq_hits::cpu.inst 896 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 896 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 896 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 896 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 896 # number of overall hits +system.cpu.icache.overall_hits::total 896 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses system.cpu.icache.overall_misses::total 362 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18996500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18996500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18996500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18996500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18996500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1257 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1257 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1257 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1257 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1257 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.287987 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.287987 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.287987 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.287987 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.287987 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52476.519337 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52476.519337 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52476.519337 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52476.519337 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18997500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18997500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18997500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18997500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18997500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.287758 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.287758 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.287758 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.287758 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.287758 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52479.281768 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52479.281768 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52479.281768 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52479.281768 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -305,32 +305,32 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 291 system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15423000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15423000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15423000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15423000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231504 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231504 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231504 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15424000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15424000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15424000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15424000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53003.436426 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53003.436426 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53003.436426 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.396977 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.660763 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy @@ -355,16 +355,16 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15104500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3320000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15105500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3319000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 18424500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4710000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 4710000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15104500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8030000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8029000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 23134500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15104500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8030000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15105500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8029000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 23134500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) @@ -388,16 +388,16 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52264.705882 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62641.509434 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52268.166090 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 62622.641509 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 53872.807018 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58148.148148 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58148.148148 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 54691.489362 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52264.705882 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59925.373134 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52268.166090 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59917.910448 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 54691.489362 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -419,16 +419,16 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2664291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14191519 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6384078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17911306 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6384078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17911306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -441,16 +441,16 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50269.641509 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41495.669591 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47642.373134 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42343.513002 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use @@ -477,14 +477,14 @@ system.cpu.dcache.demand_misses::cpu.data 474 # n system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3818500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3818500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3817500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3817500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 21812000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 21812000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 25630500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 25630500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 25630500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 25629500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 25629500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 25629500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -501,14 +501,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62598.360656 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62598.360656 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62581.967213 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 62581.967213 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52813.559322 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 52813.559322 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 54072.784810 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 54072.784810 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 54070.675105 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 54070.675105 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 557 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked @@ -533,14 +533,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3385500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3385500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4793500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 4793500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8180000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8180000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8180000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8179000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8179000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8179000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -549,14 +549,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62712.962963 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62712.962963 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62694.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62694.444444 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59179.012346 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59179.012346 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60592.592593 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 60592.592593 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60585.185185 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 60585.185185 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 745f3a55b..6136a5e78 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 11 2013 13:21:48 -gem5 started Mar 11 2013 13:21:58 +gem5 compiled Mar 26 2013 15:13:59 +gem5 started Mar 26 2013 15:14:41 gem5 executing on ribera.cs.wisc.edu command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 15471000 because target called exit() +Exiting @ tick 15474000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 50eb0a35f..63a2cacd2 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000015 # Number of seconds simulated -sim_ticks 15471000 # Number of ticks simulated -final_tick 15471000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 15474000 # Number of ticks simulated +final_tick 15474000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 25126 # Simulator instruction rate (inst/s) -host_op_rate 45518 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72243012 # Simulator tick rate (ticks/s) -host_mem_usage 287412 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 16433 # Simulator instruction rate (inst/s) +host_op_rate 29770 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47259450 # Simulator tick rate (ticks/s) +host_mem_usage 286708 # Number of bytes of host memory used +host_seconds 0.33 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9747 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19392 # Nu system.physmem.num_reads::cpu.inst 303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory system.physmem.num_reads::total 449 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1253441924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 603968716 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1857410639 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1253441924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1253441924 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1253441924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 603968716 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1857410639 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1253198914 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 603851622 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1857050536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1253198914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1253198914 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1253198914 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 603851622 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1857050536 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15455000 # Total gap between requests +system.physmem.totGap 15458000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -157,9 +157,9 @@ system.physmem.avgQLat 4211.75 # Av system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request system.physmem.avgMemAccLat 29181.26 # Average memory access latency -system.physmem.avgRdBW 1857.41 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1857.05 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1857.41 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1857.05 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 14.51 # Data bus utilization in percentage @@ -169,104 +169,104 @@ system.physmem.readRowHits 333 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 73.84 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34268.29 # Average gap between requests -system.cpu.branchPred.lookups 2992 # Number of BP lookups -system.cpu.branchPred.condPredicted 2992 # Number of conditional branches predicted +system.physmem.avgGap 34274.94 # Average gap between requests +system.cpu.branchPred.lookups 2993 # Number of BP lookups +system.cpu.branchPred.condPredicted 2993 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 546 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2482 # Number of BTB lookups +system.cpu.branchPred.BTBLookups 2483 # Number of BTB lookups system.cpu.branchPred.BTBHits 793 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 31.950040 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 31.937173 # BTB Hit Percentage system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 30943 # number of cpu cycles simulated +system.cpu.numCycles 30949 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 8896 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2992 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 8903 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14396 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2993 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 793 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3908 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2410 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 3707 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 3910 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2411 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3703 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 178 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1872 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 18558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.369490 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.871739 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 1874 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 286 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 18564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.369856 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.872055 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 14749 79.48% 79.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 190 1.02% 80.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 14753 79.47% 79.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 190 1.02% 80.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 153 0.82% 81.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 193 1.04% 82.36% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 163 0.88% 83.24% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 168 0.91% 84.15% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 264 1.42% 85.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 160 0.86% 86.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2518 13.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 168 0.90% 84.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 264 1.42% 85.56% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 161 0.87% 86.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2519 13.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 18558 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.096694 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.464952 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9433 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 18564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.096707 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.465152 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9437 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 3646 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3518 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 144 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1817 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 24275 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1817 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9777 # Number of cycles rename is idle +system.cpu.decode.RunCycles 3520 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 143 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1818 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 24283 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1818 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9780 # Number of cycles rename is idle system.cpu.rename.BlockCycles 2398 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 497 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3304 # Number of cycles rename is running +system.cpu.rename.RunCycles 3306 # Number of cycles rename is running system.cpu.rename.UnblockCycles 765 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 22769 # Number of instructions processed by rename +system.cpu.rename.RenamedInsts 22784 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 39 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 649 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24875 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 54688 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 54672 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 651 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24893 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 54727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 54711 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11063 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 13812 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 13830 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 34 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 34 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2061 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2066 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2202 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1748 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 11 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 20301 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 20310 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 36 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 17266 # Number of instructions issued +system.cpu.iq.iqInstsIssued 17272 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 205 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 9813 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 13640 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedInstsExamined 9822 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 13657 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 18558 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.930380 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.788216 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 18564 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.930403 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.788380 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 13171 70.97% 70.97% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1403 7.56% 78.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1055 5.68% 84.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 693 3.73% 87.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 728 3.92% 91.87% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 621 3.35% 95.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13176 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1404 7.56% 78.54% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1053 5.67% 84.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 694 3.74% 87.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 727 3.92% 91.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 623 3.36% 95.22% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 594 3.20% 98.42% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 251 1.35% 99.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 42 0.23% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 18558 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 18564 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 132 76.30% 76.30% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 76.30% # attempts to use FU when none available @@ -302,7 +302,7 @@ system.cpu.iq.fu_full::MemWrite 21 12.14% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 3 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 13880 80.39% 80.41% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 13885 80.39% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.41% # Type of FU issued @@ -331,21 +331,21 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.41% # Ty system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.41% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.41% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1903 11.02% 91.43% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1904 11.02% 91.43% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1480 8.57% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 17266 # Type of FU issued -system.cpu.iq.rate 0.557994 # Inst issue rate +system.cpu.iq.FU_type_0::total 17272 # Type of FU issued +system.cpu.iq.rate 0.558079 # Inst issue rate system.cpu.iq.fu_busy_cnt 173 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010020 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 53460 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 30157 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 15915 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.010016 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 53478 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 30175 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 15918 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 17432 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 17438 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 159 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -358,10 +358,10 @@ system.cpu.iew.lsq.thread0.blockedLoads 0 # Nu system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 13 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1817 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1818 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 1705 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 33 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 20337 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 20346 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 33 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2202 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1748 # Number of dispatched store instructions @@ -372,43 +372,43 @@ system.cpu.iew.memOrderViolationEvents 12 # Nu system.cpu.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 606 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 662 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 16344 # Number of executed instructions +system.cpu.iew.iewExecutedInsts 16347 # Number of executed instructions system.cpu.iew.iewExecLoadInsts 1780 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 922 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecSquashedInsts 925 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3142 # number of memory reference insts executed +system.cpu.iew.exec_refs 3143 # number of memory reference insts executed system.cpu.iew.exec_branches 1619 # Number of branches executed -system.cpu.iew.exec_stores 1362 # Number of stores executed -system.cpu.iew.exec_rate 0.528197 # Inst execution rate -system.cpu.iew.wb_sent 16113 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 15919 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10115 # num instructions producing a value -system.cpu.iew.wb_consumers 15622 # num instructions consuming a value +system.cpu.iew.exec_stores 1363 # Number of stores executed +system.cpu.iew.exec_rate 0.528192 # Inst execution rate +system.cpu.iew.wb_sent 16117 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 15922 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10116 # num instructions producing a value +system.cpu.iew.wb_consumers 15624 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.514462 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.647484 # average fanout of values written-back +system.cpu.iew.wb_rate 0.514459 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.647465 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 10589 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 10598 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 12 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 572 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 16741 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.582223 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.458057 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 16746 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.582049 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.457997 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 13206 78.88% 78.88% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13211 78.89% 78.89% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1328 7.93% 86.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 594 3.55% 90.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 704 4.21% 94.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 595 3.55% 90.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 703 4.20% 94.57% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 355 2.12% 96.69% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 141 0.84% 97.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 118 0.70% 98.24% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 140 0.84% 97.53% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 119 0.71% 98.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 74 0.44% 98.68% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 221 1.32% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 16741 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 16746 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9747 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -421,67 +421,67 @@ system.cpu.commit.int_insts 9654 # Nu system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.bw_lim_events 221 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36856 # The number of ROB reads -system.cpu.rob.rob_writes 42518 # The number of ROB writes +system.cpu.rob.rob_reads 36870 # The number of ROB reads +system.cpu.rob.rob_writes 42537 # The number of ROB writes system.cpu.timesIdled 155 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.idleCycles 12385 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9747 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 5.751487 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.751487 # CPI: Total CPI of All Threads -system.cpu.ipc 0.173868 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.173868 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 28772 # number of integer regfile reads -system.cpu.int_regfile_writes 17143 # number of integer regfile writes +system.cpu.cpi 5.752602 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.752602 # CPI: Total CPI of All Threads +system.cpu.ipc 0.173834 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.173834 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 28776 # number of integer regfile reads +system.cpu.int_regfile_writes 17146 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7129 # number of misc regfile reads +system.cpu.misc_regfile_reads 7131 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.801510 # Cycle average of tags in use -system.cpu.icache.total_refs 1474 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 144.810143 # Cycle average of tags in use +system.cpu.icache.total_refs 1475 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.848684 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.851974 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.801510 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.070704 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.070704 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1474 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1474 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1474 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1474 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1474 # number of overall hits -system.cpu.icache.overall_hits::total 1474 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses -system.cpu.icache.overall_misses::total 398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20575500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20575500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20575500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20575500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20575500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20575500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1872 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1872 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1872 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1872 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1872 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212607 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.212607 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.212607 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.212607 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.212607 # 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number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1475 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1475 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1475 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1475 # number of overall hits +system.cpu.icache.overall_hits::total 1475 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20615000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20615000 # 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miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212914 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212914 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212914 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212914 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212914 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51666.666667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 51666.666667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 51666.666667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 51666.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 51666.666667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 51666.666667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 312 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -490,45 +490,45 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44.571429 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16157000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16157000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16157000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162393 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.162393 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162393 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.162393 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53148.026316 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53148.026316 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16157500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16157500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16157500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16157500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16157500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16157500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162220 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.162220 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.162220 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53149.671053 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53149.671053 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53149.671053 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 53149.671053 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.956413 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.966730 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.938671 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.017743 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.947246 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.019484 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004423 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005431 # Average percentage of cache occupancy @@ -549,17 +549,17 @@ system.cpu.l2cache.demand_misses::total 451 # nu system.cpu.l2cache.overall_misses::cpu.inst 303 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 148 # number of overall misses system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15842500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3892500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19734500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19735000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3990500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3990500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15842000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15842500 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23725000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15842000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 23725500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15842500 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23725000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23725500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 72 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) @@ -582,17 +582,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997788 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52283.828383 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52285.478548 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54062.500000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52625.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52626.666667 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52506.578947 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52506.578947 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52605.321508 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52283.828383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52606.430155 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52285.478548 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.513514 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52605.321508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52606.430155 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,14 +615,14 @@ system.cpu.l2cache.overall_mshr_misses::total 451 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3057807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3057807 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6087848 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18179829 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6087848 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18179829 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -637,24 +637,24 @@ system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40234.302632 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40234.302632 # average ReadExReq mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41134.108108 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.042129 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.486269 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 83.491215 # Cycle average of tags in use system.cpu.dcache.total_refs 2285 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 15.650685 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.486269 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020382 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020382 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 83.491215 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020384 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020384 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1426 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1426 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout index d90ba5e01..6461709eb 100755 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:39:20 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:13 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -13,4 +13,4 @@ info: Increasing stack size by one page. info: Increasing stack size by one page. Hello world! Hello world! -Exiting @ tick 19857000 because target called exit() +Exiting @ tick 24422500 because target called exit() diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 8505308fc..a6935acc4 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24473000 # Number of ticks simulated -final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 24422500 # Number of ticks simulated +final_tick 24422500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87264 # Simulator instruction rate (inst/s) -host_op_rate 87257 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 167537445 # Simulator tick rate (ticks/s) -host_mem_usage 226344 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host +host_inst_rate 26625 # Simulator instruction rate (inst/s) +host_op_rate 26623 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51014333 # Simulator tick rate (ticks/s) +host_mem_usage 270288 # Number of bytes of host memory used +host_seconds 0.48 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 39808 # Nu system.physmem.num_reads::cpu.inst 622 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 348 # Number of read requests responded to by this memory system.physmem.num_reads::total 970 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1626608916 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 910064152 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2536673068 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1626608916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1626608916 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1626608916 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 910064152 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2536673068 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1629972362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 911945951 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2541918313 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1629972362 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1629972362 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1629972362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 911945951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2541918313 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 970 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 970 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24326500 # Total gap between requests +system.physmem.totGap 24269500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -85,12 +85,12 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 167 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 173 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 87 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -149,56 +149,56 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 22645500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests +system.physmem.totQLat 22107000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 52930750 # Sum of mem lat for all requests system.physmem.totBusLat 4850000 # Total cycles spent in databus access system.physmem.totBankLat 25973750 # Total cycles spent in bank access -system.physmem.avgQLat 23345.88 # Average queueing delay per request +system.physmem.avgQLat 22790.72 # Average queueing delay per request system.physmem.avgBankLat 26777.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55122.94 # Average memory access latency -system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 54567.78 # Average memory access latency +system.physmem.avgRdBW 2541.92 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2541.92 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 19.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 2.18 # Average read queue length over time +system.physmem.busUtil 19.86 # Data bus utilization in percentage +system.physmem.avgRdQLen 2.17 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 450 # Number of row buffer hits during reads +system.physmem.readRowHits 449 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 46.39 # Row buffer hit rate for reads +system.physmem.readRowHitRate 46.29 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25078.87 # Average gap between requests -system.cpu.branchPred.lookups 6101 # Number of BP lookups -system.cpu.branchPred.condPredicted 3457 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1231 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4432 # Number of BTB lookups -system.cpu.branchPred.BTBHits 1023 # Number of BTB hits +system.physmem.avgGap 25020.10 # Average gap between requests +system.cpu.branchPred.lookups 6091 # Number of BP lookups +system.cpu.branchPred.condPredicted 3456 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1235 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 4406 # Number of BTB lookups +system.cpu.branchPred.BTBHits 1013 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 23.082130 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 800 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 163 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 22.991375 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 798 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 166 # Number of incorrect RAS predictions. system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4461 # DTB read hits -system.cpu.dtb.read_misses 100 # DTB read misses +system.cpu.dtb.read_hits 4448 # DTB read hits +system.cpu.dtb.read_misses 96 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4561 # DTB read accesses -system.cpu.dtb.write_hits 2022 # DTB write hits -system.cpu.dtb.write_misses 83 # DTB write misses +system.cpu.dtb.read_accesses 4544 # DTB read accesses +system.cpu.dtb.write_hits 2020 # DTB write hits +system.cpu.dtb.write_misses 84 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2105 # DTB write accesses -system.cpu.dtb.data_hits 6483 # DTB hits -system.cpu.dtb.data_misses 183 # DTB misses +system.cpu.dtb.write_accesses 2104 # DTB write accesses +system.cpu.dtb.data_hits 6468 # DTB hits +system.cpu.dtb.data_misses 180 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6666 # DTB accesses -system.cpu.itb.fetch_hits 4836 # ITB hits +system.cpu.dtb.data_accesses 6648 # DTB accesses +system.cpu.itb.fetch_hits 4827 # ITB hits system.cpu.itb.fetch_misses 49 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 4885 # ITB accesses +system.cpu.itb.fetch_accesses 4876 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -213,291 +213,291 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 48947 # number of cpu cycles simulated +system.cpu.numCycles 48846 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 1376 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 33899 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6101 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1823 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5733 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1590 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 519 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 4836 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 811 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 28070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.207659 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.639587 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 1375 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 33885 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6091 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1811 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 5723 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1593 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 523 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 4827 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 809 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 28036 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.208625 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.641797 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22337 79.58% 79.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 523 1.86% 81.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 359 1.28% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 389 1.39% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 440 1.57% 85.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 399 1.42% 87.09% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 440 1.57% 88.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 368 1.31% 89.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2815 10.03% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 22313 79.59% 79.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 519 1.85% 81.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 362 1.29% 82.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 384 1.37% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 439 1.57% 85.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 391 1.39% 87.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 437 1.56% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 371 1.32% 89.94% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2820 10.06% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 28070 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.124645 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.692565 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 38855 # Number of cycles decode is idle +system.cpu.fetch.rateDist::total 28036 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.124698 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.693711 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38743 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 9028 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 4956 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 477 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2426 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 492 # Number of times decode resolved a branch +system.cpu.decode.RunCycles 4948 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 475 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2422 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 482 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 289 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30419 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 546 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2426 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 39473 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 6021 # Number of cycles rename is blocking +system.cpu.decode.DecodedInsts 30410 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 547 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2422 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 39365 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 6014 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 969 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4731 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 2122 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28264 # Number of instructions processed by rename +system.cpu.rename.RunCycles 4720 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2126 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 28231 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 2059 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21243 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 34749 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 34715 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 2058 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 21224 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 34730 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 34696 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12103 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 12084 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 49 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5573 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2924 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1330 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 5609 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2913 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1333 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2736 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1292 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.insertedLoads 2720 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1281 # Number of stores inserted to the mem dependence unit. system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25104 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 25056 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 73 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 20875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 70 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11589 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7157 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 20851 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 67 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 11467 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7098 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 39 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 28070 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.743677 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.323333 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 28036 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.743722 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.323178 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 18893 67.31% 67.31% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3427 12.21% 79.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2538 9.04% 88.56% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1546 5.51% 94.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 945 3.37% 97.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 459 1.64% 99.07% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 189 0.67% 99.74% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 18861 67.27% 67.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3429 12.23% 79.50% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2549 9.09% 88.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1540 5.49% 94.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 935 3.33% 97.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 455 1.62% 99.05% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 194 0.69% 99.74% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 59 0.21% 99.95% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 28070 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 28036 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 6 3.64% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.64% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 98 59.39% 63.03% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 36.97% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 5 2.99% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.99% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 103 61.68% 64.67% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 59 35.33% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 6970 65.71% 65.73% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.74% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.74% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.76% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2525 23.81% 89.56% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1107 10.44% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 6975 65.76% 65.78% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.79% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.79% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.81% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2523 23.79% 89.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1103 10.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10607 # Type of FU issued +system.cpu.iq.FU_type_0::total 10606 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 6762 65.86% 65.87% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.88% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.88% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.90% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2394 23.32% 89.22% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1107 10.78% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 6760 65.98% 66.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.01% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.01% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.03% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2371 23.14% 89.18% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1109 10.82% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10268 # Type of FU issued +system.cpu.iq.FU_type_1::total 10245 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 13732 65.78% 65.80% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 65.81% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 65.81% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.83% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.83% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4919 23.56% 89.39% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2214 10.61% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 13735 65.87% 65.89% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 65.90% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 65.90% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 65.92% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 65.92% # Type of FU issued +system.cpu.iq.FU_type::MemRead 4894 23.47% 89.39% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2212 10.61% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 20875 # Type of FU issued -system.cpu.iq.rate 0.426482 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 83 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 82 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 165 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.003976 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.003928 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.007904 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 70014 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 36770 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 18228 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 20851 # Type of FU issued +system.cpu.iq.rate 0.426872 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 86 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 81 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 167 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004125 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.003885 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008009 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 69931 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 36600 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 18226 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 41 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21015 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 20993 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 21 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 73 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1741 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1730 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 465 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 468 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 427 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 57 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.cacheBlocked 422 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 60 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1553 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedLoads 1537 # Number of loads squashed system.cpu.iew.lsq.thread1.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread1.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 427 # Number of stores squashed +system.cpu.iew.lsq.thread1.squashedStores 416 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 302 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 292 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2426 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2850 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 2422 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 2853 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 54 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25356 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 534 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5660 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2622 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 25308 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 582 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5633 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2614 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 73 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 24 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 26 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 218 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedTakenIncorrect 221 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 905 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1123 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 19630 # Number of executed instructions +system.cpu.iew.branchMispredicts 1126 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 19605 # Number of executed instructions system.cpu.iew.iewExecLoadInsts::0 2348 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2224 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4572 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1245 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecLoadInsts::1 2207 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4555 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1246 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed @@ -505,59 +505,59 @@ system.cpu.iew.exec_nop::0 98 # nu system.cpu.iew.exec_nop::1 81 # number of nop insts executed system.cpu.iew.exec_nop::total 179 # number of nop insts executed system.cpu.iew.exec_refs::0 3414 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3275 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6689 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1527 # Number of branches executed +system.cpu.iew.exec_refs::1 3257 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6671 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1525 # Number of branches executed system.cpu.iew.exec_branches::1 1521 # Number of branches executed -system.cpu.iew.exec_branches::total 3048 # Number of branches executed +system.cpu.iew.exec_branches::total 3046 # Number of branches executed system.cpu.iew.exec_stores::0 1066 # Number of stores executed -system.cpu.iew.exec_stores::1 1051 # Number of stores executed -system.cpu.iew.exec_stores::total 2117 # Number of stores executed -system.cpu.iew.exec_rate 0.401046 # Inst execution rate -system.cpu.iew.wb_sent::0 9349 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9181 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 18530 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9210 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9038 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 18248 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 4725 # num instructions producing a value -system.cpu.iew.wb_producers::1 4632 # num instructions producing a value -system.cpu.iew.wb_producers::total 9357 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6193 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6064 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 12257 # num instructions consuming a value +system.cpu.iew.exec_stores::1 1050 # Number of stores executed +system.cpu.iew.exec_stores::total 2116 # Number of stores executed +system.cpu.iew.exec_rate 0.401363 # Inst execution rate +system.cpu.iew.wb_sent::0 9356 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9171 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 18527 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9033 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 18246 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 4732 # num instructions producing a value +system.cpu.iew.wb_producers::1 4628 # num instructions producing a value +system.cpu.iew.wb_producers::total 9360 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6204 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6054 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12258 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.188163 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.184649 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.372811 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.762958 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.763852 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.763401 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.188613 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.184928 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.373541 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.762734 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.764453 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.763583 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12589 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 12541 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 957 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 28025 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.455986 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.237353 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 961 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27993 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.456507 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.239608 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22265 79.45% 79.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3171 11.31% 90.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1034 3.69% 94.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 483 1.72% 96.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 332 1.18% 97.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 227 0.81% 98.17% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 200 0.71% 98.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 76 0.27% 99.15% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 237 0.85% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 22231 79.42% 79.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 3185 11.38% 90.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1025 3.66% 94.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 479 1.71% 96.17% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 332 1.19% 97.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 227 0.81% 98.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 194 0.69% 98.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 80 0.29% 99.14% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 240 0.86% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 28025 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27993 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -588,27 +588,27 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 237 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 240 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 126869 # The number of ROB reads -system.cpu.rob.rob_writes 53172 # The number of ROB writes -system.cpu.timesIdled 388 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20877 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 126718 # The number of ROB reads +system.cpu.rob.rob_writes 53072 # The number of ROB writes +system.cpu.timesIdled 387 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20810 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 7.681576 # CPI: Cycles Per Instruction -system.cpu.cpi::1 7.680370 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.840486 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.130182 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.130202 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.260384 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 24701 # number of integer regfile reads -system.cpu.int_regfile_writes 13755 # number of integer regfile writes +system.cpu.cpi::0 7.665725 # CPI: Cycles Per Instruction +system.cpu.cpi::1 7.664522 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.832562 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.130451 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.130471 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.260922 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 24678 # number of integer regfile reads +system.cpu.int_regfile_writes 13757 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -616,102 +616,102 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 292.522712 # Cycle average of tags in use -system.cpu.icache.total_refs 3780 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 293.126270 # Cycle average of tags in use +system.cpu.icache.total_refs 3772 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 624 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.057692 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.044872 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 292.522712 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.142833 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.142833 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 3780 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3780 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3780 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3780 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3780 # number of overall hits -system.cpu.icache.overall_hits::total 3780 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1049 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1049 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1049 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1049 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1049 # number of overall misses -system.cpu.icache.overall_misses::total 1049 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 78577996 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 78577996 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 78577996 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 78577996 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 78577996 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 78577996 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4829 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4829 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4829 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4829 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4829 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217229 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.217229 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.217229 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.217229 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.217229 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.217229 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74907.527169 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74907.527169 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74907.527169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74907.527169 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74907.527169 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 3158 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 293.126270 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.143128 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.143128 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 3772 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3772 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3772 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3772 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3772 # number of overall hits +system.cpu.icache.overall_hits::total 3772 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1048 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1048 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1048 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1048 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1048 # number of overall misses +system.cpu.icache.overall_misses::total 1048 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 78261996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 78261996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 78261996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 78261996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 78261996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 78261996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 4820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4820 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4820 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4820 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4820 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4820 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217427 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.217427 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.217427 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.217427 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.217427 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.217427 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74677.477099 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74677.477099 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74677.477099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74677.477099 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74677.477099 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 3131 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 47.848485 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 47.439394 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 425 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 425 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 425 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 425 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 425 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 425 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 424 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 424 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 424 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 424 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 424 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 424 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 624 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 624 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 624 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48453998 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 48453998 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48453998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 48453998 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48453998 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 48453998 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129219 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.129219 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129219 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.129219 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77650.637821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77650.637821 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77650.637821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 77650.637821 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 48109998 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 48109998 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 48109998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 48109998 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 48109998 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 48109998 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.129461 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.129461 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.129461 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.129461 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 77099.355769 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 77099.355769 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 77099.355769 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 77099.355769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 77099.355769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 77099.355769 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 408.674581 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 293.629007 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 115.045574 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.008961 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003511 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.012472 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -729,17 +729,17 @@ system.cpu.l2cache.demand_misses::total 970 # nu system.cpu.l2cache.overall_misses::cpu.inst 622 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 348 # number of overall misses system.cpu.l2cache.overall_misses::total 970 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 47808000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 18056500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 65864500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12124000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 12124000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 47808000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 30180500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 77988500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 47808000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 30180500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 77988500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 47463500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17802500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 65266000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12136500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 12136500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 47463500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 29939000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 77402500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 47463500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 29939000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 77402500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 624 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 202 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 826 # number of ReadReq accesses(hits+misses) @@ -762,17 +762,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997942 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997942 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76861.736334 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 89388.613861 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 79932.645631 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83041.095890 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83041.095890 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80400.515464 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76861.736334 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86725.574713 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80400.515464 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76307.877814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88131.188119 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 79206.310680 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 83126.712329 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 83126.712329 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76307.877814 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86031.609195 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 79796.391753 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76307.877814 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86031.609195 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 79796.391753 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,17 +792,17 @@ system.cpu.l2cache.demand_mshr_misses::total 970 system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39796396 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15346068 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55142464 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10352307 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10352307 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 39796396 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25698375 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 65494771 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39796396 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25698375 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 65494771 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses @@ -814,93 +814,93 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63981.344051 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75970.633663 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66920.466019 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70906.212329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70906.212329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63981.344051 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 73845.905172 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63981.344051 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 73845.905172 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67520.382474 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 202.984846 # Cycle average of tags in use -system.cpu.dcache.total_refs 4338 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 203.203118 # Cycle average of tags in use +system.cpu.dcache.total_refs 4334 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 348 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.465517 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 12.454023 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 202.984846 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.049557 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.049557 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3316 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3316 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 203.203118 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.049610 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.049610 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3312 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3312 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1022 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1022 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4338 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4338 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4338 # number of overall hits -system.cpu.dcache.overall_hits::total 4338 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 320 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 320 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4334 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4334 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4334 # number of overall hits +system.cpu.dcache.overall_hits::total 4334 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 323 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 323 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 708 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 708 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1028 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1028 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1028 # number of overall misses -system.cpu.dcache.overall_misses::total 1028 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26222500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26222500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 53389967 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 53389967 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 79612467 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 79612467 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 79612467 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 79612467 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3636 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3636 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1031 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1031 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1031 # number of overall misses +system.cpu.dcache.overall_misses::total 1031 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 25422500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 25422500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 53416467 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 53416467 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 78838967 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 78838967 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 78838967 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 78838967 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3635 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3635 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5366 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5366 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5366 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5366 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088009 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.088009 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5365 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5365 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5365 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5365 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.088858 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.088858 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.409249 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.409249 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.191577 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.191577 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.191577 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.191577 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 81945.312500 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 81945.312500 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75409.557910 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 75409.557910 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 77444.034047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 77444.034047 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 77444.034047 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 4583 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.192171 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.192171 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.192171 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.192171 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78707.430341 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 78707.430341 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75446.987288 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 75446.987288 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76468.445199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76468.445199 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76468.445199 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 4608 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 91 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.362637 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 50.086957 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 118 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 118 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 121 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 121 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 562 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 562 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 680 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 680 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 680 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 683 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 683 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 683 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 683 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 202 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 202 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses @@ -909,30 +909,30 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 348 system.cpu.dcache.demand_mshr_misses::total 348 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 348 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 18267500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12271498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 12271498 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30538998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 30538998 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30538998 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 30538998 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055556 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055556 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12283998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12283998 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30297498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 30297498 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30297498 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 30297498 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055571 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055571 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.064853 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064853 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.064853 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 90433.168317 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 90433.168317 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84051.356164 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84051.356164 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87755.741379 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 87755.741379 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.064865 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064865 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.064865 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89175.742574 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89175.742574 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 84136.972603 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 84136.972603 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87061.775862 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 87061.775862 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 2c6b30544..1c51ba20c 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -479,6 +479,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=32 master=system.cpu.l2cache.cpu_side @@ -511,6 +512,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -521,6 +523,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 757e1f2b0..eeaf23c5e 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3- gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:08:16 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second @@ -20,4 +20,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 23180500 because target called exit() +Exiting @ tick 23775500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index eaa2ab26e..3bff44537 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 23775500 # Number of ticks simulated final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69027 # Simulator instruction rate (inst/s) -host_op_rate 69023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113671122 # Simulator tick rate (ticks/s) -host_mem_usage 232284 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 12604 # Simulator instruction rate (inst/s) +host_op_rate 12604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 20757401 # Simulator tick rate (ticks/s) +host_mem_usage 277264 # Number of bytes of host memory used +host_seconds 1.15 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -183,17 +183,17 @@ system.cpu.workload.num_syscalls 18 # Nu system.cpu.numCycles 47552 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 12219 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 12221 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 31483 # Number of instructions fetch has processed system.cpu.fetch.Branches 6770 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2889 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 9186 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 3077 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8389 # Number of cycles fetch has spent blocked +system.cpu.fetch.BlockedCycles 8387 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 1048 # Number of stall cycles due to pending traps system.cpu.fetch.CacheLines 5341 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.IcacheSquashes 447 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 32753 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.961225 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.154417 # Number of instructions fetched each cycle (Total) @@ -213,16 +213,16 @@ system.cpu.fetch.rateDist::max_value 8 # Nu system.cpu.fetch.rateDist::total 32753 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.142370 # Number of branch fetches per cycle system.cpu.fetch.rate 0.662075 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12949 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9302 # Number of cycles decode is blocked +system.cpu.decode.IdleCycles 12951 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9300 # Number of cycles decode is blocked system.cpu.decode.RunCycles 8402 # Number of cycles decode is running system.cpu.decode.UnblockCycles 193 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 1907 # Number of cycles decode is squashing system.cpu.decode.DecodedInsts 29379 # Number of instructions handled by decode system.cpu.rename.SquashCycles 1907 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13599 # Number of cycles rename is idle +system.cpu.rename.IdleCycles 13601 # Number of cycles rename is idle system.cpu.rename.BlockCycles 381 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8397 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 8395 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 8002 # Number of cycles rename is running system.cpu.rename.UnblockCycles 467 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 26943 # Number of instructions processed by rename diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index adca0d63f..49d73401e 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -1779,6 +1779,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -1789,6 +1790,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=false in_addr_map=true @@ -1817,6 +1819,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index 9fd6655b7..3c88e0e72 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 16:01:12 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second @@ -12,38 +12,38 @@ info: Entering event queue @ 0. Starting simulation... Init done [Iteration 1, Thread 1] Got lock [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock -[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 -[Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 Iteration 2 completed -[Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 3, Thread 3] Got lock -[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 Iteration 3 completed -[Iteration 4, Thread 3] Got lock -[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 -[Iteration 4, Thread 1] Got lock -[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 [Iteration 4, Thread 2] Got lock -[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 3] Got lock -[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 5, Thread 1] Got lock [Iteration 5, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2 Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 @@ -52,19 +52,19 @@ Iteration 5 completed [Iteration 6, Thread 3] Got lock [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 Iteration 6 completed +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 -[Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 Iteration 7 completed -[Iteration 8, Thread 3] Got lock -[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 [Iteration 8, Thread 1] Got lock -[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 8, Thread 2] Got lock -[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 Iteration 8 completed [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3 @@ -73,12 +73,12 @@ Iteration 8 completed [Iteration 9, Thread 2] Got lock [Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 Iteration 9 completed -[Iteration 10, Thread 1] Got lock -[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 -[Iteration 10, Thread 3] Got lock -[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 10, Thread 2] Got lock -[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 104832500 because target called exit() +Exiting @ tick 105945500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3eb29c400..f2f028686 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000106 # Number of seconds simulated -sim_ticks 105801500 # Number of ticks simulated -final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 105945500 # Number of ticks simulated +final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 173787 # Simulator instruction rate (inst/s) -host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 17750545 # Simulator tick rate (ticks/s) -host_mem_usage 247480 # Number of bytes of host memory used -host_seconds 5.96 # Real time elapsed on the host -sim_insts 1035849 # Number of instructions simulated -sim_ops 1035849 # Number of ops (including micro ops) simulated +host_inst_rate 48441 # Simulator instruction rate (inst/s) +host_op_rate 48441 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4953275 # Simulator tick rate (ticks/s) +host_mem_usage 291288 # Number of bytes of host memory used +host_seconds 21.39 # Real time elapsed on the host +sim_insts 1036095 # Number of instructions simulated +sim_ops 1036095 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 5120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory system.physmem.bytes_read::total 42240 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 5120 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 384 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 80 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 660 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 215951570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 101624268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 48392509 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12098127 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 3629438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7863783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1814719 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7863783 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 399238196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 215951570 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 48392509 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 3629438 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1814719 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 269788236 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 215951570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 101624268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 48392509 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12098127 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 3629438 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7863783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1814719 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7863783 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 71 # Reqs where no action is needed +system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 105773500 # Total gap between requests +system.physmem.totGap 105917500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -115,8 +115,8 @@ system.physmem.writePktSize::3 0 # Ca system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes system.physmem.writePktSize::6 0 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see @@ -179,157 +179,157 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.totQLat 4076500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests +system.physmem.totQLat 4080500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests system.physmem.totBusLat 3305000 # Total cycles spent in databus access system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6167.17 # Average queueing delay per request +system.physmem.avgQLat 6173.22 # Average queueing delay per request system.physmem.avgBankLat 20136.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31303.33 # Average memory access latency -system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 31309.38 # Average memory access latency +system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.12 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time +system.physmem.busUtil 3.11 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.19 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 465 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 160020.42 # Average gap between requests -system.cpu0.branchPred.lookups 82232 # Number of BP lookups -system.cpu0.branchPred.condPredicted 80005 # Number of conditional branches predicted +system.physmem.avgGap 160238.28 # Average gap between requests +system.cpu0.branchPred.lookups 82343 # Number of BP lookups +system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 79512 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 77444 # Number of BTB hits +system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 97.399135 # BTB Hit Percentage +system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target. system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions. system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 211604 # number of cpu cycles simulated +system.cpu0.numCycles 211892 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 16980 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 488068 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 82232 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 77969 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 160105 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 3869 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 13032 # Number of cycles fetch has spent blocked +system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 1378 # Number of stall cycles due to pending traps -system.cpu0.fetch.CacheLines 5906 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 485 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 193984 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.516022 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.216359 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33879 17.46% 17.46% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79263 40.86% 58.33% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 997 0.51% 59.15% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75310 38.82% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 571 0.29% 98.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 376 0.19% 98.70% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 2516 1.30% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 193984 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.388613 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.306516 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 17628 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14487 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 159104 # Number of cycles decode is running +system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2484 # Number of cycles decode is squashing -system.cpu0.decode.DecodedInsts 484973 # Number of instructions handled by decode -system.cpu0.rename.SquashCycles 2484 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 18279 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 710 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13181 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 158767 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 563 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 482144 # Number of instructions processed by rename +system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RenamedOperands 329947 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 961518 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 961518 # Number of integer rename lookups -system.cpu0.rename.CommittedMaps 316491 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 13456 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 888 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 909 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3585 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 154112 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 77863 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 75108 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 74923 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 403093 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 921 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 400275 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 92 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11012 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9891 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 362 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 193984 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.063443 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.093968 # Number of insts issued each cycle +system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 33040 17.03% 17.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4899 2.53% 19.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76941 39.66% 59.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76443 39.41% 98.63% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1604 0.83% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 703 0.36% 99.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 261 0.13% 99.95% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 76 0.04% 99.99% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 17 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 193984 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 51 22.67% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.67% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 62 27.56% 50.22% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 112 49.78% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169361 42.31% 42.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued @@ -358,157 +358,157 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153636 38.38% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77278 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 400275 # Type of FU issued -system.cpu0.iq.rate 1.891623 # Inst issue rate +system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued +system.cpu0.iq.rate 1.891860 # Inst issue rate system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.000562 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 994851 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 415081 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 398443 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 400500 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 74634 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2277 # Number of loads squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1439 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2484 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 441 # Number of cycles IEW is blocking +system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 479665 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 304 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 154112 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 77863 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 809 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 399178 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 153293 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1097 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 75651 # number of nop insts executed -system.cpu0.iew.exec_refs 230462 # number of memory reference insts executed -system.cpu0.iew.exec_branches 79264 # Number of branches executed -system.cpu0.iew.exec_stores 77169 # Number of stores executed -system.cpu0.iew.exec_rate 1.886439 # Inst execution rate -system.cpu0.iew.wb_sent 398782 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 398443 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 236156 # num instructions producing a value -system.cpu0.iew.wb_consumers 238721 # num instructions consuming a value +system.cpu0.iew.exec_nop 75778 # number of nop insts executed +system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed +system.cpu0.iew.exec_branches 79388 # Number of branches executed +system.cpu0.iew.exec_stores 77294 # Number of stores executed +system.cpu0.iew.exec_rate 1.886744 # Inst execution rate +system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 236486 # num instructions producing a value +system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.882965 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.989255 # average fanout of values written-back +system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 12542 # The number of squashed insts skipped by commit +system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 191500 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.439102 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.136121 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 33551 17.52% 17.52% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 78896 41.20% 58.72% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2340 1.22% 59.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 696 0.36% 60.30% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 545 0.28% 60.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74448 38.88% 99.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 466 0.24% 99.71% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 256 0.13% 99.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 302 0.16% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 191500 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 467088 # Number of instructions committed -system.cpu0.commit.committedOps 467088 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 467838 # Number of instructions committed +system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 228259 # Number of memory references committed -system.cpu0.commit.loads 151835 # Number of loads committed +system.cpu0.commit.refs 228634 # Number of memory references committed +system.cpu0.commit.loads 152085 # Number of loads committed system.cpu0.commit.membars 84 # Number of memory barriers committed -system.cpu0.commit.branches 78311 # Number of branches committed +system.cpu0.commit.branches 78436 # Number of branches committed system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 314822 # Number of committed integer instructions. +system.cpu0.commit.int_insts 315322 # Number of committed integer instructions. system.cpu0.commit.function_calls 223 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 302 # number cycles where commit BW limit reached +system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 669667 # The number of ROB reads -system.cpu0.rob.rob_writes 961765 # The number of ROB writes +system.cpu0.rob.rob_reads 670698 # The number of ROB reads +system.cpu0.rob.rob_writes 963274 # The number of ROB writes system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 17620 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.committedInsts 391961 # Number of Instructions Simulated -system.cpu0.committedOps 391961 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 391961 # Number of Instructions Simulated -system.cpu0.cpi 0.539860 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.539860 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.852333 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.852333 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 714059 # number of integer regfile reads -system.cpu0.int_regfile_writes 321926 # number of integer regfile writes +system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 392586 # Number of Instructions Simulated +system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated +system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 715161 # number of integer regfile reads +system.cpu0.int_regfile_writes 322387 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 232286 # number of misc regfile reads +system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 298 # number of replacements -system.cpu0.icache.tagsinuse 245.557795 # Cycle average of tags in use -system.cpu0.icache.total_refs 5162 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use +system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 8.764007 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.557795 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479605 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479605 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5162 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 5162 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5162 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 5162 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5162 # number of overall hits -system.cpu0.icache.overall_hits::total 5162 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 744 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 744 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 744 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 744 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 744 # number of overall misses -system.cpu0.icache.overall_misses::total 744 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26547500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 26547500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 26547500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 26547500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 26547500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 26547500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 5906 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 5906 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 5906 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 5906 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 5906 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 5906 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.125974 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.125974 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.125974 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.125974 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.125974 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.125974 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35682.123656 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 35682.123656 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 35682.123656 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35682.123656 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 35682.123656 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits +system.cpu0.icache.overall_hits::total 5155 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses +system.cpu0.icache.overall_misses::total 746 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -517,106 +517,106 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 154 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 154 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 154 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 154 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 156 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 156 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 156 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21154500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 21154500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21154500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 21154500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21154500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 21154500 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099898 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.099898 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099898 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.099898 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35855.084746 # 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+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21166500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 21166500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099983 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.099983 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.099983 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35875.423729 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.429999 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153854 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use +system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 905.023529 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.429999 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280137 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280137 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 78105 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 78105 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 75839 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 75839 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 78219 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 75963 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 75963 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153944 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153944 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153944 # number of overall hits -system.cpu0.dcache.overall_hits::total 153944 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 154182 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 154182 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 154182 # number of overall hits +system.cpu0.dcache.overall_hits::total 154182 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 543 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 543 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1018 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1018 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1018 # 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number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78580 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 76382 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 76382 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses +system.cpu0.dcache.overall_misses::total 1019 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154962 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154962 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154962 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154962 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006045 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006045 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007109 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007109 # miss rate for WriteReq accesses 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-system.cpu0.dcache.demand_miss_rate::total 0.006569 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006569 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.006569 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25071.578947 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 25071.578947 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45442.900552 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 45442.900552 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28833.333333 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 28833.333333 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 35937.617878 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35937.617878 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 35937.617878 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -627,365 +627,365 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 287 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 287 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 660 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 660 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 660 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 170 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 170 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 358 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 358 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 358 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5409500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5409500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5718500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5718500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 563500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 563500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11128000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11128000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11128000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 11128000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002392 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002392 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002226 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002226 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.002310 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002310 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.002310 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28773.936170 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28773.936170 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33638.235294 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33638.235294 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26833.333333 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31083.798883 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31083.798883 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 58098 # Number of BP lookups -system.cpu1.branchPred.condPredicted 55415 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 1271 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 51986 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 51313 # Number of BTB hits +system.cpu1.branchPred.lookups 56473 # Number of BP lookups +system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 98.705421 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 648 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target. system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu1.numCycles 174790 # number of cpu cycles simulated +system.cpu1.numCycles 175078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 24349 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 331605 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 58098 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 51961 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 112635 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3690 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 23829 # Number of cycles fetch has spent blocked +system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6397 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps -system.cpu1.fetch.CacheLines 15584 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 170350 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.946610 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.217345 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 57715 33.88% 33.88% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 56197 32.99% 66.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 4087 2.40% 69.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 3199 1.88% 71.15% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 641 0.38% 71.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 43239 25.38% 96.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1271 0.75% 97.65% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 756 0.44% 98.10% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 3245 1.90% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 170350 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.332387 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.897162 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 27574 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 22245 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 108585 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 3208 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2341 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 328108 # Number of instructions handled by decode -system.cpu1.rename.SquashCycles 2341 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 28283 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 9804 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11660 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 105676 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 6189 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 325946 # Number of instructions processed by rename -system.cpu1.rename.IQFullEvents 3 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 43 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 230320 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 636644 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 636644 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 217343 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 12977 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1083 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1203 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8803 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 95013 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 46485 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 44692 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 41453 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 273191 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 4270 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 273407 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 80 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10726 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10333 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 504 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 170350 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.604972 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.301874 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 54964 32.27% 32.27% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 16569 9.73% 41.99% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 46599 27.35% 69.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 47325 27.78% 97.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 3328 1.95% 99.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1208 0.71% 99.79% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 245 0.14% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 170350 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 17 5.69% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.69% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 72 24.08% 29.77% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 210 70.23% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 130168 47.61% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.61% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 97443 35.64% 83.25% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 45796 16.75% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 273407 # Type of FU issued -system.cpu1.iq.rate 1.564203 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 299 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.001094 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 717543 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 288232 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 271609 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued +system.cpu1.iq.rate 1.510424 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 273706 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 41212 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2369 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1440 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2341 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 1392 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 66 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 323061 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 370 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 95013 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 46485 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 1042 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 456 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 928 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 1384 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 272209 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 94088 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1198 # Number of squashed instructions skipped in execute +system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 45600 # number of nop insts executed -system.cpu1.iew.exec_refs 139806 # number of memory reference insts executed -system.cpu1.iew.exec_branches 54914 # Number of branches executed -system.cpu1.iew.exec_stores 45718 # Number of stores executed -system.cpu1.iew.exec_rate 1.557349 # Inst execution rate -system.cpu1.iew.wb_sent 271881 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 271609 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 156621 # num instructions producing a value -system.cpu1.iew.wb_consumers 161297 # num instructions consuming a value +system.cpu1.iew.exec_nop 44011 # number of nop insts executed +system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed +system.cpu1.iew.exec_branches 53318 # Number of branches executed +system.cpu1.iew.exec_stores 43665 # Number of stores executed +system.cpu1.iew.exec_rate 1.503964 # Inst execution rate +system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 150856 # num instructions producing a value +system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.553916 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.971010 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 12317 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 3766 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 1271 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161612 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.922772 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.097017 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 52280 32.35% 32.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 52948 32.76% 65.11% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6058 3.75% 68.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 4700 2.91% 71.77% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1571 0.97% 72.74% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 41692 25.80% 98.54% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 528 0.33% 98.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 1013 0.63% 99.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 822 0.51% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161612 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 310743 # Number of instructions committed -system.cpu1.commit.committedOps 310743 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 300197 # Number of instructions committed +system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 137689 # Number of memory references committed -system.cpu1.commit.loads 92644 # Number of loads committed -system.cpu1.commit.membars 3055 # Number of memory barriers committed -system.cpu1.commit.branches 54067 # Number of branches committed +system.cpu1.commit.refs 131930 # Number of memory references committed +system.cpu1.commit.loads 88970 # Number of loads committed +system.cpu1.commit.membars 3544 # Number of memory barriers committed +system.cpu1.commit.branches 52469 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 213879 # Number of committed integer instructions. +system.cpu1.commit.int_insts 206526 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 822 # number cycles where commit BW limit reached +system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 483263 # The number of ROB reads -system.cpu1.rob.rob_writes 648465 # The number of ROB writes -system.cpu1.timesIdled 226 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4440 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.rob.rob_reads 472949 # The number of ROB reads +system.cpu1.rob.rob_writes 627337 # The number of ROB writes +system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 262828 # Number of Instructions Simulated -system.cpu1.committedOps 262828 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 262828 # Number of Instructions Simulated -system.cpu1.cpi 0.665036 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.665036 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.503679 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.503679 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 478110 # number of integer regfile reads -system.cpu1.int_regfile_writes 222397 # number of integer regfile writes +system.cpu1.committedInsts 253388 # Number of Instructions Simulated +system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated +system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 460976 # number of integer regfile reads +system.cpu1.int_regfile_writes 214498 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 141404 # number of misc regfile reads +system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.239071 # Cycle average of tags in use -system.cpu1.icache.total_refs 15102 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use +system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 35.534118 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.239071 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.166483 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.166483 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 15102 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 15102 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 15102 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 15102 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 15102 # number of overall hits -system.cpu1.icache.overall_hits::total 15102 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 482 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 482 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 482 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses -system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10460500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10460500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10460500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10460500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10460500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10460500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 15584 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 15584 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 15584 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 15584 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 15584 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 15584 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030929 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.030929 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030929 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.030929 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030929 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.030929 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21702.282158 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 21702.282158 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 21702.282158 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21702.282158 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 21702.282158 # average overall miss latency +system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits +system.cpu1.icache.overall_hits::total 16176 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses +system.cpu1.icache.overall_misses::total 484 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -994,106 +994,106 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 57 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 57 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 57 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits 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-system.cpu1.icache.demand_mshr_miss_latency::total 8302000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8302000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8302000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.027272 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.027272 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.027272 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.027272 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19534.117647 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19534.117647 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 19534.117647 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8244000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8244000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8244000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8244000 # number of demand (read+write) MSHR miss cycles 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latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.071497 # Cycle average of tags in use -system.cpu1.dcache.total_refs 51063 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1823.678571 # Average number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.077196 # Cycle average of tags in use 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miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19482.876712 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22411.347518 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22411.347518 # average WriteReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9444.444444 # average SwapReq miss latency -system.cpu1.dcache.SwapReq_avg_miss_latency::total 9444.444444 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 20196.027634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20196.027634 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20196.027634 # average overall miss latency +system.cpu1.dcache.occ_blocks::cpu1.data 27.077196 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.052885 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.052885 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 50842 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 50842 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 42756 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 42756 # number of WriteReq hits +system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits +system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits +system.cpu1.dcache.demand_hits::cpu1.data 93598 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 93598 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 93598 # number of overall hits +system.cpu1.dcache.overall_hits::total 93598 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 557 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 557 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 557 # number of overall misses +system.cpu1.dcache.overall_misses::total 557 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8012000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 8012000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3190500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3190500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 514000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 514000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 11202500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 11202500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 11202500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 11202500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 51257 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 51257 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 42898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 42898 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 94155 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 94155 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 94155 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 94155 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008096 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.008096 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003310 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.003310 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005916 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.005916 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005916 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.005916 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19306.024096 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19306.024096 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22468.309859 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22468.309859 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10280 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 10280 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20112.208259 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20112.208259 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1102,365 +1102,365 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 286 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 264 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 320 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 320 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 320 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 320 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 152 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 152 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 107 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 107 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 54 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 54 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1798500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1798500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1487000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1487000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 402000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 402000 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3285500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 3285500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3285500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 3285500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002876 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002876 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.830769 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.830769 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.002647 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002647 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.002647 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11832.236842 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11832.236842 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13897.196262 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13897.196262 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7444.444444 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7444.444444 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12685.328185 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12685.328185 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.branchPred.lookups 45099 # Number of BP lookups -system.cpu2.branchPred.condPredicted 42400 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 1262 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 39025 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 38304 # Number of BTB hits +system.cpu2.branchPred.lookups 48435 # Number of BP lookups +system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 98.152466 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 646 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target. system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu2.numCycles 174459 # number of cpu cycles simulated +system.cpu2.numCycles 174747 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 32669 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 244823 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 45099 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 38950 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 90929 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 39674 # Number of cycles fetch has spent blocked +system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6379 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps -system.cpu2.fetch.CacheLines 24269 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 265 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172730 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.417374 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.028063 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 81801 47.36% 47.36% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 47495 27.50% 74.85% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 8404 4.87% 79.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 3201 1.85% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 675 0.39% 81.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 25947 15.02% 96.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1207 0.70% 97.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 760 0.44% 98.12% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 3240 1.88% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172730 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.258508 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.403327 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 39762 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 34129 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 82888 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 7209 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 2363 # Number of cycles decode is squashing -system.cpu2.decode.DecodedInsts 241309 # Number of instructions handled by decode -system.cpu2.rename.SquashCycles 2363 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 40462 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 21352 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11989 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 75976 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 14209 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 239275 # Number of instructions processed by rename -system.cpu2.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 36 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.RenamedOperands 165256 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 446077 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 446077 # Number of integer rename lookups -system.cpu2.rename.CommittedMaps 152520 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 12736 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 1091 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 1215 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 16777 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 64738 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 29196 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 31698 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 24168 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 195168 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 8612 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 199473 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 72 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 10767 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10430 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 654 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172730 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.154825 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.283743 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 79387 45.96% 45.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 29099 16.85% 62.81% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 29295 16.96% 79.77% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 30090 17.42% 97.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 3300 1.91% 99.10% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 1204 0.70% 99.79% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 247 0.14% 99.94% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 52 0.03% 99.97% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 56 0.03% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172730 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16 5.67% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.67% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 56 19.86% 25.53% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 210 74.47% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 99688 49.98% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.98% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 71251 35.72% 85.70% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 28534 14.30% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 199473 # Type of FU issued -system.cpu2.iq.rate 1.143380 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 282 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.001414 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 572030 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 214590 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 197726 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued +system.cpu2.iq.rate 1.246190 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 199755 # Number of integer alu accesses +system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 23953 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 2414 # Number of loads squashed +system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 43 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 1398 # Number of stores squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 2363 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 870 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 45 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 236415 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 392 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 64738 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 29196 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 44 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 43 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 913 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 1372 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 198312 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 63718 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1161 # Number of squashed instructions skipped in execute +system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 32635 # number of nop insts executed -system.cpu2.iew.exec_refs 92179 # number of memory reference insts executed -system.cpu2.iew.exec_branches 41831 # Number of branches executed -system.cpu2.iew.exec_stores 28461 # Number of stores executed -system.cpu2.iew.exec_rate 1.136726 # Inst execution rate -system.cpu2.iew.wb_sent 197998 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 197726 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 108943 # num instructions producing a value -system.cpu2.iew.wb_consumers 113613 # num instructions consuming a value +system.cpu2.iew.exec_nop 35937 # number of nop insts executed +system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed +system.cpu2.iew.exec_branches 45106 # Number of branches executed +system.cpu2.iew.exec_stores 32695 # Number of stores executed +system.cpu2.iew.exec_rate 1.239535 # Inst execution rate +system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 120625 # num instructions producing a value +system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.133367 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.958896 # average fanout of values written-back +system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 12414 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 7958 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 1262 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163988 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.365838 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.905647 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 80806 49.28% 49.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 39854 24.30% 73.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 6054 3.69% 77.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 8882 5.42% 82.69% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 1574 0.96% 83.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 24481 14.93% 98.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 507 0.31% 98.88% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 1010 0.62% 99.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 820 0.50% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163988 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 223981 # Number of instructions committed -system.cpu2.commit.committedOps 223981 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 245558 # Number of instructions committed +system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 90122 # Number of memory references committed -system.cpu2.commit.loads 62324 # Number of loads committed -system.cpu2.commit.membars 7244 # Number of memory barriers committed -system.cpu2.commit.branches 41003 # Number of branches committed +system.cpu2.commit.refs 101851 # Number of memory references committed +system.cpu2.commit.loads 69824 # Number of loads committed +system.cpu2.commit.membars 6301 # Number of memory barriers committed +system.cpu2.commit.branches 44289 # Number of branches committed system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 153248 # Number of committed integer instructions. +system.cpu2.commit.int_insts 168258 # Number of committed integer instructions. system.cpu2.commit.function_calls 322 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 820 # number cycles where commit BW limit reached +system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 398976 # The number of ROB reads -system.cpu2.rob.rob_writes 475157 # The number of ROB writes -system.cpu2.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1729 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.rob.rob_reads 421045 # The number of ROB reads +system.cpu2.rob.rob_writes 518771 # The number of ROB writes +system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 184944 # Number of Instructions Simulated -system.cpu2.committedOps 184944 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 184944 # Number of Instructions Simulated -system.cpu2.cpi 0.943307 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.943307 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.060100 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.060100 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 335090 # number of integer regfile reads -system.cpu2.int_regfile_writes 157371 # number of integer regfile writes +system.cpu2.committedInsts 204183 # Number of Instructions Simulated +system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated +system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 370277 # number of integer regfile reads +system.cpu2.int_regfile_writes 173276 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 93758 # number of misc regfile reads +system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 83.416337 # Cycle average of tags in use -system.cpu2.icache.total_refs 23791 # Total number of references to valid blocks. +system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use +system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 55.327907 # Average number of references to valid blocks. +system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 83.416337 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.162923 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.162923 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 23791 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 23791 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 23791 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 23791 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 23791 # number of overall hits -system.cpu2.icache.overall_hits::total 23791 # number of overall hits +system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits +system.cpu2.icache.overall_hits::total 21789 # number of overall hits system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses system.cpu2.icache.overall_misses::total 478 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6751000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6751000 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6751000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6751000 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6751000 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6751000 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 24269 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 24269 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 24269 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 24269 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 24269 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 24269 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.019696 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.019696 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.019696 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.019696 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.019696 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.019696 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14123.430962 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14123.430962 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14123.430962 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14123.430962 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14123.430962 # average overall miss latency +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 22267 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 22267 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 22267 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021467 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.021467 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021467 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.021467 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021467 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.021467 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14296.025105 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 14296.025105 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1481,94 +1481,94 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5435000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5435000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5435000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5435000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5435000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5435000 # number of overall MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017718 # mshr miss rate for ReadReq accesses -system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_miss_rate::total 0.017718 # mshr miss rate for demand accesses -system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017718 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_miss_rate::total 0.017718 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12639.534884 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12639.534884 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 12639.534884 # average overall mshr miss latency +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5518500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5518500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5518500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5518500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5518500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5518500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for demand accesses +system.cpu2.icache.demand_mshr_miss_rate::total 0.019311 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for overall accesses +system.cpu2.icache.overall_mshr_miss_rate::total 0.019311 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12833.720930 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 25.649065 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33911 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1169.344828 # Average number of references to valid blocks. +system.cpu2.dcache.tagsinuse 25.660288 # Cycle average of tags in use +system.cpu2.dcache.total_refs 38032 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 1358.285714 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 25.649065 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.050096 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.050096 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 39345 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 39345 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 27592 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 27592 # number of WriteReq hits +system.cpu2.dcache.occ_blocks::cpu2.data 25.660288 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.050118 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.050118 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 42624 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 42624 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 31820 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 31820 # number of WriteReq hits system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 66937 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 66937 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 66937 # number of overall hits -system.cpu2.dcache.overall_hits::total 66937 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 402 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 402 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 138 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 138 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 53 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 53 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 540 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 540 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 540 # number of overall misses -system.cpu2.dcache.overall_misses::total 540 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5276000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5276000 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2759500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2759500 # number of WriteReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 558000 # number of SwapReq miss cycles -system.cpu2.dcache.SwapReq_miss_latency::total 558000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 8035500 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 8035500 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 8035500 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 8035500 # number of overall miss cycles -system.cpu2.dcache.ReadReq_accesses::cpu2.data 39747 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 39747 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 27730 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 27730 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 68 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 67477 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 67477 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 67477 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 67477 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010114 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.010114 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004977 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.004977 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.779412 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.779412 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008003 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.008003 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008003 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.008003 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13124.378109 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 13124.378109 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19996.376812 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 19996.376812 # average WriteReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 10528.301887 # average SwapReq miss latency -system.cpu2.dcache.SwapReq_avg_miss_latency::total 10528.301887 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14880.555556 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14880.555556 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14880.555556 # average overall miss latency +system.cpu2.dcache.demand_hits::cpu2.data 74444 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 74444 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 74444 # number of overall hits +system.cpu2.dcache.overall_hits::total 74444 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 407 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 541 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 541 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 541 # number of overall misses +system.cpu2.dcache.overall_misses::total 541 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5612500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5612500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2750000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 572000 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 572000 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 8362500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 8362500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 8362500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 8362500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 43031 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 43031 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 31954 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 31954 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 74985 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 74985 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 74985 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 74985 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009458 # miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_miss_rate::total 0.009458 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004194 # miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_miss_rate::total 0.004194 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007215 # miss rate for demand accesses +system.cpu2.dcache.demand_miss_rate::total 0.007215 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007215 # miss rate for overall accesses +system.cpu2.dcache.overall_miss_rate::total 0.007215 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13789.926290 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 13789.926290 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20522.388060 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 20522.388060 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9862.068966 # average SwapReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::total 9862.068966 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 15457.486137 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 15457.486137 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1577,365 +1577,365 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.dcache.fast_writes 0 # number of fast writes performed system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 241 # number of ReadReq MSHR hits -system.cpu2.dcache.ReadReq_mshr_hits::total 241 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits -system.cpu2.dcache.demand_mshr_hits::cpu2.data 274 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_hits::total 274 # number of demand (read+write) MSHR hits -system.cpu2.dcache.overall_mshr_hits::cpu2.data 274 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_hits::total 274 # number of overall MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 105 # number of WriteReq MSHR misses -system.cpu2.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 53 # number of SwapReq MSHR misses -system.cpu2.dcache.SwapReq_mshr_misses::total 53 # number of SwapReq MSHR misses -system.cpu2.dcache.demand_mshr_misses::cpu2.data 266 # number of demand (read+write) MSHR misses -system.cpu2.dcache.demand_mshr_misses::total 266 # number of demand (read+write) MSHR misses -system.cpu2.dcache.overall_mshr_misses::cpu2.data 266 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_misses::total 266 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1358500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1358500 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1350500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1350500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 452000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.SwapReq_mshr_miss_latency::total 452000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2709000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2709000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2709000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2709000 # number of overall MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004051 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004051 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003787 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003787 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.779412 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.779412 # mshr miss rate for SwapReq accesses -system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_miss_rate::total 0.003942 # mshr miss rate for demand accesses -system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003942 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_miss_rate::total 0.003942 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8437.888199 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8437.888199 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 12861.904762 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 12861.904762 # average WriteReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 8528.301887 # average SwapReq mshr miss latency -system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 8528.301887 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10184.210526 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10184.210526 # average overall mshr miss latency +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.branchPred.lookups 47073 # Number of BP lookups -system.cpu3.branchPred.condPredicted 44334 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 1289 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 40998 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 40129 # Number of BTB hits +system.cpu3.branchPred.lookups 45379 # Number of BP lookups +system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 97.880384 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 665 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target. system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions. -system.cpu3.numCycles 174149 # number of cpu cycles simulated +system.cpu3.numCycles 174437 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 31334 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 257802 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 47073 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 40794 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 94093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 3784 # Number of cycles fetch has spent squashing -system.cpu3.fetch.BlockedCycles 37693 # Number of cycles fetch has spent blocked +system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6388 # Number of stall cycles due to no active thread to fetch from -system.cpu3.fetch.PendingTrapStallCycles 691 # Number of stall cycles due to pending traps -system.cpu3.fetch.CacheLines 23091 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 274 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172622 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.493448 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.066617 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 78529 45.49% 45.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 48697 28.21% 73.70% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 7780 4.51% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3181 1.84% 80.05% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 739 0.43% 80.48% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 28510 16.52% 97.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 1109 0.64% 97.64% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 774 0.45% 98.09% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 3303 1.91% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172622 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.270303 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.480353 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 38095 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 32492 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 86590 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 6639 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 2418 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 254216 # Number of instructions handled by decode -system.cpu3.rename.SquashCycles 2418 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 38798 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 19631 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 12074 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 80231 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 13082 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 251848 # Number of instructions processed by rename +system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LSQFullEvents 33 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 174600 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 473869 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 473869 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 161804 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 12796 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 1100 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 1222 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 15769 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 69165 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 31749 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 33643 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 26714 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 206536 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 7999 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 210100 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10964 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10853 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 623 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172622 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.217110 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.294923 # Number of insts issued each cycle +system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 76068 44.07% 44.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 27297 15.81% 59.88% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 31861 18.46% 78.34% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 32569 18.87% 97.20% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 3286 1.90% 99.11% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 1177 0.68% 99.79% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 258 0.15% 99.94% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172622 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 11 3.79% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 69 23.79% 27.59% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 210 72.41% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 104024 49.51% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.51% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 75016 35.70% 85.22% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 31060 14.78% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 210100 # Type of FU issued -system.cpu3.iq.rate 1.206438 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 290 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.001380 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 593222 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 225545 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 208328 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued +system.cpu3.iq.rate 1.148908 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 210390 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 26418 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 2499 # Number of loads squashed +system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 1475 # Number of stores squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 2418 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 854 # Number of cycles IEW is blocking +system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 249047 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 315 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 69165 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 31749 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 1065 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 46 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 473 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 935 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 1408 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 208934 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 68077 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1166 # Number of squashed instructions skipped in execute +system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 34512 # number of nop insts executed -system.cpu3.iew.exec_refs 99056 # number of memory reference insts executed -system.cpu3.iew.exec_branches 43690 # Number of branches executed -system.cpu3.iew.exec_stores 30979 # Number of stores executed -system.cpu3.iew.exec_rate 1.199743 # Inst execution rate -system.cpu3.iew.wb_sent 208597 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 208328 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 115832 # num instructions producing a value -system.cpu3.iew.wb_consumers 120507 # num instructions consuming a value +system.cpu3.iew.exec_nop 32807 # number of nop insts executed +system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed +system.cpu3.iew.exec_branches 41971 # Number of branches executed +system.cpu3.iew.exec_stores 28736 # Number of stores executed +system.cpu3.iew.exec_rate 1.142235 # Inst execution rate +system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 109565 # num instructions producing a value +system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.196263 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.961206 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 12582 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 7376 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 1289 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163816 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.443357 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.942306 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 76810 46.89% 46.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 41800 25.52% 72.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 6086 3.72% 76.12% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 8257 5.04% 81.16% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 1545 0.94% 82.10% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 27022 16.50% 98.60% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 472 0.29% 98.89% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 1012 0.62% 99.50% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163816 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 236445 # Number of instructions committed -system.cpu3.commit.committedOps 236445 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 225028 # Number of instructions committed +system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 96940 # Number of memory references committed -system.cpu3.commit.loads 66666 # Number of loads committed -system.cpu3.commit.membars 6656 # Number of memory barriers committed -system.cpu3.commit.branches 42889 # Number of branches committed +system.cpu3.commit.refs 90734 # Number of memory references committed +system.cpu3.commit.loads 62697 # Number of loads committed +system.cpu3.commit.membars 7153 # Number of memory barriers committed +system.cpu3.commit.branches 41151 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 161946 # Number of committed integer instructions. +system.cpu3.commit.int_insts 154003 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. -system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached +system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 411444 # The number of ROB reads -system.cpu3.rob.rob_writes 500477 # The number of ROB writes -system.cpu3.timesIdled 219 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1527 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.rob.rob_reads 400338 # The number of ROB reads +system.cpu3.rob.rob_writes 477767 # The number of ROB writes +system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 196116 # Number of Instructions Simulated -system.cpu3.committedOps 196116 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 196116 # Number of Instructions Simulated -system.cpu3.cpi 0.887990 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.887990 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.126139 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.126139 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 355696 # number of integer regfile reads -system.cpu3.int_regfile_writes 166589 # number of integer regfile writes +system.cpu3.committedInsts 185938 # Number of Instructions Simulated +system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated +system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 337021 # number of integer regfile reads +system.cpu3.int_regfile_writes 158120 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 100584 # number of misc regfile reads +system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 80.204482 # Cycle average of tags in use -system.cpu3.icache.total_refs 22614 # Total number of references to valid blocks. +system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use +system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 52.713287 # Average number of references to valid blocks. +system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 80.204482 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.156649 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.156649 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 22614 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 22614 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 22614 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 22614 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 22614 # number of overall hits -system.cpu3.icache.overall_hits::total 22614 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 477 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 477 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 477 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 477 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 477 # number of overall misses -system.cpu3.icache.overall_misses::total 477 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6252000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6252000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6252000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6252000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6252000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6252000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 23091 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 23091 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 23091 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 23091 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 23091 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 23091 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.020657 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.020657 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.020657 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.020657 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.020657 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.020657 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13106.918239 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13106.918239 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13106.918239 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13106.918239 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13106.918239 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 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9965.116279 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 258 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 258 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 290 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 290 # number of overall MSHR hits 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number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5402500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 997000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 868500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 757000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 8025000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 18249500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 10005500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4327000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1663000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 840500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 937000 # number of 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+system.l2c.overall_miss_latency::total 37064500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) @@ -2238,10 +2238,10 @@ system.l2c.ReadReq_accesses::total 1989 # nu system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 16 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 74 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) @@ -2267,18 +2267,18 @@ system.l2c.overall_accesses::cpu3.data 24 # nu system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.195294 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.027907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.032558 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.013986 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.inst 0.011655 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.959459 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses @@ -2286,54 +2286,54 @@ system.l2c.ReadExReq_miss_rate::cpu3.data 1 # m system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.195294 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.192941 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.027907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.032558 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.013986 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.inst 0.011655 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.195294 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.192941 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.027907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.032558 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.013986 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.inst 0.011655 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.318396 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50659.722222 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 62364.864865 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53006.024096 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 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54897.777778 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::total 53381.433824 # average ReadReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57473.404255 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76692.307692 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72375 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3.data 63083.333333 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 61259.541985 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 50693.055556 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 59556.547619 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 52768.292683 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 83150 # average overall miss latency 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cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 113753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 664761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28141994 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses @@ -2444,7 +2444,7 @@ system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.959459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -2452,59 +2452,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.013953 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini index c755fbf49..b4eef5d4b 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini @@ -439,6 +439,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 master=system.physmem.port @@ -462,6 +463,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout index d217747b2..adbb7069b 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout @@ -3,33 +3,33 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 15:49:24 -gem5 started Jan 23 2013 15:51:52 +gem5 compiled Mar 26 2013 15:04:14 +gem5 started Mar 26 2013 15:04:37 gem5 executing on ribera.cs.wisc.edu command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Init done +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 1, Thread 3] Got lock -[Iteration 1, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 [Iteration 1, Thread 2] Got lock [Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 -[Iteration 1, Thread 1] Got lock -[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 Iteration 1 completed -[Iteration 2, Thread 2] Got lock -[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 2, Thread 3] Got lock -[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 [Iteration 2, Thread 1] Got lock -[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 Iteration 2 completed -[Iteration 3, Thread 2] Got lock -[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 3, Thread 1] Got lock -[Iteration 3, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 3, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 3, Thread 3] Got lock [Iteration 3, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2 Iteration 3 completed [Iteration 4, Thread 2] Got lock [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 @@ -38,12 +38,12 @@ Iteration 3 completed [Iteration 4, Thread 1] Got lock [Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 Iteration 4 completed -[Iteration 5, Thread 2] Got lock -[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 5, Thread 1] Got lock -[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 5, Thread 3] Got lock [Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 Iteration 5 completed [Iteration 6, Thread 2] Got lock [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 @@ -52,12 +52,12 @@ Iteration 5 completed [Iteration 6, Thread 1] Got lock [Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 Iteration 6 completed -[Iteration 7, Thread 2] Got lock -[Iteration 7, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 7, Thread 1] Got lock -[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 7, Thread 3] Got lock [Iteration 7, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 Iteration 7 completed [Iteration 8, Thread 2] Got lock [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2 @@ -66,12 +66,12 @@ Iteration 7 completed [Iteration 8, Thread 1] Got lock [Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 Iteration 8 completed -[Iteration 9, Thread 2] Got lock -[Iteration 9, Thread 2] Critical section done, previously next=0, now next=2 [Iteration 9, Thread 1] Got lock -[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 [Iteration 9, Thread 3] Got lock [Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 Iteration 9 completed [Iteration 10, Thread 2] Got lock [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2 @@ -81,4 +81,4 @@ Iteration 9 completed [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1 Iteration 10 completed PASSED :-) -Exiting @ tick 261623500 because target called exit() +Exiting @ tick 262970500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt index 03a5c597b..f34b8a118 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt @@ -1,130 +1,130 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000262 # Number of seconds simulated -sim_ticks 261623500 # Number of ticks simulated -final_tick 261623500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000263 # Number of seconds simulated +sim_ticks 262970500 # Number of ticks simulated +final_tick 262970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 226128 # Simulator instruction rate (inst/s) -host_op_rate 226126 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 89603226 # Simulator tick rate (ticks/s) -host_mem_usage 289396 # Number of bytes of host memory used -host_seconds 2.92 # Real time elapsed on the host -sim_insts 660239 # Number of instructions simulated -sim_ops 660239 # Number of ops (including micro ops) simulated +host_inst_rate 110323 # Simulator instruction rate (inst/s) +host_op_rate 110323 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43749084 # Simulator tick rate (ticks/s) +host_mem_usage 287188 # Number of bytes of host memory used +host_seconds 6.01 # Real time elapsed on the host +sim_insts 663135 # Number of instructions simulated +sim_ops 663135 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 18240 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 3392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 4224 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 1472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 960 # Number of bytes read from this memory system.physmem.bytes_read::total 36608 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 18240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 576 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 3392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 4224 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 64 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 22656 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu0.inst 285 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 53 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 66 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 23 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 572 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 69718508 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 40363347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 1712384 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 3669395 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 2201637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 3914021 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 12965196 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 5381780 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 139926268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 69718508 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 1712384 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 2201637 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 12965196 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 86597725 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 69718508 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 40363347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1712384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3669395 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 2201637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 3914021 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 12965196 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 5381780 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 139926268 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 69361392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 40156596 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 16062638 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5597586 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 486747 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 3650600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 243373 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 3650600 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 139209531 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 69361392 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 16062638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 486747 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 243373 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 86154150 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 69361392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 40156596 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 16062638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 5597586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 486747 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 3650600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 243373 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 3650600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 139209531 # Total bandwidth to/from this memory (bytes/s) system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 523247 # number of cpu cycles simulated +system.cpu0.numCycles 525941 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 158010 # Number of instructions committed -system.cpu0.committedOps 158010 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 108832 # Number of integer alu accesses +system.cpu0.committedInsts 158580 # Number of instructions committed +system.cpu0.committedOps 158580 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109212 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 25938 # number of instructions that are conditional controls -system.cpu0.num_int_insts 108832 # number of integer instructions +system.cpu0.num_conditional_control_insts 26033 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109212 # number of integer instructions system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 314654 # number of times the integer registers were read -system.cpu0.num_int_register_writes 110438 # number of times the integer registers were written +system.cpu0.num_int_register_reads 315794 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110818 # number of times the integer registers were written system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 73739 # number of memory refs -system.cpu0.num_load_insts 48819 # Number of load instructions -system.cpu0.num_store_insts 24920 # Number of store instructions +system.cpu0.num_mem_refs 74024 # number of memory refs +system.cpu0.num_load_insts 49009 # Number of load instructions +system.cpu0.num_store_insts 25015 # Number of store instructions system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 523247 # Number of busy cycles +system.cpu0.num_busy_cycles 525941 # Number of busy cycles system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu0.idle_fraction 0 # Percentage of idle cycles system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 212.464540 # Cycle average of tags in use -system.cpu0.icache.total_refs 157606 # Total number of references to valid blocks. +system.cpu0.icache.tagsinuse 212.410852 # Cycle average of tags in use +system.cpu0.icache.total_refs 158176 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 337.486081 # Average number of references to valid blocks. +system.cpu0.icache.avg_refs 338.706638 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 212.464540 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.414970 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.414970 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 157606 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 157606 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 157606 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 157606 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 157606 # number of overall hits -system.cpu0.icache.overall_hits::total 157606 # number of overall hits +system.cpu0.icache.occ_blocks::cpu0.inst 212.410852 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.414865 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.414865 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 158176 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 158176 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 158176 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 158176 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 158176 # number of overall hits +system.cpu0.icache.overall_hits::total 158176 # number of overall hits system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18144000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 18144000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 18144000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 18144000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 18144000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 18144000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 158073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 158073 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 158073 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 158073 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 158073 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 158073 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002954 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002954 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002954 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002954 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002954 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002954 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38852.248394 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 38852.248394 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 38852.248394 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38852.248394 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 38852.248394 # average overall miss latency +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18143000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18143000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18143000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18143000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18143000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18143000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 158643 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 158643 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 158643 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 158643 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 158643 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 158643 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002944 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.002944 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002944 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.002944 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002944 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.002944 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 38850.107066 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 38850.107066 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 38850.107066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 38850.107066 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 38850.107066 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -139,94 +139,94 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 17210000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 17210000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17210000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 17210000 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002954 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.002954 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002954 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.002954 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36852.248394 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36852.248394 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 36852.248394 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17209000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17209000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17209000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17209000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17209000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17209000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.002944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.002944 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002944 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.002944 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 36850.107066 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36850.107066 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 36850.107066 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 145.601248 # Cycle average of tags in use -system.cpu0.dcache.total_refs 73215 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 145.568014 # Cycle average of tags in use +system.cpu0.dcache.total_refs 73491 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 438.413174 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 440.065868 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 145.601248 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.284377 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.284377 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 48647 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 48647 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 24686 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 24686 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 145.568014 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284313 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284313 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 48828 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 48828 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 24780 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 24780 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 16 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 73333 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 73333 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 73333 # number of overall hits -system.cpu0.dcache.overall_hits::total 73333 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 162 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 162 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 183 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 183 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 73608 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 73608 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 73608 # number of overall hits +system.cpu0.dcache.overall_hits::total 73608 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 171 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 171 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 184 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 184 # number of WriteReq misses system.cpu0.dcache.SwapReq_misses::cpu0.data 26 # number of SwapReq misses system.cpu0.dcache.SwapReq_misses::total 26 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 345 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345 # number of overall misses -system.cpu0.dcache.overall_misses::total 345 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4649500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4649500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7005000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7005000 # number of WriteReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 363500 # number of SwapReq miss cycles -system.cpu0.dcache.SwapReq_miss_latency::total 363500 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 11654500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 11654500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 11654500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 11654500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 48809 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 48809 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 24869 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 24869 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 355 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 355 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 355 # number of overall misses +system.cpu0.dcache.overall_misses::total 355 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4683500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4683500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7047500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7047500 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 364500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 364500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11731000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11731000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11731000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11731000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 48999 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 48999 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 24964 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 24964 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 73678 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 73678 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 73678 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 73678 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003319 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.003319 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007359 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.007359 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 73963 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 73963 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 73963 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 73963 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.003490 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.003490 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007371 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.007371 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.619048 # miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_miss_rate::total 0.619048 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004683 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.004683 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004683 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.004683 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 28700.617284 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 28700.617284 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38278.688525 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38278.688525 # average WriteReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 13980.769231 # average SwapReq miss latency -system.cpu0.dcache.SwapReq_avg_miss_latency::total 13980.769231 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33781.159420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33781.159420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33781.159420 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.004800 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.004800 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.004800 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.004800 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27388.888889 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 27388.888889 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38301.630435 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38301.630435 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14019.230769 # average SwapReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::total 14019.230769 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33045.070423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33045.070423 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33045.070423 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -237,114 +237,114 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 162 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 162 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 183 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 183 # number of WriteReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 171 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 184 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 184 # number of WriteReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 26 # number of SwapReq MSHR misses system.cpu0.dcache.SwapReq_mshr_misses::total 26 # number of SwapReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 345 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 345 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 345 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4325500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4325500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6639000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6639000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 311500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.SwapReq_mshr_miss_latency::total 311500 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10964500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10964500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10964500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10964500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003319 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007359 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007359 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 355 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 355 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 355 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4341500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4341500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6679500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 312500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 312500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11021000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11021000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11021000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.003490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.003490 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.007371 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007371 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.619048 # mshr miss rate for SwapReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.619048 # mshr miss rate for SwapReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.004683 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004683 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.004683 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26700.617284 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 26700.617284 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36278.688525 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36278.688525 # average WriteReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11980.769231 # average SwapReq mshr miss latency -system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 11980.769231 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31781.159420 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31781.159420 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.004800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.004800 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.004800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25388.888889 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25388.888889 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36301.630435 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 36301.630435 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 12019.230769 # average SwapReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 12019.230769 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31045.070423 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31045.070423 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 523247 # number of cpu cycles simulated +system.cpu1.numCycles 525940 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 173283 # Number of instructions committed -system.cpu1.committedOps 173283 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 108736 # Number of integer alu accesses +system.cpu1.committedInsts 166746 # Number of instructions committed +system.cpu1.committedOps 166746 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 110403 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu1.num_func_calls 637 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 36284 # number of instructions that are conditional controls -system.cpu1.num_int_insts 108736 # number of integer instructions +system.cpu1.num_conditional_control_insts 32184 # number of instructions that are conditional controls +system.cpu1.num_int_insts 110403 # number of integer instructions system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 252002 # number of times the integer registers were read -system.cpu1.num_int_register_writes 93825 # number of times the integer registers were written +system.cpu1.num_int_register_reads 275077 # number of times the integer registers were read +system.cpu1.num_int_register_writes 104543 # number of times the integer registers were written system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 48621 # number of memory refs -system.cpu1.num_load_insts 40031 # Number of load instructions -system.cpu1.num_store_insts 8590 # Number of store instructions -system.cpu1.num_idle_cycles 68750.001737 # Number of idle cycles -system.cpu1.num_busy_cycles 454496.998263 # Number of busy cycles -system.cpu1.not_idle_fraction 0.868609 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.131391 # Percentage of idle cycles +system.cpu1.num_mem_refs 54388 # number of memory refs +system.cpu1.num_load_insts 40871 # Number of load instructions +system.cpu1.num_store_insts 13517 # Number of store instructions +system.cpu1.num_idle_cycles 69336.869902 # Number of idle cycles +system.cpu1.num_busy_cycles 456603.130098 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868166 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131834 # Percentage of idle cycles system.cpu1.icache.replacements 280 # number of replacements -system.cpu1.icache.tagsinuse 65.593035 # Cycle average of tags in use -system.cpu1.icache.total_refs 172950 # Total number of references to valid blocks. +system.cpu1.icache.tagsinuse 70.021877 # Cycle average of tags in use +system.cpu1.icache.total_refs 166413 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 472.540984 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 454.680328 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 65.593035 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.128111 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.128111 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 172950 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 172950 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 172950 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 172950 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 172950 # number of overall hits -system.cpu1.icache.overall_hits::total 172950 # number of overall hits +system.cpu1.icache.occ_blocks::cpu1.inst 70.021877 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.136761 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.136761 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 166413 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 166413 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 166413 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 166413 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 166413 # number of overall hits +system.cpu1.icache.overall_hits::total 166413 # number of overall hits system.cpu1.icache.ReadReq_misses::cpu1.inst 366 # number of ReadReq misses system.cpu1.icache.ReadReq_misses::total 366 # number of ReadReq misses system.cpu1.icache.demand_misses::cpu1.inst 366 # number of demand (read+write) misses system.cpu1.icache.demand_misses::total 366 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 366 # number of overall misses system.cpu1.icache.overall_misses::total 366 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5373500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5373500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5373500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5373500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5373500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5373500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 173316 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 173316 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 173316 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 173316 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 173316 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 173316 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002112 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002112 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002112 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002112 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002112 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002112 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14681.693989 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14681.693989 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14681.693989 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14681.693989 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14681.693989 # average overall miss latency +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7565000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7565000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7565000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7565000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7565000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7565000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 166779 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 166779 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 166779 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 166779 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 166779 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 166779 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002195 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.002195 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002195 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.002195 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002195 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.002195 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20669.398907 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20669.398907 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20669.398907 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20669.398907 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20669.398907 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -359,94 +359,94 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 366 system.cpu1.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 366 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4641500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 4641500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4641500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 4641500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4641500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4641500 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002112 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.002112 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002112 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.002112 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 12681.693989 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12681.693989 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 12681.693989 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6833000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6833000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6833000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6833000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6833000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6833000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.002195 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.002195 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.002195 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.002195 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18669.398907 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18669.398907 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18669.398907 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 25.918058 # Cycle average of tags in use -system.cpu1.dcache.total_refs 19532 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.686467 # Cycle average of tags in use +system.cpu1.dcache.total_refs 29411 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 651.066667 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 980.366667 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 25.918058 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.050621 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.050621 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 39847 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 39847 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 8412 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 8412 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 16 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 16 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 48259 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 48259 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 48259 # number of overall hits -system.cpu1.dcache.overall_hits::total 48259 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 177 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 177 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 105 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 105 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 55 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 282 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 282 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 282 # number of overall misses -system.cpu1.dcache.overall_misses::total 282 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3316000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3316000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1875500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 1875500 # number of WriteReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 659500 # number of SwapReq miss cycles -system.cpu1.dcache.SwapReq_miss_latency::total 659500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 5191500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 5191500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 5191500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 5191500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40024 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 8517 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 8517 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 48541 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 48541 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 48541 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 48541 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004422 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004422 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012328 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.012328 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.774648 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.774648 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005810 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005810 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005810 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005810 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18734.463277 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18734.463277 # average ReadReq miss latency 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of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 65 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 54313 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 54313 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 54313 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 54313 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003744 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.003744 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.007881 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.007881 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.769231 # miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_miss_rate::total 0.769231 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.004769 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.004769 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.004769 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.004769 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19310.457516 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19310.457516 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18509.433962 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 18509.433962 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5480 # average SwapReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::total 5480 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18982.625483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18982.625483 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18982.625483 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -455,114 +455,114 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 177 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 177 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 105 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 105 # number of WriteReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 55 # number of SwapReq MSHR misses -system.cpu1.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 282 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 282 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 282 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 282 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2962000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2962000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1665500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1665500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 549500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.SwapReq_mshr_miss_latency::total 549500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4627500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4627500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4627500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4627500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.004422 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.004422 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012328 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012328 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.774648 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.774648 # mshr miss rate for SwapReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.005810 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.005810 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.005810 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16734.463277 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16734.463277 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15861.904762 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15861.904762 # average WriteReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 9990.909091 # average SwapReq mshr miss latency -system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 9990.909091 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16409.574468 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16409.574468 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 153 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 153 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 106 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2648500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2648500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1750000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1750000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 174000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 174000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4398500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4398500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4398500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4398500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003744 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003744 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.007881 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.007881 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.769231 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.769231 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.004769 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.004769 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.004769 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17310.457516 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 17310.457516 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 16509.433962 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 3480 # average SwapReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 3480 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.625483 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.625483 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 523246 # number of cpu cycles simulated +system.cpu2.numCycles 525941 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 160665 # Number of instructions committed -system.cpu2.committedOps 160665 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 113639 # Number of integer alu accesses +system.cpu2.committedInsts 169995 # Number of instructions committed +system.cpu2.committedOps 169995 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 110917 # Number of integer alu accesses system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu2.num_func_calls 637 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 27518 # number of instructions that are conditional controls -system.cpu2.num_int_insts 113639 # number of integer instructions +system.cpu2.num_conditional_control_insts 33551 # number of instructions that are conditional controls +system.cpu2.num_int_insts 110917 # number of integer instructions system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 306682 # number of times the integer registers were read -system.cpu2.num_int_register_writes 118721 # number of times the integer registers were written +system.cpu2.num_int_register_reads 271666 # number of times the integer registers were read +system.cpu2.num_int_register_writes 102578 # number of times the integer registers were written system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 62290 # number of memory refs -system.cpu2.num_load_insts 42488 # Number of load instructions -system.cpu2.num_store_insts 19802 # Number of store instructions -system.cpu2.num_idle_cycles 69015.869837 # Number of idle cycles -system.cpu2.num_busy_cycles 454230.130163 # Number of busy cycles -system.cpu2.not_idle_fraction 0.868101 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.131899 # Percentage of idle cycles -system.cpu2.icache.replacements 281 # number of replacements -system.cpu2.icache.tagsinuse 67.731754 # Cycle average of tags in use -system.cpu2.icache.total_refs 160331 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 367 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 436.869210 # Average number of references to valid blocks. +system.cpu2.num_mem_refs 53535 # number of memory refs +system.cpu2.num_load_insts 41127 # Number of load instructions +system.cpu2.num_store_insts 12408 # Number of store instructions +system.cpu2.num_idle_cycles 69585.001735 # Number of idle cycles +system.cpu2.num_busy_cycles 456355.998265 # Number of busy cycles +system.cpu2.not_idle_fraction 0.867694 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.132306 # Percentage of idle cycles +system.cpu2.icache.replacements 280 # number of replacements +system.cpu2.icache.tagsinuse 65.527396 # Cycle average of tags in use +system.cpu2.icache.total_refs 169662 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 366 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 463.557377 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 67.731754 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.132289 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.132289 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 160331 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 160331 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 160331 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 160331 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 160331 # number of overall hits -system.cpu2.icache.overall_hits::total 160331 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 367 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 367 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 367 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 367 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 367 # number of overall misses -system.cpu2.icache.overall_misses::total 367 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5321500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 5321500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 5321500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 5321500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 5321500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 5321500 # number of overall miss cycles -system.cpu2.icache.ReadReq_accesses::cpu2.inst 160698 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 160698 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 160698 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 160698 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 160698 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 160698 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002284 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002284 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002284 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002284 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002284 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002284 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14500 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 14500 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14500 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 14500 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14500 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 14500 # average overall miss latency +system.cpu2.icache.occ_blocks::cpu2.inst 65.527396 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.127983 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.127983 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 169662 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 169662 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 169662 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 169662 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 169662 # number of overall hits +system.cpu2.icache.overall_hits::total 169662 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 366 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 366 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 366 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 366 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 366 # number of overall misses +system.cpu2.icache.overall_misses::total 366 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 5281000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 5281000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 5281000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 5281000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 5281000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 5281000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 170028 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 170028 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 170028 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 170028 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 170028 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 170028 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002153 # miss rate for ReadReq accesses +system.cpu2.icache.ReadReq_miss_rate::total 0.002153 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002153 # miss rate for demand accesses +system.cpu2.icache.demand_miss_rate::total 0.002153 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002153 # miss rate for overall accesses +system.cpu2.icache.overall_miss_rate::total 0.002153 # miss rate for overall accesses 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accesses +system.cpu2.dcache.demand_mshr_miss_rate::total 0.004901 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004901 # mshr miss rate for overall accesses +system.cpu2.dcache.overall_mshr_miss_rate::total 0.004901 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 15544.585987 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 15544.585987 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16233.333333 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 16233.333333 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 3607.843137 # average SwapReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 3607.843137 # average SwapReq mshr miss latency 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alu accesses +system.cpu3.committedInsts 167814 # Number of instructions committed +system.cpu3.committedOps 167814 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 111369 # Number of integer alu accesses system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu3.num_func_calls 637 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 33752 # number of instructions that are conditional controls -system.cpu3.num_int_insts 108796 # number of integer instructions +system.cpu3.num_conditional_control_insts 32222 # number of instructions that are conditional controls +system.cpu3.num_int_insts 111369 # number of integer instructions system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 262371 # number of times the integer registers were read -system.cpu3.num_int_register_writes 98980 # number of times the integer registers were written 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Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 366 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 458.874317 # Average number of references to valid blocks. +system.cpu3.num_mem_refs 55316 # number of memory refs +system.cpu3.num_load_insts 41342 # Number of load instructions +system.cpu3.num_store_insts 13974 # Number of store instructions +system.cpu3.num_idle_cycles 69844.868934 # Number of idle cycles +system.cpu3.num_busy_cycles 456095.131066 # Number of busy cycles +system.cpu3.not_idle_fraction 0.867200 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.132800 # Percentage of idle cycles +system.cpu3.icache.replacements 281 # number of replacements +system.cpu3.icache.tagsinuse 67.672766 # Cycle average of tags in use +system.cpu3.icache.total_refs 167480 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 367 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 456.348774 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 70.063196 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.136842 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.136842 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 167948 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 167948 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 167948 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 167948 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 167948 # number of overall hits -system.cpu3.icache.overall_hits::total 167948 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 366 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 366 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 366 # number of overall misses -system.cpu3.icache.overall_misses::total 366 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 7343000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 7343000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 7343000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 7343000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 7343000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 7343000 # number of overall miss cycles -system.cpu3.icache.ReadReq_accesses::cpu3.inst 168314 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 168314 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 168314 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 168314 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 168314 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 168314 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002175 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002175 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002175 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002175 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002175 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002175 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 20062.841530 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 20062.841530 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 20062.841530 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 20062.841530 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 20062.841530 # average overall miss latency +system.cpu3.icache.occ_blocks::cpu3.inst 67.672766 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.132173 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.132173 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 167480 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 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cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 5162000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 5162000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 5162000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 5162000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 167847 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 167847 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 167847 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 167847 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 167847 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 167847 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002187 # miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_miss_rate::total 0.002187 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002187 # miss rate for demand accesses +system.cpu3.icache.demand_miss_rate::total 0.002187 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002187 # miss rate for overall accesses +system.cpu3.icache.overall_miss_rate::total 0.002187 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14065.395095 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 14065.395095 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 14065.395095 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14065.395095 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 14065.395095 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -789,100 +789,100 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs nan system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.icache.fast_writes 0 # number of fast writes performed system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 366 # number of ReadReq MSHR misses -system.cpu3.icache.ReadReq_mshr_misses::total 366 # number of ReadReq MSHR misses -system.cpu3.icache.demand_mshr_misses::cpu3.inst 366 # number of demand (read+write) MSHR misses -system.cpu3.icache.demand_mshr_misses::total 366 # number of demand (read+write) MSHR misses -system.cpu3.icache.overall_mshr_misses::cpu3.inst 366 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_misses::total 366 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 6611000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 6611000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 6611000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 6611000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 6611000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 6611000 # number of overall MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002175 # mshr miss rate for ReadReq accesses -system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_miss_rate::total 0.002175 # mshr miss rate for demand accesses -system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002175 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_miss_rate::total 0.002175 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 18062.841530 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 18062.841530 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 18062.841530 # average overall mshr miss latency +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 367 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 367 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 367 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 367 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 367 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4428000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4428000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4428000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4428000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4428000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for ReadReq accesses +system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.002187 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for demand accesses +system.cpu3.icache.demand_mshr_miss_rate::total 0.002187 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.002187 # mshr miss rate for overall accesses +system.cpu3.icache.overall_mshr_miss_rate::total 0.002187 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 12065.395095 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12065.395095 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 12065.395095 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 27.713697 # Cycle average of tags in use -system.cpu3.dcache.total_refs 24536 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 26.814972 # Cycle average of tags in use +system.cpu3.dcache.total_refs 30179 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 29 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 846.068966 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1040.655172 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 27.713697 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.054128 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.054128 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 39885 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 39885 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 10974 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 10974 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits 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(read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004294 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.004294 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.009388 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.009388 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.797101 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.797101 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005397 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.005397 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005397 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.005397 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 19796.511628 # average ReadReq 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WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 79 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 55228 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 55228 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 55228 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 55228 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004137 # miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_miss_rate::total 0.004137 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007630 # miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_miss_rate::total 0.007630 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.873418 # miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_miss_rate::total 0.873418 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.005016 # miss rate for demand accesses +system.cpu3.dcache.demand_miss_rate::total 0.005016 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.005016 # miss rate for overall accesses +system.cpu3.dcache.overall_miss_rate::total 0.005016 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16394.736842 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 16394.736842 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20768.867925 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 20768.867925 # average WriteReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 5333.333333 # average SwapReq miss latency +system.cpu3.dcache.SwapReq_avg_miss_latency::total 5333.333333 # average SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 18068.592058 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 18068.592058 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 18068.592058 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -891,225 +891,225 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.dcache.fast_writes 0 # number of fast writes performed system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 172 # number of ReadReq MSHR misses -system.cpu3.dcache.ReadReq_mshr_misses::total 172 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 104 # number of WriteReq MSHR misses -system.cpu3.dcache.WriteReq_mshr_misses::total 104 # number of WriteReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 55 # number of SwapReq MSHR misses -system.cpu3.dcache.SwapReq_mshr_misses::total 55 # number of SwapReq MSHR misses -system.cpu3.dcache.demand_mshr_misses::cpu3.data 276 # number of demand (read+write) MSHR misses -system.cpu3.dcache.demand_mshr_misses::total 276 # number of demand (read+write) MSHR misses -system.cpu3.dcache.overall_mshr_misses::cpu3.data 276 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_misses::total 276 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 3061000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 3061000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1763500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1763500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 543500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.SwapReq_mshr_miss_latency::total 543500 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 4824500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 4824500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 4824500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 4824500 # number of overall MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004294 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004294 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.009388 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.009388 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.797101 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.797101 # mshr miss rate for SwapReq accesses -system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_miss_rate::total 0.005397 # mshr miss rate for demand accesses -system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005397 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_miss_rate::total 0.005397 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 17796.511628 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 17796.511628 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16956.730769 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 16956.730769 # average WriteReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 9881.818182 # average SwapReq mshr miss latency -system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 9881.818182 # average SwapReq mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 17480.072464 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency::total 17480.072464 # average overall mshr miss latency +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 171 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 171 # number of ReadReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses +system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 69 # number of SwapReq MSHR misses +system.cpu3.dcache.SwapReq_mshr_misses::total 69 # number of SwapReq MSHR misses +system.cpu3.dcache.demand_mshr_misses::cpu3.data 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.demand_mshr_misses::total 277 # number of demand (read+write) MSHR misses +system.cpu3.dcache.overall_mshr_misses::cpu3.data 277 # number of overall MSHR misses +system.cpu3.dcache.overall_mshr_misses::total 277 # number of overall MSHR misses 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overall MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004137 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004137 # mshr miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.007630 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.007630 # mshr miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.873418 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.873418 # mshr miss rate for SwapReq accesses +system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for demand accesses +system.cpu3.dcache.demand_mshr_miss_rate::total 0.005016 # mshr miss rate for demand accesses +system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.005016 # mshr miss rate for overall accesses +system.cpu3.dcache.overall_mshr_miss_rate::total 0.005016 # mshr miss rate for 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 82500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 611500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 40000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 609500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 22913000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.929577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.090909 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.181818 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.636364 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.727273 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.090909 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.090909 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.257485 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.977011 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.975610 # mshr miss rate for UpgradeReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses @@ -1286,59 +1283,59 @@ system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.315673 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.610278 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.019126 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.600000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.024523 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.640000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.inst 0.144809 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3.data 0.846154 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.180328 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.884615 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.005464 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.600000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.600000 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.315673 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 41250 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.930233 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40018.604651 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40160.392857 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40138.611111 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40105.052632 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40105.670588 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40357.142857 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40464.285714 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40633.333333 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40147.887324 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40099.800000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40187.187500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40112.287500 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40040.404040 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40821.428571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40678.571429 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40176.056338 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40022.807018 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40357.142857 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40406.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40019.298246 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40024.242424 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 41250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40766.666667 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40431.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40052.447552 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40633.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40057.692308 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini index 120840f6d..1f567a1b9 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini @@ -16,7 +16,7 @@ kernel= load_addr_mask=1099511627775 mem_mode=timing mem_ranges= -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= @@ -415,6 +415,7 @@ type=CoherentBus block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=16 master=system.physmem.port @@ -438,6 +439,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=16 master=system.l2c.cpu_side diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr index ac8f30c3e..014cde607 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simerr @@ -1,74 +1,74 @@ -system.cpu4: completed 10000 read, 5213 write accesses @76807500 -system.cpu7: completed 10000 read, 5302 write accesses @79251000 -system.cpu3: completed 10000 read, 5351 write accesses @81062000 -system.cpu5: completed 10000 read, 5541 write accesses @82066500 -system.cpu1: completed 10000 read, 5479 write accesses @82140500 -system.cpu2: completed 10000 read, 5270 write accesses @82209500 -system.cpu6: completed 10000 read, 5352 write accesses @82224000 -system.cpu0: completed 10000 read, 5437 write accesses @83502000 -system.cpu4: completed 20000 read, 10638 write accesses @152852500 -system.cpu7: completed 20000 read, 10671 write accesses @153245500 -system.cpu5: completed 20000 read, 10802 write accesses @155921500 -system.cpu1: completed 20000 read, 10780 write accesses @157898500 -system.cpu3: completed 20000 read, 10762 write accesses @158207000 -system.cpu2: completed 20000 read, 10562 write accesses @158441500 -system.cpu6: completed 20000 read, 10817 write accesses @160812000 -system.cpu0: completed 20000 read, 10942 write accesses @162138000 -system.cpu4: completed 30000 read, 15885 write accesses @226882500 -system.cpu7: completed 30000 read, 16162 write accesses @230488000 -system.cpu1: completed 30000 read, 15996 write accesses @231220000 -system.cpu5: completed 30000 read, 16227 write accesses @232272500 -system.cpu3: completed 30000 read, 16181 write accesses @234012000 -system.cpu6: completed 30000 read, 16285 write accesses @236458500 -system.cpu2: completed 30000 read, 16117 write accesses @236552000 -system.cpu0: completed 30000 read, 16426 write accesses @240306500 -system.cpu4: completed 40000 read, 21151 write accesses @301825500 -system.cpu7: completed 40000 read, 21649 write accesses @305825500 -system.cpu1: completed 40000 read, 21293 write accesses @308437500 -system.cpu3: completed 40000 read, 21436 write accesses @308497500 -system.cpu5: completed 40000 read, 21614 write accesses @310554000 -system.cpu2: completed 40000 read, 21323 write accesses @312243500 -system.cpu6: completed 40000 read, 21541 write accesses @312536000 -system.cpu0: completed 40000 read, 21919 write accesses @320331000 -system.cpu4: completed 50000 read, 26446 write accesses @376676500 -system.cpu7: completed 50000 read, 26971 write accesses @382643500 -system.cpu1: completed 50000 read, 26742 write accesses @382692500 -system.cpu3: completed 50000 read, 26868 write accesses @383729000 -system.cpu5: completed 50000 read, 26982 write accesses @388892000 -system.cpu2: completed 50000 read, 26690 write accesses @389746500 -system.cpu6: completed 50000 read, 26890 write accesses @390639500 -system.cpu0: completed 50000 read, 27239 write accesses @394395001 -system.cpu4: completed 60000 read, 31859 write accesses @454814000 -system.cpu3: completed 60000 read, 32157 write accesses @455574000 -system.cpu1: completed 60000 read, 32039 write accesses @458833000 -system.cpu7: completed 60000 read, 32494 write accesses @460248000 -system.cpu2: completed 60000 read, 32094 write accesses @465749500 -system.cpu5: completed 60000 read, 32378 write accesses @466634000 -system.cpu6: completed 60000 read, 32333 write accesses @468161500 -system.cpu0: completed 60000 read, 32569 write accesses @469644500 -system.cpu3: completed 70000 read, 37524 write accesses @531095000 -system.cpu4: completed 70000 read, 37387 write accesses @531724000 -system.cpu1: completed 70000 read, 37455 write accesses @534864500 -system.cpu2: completed 70000 read, 37386 write accesses @539742500 -system.cpu7: completed 70000 read, 38025 write accesses @540171500 -system.cpu5: completed 70000 read, 37779 write accesses @540661000 -system.cpu0: completed 70000 read, 37912 write accesses @543002000 -system.cpu6: completed 70000 read, 37876 write accesses @544926000 -system.cpu4: completed 80000 read, 42765 write accesses @607648000 -system.cpu3: completed 80000 read, 42947 write accesses @608627500 -system.cpu1: completed 80000 read, 42804 write accesses @612176500 -system.cpu5: completed 80000 read, 43215 write accesses @614679500 -system.cpu2: completed 80000 read, 42837 write accesses @616130500 -system.cpu7: completed 80000 read, 43372 write accesses @618251000 -system.cpu0: completed 80000 read, 43388 write accesses @620992000 -system.cpu6: completed 80000 read, 43420 write accesses @622851000 -system.cpu4: completed 90000 read, 48066 write accesses @681361000 -system.cpu3: completed 90000 read, 48251 write accesses @683201500 -system.cpu1: completed 90000 read, 48377 write accesses @690035500 -system.cpu5: completed 90000 read, 48546 write accesses @692142000 -system.cpu2: completed 90000 read, 48240 write accesses @693946000 -system.cpu7: completed 90000 read, 48816 write accesses @696757000 -system.cpu0: completed 90000 read, 48758 write accesses @697163500 -system.cpu6: completed 90000 read, 48649 write accesses @698059000 -system.cpu4: completed 100000 read, 53418 write accesses @758619000 +system.cpu6: completed 10000 read, 5435 write accesses @79021500 +system.cpu0: completed 10000 read, 5363 write accesses @79194500 +system.cpu7: completed 10000 read, 5392 write accesses @79770500 +system.cpu2: completed 10000 read, 5375 write accesses @80689500 +system.cpu1: completed 10000 read, 5373 write accesses @81623500 +system.cpu4: completed 10000 read, 5458 write accesses @81916000 +system.cpu5: completed 10000 read, 5507 write accesses @81975000 +system.cpu3: completed 10000 read, 5421 write accesses @82381000 +system.cpu2: completed 20000 read, 10678 write accesses @153864500 +system.cpu0: completed 20000 read, 10854 write accesses @154789000 +system.cpu7: completed 20000 read, 10817 write accesses @154953500 +system.cpu1: completed 20000 read, 10781 write accesses @155855500 +system.cpu3: completed 20000 read, 10799 write accesses @157033000 +system.cpu4: completed 20000 read, 10854 write accesses @157158000 +system.cpu6: completed 20000 read, 10878 write accesses @157795000 +system.cpu5: completed 20000 read, 10963 write accesses @159866500 +system.cpu0: completed 30000 read, 16180 write accesses @228385000 +system.cpu2: completed 30000 read, 15995 write accesses @229109500 +system.cpu7: completed 30000 read, 16232 write accesses @231170000 +system.cpu1: completed 30000 read, 16165 write accesses @231658500 +system.cpu4: completed 30000 read, 16252 write accesses @232783000 +system.cpu6: completed 30000 read, 16228 write accesses @233712000 +system.cpu3: completed 30000 read, 16226 write accesses @236523000 +system.cpu5: completed 30000 read, 16456 write accesses @239602000 +system.cpu0: completed 40000 read, 21598 write accesses @305262000 +system.cpu2: completed 40000 read, 21332 write accesses @306571000 +system.cpu1: completed 40000 read, 21599 write accesses @307778500 +system.cpu4: completed 40000 read, 21599 write accesses @307971000 +system.cpu7: completed 40000 read, 21551 write accesses @308441000 +system.cpu6: completed 40000 read, 21597 write accesses @310397000 +system.cpu3: completed 40000 read, 21704 write accesses @312891000 +system.cpu5: completed 40000 read, 21914 write accesses @315565000 +system.cpu4: completed 50000 read, 26891 write accesses @381925000 +system.cpu0: completed 50000 read, 26990 write accesses @382095500 +system.cpu2: completed 50000 read, 26686 write accesses @382917500 +system.cpu1: completed 50000 read, 26983 write accesses @384289000 +system.cpu6: completed 50000 read, 27066 write accesses @384539000 +system.cpu7: completed 50000 read, 26943 write accesses @385136500 +system.cpu3: completed 50000 read, 27037 write accesses @389922000 +system.cpu5: completed 50000 read, 27423 write accesses @393691500 +system.cpu6: completed 60000 read, 32353 write accesses @457634500 +system.cpu4: completed 60000 read, 32228 write accesses @457992000 +system.cpu1: completed 60000 read, 32457 write accesses @460714000 +system.cpu2: completed 60000 read, 32178 write accesses @461196500 +system.cpu0: completed 60000 read, 32542 write accesses @461690000 +system.cpu7: completed 60000 read, 32302 write accesses @462388500 +system.cpu3: completed 60000 read, 32488 write accesses @466103000 +system.cpu5: completed 60000 read, 32744 write accesses @469778000 +system.cpu6: completed 70000 read, 37747 write accesses @533745000 +system.cpu2: completed 70000 read, 37532 write accesses @535320500 +system.cpu4: completed 70000 read, 37773 write accesses @535591500 +system.cpu7: completed 70000 read, 37639 write accesses @538124500 +system.cpu0: completed 70000 read, 37909 write accesses @538334500 +system.cpu1: completed 70000 read, 37921 write accesses @541231500 +system.cpu3: completed 70000 read, 37871 write accesses @542226500 +system.cpu5: completed 70000 read, 38229 write accesses @548322500 +system.cpu4: completed 80000 read, 42983 write accesses @610769500 +system.cpu6: completed 80000 read, 43020 write accesses @610776000 +system.cpu2: completed 80000 read, 42982 write accesses @611661000 +system.cpu0: completed 80000 read, 43374 write accesses @615085500 +system.cpu1: completed 80000 read, 43250 write accesses @615627500 +system.cpu7: completed 80000 read, 43033 write accesses @615746000 +system.cpu3: completed 80000 read, 43154 write accesses @619760000 +system.cpu5: completed 80000 read, 43738 write accesses @625688001 +system.cpu6: completed 90000 read, 48339 write accesses @685422000 +system.cpu2: completed 90000 read, 48272 write accesses @687608500 +system.cpu4: completed 90000 read, 48507 write accesses @688615500 +system.cpu7: completed 90000 read, 48310 write accesses @688789000 +system.cpu0: completed 90000 read, 48650 write accesses @689991000 +system.cpu1: completed 90000 read, 48621 write accesses @693117500 +system.cpu3: completed 90000 read, 48493 write accesses @697608000 +system.cpu5: completed 90000 read, 49008 write accesses @701381500 +system.cpu6: completed 100000 read, 53851 write accesses @761435500 hack: be nice to actually delete the event here diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout index 86075abc3..077a1416b 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout @@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 13:29:14 -gem5 started Jan 23 2013 13:46:00 +gem5 compiled Mar 26 2013 14:38:52 +gem5 started Mar 26 2013 14:39:12 gem5 executing on ribera.cs.wisc.edu command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 758619000 because maximum number of loads reached +Exiting @ tick 761435500 because maximum number of loads reached diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 08d964bc4..5ed14465a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,633 +1,633 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000758 # Number of seconds simulated -sim_ticks 758227000 # Number of ticks simulated -final_tick 758227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000761 # Number of seconds simulated +sim_ticks 761435500 # Number of ticks simulated +final_tick 761435500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 200763174 # Simulator tick rate (ticks/s) -host_mem_usage 353776 # Number of bytes of host memory used -host_seconds 3.78 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 94296 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 93084 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 90684 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 91125 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 90329 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 98961 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 91564 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 94442 # Number of bytes read from this memory -system.physmem.bytes_read::total 744485 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 495744 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5338 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5288 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5371 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5302 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5445 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5231 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5370 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5430 # Number of bytes written to this memory -system.physmem.bytes_written::total 538519 # Number of bytes written to this memory -system.physmem.num_reads::cpu0 11262 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 10932 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11115 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 11075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11202 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11345 # Number of read requests responded to by this memory -system.physmem.num_reads::total 89033 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7746 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5338 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5288 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5371 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5302 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5445 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5231 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5370 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5430 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50521 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 124363812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 122765346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 119600067 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 120181687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 119131869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 130516323 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 120760669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 124556366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 981876140 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 653820030 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7040108 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6974165 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7083631 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 6992629 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7181227 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 6898989 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7082312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 7161444 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 710234534 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 653820030 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 131403920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 129739511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 126683698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 127174316 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 126313096 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 137415312 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 127842981 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 131717810 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1692110674 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15709 # number of replacements -system.l2c.tagsinuse 802.621152 # Cycle average of tags in use -system.l2c.total_refs 152986 # Total number of references to valid blocks. -system.l2c.sampled_refs 16508 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.267386 # Average number of references to valid blocks. +host_tick_rate 112752764 # Simulator tick rate (ticks/s) +host_mem_usage 399024 # Number of bytes of host memory used +host_seconds 6.75 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 92287 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 88521 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 93126 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 92216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 93858 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 91205 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 94911 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 89917 # Number of bytes read from this memory +system.physmem.bytes_read::total 736041 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 486336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5427 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5222 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5377 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5288 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5289 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5451 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5508 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5340 # Number of bytes written to this memory +system.physmem.bytes_written::total 529238 # Number of bytes written to this memory +system.physmem.num_reads::cpu0 11206 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1 11157 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11261 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11265 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11258 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11247 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11104 # Number of read requests responded to by this memory +system.physmem.num_reads::total 89661 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7599 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5427 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5222 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5377 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5288 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5289 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5451 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5508 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5340 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50501 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 121201336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 116255415 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 122303202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 121108091 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 123264544 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 119780336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 124647459 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 118088794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 966649178 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 638709385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7127327 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6858099 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 7061662 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 6944777 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6946091 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7158847 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7233705 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7013069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 695052962 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 638709385 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 128328663 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 123113514 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 129364864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 128052869 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 130210635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 126939183 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 131881164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 125101864 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1661702140 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15611 # number of replacements +system.l2c.tagsinuse 803.524746 # Cycle average of tags in use +system.l2c.total_refs 152738 # Total number of references to valid blocks. +system.l2c.sampled_refs 16409 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.308185 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 738.344301 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.856749 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.750709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 7.581062 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 8.075895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.623690 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 8.411297 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 8.326520 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 8.650930 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.721039 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007569 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.007403 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007887 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007445 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.008214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.008131 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.008448 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.783810 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 11060 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10905 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10917 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10908 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 11025 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10769 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 11003 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 11044 # number of ReadReq hits -system.l2c.ReadReq_hits::total 87631 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 77283 # number of Writeback hits -system.l2c.Writeback_hits::total 77283 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 381 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 372 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 389 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 412 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 335 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 375 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 371 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2982 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2017 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 2086 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 1996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2001 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 2062 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 1995 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2076 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2009 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16242 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 13077 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12991 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12913 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12909 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 13087 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12764 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 13079 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 13053 # number of demand (read+write) hits -system.l2c.demand_hits::total 103873 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 13077 # number of overall hits -system.l2c.overall_hits::cpu1 12991 # number of overall hits -system.l2c.overall_hits::cpu2 12913 # number of overall hits -system.l2c.overall_hits::cpu3 12909 # number of overall hits -system.l2c.overall_hits::cpu4 13087 # number of overall hits -system.l2c.overall_hits::cpu5 12764 # number of overall hits -system.l2c.overall_hits::cpu6 13079 # number of overall hits -system.l2c.overall_hits::cpu7 13053 # number of overall hits -system.l2c.overall_hits::total 103873 # number of overall hits -system.l2c.ReadReq_misses::cpu0 831 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 825 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 807 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 851 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 911 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 848 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 890 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6791 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1902 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1837 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1834 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1940 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1893 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1907 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1914 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 15167 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4262 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4280 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4373 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4275 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4319 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4433 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4324 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 34643 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5093 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 5105 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5180 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 5205 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5281 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5214 # number of demand (read+write) misses -system.l2c.demand_misses::total 41434 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5093 # number of overall misses -system.l2c.overall_misses::cpu1 5105 # number of overall misses -system.l2c.overall_misses::cpu2 5180 # number of overall misses -system.l2c.overall_misses::cpu3 5126 # number of overall misses -system.l2c.overall_misses::cpu4 5205 # number of overall misses -system.l2c.overall_misses::cpu5 5230 # number of overall misses -system.l2c.overall_misses::cpu6 5281 # number of overall misses -system.l2c.overall_misses::cpu7 5214 # number of overall misses -system.l2c.overall_misses::total 41434 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 50386435 # 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number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11680 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11851 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11934 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 94422 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 77283 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 77283 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2321 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2274 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2226 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2246 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2275 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2240 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2282 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2285 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18149 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6279 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6366 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6369 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6439 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6314 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6509 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6333 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50885 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 18170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 18096 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18093 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 18035 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 18292 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17994 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 18360 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18267 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 145307 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 18170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 18096 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18093 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 18035 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 18292 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17994 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 18360 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18267 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 145307 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.069885 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.070332 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.068833 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.072370 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.069856 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.077997 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.071555 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.074577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.071922 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.835847 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.836412 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.825247 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.816563 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.852747 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.845089 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.835670 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.837637 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.835693 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.678771 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.672322 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.686607 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.681166 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.679764 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.684035 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.681057 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.682773 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.680810 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.280297 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.282107 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.286299 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.284225 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.284551 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.290652 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.287636 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.285433 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.285148 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.280297 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.282107 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.286299 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.284225 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.284551 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.290652 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.287636 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.285433 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.285148 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 60633.495788 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 60106.585455 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 60578.608426 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 59535.757932 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 61088.085749 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 59778.755214 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 60649.102594 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 59660.591011 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 60240.609778 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28790.936082 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28313.562566 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28965.924878 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 27764.952563 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28509.746392 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 29535.869519 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28578.868380 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 29125.080982 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28700.715699 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 53922.021821 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.919159 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 53940.341642 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 53965.756491 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 53790.637423 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 54003.155823 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 53845.271374 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 53882.317299 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53897.337759 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 55017.100334 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 54845.944564 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 54974.527220 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 54890.468006 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 54951.499520 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 55009.192352 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 54937.800985 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 54868.635596 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 54936.995052 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 55017.100334 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 54845.944564 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 54974.527220 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 54890.468006 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 54951.499520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 55009.192352 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 54937.800985 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 54868.635596 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 54936.995052 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 12946 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 740.398086 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.878873 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.659983 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 8.123766 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.474129 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 8.226019 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.053219 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.543884 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.166787 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.723045 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007694 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007480 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007933 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007299 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.008033 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.007864 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008344 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.006999 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784692 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10900 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10939 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10998 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10816 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 11039 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10812 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 11089 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 11073 # number of ReadReq hits +system.l2c.ReadReq_hits::total 87666 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 77271 # number of Writeback hits +system.l2c.Writeback_hits::total 77271 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 347 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 357 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 381 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 350 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 346 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 406 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2895 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 1978 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2136 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 2005 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 1996 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 1979 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2046 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 2087 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2088 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16315 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12878 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 13075 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 13003 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12812 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 13018 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 12858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 13176 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 13161 # number of demand (read+write) hits +system.l2c.demand_hits::total 103981 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12878 # number of overall hits +system.l2c.overall_hits::cpu1 13075 # number of overall hits +system.l2c.overall_hits::cpu2 13003 # number of overall hits +system.l2c.overall_hits::cpu3 12812 # number of overall hits +system.l2c.overall_hits::cpu4 13018 # number of overall hits +system.l2c.overall_hits::cpu5 12858 # number of overall hits +system.l2c.overall_hits::cpu6 13176 # number of overall hits +system.l2c.overall_hits::cpu7 13161 # number of overall hits +system.l2c.overall_hits::total 103981 # number of overall hits +system.l2c.ReadReq_misses::cpu0 842 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 806 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 858 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 816 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 872 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 849 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 881 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 820 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6744 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1862 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1924 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1971 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1858 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1932 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1882 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1937 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1981 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15347 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4273 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4353 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4268 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4257 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4400 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4320 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4282 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4210 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34363 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5115 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5159 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5126 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5073 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5272 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5169 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses +system.l2c.demand_misses::total 41107 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5115 # number of overall misses +system.l2c.overall_misses::cpu1 5159 # number of overall misses +system.l2c.overall_misses::cpu2 5126 # number of overall misses +system.l2c.overall_misses::cpu3 5073 # number of overall misses +system.l2c.overall_misses::cpu4 5272 # number of overall misses +system.l2c.overall_misses::cpu5 5169 # number of overall misses +system.l2c.overall_misses::cpu6 5163 # number of overall misses +system.l2c.overall_misses::cpu7 5030 # number of overall misses +system.l2c.overall_misses::total 41107 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50835946 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 48414928 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 51478420 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 48581936 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 52640430 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 50070934 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 52891428 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 49101459 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 404015481 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54966909 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 55263407 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 54925394 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53857894 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 54541411 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 53722422 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 55425398 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 56851911 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 439554746 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 229863626 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234328104 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 229945624 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 229282087 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 236284615 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 232406616 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 230024647 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 226955142 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1849090461 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 280699572 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 282743032 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 281424044 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 277864023 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 288925045 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 282477550 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 282916075 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 276056601 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2253105942 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 280699572 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 282743032 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 281424044 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 277864023 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 288925045 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 282477550 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 282916075 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 276056601 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2253105942 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11742 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11856 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11632 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11911 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11661 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11970 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11893 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 94410 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 77271 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 77271 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2209 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2281 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2352 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2208 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2286 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2228 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2343 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2335 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18242 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6251 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6489 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6273 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6253 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6379 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6366 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6369 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6298 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50678 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17993 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18234 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 18129 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 17885 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18290 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18027 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 18339 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 18191 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 145088 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17993 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18234 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 18129 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 17885 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18290 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18027 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 18339 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 18191 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 145088 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.071708 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.068625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.072368 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.070151 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.073210 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.072807 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.073601 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.068948 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.071433 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.842915 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.843490 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.838010 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.841486 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.845144 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.844704 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.826718 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.848394 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.841300 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.683571 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.670828 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.680376 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.680793 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.689763 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.678605 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.672319 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.668466 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.678065 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.284277 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.282933 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.282751 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283646 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.288245 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.286737 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.281531 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.276510 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.283325 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.284277 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.282933 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.282751 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283646 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.288245 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.286737 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.281531 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.276510 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.283325 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 60375.232779 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 60068.148883 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 59998.158508 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59536.686275 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 60367.465596 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 58976.365135 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 60035.673099 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59879.828049 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59907.396352 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 29520.359291 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 28723.184511 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 27866.765094 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 28987.025834 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28230.543996 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28545.388948 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28614.041301 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 28698.592125 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28641.085945 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53794.436227 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53831.404549 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53876.669166 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.015739 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53701.048864 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53797.827778 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53718.974078 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53908.584798 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53810.507261 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54877.726686 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54805.782516 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54901.296137 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54773.117090 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54803.688354 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54648.394274 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54796.838079 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54882.028032 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54810.760746 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54877.726686 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54805.782516 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54901.296137 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54773.117090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54803.688354 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54648.394274 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54796.838079 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54882.028032 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54810.760746 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 11382 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 1808 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1550 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 7.160398 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.343226 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7746 # number of writebacks -system.l2c.writebacks::total 7746 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 3 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 2 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu1 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7599 # number of writebacks +system.l2c.writebacks::total 7599 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 8 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 3 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu2 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu5 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu2 4 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 5 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 7 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu5 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 29 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 3 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 3 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 70 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 828 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 815 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 804 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 844 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 824 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 909 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 843 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 883 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6750 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1940 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1901 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1837 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1834 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1940 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1892 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1907 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1914 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 15165 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4276 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4373 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4271 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4372 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4316 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4430 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4321 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 34614 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5083 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 5091 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5177 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5115 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 5196 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5225 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5273 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5204 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 41364 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5083 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 5091 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5177 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5115 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 5196 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5225 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5273 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5204 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 41364 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 40211435 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 39357435 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 39064937 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 40158430 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 40512435 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 43385946 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 40969439 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 42146427 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 325806484 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 79643349 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78062835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 75255324 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 75287345 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79635834 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77713835 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 78284820 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 78593341 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 622476683 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 178045657 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 178454114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 182867114 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 178794609 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 182240620 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 180819630 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 184924089 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 180516140 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1446661973 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 218257092 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 217811549 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 221932051 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 218953039 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 222753055 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 224205576 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 225893528 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 222662567 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1772468457 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 218257092 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 217811549 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 221932051 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 218953039 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 222753055 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 224205576 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 225893528 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 222662567 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1772468457 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 410453631 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 397457157 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406979111 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 406829637 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 405432120 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 405171118 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 400882109 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 414057617 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3247262500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 226073488 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 225167477 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 228704981 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 225137481 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 230851979 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 222187990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 228117990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 230091986 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1816333372 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 636527119 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 622624634 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 635684092 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 631967118 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 636284099 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 627359108 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 629000099 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 644149603 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5063595872 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.069632 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.069480 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068577 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071775 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.069518 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.077825 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.071133 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073990 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.071488 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.835847 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.835972 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.825247 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.816563 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.852747 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844643 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835670 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837637 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.835583 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677656 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.671693 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.686607 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680529 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678987 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.683560 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.680596 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.682299 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.680240 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.284666 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.279747 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.281333 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.286133 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.283615 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.284059 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.290375 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.287200 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.284885 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.284666 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48564.535024 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48291.331288 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48588.230100 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47581.078199 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 49165.576456 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47729.313531 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 48599.571767 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47730.947905 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 48267.627259 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41053.272680 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41064.089953 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40966.425694 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41050.896947 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41049.398969 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41074.965645 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41051.295228 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41062.351620 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41046.929311 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41843.867685 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41733.890084 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41817.313972 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41862.469913 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41683.581885 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41895.187674 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41743.586682 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41776.473039 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 41794.128763 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 42938.637025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 42783.647417 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 42868.852811 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 42806.068231 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 42870.102964 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 42910.158086 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 42839.660156 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 42786.811491 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42850.509066 # average overall mshr miss latency +system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 25 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 11 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 9 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu7 3 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 76 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 11 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 9 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu7 3 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 76 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 833 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 800 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 853 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 808 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 867 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 841 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 874 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 817 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6693 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1862 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1924 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1858 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1932 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1881 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1937 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1981 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 15345 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4271 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4350 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4264 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4253 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4393 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4317 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4280 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4210 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34338 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5104 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5117 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5061 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5260 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5158 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5154 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5027 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 41031 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5104 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5117 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5061 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5260 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5158 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5154 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5027 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 41031 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 40464447 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 38550929 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 41027920 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 38515937 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 41941930 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 39649436 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 41931428 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 39012959 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 321094986 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 76446342 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 78808343 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 80788312 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 76138817 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 79209815 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77051840 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 79478835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 81341333 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 629263637 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 178032127 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181508104 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 178129124 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 177575588 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 182792115 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 179941616 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 178029147 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 175952642 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1431960463 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 218496574 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 220059033 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 219157044 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 216091525 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 224734045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 219591052 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 219960575 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 214965601 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1753055449 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 218496574 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 220059033 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 219157044 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 216091525 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 224734045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 219591052 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 219960575 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 214965601 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1753055449 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 408840154 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 409932127 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 406697168 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412407125 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 410618544 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 412439590 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 408986543 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 406399119 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3276320370 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 229120490 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 221422480 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 227576980 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 223709488 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225472990 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 232298486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 233243987 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 227452978 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1820297879 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 637960644 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 631354607 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 634274148 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 636116613 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 636091534 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 644738076 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 642230530 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 633852097 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5096618249 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070942 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.068114 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.071947 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069464 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.072790 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.072121 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073016 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.068696 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.070893 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.842915 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.843490 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.837585 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.841486 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.845144 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.844255 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.826718 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.848394 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.841191 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.683251 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.670365 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679739 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.680154 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.688666 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.678134 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.672005 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.668466 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.677572 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.282801 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.283666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.282439 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.282255 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282975 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.287589 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.286126 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.281040 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.276345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.282801 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 48576.767107 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48188.661250 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 48098.382181 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 47668.238861 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 48375.928489 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 47145.583829 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 47976.462243 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47751.479804 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47974.747647 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.037594 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40960.677235 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41009.295431 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40978.911195 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40998.869048 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40963.232323 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41031.923077 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41060.743564 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41007.731313 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41683.944509 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41726.000920 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41775.122889 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41753.018575 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41609.860005 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41682.097753 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41595.595093 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41793.976722 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41701.918079 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42808.889890 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42729.909320 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42829.205394 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42697.396760 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42725.103612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42572.906553 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42677.643578 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42762.204297 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42725.145597 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -656,114 +656,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98877 # number of read accesses completed -system.cpu0.num_writes 53303 # number of write accesses completed +system.cpu0.num_reads 99397 # number of read accesses completed +system.cpu0.num_writes 53728 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22594 # number of replacements -system.cpu0.l1c.tagsinuse 395.326045 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13097 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 23010 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.569187 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 22406 # number of replacements +system.cpu0.l1c.tagsinuse 396.107523 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13328 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 22796 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.584664 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 395.326045 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.772121 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.772121 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8525 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8525 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9567 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9567 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9567 # number of overall hits -system.cpu0.l1c.overall_hits::total 9567 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 36170 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 36170 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 23033 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 59203 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 59203 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 59203 # number of overall misses -system.cpu0.l1c.overall_misses::total 59203 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 1338428684 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 1338428684 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 1081120140 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 1081120140 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 2419548824 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 2419548824 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 2419548824 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 2419548824 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44695 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44695 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 24075 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 24075 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68770 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68770 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68770 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68770 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.809263 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.809263 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956719 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.956719 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.860884 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.860884 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.860884 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.860884 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37003.834227 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 37003.834227 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 46937.877827 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 46937.877827 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 40868.686114 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 40868.686114 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 40868.686114 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 40868.686114 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1431079 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 396.107523 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.773648 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.773648 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8751 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8751 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1114 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1114 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9865 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9865 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9865 # number of overall hits +system.cpu0.l1c.overall_hits::total 9865 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 36190 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 36190 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 23005 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 23005 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 59195 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 59195 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 59195 # number of overall misses +system.cpu0.l1c.overall_misses::total 59195 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1343389412 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1343389412 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1089518245 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1089518245 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2432907657 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2432907657 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2432907657 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2432907657 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 44941 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 24119 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 24119 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 69060 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 69060 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 69060 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 69060 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.953812 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.953812 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.857153 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.857153 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.857153 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.857153 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37120.459022 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37120.459022 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47360.062812 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 47360.062812 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 41099.884399 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 41099.884399 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 41099.884399 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 41099.884399 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1437100 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 67309 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 67352 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.261332 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.337154 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9829 # number of writebacks -system.cpu0.l1c.writebacks::total 9829 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36170 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 36170 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23033 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 59203 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 59203 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 59203 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 59203 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1266094684 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1266094684 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1035054140 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1035054140 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2301148824 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 2301148824 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2301148824 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 2301148824 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 713940998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 713940998 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 425679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 425679500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1139620498 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1139620498 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.809263 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.809263 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956719 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956719 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.860884 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.860884 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.860884 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35004.000111 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35004.000111 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 44937.877827 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 44937.877827 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 38868.787460 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 38868.787460 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks +system.cpu0.l1c.writebacks::total 9722 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 36190 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 36190 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 23005 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 23005 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 59195 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 59195 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 59195 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 59195 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1271011412 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1271011412 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1043514245 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1043514245 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2314525657 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2314525657 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2314525657 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2314525657 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 712928581 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 712928581 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 437133462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 437133462 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1150062043 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1150062043 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.953812 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.953812 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.857153 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.857153 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.857153 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35120.514286 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35120.514286 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45360.323625 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45360.323625 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39100.019546 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39100.019546 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -771,114 +771,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 98330 # number of read accesses completed -system.cpu1.num_writes 53283 # number of write accesses completed +system.cpu1.num_reads 98684 # number of read accesses completed +system.cpu1.num_writes 53281 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 22413 # number of replacements -system.cpu1.l1c.tagsinuse 397.274781 # Cycle average of tags in use -system.cpu1.l1c.total_refs 13337 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 22810 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.584700 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 21834 # number of replacements +system.cpu1.l1c.tagsinuse 394.001606 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13244 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22217 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.596120 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 397.274781 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.775927 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.775927 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8758 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8758 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1087 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1087 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9845 # 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number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 1098702208 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 2437959035 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 2437959035 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 2437959035 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 2437959035 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 44521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 24147 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 24147 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 68668 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 68668 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 68668 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 68668 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803284 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.803284 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.954984 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.954984 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.856629 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.856629 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.856629 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.856629 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37448.111931 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 37448.111931 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47645.368951 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 47645.368951 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 41445.676606 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 41445.676606 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 41445.676606 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 41445.676606 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1431601 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 394.001606 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.769534 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.769534 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8661 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8661 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1083 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9744 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9744 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9744 # number of overall hits +system.cpu1.l1c.overall_hits::total 9744 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35792 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35792 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 23021 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 23021 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58813 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58813 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58813 # number of overall misses +system.cpu1.l1c.overall_misses::total 58813 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1333175718 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1333175718 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1095650216 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1095650216 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2428825934 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2428825934 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2428825934 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2428825934 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44453 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44453 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 24104 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 24104 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68557 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68557 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68557 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68557 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805165 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805165 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955070 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.955070 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857870 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857870 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857870 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857870 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37247.868742 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37247.868742 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47593.510968 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47593.510968 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41297.433119 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41297.433119 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41297.433119 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41297.433119 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1437849 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 66652 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66915 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.478740 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.487693 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9847 # number of writebacks -system.cpu1.l1c.writebacks::total 9847 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35763 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 35763 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23060 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 23060 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 58823 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 58823 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 58823 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 58823 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1267732827 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1267732827 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1052584208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1052584208 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2320317035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 2320317035 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2320317035 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 2320317035 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 694424746 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 694424746 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 428704098 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 428704098 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1123128844 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1123128844 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803284 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803284 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.954984 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.954984 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.856629 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856629 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.856629 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35448.167855 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35448.167855 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45645.455681 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45645.455681 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39445.744607 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39445.744607 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9612 # number of writebacks +system.cpu1.l1c.writebacks::total 9612 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35792 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 23021 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 23021 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58813 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58813 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58813 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58813 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1261597219 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1261597219 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1049610216 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1049610216 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2311207435 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2311207435 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2311207435 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2311207435 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 716556549 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 716556549 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 420969607 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 420969607 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1137526156 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1137526156 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805165 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805165 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955070 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955070 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857870 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857870 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857870 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35248.022435 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35248.022435 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45593.597845 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45593.597845 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39297.560658 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39297.560658 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -886,114 +886,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 98918 # number of read accesses completed -system.cpu2.num_writes 53026 # number of write accesses completed +system.cpu2.num_reads 99895 # number of read accesses completed +system.cpu2.num_writes 53724 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22091 # number of replacements -system.cpu2.l1c.tagsinuse 394.122068 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13053 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 22474 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.580804 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 22670 # number of replacements +system.cpu2.l1c.tagsinuse 395.972858 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13513 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 23058 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.586044 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 394.122068 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.769770 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.769770 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8657 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8657 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1062 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1062 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9719 # 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number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 1086319531 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 2420859668 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 2420859668 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 2420859668 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 2420859668 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 44449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 44449 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23844 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23844 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68293 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68293 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68293 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68293 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805237 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805237 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.955460 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.955460 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.857687 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.857687 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.857687 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.857687 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37285.989523 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 37285.989523 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47683.238127 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 47683.238127 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 41329.935944 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 41329.935944 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 41329.935944 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 41329.935944 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1431481 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 395.972858 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.773384 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.773384 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8816 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8816 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1120 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1120 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9936 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9936 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9936 # number of overall hits +system.cpu2.l1c.overall_hits::total 9936 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 36217 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 36217 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 23141 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 23141 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 59358 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 59358 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 59358 # number of overall misses +system.cpu2.l1c.overall_misses::total 59358 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1347141340 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1347141340 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1089667259 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1089667259 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2436808599 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2436808599 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2436808599 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2436808599 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 45033 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 45033 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 24261 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 24261 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 69294 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 69294 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 69294 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 69294 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.804232 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.804232 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953835 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953835 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.856611 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.856611 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.856611 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.856611 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37196.381257 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37196.381257 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47088.166415 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47088.166415 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41052.740978 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41052.740978 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41052.740978 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41052.740978 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1437012 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 66558 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 67454 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.507272 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.303585 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9590 # number of writebacks -system.cpu2.l1c.writebacks::total 9590 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35792 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 35792 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22782 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22782 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 58574 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 58574 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 58574 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 58574 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1262960137 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1262960137 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1040755531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1040755531 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2303715668 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 2303715668 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2303715668 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 2303715668 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 710805276 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 710805276 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 431026471 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 431026471 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1141831747 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1141831747 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805237 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805237 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.955460 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.955460 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.857687 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857687 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.857687 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35286.101280 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35286.101280 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45683.238127 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45683.238127 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39330.004234 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39330.004234 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9964 # number of writebacks +system.cpu2.l1c.writebacks::total 9964 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36217 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 36217 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 23141 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 23141 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 59358 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 59358 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1274713340 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1274713340 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1043385259 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1043385259 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2318098599 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2318098599 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2318098599 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2318098599 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 709358616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 709358616 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 436023988 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 436023988 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1145382604 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1145382604 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.804232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.804232 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953835 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953835 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.856611 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.856611 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.856611 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35196.546925 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35196.546925 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45088.166415 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45088.166415 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39052.842060 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39052.842060 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1001,114 +1001,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98879 # number of read accesses completed -system.cpu3.num_writes 53514 # number of write accesses completed +system.cpu3.num_reads 98442 # number of read accesses completed +system.cpu3.num_writes 53057 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22321 # number of replacements -system.cpu3.l1c.tagsinuse 395.059941 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13052 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22702 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.574927 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 21593 # number of replacements +system.cpu3.l1c.tagsinuse 392.026155 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13022 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 21995 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.592044 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 395.059941 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.771601 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.771601 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8562 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8562 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1034 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1034 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9596 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9596 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9596 # number of overall hits -system.cpu3.l1c.overall_hits::total 9596 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 35946 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 35946 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22965 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22965 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58911 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58911 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58911 # number of overall misses -system.cpu3.l1c.overall_misses::total 58911 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 1334193508 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 1334193508 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 1085703243 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 1085703243 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 2419896751 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 2419896751 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 2419896751 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 2419896751 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44508 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44508 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 23999 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 23999 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68507 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68507 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68507 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68507 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.807630 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.807630 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956915 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.956915 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.859927 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.859927 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.859927 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.859927 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37116.605686 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 37116.605686 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47276.431221 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 47276.431221 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 41077.163026 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 41077.163026 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 41077.163026 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 41077.163026 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1431288 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 392.026155 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.765676 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.765676 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8553 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8553 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1036 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1036 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9589 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9589 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9589 # number of overall hits +system.cpu3.l1c.overall_hits::total 9589 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35616 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35616 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 22828 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 22828 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 58444 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 58444 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 58444 # number of overall misses +system.cpu3.l1c.overall_misses::total 58444 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1343250290 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1343250290 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1077342427 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1077342427 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2420592717 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2420592717 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2420592717 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2420592717 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44169 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44169 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 23864 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 23864 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68033 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68033 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68033 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68033 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.806357 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.806357 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.956587 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.956587 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.859054 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.859054 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.859054 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.859054 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 37714.799248 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 37714.799248 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47193.903408 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47193.903408 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 41417.300613 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 41417.300613 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 41417.300613 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 41417.300613 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1437847 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 66945 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 66560 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.380058 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.602269 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9751 # number of writebacks -system.cpu3.l1c.writebacks::total 9751 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35946 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 35946 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22965 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22965 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58911 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58911 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58911 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58911 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1262305508 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1262305508 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1039775243 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1039775243 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2302080751 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 2302080751 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2302080751 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 2302080751 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 712475632 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 712475632 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 424398019 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 424398019 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1136873651 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1136873651 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.807630 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.807630 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956915 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956915 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.859927 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859927 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.859927 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35116.716964 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35116.716964 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45276.518310 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45276.518310 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39077.264874 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39077.264874 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9543 # number of writebacks +system.cpu3.l1c.writebacks::total 9543 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35616 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35616 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22828 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 22828 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 58444 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 58444 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 58444 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 58444 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1272022290 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1272022290 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1031688427 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1031688427 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2303710717 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2303710717 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2303710717 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2303710717 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 723405993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 723405993 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 425307050 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 425307050 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1148713043 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1148713043 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.806357 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.806357 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.956587 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.956587 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.859054 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.859054 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.859054 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 35714.911557 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 35714.911557 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45193.991020 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45193.991020 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 39417.403275 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 39417.403275 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1116,114 +1116,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 99302 # number of read accesses completed -system.cpu4.num_writes 53818 # number of write accesses completed +system.cpu4.num_reads 99668 # number of read accesses completed +system.cpu4.num_writes 53668 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 22353 # number of replacements -system.cpu4.l1c.tagsinuse 396.021323 # Cycle average of tags in use -system.cpu4.l1c.total_refs 13287 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 22757 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.583864 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22398 # number of replacements +system.cpu4.l1c.tagsinuse 394.185618 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13312 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22817 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.583425 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 396.021323 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.773479 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.773479 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8768 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8768 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 1075 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 1075 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9843 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9843 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9843 # number of overall hits -system.cpu4.l1c.overall_hits::total 9843 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 36125 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 36125 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22981 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22981 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 59106 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 59106 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 59106 # number of overall misses -system.cpu4.l1c.overall_misses::total 59106 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 1336431585 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 1336431585 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 1085022253 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 1085022253 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 2421453838 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 2421453838 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 2421453838 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 2421453838 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 44893 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 44893 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 24056 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 24056 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 68949 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 68949 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 68949 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 68949 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804691 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.804691 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.955313 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.955313 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.857242 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.857242 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.857242 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.857242 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 36994.645952 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 36994.645952 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47213.883338 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 47213.883338 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 40967.986973 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 40967.986973 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 40967.986973 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 40967.986973 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1430986 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 394.185618 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.769894 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.769894 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8742 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8742 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1059 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1059 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9801 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9801 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9801 # number of overall hits +system.cpu4.l1c.overall_hits::total 9801 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36283 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36283 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 23024 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 23024 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 59307 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 59307 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 59307 # number of overall misses +system.cpu4.l1c.overall_misses::total 59307 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1350032249 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1350032249 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1082307804 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1082307804 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2432340053 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2432340053 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2432340053 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2432340053 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 45025 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 45025 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 24083 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 24083 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 69108 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 69108 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 69108 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 69108 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.805841 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.805841 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.956027 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.956027 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.858179 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.858179 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.858179 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.858179 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37208.396467 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 37208.396467 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 47007.809416 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 47007.809416 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 41012.697540 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 41012.697540 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 41012.697540 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 41012.697540 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1437185 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 67143 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 67419 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.312512 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.317210 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9680 # number of writebacks -system.cpu4.l1c.writebacks::total 9680 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36125 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 36125 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22981 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22981 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 59106 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 59106 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 59106 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 59106 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1264183585 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1264183585 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1039060253 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1039060253 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2303243838 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 2303243838 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2303243838 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 2303243838 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 711442657 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 711442657 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 433569420 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 433569420 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1145012077 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1145012077 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804691 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804691 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.955313 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.955313 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.857242 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.857242 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.857242 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 34994.701315 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 34994.701315 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45213.883338 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45213.883338 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 38968.020810 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 38968.020810 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9672 # number of writebacks +system.cpu4.l1c.writebacks::total 9672 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36283 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36283 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 23024 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 23024 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 59307 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 59307 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 59307 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 59307 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1277470249 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1277470249 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1036263804 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1036263804 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2313734053 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2313734053 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2313734053 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2313734053 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 713854071 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 713854071 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 422821531 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 422821531 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1136675602 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1136675602 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.805841 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.805841 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.956027 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.956027 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.858179 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.858179 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.858179 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35208.506711 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35208.506711 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 45007.983148 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 45007.983148 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39012.832431 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39012.832431 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1231,114 +1231,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98038 # number of read accesses completed -system.cpu5.num_writes 52677 # number of write accesses completed +system.cpu5.num_reads 98297 # number of read accesses completed +system.cpu5.num_writes 53409 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 21614 # number of replacements -system.cpu5.l1c.tagsinuse 395.041478 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13218 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22030 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.600000 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 21793 # number of replacements +system.cpu5.l1c.tagsinuse 394.840854 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13019 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22214 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.586072 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 395.041478 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.771565 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.771565 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8654 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8654 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1143 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1143 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9797 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9797 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9797 # number of overall hits -system.cpu5.l1c.overall_hits::total 9797 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35607 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35607 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22649 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22649 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58256 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58256 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58256 # number of overall misses -system.cpu5.l1c.overall_misses::total 58256 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 1343353904 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 1343353904 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 1075550971 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 1075550971 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 2418904875 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 2418904875 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 2418904875 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 2418904875 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44261 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44261 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 23792 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 23792 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68053 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68053 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68053 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68053 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.804478 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.804478 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.951959 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.951959 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.856039 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.856039 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.856039 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.856039 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37727.241947 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 37727.241947 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47487.790675 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 47487.790675 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 41521.987006 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 41521.987006 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 41521.987006 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 41521.987006 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1431933 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 394.840854 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771174 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771174 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8574 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8574 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1037 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1037 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9611 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9611 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9611 # number of overall hits +system.cpu5.l1c.overall_hits::total 9611 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35608 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35608 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22949 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22949 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58557 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58557 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58557 # number of overall misses +system.cpu5.l1c.overall_misses::total 58557 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1333115373 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1333115373 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1089027179 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1089027179 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2422142552 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2422142552 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2422142552 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2422142552 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44182 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44182 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 23986 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 23986 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68168 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68168 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68168 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68168 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.805939 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.805939 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.956766 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.956766 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.859010 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.859010 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.859010 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.859010 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37438.647860 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37438.647860 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47454.232385 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47454.232385 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41363.842956 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41363.842956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41363.842956 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41363.842956 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1437965 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 66282 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66766 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.603648 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.537384 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9279 # number of writebacks -system.cpu5.l1c.writebacks::total 9279 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35607 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35607 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22649 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22649 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58256 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58256 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58256 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58256 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1272141904 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1272141904 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1030256971 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1030256971 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2302398875 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 2302398875 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2302398875 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 2302398875 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 712509152 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 712509152 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 420356599 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 420356599 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1132865751 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1132865751 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.804478 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.804478 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.951959 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.951959 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.856039 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.856039 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.856039 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35727.298116 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35727.298116 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45487.967283 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45487.967283 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39522.089999 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39522.089999 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9530 # number of writebacks +system.cpu5.l1c.writebacks::total 9530 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35608 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35608 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22949 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22949 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58557 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58557 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58557 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58557 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1261899373 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1261899373 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1043133179 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1043133179 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2305032552 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2305032552 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2305032552 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2305032552 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 722637545 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 722637545 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 432075918 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 432075918 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1154713463 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1154713463 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.805939 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.805939 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.956766 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.956766 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.859010 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.859010 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.859010 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35438.647860 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35438.647860 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45454.406684 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45454.406684 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39363.911266 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39363.911266 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1346,114 +1346,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 98486 # number of read accesses completed -system.cpu6.num_writes 53296 # number of write accesses completed +system.cpu6.num_reads 100000 # number of read accesses completed +system.cpu6.num_writes 53851 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 22107 # number of replacements -system.cpu6.l1c.tagsinuse 394.242179 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13254 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22518 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.588596 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 22533 # number of replacements +system.cpu6.l1c.tagsinuse 396.232181 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13413 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22918 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.585260 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 394.242179 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.770004 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.770004 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8629 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8629 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1104 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1104 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9733 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9733 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9733 # number of overall hits -system.cpu6.l1c.overall_hits::total 9733 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35833 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35833 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 23033 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 23033 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 58866 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 58866 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 58866 # number of overall misses -system.cpu6.l1c.overall_misses::total 58866 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 1334639245 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 1334639245 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 1095786214 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 1095786214 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 2430425459 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 2430425459 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 2430425459 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 2430425459 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 44462 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 44462 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 24137 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 68599 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 68599 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 68599 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 68599 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805924 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.805924 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954261 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954261 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858117 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858117 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858117 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858117 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37246.092847 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 37246.092847 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47574.619633 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 47574.619633 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 41287.423283 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 41287.423283 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 41287.423283 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 41287.423283 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1431647 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 396.232181 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.773891 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.773891 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8765 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8765 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1112 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9877 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9877 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9877 # number of overall hits +system.cpu6.l1c.overall_hits::total 9877 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 36287 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 36287 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 23071 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 23071 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 59358 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 59358 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 59358 # number of overall misses +system.cpu6.l1c.overall_misses::total 59358 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1346746093 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1346746093 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1082399151 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1082399151 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2429145244 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2429145244 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2429145244 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2429145244 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 45052 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 45052 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 24183 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 24183 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 69235 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 69235 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 69235 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 69235 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805447 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805447 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954017 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954017 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.857341 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.857341 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.857341 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.857341 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37113.734753 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37113.734753 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 46916.004985 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 46916.004985 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 40923.636982 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 40923.636982 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 40923.636982 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 40923.636982 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1436888 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 66759 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 67354 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.445004 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.333373 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9651 # number of writebacks -system.cpu6.l1c.writebacks::total 9651 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35833 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35833 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 23033 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 58866 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 58866 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 58866 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 58866 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1262977245 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1262977245 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1049724214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1049724214 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2312701459 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 2312701459 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2312701459 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 2312701459 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 702275141 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 702275141 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 427671023 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 427671023 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1129946164 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1129946164 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805924 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805924 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954261 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954261 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858117 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858117 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858117 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35246.204476 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35246.204476 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45574.793297 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45574.793297 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39287.559185 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39287.559185 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9760 # number of writebacks +system.cpu6.l1c.writebacks::total 9760 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 36287 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 36287 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 23071 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 23071 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 59358 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 59358 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 59358 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 59358 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1274178093 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1274178093 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1036259151 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1036259151 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2310437244 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2310437244 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2310437244 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2310437244 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 716759617 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 716759617 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 439137857 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 439137857 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1155897474 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1155897474 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805447 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805447 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954017 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954017 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.857341 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.857341 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.857341 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35113.900102 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35113.900102 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 44916.091674 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 44916.091674 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 38923.771758 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 38923.771758 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1461,114 +1461,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 53815 # number of write accesses completed +system.cpu7.num_reads 99311 # number of read accesses completed +system.cpu7.num_writes 53396 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22563 # number of replacements -system.cpu7.l1c.tagsinuse 397.316418 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13400 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 22950 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.583878 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22280 # number of replacements +system.cpu7.l1c.tagsinuse 395.094392 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13351 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22696 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.588253 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 397.316418 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.776009 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.776009 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8738 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8738 # number of ReadReq hits -system.cpu7.l1c.WriteReq_hits::cpu7 1123 # number of WriteReq hits -system.cpu7.l1c.WriteReq_hits::total 1123 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9861 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9861 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9861 # number of overall hits -system.cpu7.l1c.overall_hits::total 9861 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 36561 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 36561 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22883 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22883 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 59444 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 59444 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 59444 # number of overall misses -system.cpu7.l1c.overall_misses::total 59444 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 1338317183 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 1338317183 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 1076026419 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 1076026419 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 2414343602 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 2414343602 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 2414343602 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 2414343602 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 45299 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 24006 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 69305 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 69305 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 69305 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 69305 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807104 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.807104 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953220 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953220 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857716 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857716 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857716 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857716 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 36605.048631 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 36605.048631 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47022.961106 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 47022.961106 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 40615.429682 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 40615.429682 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 40615.429682 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 40615.429682 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1430407 # number of cycles access was blocked +system.cpu7.l1c.occ_blocks::cpu7 395.094392 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.771669 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.771669 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8656 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8656 # number of ReadReq hits +system.cpu7.l1c.WriteReq_hits::cpu7 1129 # number of WriteReq hits +system.cpu7.l1c.WriteReq_hits::total 1129 # number of WriteReq hits +system.cpu7.l1c.demand_hits::cpu7 9785 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9785 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9785 # number of overall hits +system.cpu7.l1c.overall_hits::total 9785 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 36252 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 36252 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23067 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23067 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 59319 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 59319 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 59319 # number of overall misses +system.cpu7.l1c.overall_misses::total 59319 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1344539775 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1344539775 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1092348717 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1092348717 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2436888492 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2436888492 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2436888492 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2436888492 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44908 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44908 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24196 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24196 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 69104 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 69104 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 69104 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 69104 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.807250 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.807250 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953339 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.953339 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.858402 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.858402 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.858402 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.858402 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37088.706140 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 37088.706140 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47355.473924 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47355.473924 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 41081.078440 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 41081.078440 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 41081.078440 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 41081.078440 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1437300 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 67553 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 67375 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.174589 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.332839 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9844 # number of writebacks -system.cpu7.l1c.writebacks::total 9844 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36561 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 36561 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22883 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22883 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 59444 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 59444 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 59444 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 59444 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1265201183 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1265201183 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1030262419 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1030262419 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2295463602 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 2295463602 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2295463602 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 2295463602 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 718920000 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 718920000 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432823408 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432823408 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1151743408 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1151743408 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807104 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807104 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953220 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953220 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857716 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857716 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857716 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 34605.212740 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 34605.212740 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45023.048508 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45023.048508 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 38615.564262 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 38615.564262 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9656 # number of writebacks +system.cpu7.l1c.writebacks::total 9656 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 36252 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 36252 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23067 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23067 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 59319 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 59319 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 59319 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 59319 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1272035775 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1272035775 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1046218717 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1046218717 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2318254492 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2318254492 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2318254492 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2318254492 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 709343608 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 709343608 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 432591529 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 432591529 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1141935137 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1141935137 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.807250 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.807250 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953339 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953339 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.858402 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.858402 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.858402 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35088.706140 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35088.706140 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45355.647332 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45355.647332 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39081.145872 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39081.145872 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |