diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/quick/se | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/quick/se')
15 files changed, 712 insertions, 937 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9e62381ba..a38dae954 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19476000 # Number of ticks simulated final_tick 19476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 78389 # Simulator instruction rate (inst/s) -host_op_rate 78368 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 238789679 # Simulator tick rate (ticks/s) -host_mem_usage 223680 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1322 # Simulator instruction rate (inst/s) +host_op_rate 1322 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4028719 # Simulator tick rate (ticks/s) +host_mem_usage 223696 # Number of bytes of host memory used +host_seconds 4.83 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 469 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 301 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2628216 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13374466 # Sum of mem lat for all requests +system.physmem.totQLat 2627750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13374000 # Sum of mem lat for all requests system.physmem.totBusLat 2345000 # Total cycles spent in databus access system.physmem.totBankLat 8401250 # Total cycles spent in bank access -system.physmem.avgQLat 5603.87 # Average queueing delay per request +system.physmem.avgQLat 5602.88 # Average queueing delay per request system.physmem.avgBankLat 17913.11 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28516.99 # Average memory access latency +system.physmem.avgMemAccLat 28515.99 # Average memory access latency system.physmem.avgRdBW 1537.89 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1537.89 # Average consumed read bandwidth in MB/s @@ -372,13 +357,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52524.834437 system.cpu.icache.overall_avg_mshr_miss_latency::total 52524.834437 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.973805 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 199.973821 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 143.049582 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.924223 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 143.049595 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.924226 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004366 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001737 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006103 # Average percentage of cache occupancy @@ -462,17 +447,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177366 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993865 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666348 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843714 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18660213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843714 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18660213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11816250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4177308 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15993558 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2666299 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11816250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6843607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18659857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11816250 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6843607 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18659857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -484,17 +469,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39257.471761 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43972.273684 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40388.547980 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36525.315068 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39257.471761 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40736.392857 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39787.234542 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39256.644518 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43971.663158 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40387.772727 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36524.643836 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39256.644518 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40735.755952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39786.475480 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 104.433203 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index d7bf6a6b9..8b0cd4f27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000016 # Number of seconds simulated -sim_ticks 16030500 # Number of ticks simulated -final_tick 16030500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 16039500 # Number of ticks simulated +final_tick 16039500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76258 # Simulator instruction rate (inst/s) -host_op_rate 76239 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 191753794 # Simulator tick rate (ticks/s) -host_mem_usage 225728 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 1336 # Simulator instruction rate (inst/s) +host_op_rate 1336 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3362323 # Simulator tick rate (ticks/s) +host_mem_usage 225744 # Number of bytes of host memory used +host_seconds 4.77 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19968 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19968 # Nu system.physmem.num_reads::cpu.inst 312 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1245625526 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 694675774 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1940301301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1245625526 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1245625526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 694675774 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1940301301 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1244926587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 694285981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1939212569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1244926587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1244926587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 694285981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1939212569 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 486 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 15817000 # Total gap between requests +system.physmem.totGap 15803000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 486 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 62 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,28 +149,27 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2909986 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13644986 # Sum of mem lat for all requests +system.physmem.totQLat 2921750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13656750 # Sum of mem lat for all requests system.physmem.totBusLat 2430000 # Total cycles spent in databus access system.physmem.totBankLat 8305000 # Total cycles spent in bank access -system.physmem.avgQLat 5987.63 # Average queueing delay per request +system.physmem.avgQLat 6011.83 # Average queueing delay per request system.physmem.avgBankLat 17088.48 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28076.10 # Average memory access latency -system.physmem.avgRdBW 1940.30 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28100.31 # Average memory access latency +system.physmem.avgRdBW 1939.21 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1940.30 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1939.21 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.16 # Data bus utilization in percentage +system.physmem.busUtil 15.15 # Data bus utilization in percentage system.physmem.avgRdQLen 0.85 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 396 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.48 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 32545.27 # Average gap between requests +system.physmem.avgGap 32516.46 # Average gap between requests system.cpu.branchPred.lookups 2896 # Number of BP lookups system.cpu.branchPred.condPredicted 1698 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 513 # Number of conditional branches incorrect @@ -227,7 +212,7 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 32062 # number of cpu cycles simulated +system.cpu.numCycles 32080 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.fetch.icacheStallCycles 8352 # Number of cycles fetch is stalled on an Icache miss @@ -258,8 +243,8 @@ system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Nu system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 14509 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090325 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.515470 # Number of inst fetches per cycle +system.cpu.fetch.branchRate 0.090274 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.515181 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 9308 # Number of cycles decode is idle system.cpu.decode.BlockedCycles 1148 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2753 # Number of cycles decode is running @@ -384,7 +369,7 @@ system.cpu.iq.FU_type_0::MemWrite 1140 10.55% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10806 # Type of FU issued -system.cpu.iq.rate 0.337034 # Inst issue rate +system.cpu.iq.rate 0.336845 # Inst issue rate system.cpu.iq.fu_busy_cnt 118 # FU busy when requested system.cpu.iq.fu_busy_rate 0.010920 # FU busy rate (busy events/executed inst) system.cpu.iq.int_inst_queue_reads 36268 # Number of integer instruction queue reads @@ -428,13 +413,13 @@ system.cpu.iew.exec_nop 86 # nu system.cpu.iew.exec_refs 3233 # number of memory reference insts executed system.cpu.iew.exec_branches 1613 # Number of branches executed system.cpu.iew.exec_stores 1101 # Number of stores executed -system.cpu.iew.exec_rate 0.316699 # Inst execution rate +system.cpu.iew.exec_rate 0.316521 # Inst execution rate system.cpu.iew.wb_sent 9857 # cumulative count of insts sent to commit system.cpu.iew.wb_count 9710 # cumulative count of insts written-back system.cpu.iew.wb_producers 5134 # num instructions producing a value system.cpu.iew.wb_consumers 6919 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.302851 # insts written-back per cycle +system.cpu.iew.wb_rate 0.302681 # insts written-back per cycle system.cpu.iew.wb_fanout 0.742015 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 6741 # The number of squashed insts skipped by commit @@ -472,14 +457,14 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 25928 # The number of ROB reads system.cpu.rob.rob_writes 27481 # The number of ROB writes system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 17553 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 17571 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 5.031701 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.031701 # CPI: Total CPI of All Threads -system.cpu.ipc 0.198740 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.198740 # IPC: Total IPC of All Threads +system.cpu.cpi 5.034526 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.034526 # CPI: Total CPI of All Threads +system.cpu.ipc 0.198628 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.198628 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 12888 # number of integer regfile reads system.cpu.int_regfile_writes 7343 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads @@ -487,14 +472,14 @@ system.cpu.fp_regfile_writes 2 # nu system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 159.192237 # Cycle average of tags in use +system.cpu.icache.tagsinuse 159.281471 # Cycle average of tags in use system.cpu.icache.total_refs 1869 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 313 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.971246 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 159.192237 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.077731 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.077731 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 159.281471 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.077774 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.077774 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1869 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1869 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1869 # number of demand (read+write) hits @@ -507,12 +492,12 @@ system.cpu.icache.demand_misses::cpu.inst 480 # n system.cpu.icache.demand_misses::total 480 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 480 # number of overall misses system.cpu.icache.overall_misses::total 480 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22202500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22202500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22202500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22202500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22202500 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 22197500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 22197500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 22197500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 22197500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 22197500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2349 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2349 # number of demand (read+write) accesses @@ -525,12 +510,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.204342 system.cpu.icache.demand_miss_rate::total 0.204342 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.204342 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.204342 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46255.208333 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46255.208333 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46255.208333 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46255.208333 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46244.791667 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46244.791667 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46244.791667 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46244.791667 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -551,36 +536,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 313 system.cpu.icache.demand_mshr_misses::total 313 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 313 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16102000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16102000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16102000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16102000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16111000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16111000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16111000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16111000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.133248 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.133248 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.133248 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.133248 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51444.089457 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51444.089457 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51444.089457 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51472.843450 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51472.843450 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51472.843450 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 219.643453 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 219.754912 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 159.327355 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.316098 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004862 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 159.415983 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.338929 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004865 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006703 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006706 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -598,17 +583,17 @@ system.cpu.l2cache.demand_misses::total 486 # nu system.cpu.l2cache.overall_misses::cpu.inst 312 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15777000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15786000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6080500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21857500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21866500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3687500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3687500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 15777000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15786000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::cpu.data 9768000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 25545000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 15777000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::total 25554000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15786000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::cpu.data 9768000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 25545000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 25554000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 313 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) @@ -631,17 +616,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997947 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50567.307692 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50596.153846 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60202.970297 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52923.728814 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52945.520581 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50513.698630 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50513.698630 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52561.728395 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50567.307692 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52580.246914 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50596.153846 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56137.931034 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52561.728395 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52580.246914 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -661,17 +646,17 @@ system.cpu.l2cache.demand_mshr_misses::total 486 system.cpu.l2cache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11907990 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848832 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16756822 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795812 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11907990 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644644 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19552634 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11907990 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644644 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19552634 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916495 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4848791 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16765286 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2795781 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916495 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7644572 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19561067 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916495 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7644572 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19561067 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses @@ -683,27 +668,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38166.634615 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48008.237624 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40573.418886 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.794521 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38166.634615 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.735632 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40231.757202 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38193.894231 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48007.831683 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40593.912833 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38298.369863 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38193.894231 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43934.321839 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40249.109053 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.713176 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 107.750370 # Cycle average of tags in use system.cpu.dcache.total_refs 2262 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 13 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.713176 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026297 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026297 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 107.750370 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026306 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026306 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1756 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1756 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index 6b89534e6..c84a7ed5c 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000009 # Nu sim_ticks 9350000 # Number of ticks simulated final_tick 9350000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 146 # Simulator instruction rate (inst/s) -host_op_rate 146 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 570039 # Simulator tick rate (ticks/s) -host_mem_usage 224412 # Number of bytes of host memory used -host_seconds 16.40 # Real time elapsed on the host +host_inst_rate 55287 # Simulator instruction rate (inst/s) +host_op_rate 55271 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 216439769 # Simulator tick rate (ticks/s) +host_mem_usage 224436 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 272 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 148 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 87 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 26 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1329022 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7872772 # Sum of mem lat for all requests +system.physmem.totQLat 1328750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 7872500 # Sum of mem lat for all requests system.physmem.totBusLat 1360000 # Total cycles spent in databus access system.physmem.totBankLat 5183750 # Total cycles spent in bank access -system.physmem.avgQLat 4886.11 # Average queueing delay per request +system.physmem.avgQLat 4885.11 # Average queueing delay per request system.physmem.avgBankLat 19057.90 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28944.01 # Average memory access latency +system.physmem.avgMemAccLat 28943.01 # Average memory access latency system.physmem.avgRdBW 1861.82 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1861.82 # Average consumed read bandwidth in MB/s @@ -571,13 +556,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51481.278075 system.cpu.icache.overall_avg_mshr_miss_latency::total 51481.278075 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 119.099628 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 119.099647 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 91.174739 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 27.924890 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 91.174754 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.924893 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.002782 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000852 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.003635 # Average percentage of cache occupancy @@ -655,17 +640,17 @@ system.cpu.l2cache.demand_mshr_misses::total 272 system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118288 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9957104 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118288 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952840 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11071128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118288 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952840 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11071128 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7118144 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2838783 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9956927 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1114012 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7118144 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3952795 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 11070939 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7118144 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3952795 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 11070939 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -677,17 +662,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38065.711230 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.967213 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40149.612903 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38065.711230 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46504 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40702.676471 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38064.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46537.426230 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40148.899194 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46417.166667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38064.941176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46503.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40701.981618 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 44.507812 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 80cf199ee..ed4523776 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 51480 # Simulator instruction rate (inst/s) -host_op_rate 64222 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 153638426 # Simulator tick rate (ticks/s) -host_mem_usage 239936 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 31817 # Simulator instruction rate (inst/s) +host_op_rate 39697 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 94976589 # Simulator tick rate (ticks/s) +host_mem_usage 239960 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -624,13 +609,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -723,17 +708,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -745,17 +730,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 13489057c..ef2f22c88 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 13709000 # Number of ticks simulated final_tick 13709000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 58002 # Simulator instruction rate (inst/s) -host_op_rate 72354 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173086159 # Simulator tick rate (ticks/s) -host_mem_usage 238920 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host +host_inst_rate 36221 # Simulator instruction rate (inst/s) +host_op_rate 45190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 108117571 # Simulator tick rate (ticks/s) +host_mem_usage 238932 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 4591 # Number of instructions simulated sim_ops 5729 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 394 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2508144 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11751894 # Sum of mem lat for all requests +system.physmem.totQLat 2507750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests system.physmem.totBusLat 1970000 # Total cycles spent in databus access system.physmem.totBankLat 7273750 # Total cycles spent in bank access -system.physmem.avgQLat 6365.85 # Average queueing delay per request +system.physmem.avgQLat 6364.85 # Average queueing delay per request system.physmem.avgBankLat 18461.29 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29827.14 # Average memory access latency +system.physmem.avgMemAccLat 29826.14 # Average memory access latency system.physmem.avgRdBW 1839.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1839.38 # Average consumed read bandwidth in MB/s @@ -579,13 +564,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50146.048110 system.cpu.icache.overall_avg_mshr_miss_latency::total 50146.048110 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 185.063220 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 185.063238 # Cycle average of tags in use system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 138.360527 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.702693 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 138.360542 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.702695 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004222 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005648 # Average percentage of cache occupancy @@ -678,17 +663,17 @@ system.cpu.l2cache.demand_mshr_misses::total 394 system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10736168 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756318 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492486 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896792 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10736168 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653110 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16389278 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10736168 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653110 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16389278 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735959 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14492243 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735959 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16389014 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735959 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16389014 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses @@ -700,17 +685,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39471.205882 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46374.296296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41055.201133 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46263.219512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39471.205882 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.967213 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41597.152284 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39470.437500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41054.512748 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39470.437500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41596.482234 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 86.502557 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 4baa76c40..d65cf38dc 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000019 # Nu sim_ticks 19339000 # Number of ticks simulated final_tick 19339000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100636 # Simulator instruction rate (inst/s) -host_op_rate 100592 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 334460805 # Simulator tick rate (ticks/s) -host_mem_usage 224316 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 54855 # Simulator instruction rate (inst/s) +host_op_rate 54842 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 182382541 # Simulator tick rate (ticks/s) +host_mem_usage 224336 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 455 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 293 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2650454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13959204 # Sum of mem lat for all requests +system.physmem.totQLat 2650000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13958750 # Sum of mem lat for all requests system.physmem.totBusLat 2275000 # Total cycles spent in databus access system.physmem.totBankLat 9033750 # Total cycles spent in bank access -system.physmem.avgQLat 5825.17 # Average queueing delay per request +system.physmem.avgQLat 5824.18 # Average queueing delay per request system.physmem.avgBankLat 19854.40 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30679.57 # Average memory access latency +system.physmem.avgMemAccLat 30678.57 # Average memory access latency system.physmem.avgRdBW 1505.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1505.77 # Average consumed read bandwidth in MB/s @@ -358,13 +343,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54322.884013 system.cpu.icache.overall_avg_mshr_miss_latency::total 54322.884013 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 206.866516 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 206.866533 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 151.045976 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.820540 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 151.045990 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.820543 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004610 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001704 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006313 # Average percentage of cache occupancy @@ -448,17 +433,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055529 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090608 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17146137 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925076 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015684 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 19071213 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055529 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015684 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 19071213 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13055265 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4090554 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17145819 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1925038 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13055265 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6015592 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 19070857 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13055265 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6015592 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 19070857 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -470,17 +455,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41184.634069 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47018.482759 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.933168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37746.588235 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41184.634069 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.913043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41914.753846 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41183.801262 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47017.862069 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42440.146040 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37745.843137 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41183.801262 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43591.246377 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41913.971429 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 89.917113 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 7feba62df..13fbe689c 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 17026500 # Number of ticks simulated final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76348 # Simulator instruction rate (inst/s) -host_op_rate 76319 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 251939378 # Simulator tick rate (ticks/s) -host_mem_usage 226380 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 44899 # Simulator instruction rate (inst/s) +host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 148205995 # Simulator tick rate (ticks/s) +host_mem_usage 226388 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 478 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2863474 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests +system.physmem.totQLat 2863000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests system.physmem.totBusLat 2390000 # Total cycles spent in databus access system.physmem.totBankLat 9363750 # Total cycles spent in bank access -system.physmem.avgQLat 5990.53 # Average queueing delay per request +system.physmem.avgQLat 5989.54 # Average queueing delay per request system.physmem.avgBankLat 19589.44 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30579.97 # Average memory access latency +system.physmem.avgMemAccLat 30578.97 # Average memory access latency system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s @@ -556,13 +541,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 478 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index ccc0289be..69396a815 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 14724500 # Number of ticks simulated final_tick 14724500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 87376 # Simulator instruction rate (inst/s) -host_op_rate 87343 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 221965921 # Simulator tick rate (ticks/s) -host_mem_usage 222644 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 62176 # Simulator instruction rate (inst/s) +host_op_rate 62167 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 158021685 # Simulator tick rate (ticks/s) +host_mem_usage 222660 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 446 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 232 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 147 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2286195 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12779945 # Sum of mem lat for all requests +system.physmem.totQLat 2285750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12779500 # Sum of mem lat for all requests system.physmem.totBusLat 2230000 # Total cycles spent in databus access system.physmem.totBankLat 8263750 # Total cycles spent in bank access -system.physmem.avgQLat 5126.00 # Average queueing delay per request +system.physmem.avgQLat 5125.00 # Average queueing delay per request system.physmem.avgBankLat 18528.59 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28654.59 # Average memory access latency +system.physmem.avgMemAccLat 28653.59 # Average memory access latency system.physmem.avgRdBW 1938.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1938.54 # Average consumed read bandwidth in MB/s @@ -553,13 +538,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50659.544160 system.cpu.icache.overall_avg_mshr_miss_latency::total 50659.544160 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.145802 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.145822 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 166.786148 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.359654 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 166.786167 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.359655 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005090 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006047 # Average percentage of cache occupancy @@ -646,17 +631,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13081037 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509304 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590341 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332794 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13081037 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842098 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17923135 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13081037 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842098 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17923135 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13080769 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2509277 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15590046 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2332772 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13080769 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4842049 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17922818 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13080769 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4842049 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17922818 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,17 +653,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37916.049275 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.592593 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39073.536341 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.914894 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37916.049275 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.564356 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40186.401345 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37915.272464 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46468.092593 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39072.796992 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49633.446809 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37915.272464 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47941.079208 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40185.690583 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 63.324462 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index a586f3039..d53327dbb 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16783500 # Number of ticks simulated final_tick 16783500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84096 # Simulator instruction rate (inst/s) -host_op_rate 84062 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 264753473 # Simulator tick rate (ticks/s) -host_mem_usage 230292 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 48421 # Simulator instruction rate (inst/s) +host_op_rate 48416 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 152524495 # Simulator tick rate (ticks/s) +host_mem_usage 230316 # Number of bytes of host memory used +host_seconds 0.11 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 423 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2673172 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12996922 # Sum of mem lat for all requests +system.physmem.totQLat 2672750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12996500 # Sum of mem lat for all requests system.physmem.totBusLat 2115000 # Total cycles spent in databus access system.physmem.totBankLat 8208750 # Total cycles spent in bank access -system.physmem.avgQLat 6319.56 # Average queueing delay per request +system.physmem.avgQLat 6318.56 # Average queueing delay per request system.physmem.avgBankLat 19406.03 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 30725.58 # Average memory access latency +system.physmem.avgMemAccLat 30724.59 # Average memory access latency system.physmem.avgRdBW 1613.01 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1613.01 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 system.cpu.icache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 167.397199 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 167.397215 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 140.660988 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.736211 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 140.661002 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 26.736213 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004293 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000816 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005109 # Average percentage of cache occupancy @@ -433,17 +418,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527456 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665331 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192787 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719824 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527456 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385155 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17912611 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527456 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385155 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17912611 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11527228 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2665291 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14192519 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3719787 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11527228 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6385078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17912306 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11527228 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6385078 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17912306 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -455,17 +440,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39887.391003 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50289.264151 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41499.377193 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.753086 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39887.391003 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47650.410448 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42346.598109 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39886.602076 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 50288.509434 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41498.593567 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 45923.296296 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39886.602076 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 47649.835821 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42345.877069 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 84.137936 # Cycle average of tags in use diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index b6a3a3279..03f9c34cb 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000015 # Nu sim_ticks 15468000 # Number of ticks simulated final_tick 15468000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31666 # Simulator instruction rate (inst/s) -host_op_rate 57357 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 91020367 # Simulator tick rate (ticks/s) -host_mem_usage 241544 # Number of bytes of host memory used +host_inst_rate 31901 # Simulator instruction rate (inst/s) +host_op_rate 57781 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 91692634 # Simulator tick rate (ticks/s) +host_mem_usage 241568 # Number of bytes of host memory used host_seconds 0.17 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 451 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 231 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 58 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1899951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13161201 # Sum of mem lat for all requests +system.physmem.totQLat 1899500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13160750 # Sum of mem lat for all requests system.physmem.totBusLat 2255000 # Total cycles spent in databus access system.physmem.totBankLat 9006250 # Total cycles spent in bank access -system.physmem.avgQLat 4212.75 # Average queueing delay per request +system.physmem.avgQLat 4211.75 # Average queueing delay per request system.physmem.avgBankLat 19969.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29182.26 # Average memory access latency +system.physmem.avgMemAccLat 29181.26 # Average memory access latency system.physmem.avgRdBW 1857.77 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1857.77 # Average consumed read bandwidth in MB/s @@ -536,13 +521,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53148.026316 system.cpu.icache.overall_avg_mshr_miss_latency::total 53148.026316 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 177.982441 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 177.982459 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.961595 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.020847 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.961610 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.020849 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004424 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005432 # Average percentage of cache occupancy @@ -626,17 +611,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12092212 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030082 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122294 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058112 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12092212 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088194 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18180406 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12092212 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088194 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18180406 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12091981 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3030041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15122022 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3058056 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12091981 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6088097 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18180078 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12091981 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6088097 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18180078 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -648,17 +633,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39908.290429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42084.472222 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40326.117333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40238.315789 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39908.290429 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41136.445946 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40311.321508 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39907.528053 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42083.902778 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40325.392000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40237.578947 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39907.528053 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41135.790541 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40310.594235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 83.496642 # Cycle average of tags in use diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 329680740..8505308fc 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000024 # Nu sim_ticks 24473000 # Number of ticks simulated final_tick 24473000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4068 # Simulator instruction rate (inst/s) -host_op_rate 4068 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7811345 # Simulator tick rate (ticks/s) -host_mem_usage 226312 # Number of bytes of host memory used -host_seconds 3.13 # Real time elapsed on the host +host_inst_rate 87264 # Simulator instruction rate (inst/s) +host_op_rate 87257 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 167537445 # Simulator tick rate (ticks/s) +host_mem_usage 226344 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 39808 # Number of bytes read from this memory @@ -78,29 +78,16 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 970 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 260 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 261 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 253 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 174 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 86 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 29 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 22646466 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 53470216 # Sum of mem lat for all requests +system.physmem.totQLat 22645500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 53469250 # Sum of mem lat for all requests system.physmem.totBusLat 4850000 # Total cycles spent in databus access system.physmem.totBankLat 25973750 # Total cycles spent in bank access -system.physmem.avgQLat 23346.87 # Average queueing delay per request +system.physmem.avgQLat 23345.88 # Average queueing delay per request system.physmem.avgBankLat 26777.06 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 55123.93 # Average memory access latency +system.physmem.avgMemAccLat 55122.94 # Average memory access latency system.physmem.avgRdBW 2536.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2536.67 # Average consumed read bandwidth in MB/s @@ -717,13 +702,13 @@ system.cpu.icache.no_allocate_misses 0 # Nu system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 407.828883 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 407.828902 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 824 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002427 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 293.011617 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 114.817266 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 293.011633 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 114.817269 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.008942 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.003504 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.012446 # Average percentage of cache occupancy @@ -807,17 +792,17 @@ system.cpu.l2cache.demand_mshr_misses::total 970 system.cpu.l2cache.overall_mshr_misses::cpu.inst 622 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 348 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 970 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40142034 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600631 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742665 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339864 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40142034 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940495 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 66082529 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40142034 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940495 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 66082529 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 40141642 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 15600566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 55742208 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10339807 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 40141642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 25940373 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 66082015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 40141642 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 25940373 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 66082015 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997579 # mshr miss rate for ReadReq accesses @@ -829,17 +814,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997942 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997942 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64537.032154 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.846535 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.865291 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.986301 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64537.032154 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.652299 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68126.318557 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64536.401929 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77230.524752 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67648.310680 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70820.595890 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64536.401929 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74541.301724 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68125.788660 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 3cd467a4b..7316b9759 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000023 # Nu sim_ticks 23146500 # Number of ticks simulated final_tick 23146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62448 # Simulator instruction rate (inst/s) -host_op_rate 62442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95315643 # Simulator tick rate (ticks/s) -host_mem_usage 230224 # Number of bytes of host memory used -host_seconds 0.24 # Real time elapsed on the host +host_inst_rate 95077 # Simulator instruction rate (inst/s) +host_op_rate 95070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 145124480 # Simulator tick rate (ticks/s) +host_mem_usage 230244 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 436 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 272 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 33 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2156686 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12064186 # Sum of mem lat for all requests +system.physmem.totQLat 2156250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12063750 # Sum of mem lat for all requests system.physmem.totBusLat 2180000 # Total cycles spent in databus access system.physmem.totBankLat 7727500 # Total cycles spent in bank access -system.physmem.avgQLat 4946.53 # Average queueing delay per request +system.physmem.avgQLat 4945.53 # Average queueing delay per request system.physmem.avgBankLat 17723.62 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27670.15 # Average memory access latency +system.physmem.avgMemAccLat 27669.15 # Average memory access latency system.physmem.avgRdBW 1205.54 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1205.54 # Average consumed read bandwidth in MB/s @@ -340,13 +325,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49700.996678 system.cpu.icache.overall_avg_mshr_miss_latency::total 49700.996678 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 203.582900 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 203.582912 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.517590 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 32.065310 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 171.517600 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.065312 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005234 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000979 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006213 # Average percentage of cache occupancy @@ -430,17 +415,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10987236 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575826 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13563062 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583070 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10987236 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158896 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 17146132 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10987236 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158896 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 17146132 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10986993 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2575788 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13562781 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3583035 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10986993 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6158823 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17145816 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10986993 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6158823 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17145816 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -452,17 +437,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36746.608696 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48600.490566 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38531.426136 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.764706 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36746.608696 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.681159 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39236 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36745.795987 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48599.773585 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38530.627841 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42153.352941 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36745.795987 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44629.152174 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39235.276888 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.212064 # Cycle average of tags in use diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index cd86d7e47..eaa2ab26e 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000024 # Nu sim_ticks 23775500 # Number of ticks simulated final_tick 23775500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 69212 # Simulator instruction rate (inst/s) -host_op_rate 69204 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 113962469 # Simulator tick rate (ticks/s) -host_mem_usage 232268 # Number of bytes of host memory used +host_inst_rate 69027 # Simulator instruction rate (inst/s) +host_op_rate 69023 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 113671122 # Simulator tick rate (ticks/s) +host_mem_usage 232284 # Number of bytes of host memory used host_seconds 0.21 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated @@ -78,26 +78,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 483 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see @@ -130,7 +117,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -163,15 +149,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4632480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 15613730 # Sum of mem lat for all requests +system.physmem.totQLat 4632000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 15613250 # Sum of mem lat for all requests system.physmem.totBusLat 2415000 # Total cycles spent in databus access system.physmem.totBankLat 8566250 # Total cycles spent in bank access -system.physmem.avgQLat 9591.06 # Average queueing delay per request +system.physmem.avgQLat 9590.06 # Average queueing delay per request system.physmem.avgBankLat 17735.51 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 32326.56 # Average memory access latency +system.physmem.avgMemAccLat 32325.57 # Average memory access latency system.physmem.avgRdBW 1300.16 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1300.16 # Average consumed read bandwidth in MB/s @@ -533,13 +518,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52118.343195 system.cpu.icache.overall_avg_mshr_miss_latency::total 52118.343195 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 224.642209 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.642221 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 189.932225 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.709984 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 189.932236 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.709985 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005796 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001059 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.006856 # Average percentage of cache occupancy @@ -623,17 +608,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099526 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042315 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141841 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145826 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099526 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188141 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 21287667 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099526 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188141 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 21287667 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13099263 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4042283 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17141546 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4145788 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13099263 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8188071 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 21287334 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13099263 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8188071 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 21287334 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses @@ -645,17 +630,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38986.684524 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63161.171875 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42854.602500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.710843 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38986.684524 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.639456 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.844720 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38985.901786 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63160.671875 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42853.865000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49949.253012 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38985.901786 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55701.163265 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44073.155280 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 99.563734 # Cycle average of tags in use diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index 3dd8cecd5..3eb29c400 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000106 # Nu sim_ticks 105801500 # Number of ticks simulated final_tick 105801500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99938 # Simulator instruction rate (inst/s) -host_op_rate 99937 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 10207562 # Simulator tick rate (ticks/s) -host_mem_usage 247464 # Number of bytes of host memory used -host_seconds 10.37 # Real time elapsed on the host +host_inst_rate 173787 # Simulator instruction rate (inst/s) +host_op_rate 173787 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 17750545 # Simulator tick rate (ticks/s) +host_mem_usage 247480 # Number of bytes of host memory used +host_seconds 5.96 # Real time elapsed on the host sim_insts 1035849 # Number of instructions simulated sim_ops 1035849 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory @@ -59,7 +59,7 @@ system.physmem.bw_total::cpu3.data 7863783 # To system.physmem.bw_total::total 399238196 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 661 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 978 # Reqs generatd by CPU via cache - shady +system.physmem.cpureqs 732 # Reqs generatd by CPU via cache - shady system.physmem.bytesRead 42240 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize() @@ -108,26 +108,13 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 661 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 71 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 377 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see @@ -160,7 +147,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -193,15 +179,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 4077160 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 20692160 # Sum of mem lat for all requests +system.physmem.totQLat 4076500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 20691500 # Sum of mem lat for all requests system.physmem.totBusLat 3305000 # Total cycles spent in databus access system.physmem.totBankLat 13310000 # Total cycles spent in bank access -system.physmem.avgQLat 6168.17 # Average queueing delay per request +system.physmem.avgQLat 6167.17 # Average queueing delay per request system.physmem.avgBankLat 20136.16 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 31304.33 # Average memory access latency +system.physmem.avgMemAccLat 31303.33 # Average memory access latency system.physmem.avgRdBW 399.24 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 399.24 # Average consumed read bandwidth in MB/s @@ -2117,17 +2102,17 @@ system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9965.116279 system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9965.116279 # average overall mshr miss latency system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 425.230692 # Cycle average of tags in use +system.l2c.tagsinuse 425.230696 # Cycle average of tags in use system.l2c.total_refs 1445 # Total number of references to valid blocks. system.l2c.sampled_refs 527 # Sample count of references to valid blocks. system.l2c.avg_refs 2.741935 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 0.824596 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.832857 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.832859 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.data 59.073855 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 61.730806 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 61.730807 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 5.603647 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 4.388881 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 4.388882 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu2.data 0.760374 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.inst 2.293580 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu3.data 0.722095 # Average occupied blocks per requestor @@ -2409,43 +2394,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13753074 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705088 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257128 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230760 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86256 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56252 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 21723071 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13752787 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3705044 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3257064 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 230755 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 86253 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 21722661 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 190518 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 161513 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 191511 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 727552 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247116 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838760 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720020 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607520 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 6413416 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 13753074 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 7952204 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 3257128 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 1417021 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 230760 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 776272 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.inst 86256 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3.data 663772 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 28136487 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 13753074 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 7952204 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 3257128 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 1417021 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 230760 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 776272 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.inst 86256 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3.data 663772 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 28136487 # number of overall MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 838755 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 607510 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 6413333 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 13752787 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7952102 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 3257064 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 1417011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 230755 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 86253 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.data 663761 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 28135994 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 13752787 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 7952102 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 3257064 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 1417011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 230755 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 86253 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 663761 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 28135994 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.188235 # mshr miss rate for ReadReq accesses @@ -2483,43 +2468,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.756757 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608.714286 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38460 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28752 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.926415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 50068.162162 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 28751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40986.152830 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.263158 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10094.562500 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10639.500000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10247.211268 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45182.085106 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64520 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60001.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50626.666667 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 48957.374046 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38416.407821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47334.547619 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40714.100000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70851.050000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38460 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59713.230769 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51059.384615 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 42566.546142 # average overall mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64519.615385 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50625.833333 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 48956.740458 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38415.606145 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47333.940476 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40713.300000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70850.550000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 38459.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 28751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51058.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42565.800303 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt index e7866c92f..adb4052b9 100644 --- a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-dram/stats.txt @@ -4,9 +4,9 @@ sim_seconds 0.100000 # Nu sim_ticks 100000000000 # Number of ticks simulated final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 29045358432 # Simulator tick rate (ticks/s) -host_mem_usage 222412 # Number of bytes of host memory used -host_seconds 3.44 # Real time elapsed on the host +host_tick_rate 31852968745 # Simulator tick rate (ticks/s) +host_mem_usage 226592 # Number of bytes of host memory used +host_seconds 3.14 # Real time elapsed on the host system.physmem.bytes_read::cpu 213337536 # Number of bytes read from this memory system.physmem.bytes_read::total 213337536 # Number of bytes read from this memory system.physmem.num_reads::cpu 3333399 # Number of read requests responded to by this memory @@ -66,37 +66,24 @@ system.physmem.readPktSize::3 0 # Ca system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes system.physmem.readPktSize::6 3333400 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 0 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 0 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 0 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 0 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 0 # Categorize write packet sizes system.physmem.rdQLenPdf::0 3200711 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 105371 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 4811 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3752 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 4283 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 3751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 4280 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3757 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 3749 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 3205 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 2146 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 1602 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 2146 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1076 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 2148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 1074 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 546 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see @@ -118,7 +105,6 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see @@ -151,15 +137,14 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 6115686626 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 69505296626 # Sum of mem lat for all requests +system.physmem.totQLat 6112380100 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 69501990100 # Sum of mem lat for all requests system.physmem.totBusLat 16667000000 # Total cycles spent in databus access system.physmem.totBankLat 46722610000 # Total cycles spent in bank access -system.physmem.avgQLat 1834.67 # Average queueing delay per request +system.physmem.avgQLat 1833.68 # Average queueing delay per request system.physmem.avgBankLat 14016.50 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 20851.17 # Average memory access latency +system.physmem.avgMemAccLat 20850.18 # Average memory access latency system.physmem.avgRdBW 2133.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2133.38 # Average consumed read bandwidth in MB/s @@ -278,9 +263,9 @@ system.monitor.writeBandwidthHist::total 100 # Hi system.monitor.averageWriteBandwidth 0 # Average write bandwidth (bytes/s) system.monitor.totalWrittenBytes 0 # Number of bytes written system.monitor.readLatencyHist::samples 3333399 # Read request-response latency -system.monitor.readLatencyHist::mean 20879.051770 # Read request-response latency -system.monitor.readLatencyHist::gmean 19622.150808 # Read request-response latency -system.monitor.readLatencyHist::stdev 15688.008500 # Read request-response latency +system.monitor.readLatencyHist::mean 20878.092191 # Read request-response latency +system.monitor.readLatencyHist::gmean 19621.155070 # Read request-response latency +system.monitor.readLatencyHist::stdev 15688.085413 # Read request-response latency system.monitor.readLatencyHist::0-32767 3201881 96.05% 96.05% # Read request-response latency system.monitor.readLatencyHist::32768-65535 104731 3.14% 99.20% # Read request-response latency system.monitor.readLatencyHist::65536-98303 5355 0.16% 99.36% # Read request-response latency |